Apple Macbook A1181 (K36C MLB)

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
K36C MLB SCHEMATIC
02
691395
ENGINEERING RELEASED
DATE
04/09/09 ?
APR/10/2009
(.csa)
(.csa)
Date
Page
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
08/22/2007
Table of Contents
K36BH_MLB
08/17/2008
System Block Diagram
K36B_MLB
Power Block Diagram
K36B_MLB
CONFIGURATION OPTIONS
K36B_MLB
Revision History
K36B_MLB
JTAG Scan Chain
K36B_MLB
08/17/2008
08/17/2008
5
6
08/17//2008
08/17/2008
FUNC TEST
K36B_MLB
Power Aliases
K36B_MLB
SIGNAL ALIAS
K36B_MLB
8
9
10
08/18/2008
CPU FSB
K36B_MLB
CPU Power & Ground
K36B_MLB
11
08/17/2008
12
08/17/2008
CPU Decoupling
K36B_MLB
eXtended Debug Port(MiniXDP)
M99_MLB
13
01/08/2008
14
08/17/2008
MCP CPU Interface
K36B_MLB
MCP Memory Interface
K36B_MLB
15
08/17/2008
16
08/17/2008
MCP Memory Misc
K36B_MLB
17
08/17/2008
MCP PCIe Interfaces
K36B_MLB
MCP Ethernet & Graphics
K36B_MLB
18
08/17/2008
19
08/17/2008
MCP PCI & LPC
K36B_MLB
MCP SATA & USB
K36B_MLB
20
08/17/2008
21
08/17/2008
MCP HDA & MISC
K36B_MLB
MCP Power & Ground
K36B_MLB
22
08/17/2008
24
08/17/2008
MCP79 A01 Silicon Support
K36B_MLB
25
08/17/2008
MCP Standard Decoupling
K36B_MLB
MCP Graphics Support
K36B_MLB
26
08/17/2008
28
08/17/2008
SB Misc
K36B_MLB
FSB/DDR2 VREF MARGINING
K36B_MLB
29
08/17/2008
31
08/17/2008
DDR2 SO-DIMM Connector A
K36B_MLB
DDR2 SO-DIMM Connector B
K36B_MLB
32
08/17/2008
33
08/17/2008
Memory Active Termination
K36B_MLB
34
08/17/2008
Right Clutch Connector
K36B_MLB
37
03/20/2008
Ethernet PHY (RTL8211CL)
SUMA
Ethernet & AirPort Support
SUMA
ETHERNET CONNECTOR
SUMA
38
04/04/2008
39
04/04/2008
41
08/17/2008
FireWire LLC/PHY(FW643E)
K36B_MLB
42
08/17/2008
FireWire Port Power
K36B_MLB
FireWire Ports
K36B_MLB
43
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
(MASTER)
Contents
45
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
08/17/2008
SATA Connectors
K36B_MLB
External USB Connectors
K36B_MLB
Front Flex Support
K36B_MLB
SMC
K36B_MLB
SMC Support
K36B_MLB
LPC+SPI Debug Connector
K36B_MLB
SMBUS CONNECTIONS
K36B_MLB
VOLTAGE SENSING
K36B_MLB
Current Sensing
K36B_MLB
Thermal Sensors
K36B_MLB
Fan
K36B_MLB
GEYSER
K36B_MLB
SMS
K36B_MLB
SPI ROM
K36B_MLB
46
08/17/2008
48
07/17/2008
49
08/17/2008
50
08/17/2008
51
08/17/2008
52
08/17/2008
53
08/17/2008
54
08/17/2008
55
08/17/2008
56
08/17/2008
58
08/17/2008
59
08/17/2008
61
081/17/2008
62
08/29/2008
AUDIO: CODEC
K36A_MLB
AUDI0: SPEAKER AMP
K36A_MLB
AUDIO: JACK
K36A_MLB
AUDIO: JACK TRANSLATORS
K36A_MLB
DC-In & Battery Connectors
RAYMOND
PBUS Supply/Battery Charger
K36B_MLB
5V/3.3V SUPPLY
K36B_MLB
1.8V/0.9V DDR2 SUPPLY
K36B_MLB
IMVP6 CPU VCore Regulator
K36B_MLB
MCP VCORE REGULATOR
K36B_MLB
CPU VTT(1.05V) SUPPLY
K36B_MLB
MISC POWER SUPPLIES
K36B_MLB
POWER SEQUENCING
K36B_MLB
POWER FETS
K36B_MLB
INVERTER,LVDS
K36B_MLB
TMDS ALIASES
K36B_MLB
MINI-DVI CONNECTOR
K36B_MLB
CPU/FSB Constraints
K36B_MLB
Memory Constraints
K36B_MLB
MCP Constraints 1
K36B_MLB
MCP Constraints 2
K36B_MLB
Ethernet Constraints
K36B_MLB
FireWire Constraints
K36B_MLB
SMC Constraints
K36B_MLB
K36B RULE DEFINITIONS
K36B_MLB
66
08/29/2008
67
08/29/2008
68
08/29/2008
69
08/17/2008
70
08/17/2008
72
08/17/2008
73
08/17/2008
74
08/17/2008
75
08/17/2008
76
08/17/2008
77
08/17/2008
78
08/17/2008
79
08/17/2008
90
08/17/2008
93
08/17/2008
94
08/17/2008
100
08/17/2008
101
08/17/2008
102
08/17/2008
103
08/17/2008
104
08/17/2008
105
08/17/2008
106
08/17/2008
109
08/17/2008
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-8089
SCHEM,MLB,K36C
SCH
CRITICAL
820-2496
PCBF,MLB,K36B
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
TITLE
DO NOT SCALE DRAWING
BOM OPTION
SCHEM,MLB,K36C
NONE
SIZE
THIRD ANGLE PROJECTION
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-8089
02
SHT
OF
109
U1000
J1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
FSB
J6950
64-Bit
800/1067/1333 MHz
DC/BATT
POWER SUPPLY
PG 13
PG 60
J3100,3200
MAIN
FSB INTERFACE
GPIOs
MEMORY
2 UDIMMs
DDR2-800MHZ
DIMM
PG 14
J5520
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH
POWER SENSE
PG 45
SPI
Boot ROM
J4501
J5601
FAN CONN AND CONTROL
SPI
SATA
PG 52
Conn
3GHZ.
PG 48,49
PG 20
PG 38
HD
NVIDIA
J4500
U4900
B,0
SATA
Conn
PG 38
ADC
BSB
Fan
Ser
J5100
MCP79
SATA
3GHZ.
Prt
SMC
LPC Conn
LPC
PG 19
ODD
Port80,serial
PG 41
PG 43
PG 18
U1400
J9001
PWR
LVDS
CONN
CTRL
LVDS OUT
PG 71
RGB OUT
J4810
DP OUT
J5800
J4501
J9001
TRACKPAD/
KEYBOARD
Bluetooth
J9401
IR
J4600,4601
CAMERA
HDMI OUT
PG 40
PG 40
PG 16
9
8
7
6
5
4
0
PCI-E
UP TO 20 LANES3
PG 17
USB
TMDS OUT
PG 19
PG 71
PG 40
PG 39
DVI OUT
(UP TO 12 DEVICES)
MINI DVI
CONN
EXTERNAL
USB
Connectors
PG 40
B
SMB
SMB
PG 20
CONN
RGMII
HDA
PCI
PG 44
DIMMs
(UP TO FOUR PORTS)

PG 17
PG 18
PG 20
U6200
Audio
U4100
Codec
PCI-E
FIREWIRE
PG 53
FW643E
PG 35
J4300
U6801
U6801
System Block Diagram
U6610,6620,6630
U3700
FW PORT
GB
Conn
E-NET
HEADPHONE
Line Out
Speaker
Amp
Amp
Amps
PG 55
PG 56
PG 57
SYNC_MASTER=K36B_MLB
SYNC_DATE=08/17/2008
88E1116
PG 37

PG 31

J3400
J3900
MINI PCI-E
J6800,6801,6802,6803
E-NET
AirPort
Conn
PG 28
Audio
SIZE
Conns
PG 33
PG 59
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-8089
02
OF
2
109
K36B POWER SYSTEM ARCHITECTURE

D6905
02
PPVIN_G3H_P3V42G3H
D6905
7A FUSE
PPVBAT_G3H_CHGR_REG
01
03
SHDN*
3.425V G3HOT
VIN LT3470 VOUT
U6990
PBUS_VSENSE
PP3V42_G3H_REG
02
22
VIN
AC
DCIN(16.5V)
ADAPTER
IN
CPUVTTS0_EN
(S0)
VIN
VOUT
SMC_BATT_ISENSE
01
02
VOUT
ISL9504B
CHGR_BGATE
P3V3S3_EN
U4900
RC
DELAY
U1400
DDRREG_EN
P60
04-1
ENTRIP1
PP1V05_S5_REG
P1V05_S5_PGOOD
VIN
EN1
SMC_PM_G2_EN
5V
(RT)
VOUT1
(S5)
ENTRIP2
3.3V
11-2 P5VLTS3_EN
PGOOD
RESET*
08
32
09
PP5VRT_S0_REG
PP5VLT_S3_REG
17
PP3V3_S5
06
(4A MAX CURRENT)
Q7910
TPS51125
U7200
05
PP4V6_AUDIO_ANALOG
OVT
(4A MAX CURRENT)

VOUT2
EN2
PWRGOOD
U1000
PP3V3_S5_REG
RC
DELAY
RC
DELAY
U6201
EN
VOUT
PG
02
Q7800
PCI_RESET0#
31
1.05V (S5)
P1V05_S5_EN
RC
DELAY
4.6V AUDIO
IN MAX8902A
TPS62510
PVIN U7750
SMC P16
11-3
CPU_RESET#
U1400
U2850
CPU
07
15
29
26
U7400
EN
11-1
MCP_PS_PWRGD PS_PWRGD
PPBUS_G3H
PM_SLP_S4_L
CPU_PWRGD
28
VR_PWRGOOD_DELAY
PGOOD
25
11
30
PPVCORE_S0_CPU_REG
(44A MAX CURRENT)
SMC_CPU_ISENSE
VR_ON
PPVBAT_G3H_CHGR_OUT
29-1
RSMRST*
SMC_CPU_VSENSE
CPU VCORE
IMVP_VR_ON
Q7050
BATT_POS_F
LPC_RESET_L
LPC_RESET0*
CPUPWRGD
VIN
MCP79
CPUVTTS0_PGOOD
J6950
3S2P
PP1V05_S0_FET
PGOOD
ISL6258A
U7000
SLP_S3#
09-1
PWRBTN*
R7955
TPS51117
U7600
U5403
SMC_DCIN_ISENSE
MCP79
PPCPUVTT_S0_REG
(8A MAX CURRENT)
VOUT
CPUVTT
ENABLES
PBUS SUPPLY/
BATTERY CHARGER
(9 TO 12.6V)
EN_PSV
(1.05V)
6A FUSE
SMC_RESET_L
Q5315
PPBUS_G3H
CHGR_EN
(S5)
04
SMC PWRGD
RN5VD30A-F
U5000
PP3V3_S3_FET
VREG3
13
11-1
P3V3S3_EN
P5V3V3_PGOOD
Q7930
18
PP3V3_S0_FET
15
PM_SLP_S3_L
RSMRST_OUT(P15)
PWRGD(P12)
09-1
RSMRST_PWRGD
Q3805
P3V3S0_EN
Q3810
P3V3_ENET_FET
1.5V (S0)
PM_WLAN_EN_L
PVIN
16
19-1
PP1V5_S0_FET
TPS62510
16-3
P1V5S0_EN
EN
U7740
SMC_ONOFF_L
99ms DLY
IMVP_VR_ON(P16)
RSMRST_IN(P13)
SMC_LRESET_L
PWR_BUTTON(P90)
P17(BTN_OUT)
VOUT
P3V3ENET_EN_L
P5V3V3_PGOOD
AP_PWR_EN
P1V5_S0_PGOOD
PP1V8_S0_FET
SMC_ADAPTER_EN
02
VIN
=DDRREG_EN
=DDRVTT_EN
P1V5S0_EN
RC
DELAY
MCPDDR_EN
RC
DELAY
CPUVTTS0_EN
RC
DELAY
16-3
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
16-3
PBUSVSENS_EN
(S0)
16-2
P5VRTS0_EN_L
(S0)
16-1
16-4
S3
14
1.8V
VOUT1
0.9V VOUT2
PP1V5_S0_FET
R5490
PP1V5_S0
MCPCORES0_EN
11-2 P5VLTS3_EN
VOUT2
EN2
5V (LT)
EN1
SLP_S4_L
SLP_S3_L
P5V_LT_S3_PGOOD
SMC_RESET_L
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
21
PPVCORE_S0_MCP_REG_R
R5490
PPVCORE_S0_MCP
PP3V3_S0
SEL
PP1V8_S0
ADJ1
PP1V05_S0
ADJ2 LTC2909
20
Power Block Diagram


(23A MAX CURRENT)

PP5VLT_S3_REG
PP5VLT_S3
U7870
12

VOUT1
SIZE
PP5V_LT_S3_PGOOD
PGOOD1
U7500
DRAWING NUMBER
SN0802043
02
PM_PWRBTN_L
SLP_S5_L(P95)
(4.5A MAX CURRENT)

VIN
25
RST*
PP0V9_S0_REG
(1A MAX CURRENT)
MCP_CORE
IMVP_VR_ON
(Q7901 & Q7971)
PP1V8_S3_REG
(12A MAX CURRENT)
TPS51116
U7300
16-2
16-2
MCPCORES0_EN
16-2
S5
SLP_S5_L
S0PGOOD_PWROK
S3 TO S0
FETS
RC
DELAY
21
PP1V8_S0_REG
FL7700
04-1
PM_SLP_S3_L
1.8V S0
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
PM_RSMRST_L
RST*
P1V5_S0_PGOOD
Q3805
10
SMC
24
ALL_SYS_PWRGD
MCPCORES0_PGOOD
APPLE INC.
PGOOD2
SCALE
SHT
NONE
REV.
051-8089
02
OF
3
109
PAGE_BORDER=TRUE
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
ALTERNATES OPTION
BOM OPTION
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
REF DES
COMMENTS:
128S0093
128S0218
ALL
ALTERNATE PER CYNDI
152S0694
152S0138
ALL
ALTERNATE PER CYNDI
152S0847
152S0586
ALL
ALTERNATE PER CYNDI
152S0874
152S0516
ALL
ALTERNATE PER CYNDI
152S0796
152S0685
ALL
ALTERNATE PER CYNDI
152S0778
152S0693
ALL
ALTERNATE PER CYNDI
157S0058
157S0055
ALL
ALTERNATE PER CYNDI
TABLE_5_ITEM
341S2420
IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK
U4900
CRITICAL
SMC_PROG
341S2418
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_PROG
BOM OPTION
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
341S2093
IC, CYPRESS, CY7C63833
U4800
CRITICAL
338S0654
IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127
U4100
CRITICAL
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
TABLE_ALT_ITEM
BOM OPTION
TABLE_5_ITEM
826-4393
[EEE:3TN]
LBL,P/N LABEL,PCB,28MMX6MM
TABLE_ALT_ITEM
CRITICAL
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_5_HEAD
337S3769
U1000
PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7750
CRITICAL
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
514-0665
CONN,RCPT,MINI-DVI,32P,R/A
J9401
CRITICAL
514-0666
CONN,RCPT,3.5MM AUDIO IN,R/A
J6750
CRITICAL
514-0667
CONN,RCPT,3.5MM AUDIO OUT,R/A
J6700
CRITICAL
514-0668
CONN,RCPT,RJ45,NO FILTER,8P
J3900
CRITICAL
514-0669
CONN,RCPT,USB,4P,MIDPLANE
J4600
CRITICAL
514-0669
CONN,RCPT,USB,4P,MIDPLANE
J4601
CRITICAL
TABLE_5_ITEM
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
338S0702
U1400
IC,GMCP,MCP79,35X35MM,BGA1437,B03
CRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
338S0694
IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P
U3700
CRITICAL
BOARD STACK-UP AND CONSTRUCTION

Top
2
3
4
5
6
7
8
9
10
11
BOTTOM
SIGNAL
GROUND
SIGNAL(High
SIGNAL(High
GROUND
POWER
POWER
GROUND
SIGNAL(High
SIGNAL(High
GROUND
SIGNAL
Speed)
Speed)
CONFIGURATION OPTIONS
Speed)
Speed)

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-8089
SCALE
SHT
NONE
02
OF
4
109
Revision History
*****2008/08/21*****
PAGE 61:
- U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC.
- U7500 PIN TONSEL LINK TO GND DIRECTLY.
PAGE 64:
- R7859 CHANGE TO 100 OHM.
- R7879 CHANGE TO 100K OHM.
PAGE 65:
- DELETE 1.05V S0 FET CIRCUIT.
PAGE 57:
- R7011 CHANGE TO 9.31K OHM, 1%
*****2008/08/22*****
PAGE 7:
- ADD SMC_EXCARD_PWR_EN TEST_POINT
PAGE 8:
- ADD =PP3V42_G3H_RTC_D LINK TO =PP3V42_G3H_REG
PAGE 14:
- R1410 CHANGE TO 49.9 OHM
- CHANGE R1440 TO 150_5% AND NO STUFF
PAGE 26:
- R2872 CHANGE TO 0OHM
- RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION
- MCP S0 PWRGD FOLLOW M97 DESIGN
PAGE 29:
- PULL R3240 DOWN TO GND. PULL R3241 HIGH
PAGE 32,33,34
- FOLLOW M97 DESIGN
PAGE 39:
- D4600/D4601/PIN-6 CONNECT TO USB VBUS (FOLLOW M97D)
PAGE 44:
- R5270/R5271 = 1K (FOLLOW M97D)
- R5280/R5281 = 1K (FOLLOW M97D)
PAGE 68:
- CHANGE C9411, C9412 TO 220PF
- CHANGE R9462, R9463 TO 2.7KOHM
- ADD C9480 0.1UF_16V_0402 FROM GND_CHASSIS_TMDS_DOWN TO GND
- CHANGE R9460,R9461 TO 0OHM,
- CHANG C9442 AND C9443 TO 47PF
*****2008/08/23*****
MODIFY ALL NOSTUFF TO NO STUFF.
PAGE 6:
- REMOVE ETHERNET CIRCUIT.
PAGE 8:
- ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5
- ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET.
PAGE 9:
- ADD =RTL8211_ENSWRE LINK TO GND.
- ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG.
- ADD =RTL8211_REGOUT LINK TO NC_RTL8211_REGOUT.
- =P3V3ENET_EN_L LINK TO PM_SLP_RMGT_L
- =P1V05ENET_EN LINK TO PM_SLP_RMGT_L
PAGE 10:
- CHANGE XDP_TDO_CONN TO XDP_TDO
PAGE 13:
- XDP FOLLOW M98 DESIGN. CONNECTOR FROM 516S0625 CHANGE TO 998-1571.
PLAGE 23:
- DELETE R2400~R2413 FOR MCP A01 VERSION.
PAGE 31:
- REMOVE R3400, R3401
- L3401 FROM NO STUFF CHANGE TO STUFF.
PAGE 39
- DELETE R4699.
- R4690 FROM NO STUFF CHANGE TO STUFF.
PAGE 41:
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE
PAGE 46:
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE
- R5417 ADD BOM OPTION FOR NO STUFF
- R5416 ADD BOM OPTION FOR NO STUFF
PAGE 50:
- ADD C5926 (10UF,20%.0603) TO =PP3V3_S3_SMS
PAGE 63:
- REMOVE USB_PWR_EN_S3
PAGE 66:
- REMOVE R9010, R9011
*****2008/08/24*****
PAGE 6:
- R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF.
PAGE 13:
- XDP FOLLOW M97 DESIGN. CONNECTOR FROM 998-1571 CHANGE TO 516S0625.
PAGE 18:
- R1860 AND R1861 CHANGE TO PAGE 68.
PAGE 25:
- C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1)
- C2516-C2517 FROM 138S0578(402) CHANGE TO 138S0614(402-1)
PAG3 35:
- R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402)
PAGE 58:
- C7281, C7241, C7272 FROM 138S0555(603) CHANGE TO 138S0615(603-1)
- C7280, C7240 FROM 128S0092(POLY) CHANGE TO 128S0128(POLY-TANT)
- C7291, C7292, C7252, C7251 FROM 128S0115(POLY,CASE-B2) CHANGE TO
128S0222(POLY,CASE-B2-SM)
- Q7260, Q7261 FROM 376S0512 CHANGE TO 376S0652 (H-F)
PAGE 59:
- Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F)
- Q7321 FROM 376S0511 CHANGE TO 376S0651 (H-F)
- C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM)
- C7343 FROM 128S0073 CHANGE TO 128S0233.
PAGE 60:
- XW7400 ADD BOMOPTION OMIT.
- Q7400, Q7402 FROM 376S0472 CHANGE TO 376S0617.
PAGE 61:
- L7500 FROM 152S0869 CHANGE TO 152S0685.
- Q7500 FROM 376S0512 CHANGE TO 376S0652.
PAGE 62:
- Q7620 FROM 376S0512 CHANGE TO 376S0652.
*****2008/08/25*****
CHANGE CSA BASE ON WILLS SUGGESTION.
PAGE 9:
- ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES.
PAGE 18:
- NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L.
- ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L
PAGE 19:
- DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979
(FOLLOW M97 DESIGN).
- NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN
- NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME
- NET DPMUX_SEL_IG_L SYNC M97 NETNAME
PAGE 28:
- REMOVE NET DIMM_OVERTEMPA_L
PAGE 29:
- REMOVE NET DIMM_OVERTEMPA_L
PAGE 42:
- ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN
- ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L
- ADD ALS_GAIN TO NC_ALS_GAIN
- ADD ESTARLDO_EN TO NC_ESTARLDO_EN
- ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID
- ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED
- ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND.
- ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND.
PAGE 43:
- R5142 CHANGE TO NO STUFF.
PAGE 46:
- R5416 CHANGE TO 4.53K AND DELETE BOM OPTION.
PAGE 57:
- NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF
- NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE
PAGE :
- REMOVE R7884 AND C7884
PAGE 66:
- REMOVE J9001 PIN 20 AND PIN21 NET.
*****2008/09/02*****
PAGE 45:
- CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719
*****2008/09/27*****
PAGE 9:
- ADD STANDOFF 860-0964 X 4
PAGE 29:
- REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911
PAGE 66:
- C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT
- C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT
PAGE 68:
- C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT
PAGE 72:
- R7272 CHANGE FROM 57.6K 1%(114s0389) TO 75K 1%(114s0399)
*****2008/10/31*****
PAGE 41:
- U4100 CHANGE FROM 338S0523 TO 338S0654
*****2008/11/01*****
PAGE 4:
- BOM change U1400 CHANGE FROM 338S0678 TO 338S0702
*****2008/11/05*****
PAGE 62:
- C6210 CHANGE FROM 127S0062 TO 127S0108
PAGE 68:
- C6832, C6833 CHANGE FROM 127S0062 TO 127S0108
PAGE 45:
- DELETE L4502, NET SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
- L4501 / Fl4520 / FL4525 CHANGE FROM 155S0303 TO 155S0371
PAGE 102:
- DELETE PHYSICAL/SPACING SETTING OF SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
*****2008/11/06*****
- R7417 CHANGE FROM 5.36K(114S0289) TO 4.42K(114S0280)
*****2008/11/12*****
*****2008/11/19*****
- J6950 CHANGE FROM 516S0620 TO 516S0735
- J9401 CHANGE FROM 514-0517 TO 514-0665
- J6750 CHANGE FROM 514-0519 TO 514-0666
- J6700 CHANGE FROM 514-0521 TO 514-0667
- J3900 CHANGE FROM 514-0523 TO 514-0668
- J4600, J4601 CHANGE FROM 514-0527 TO 514-0669
*****2008/11/26*****
- PAGE 61 NOTE : CORRECT REFERENCE TO R5164 AND R5144
- J3400 CHANGE TO 516S0729
*****2008/12/12*****
- R5144 and R5164 changed to 10K 5% 0402 (116S0090)
*****2008/12/17*****
- U4900 symbol update
*****2008/12/20*****
- R5156, R5157, R5158 change from 0 to 33 ohm, 5%, 0402(116s0030)
*****2008/10/20*****
PAGE 29:
- ADD R2903/R2905 BOMOTION AND CHANGE VALUE TO 200 OHM
PAGE 50:
- REMOVE ALT TABLE
PAGE 74:
- REMOVE ALT TABLE
PAGE 94:
- REMOVE K36 BOM OPTION TABLE AND ALT TABLE
*****2008/10/22*****
PAGE 12:
- C1200 ~ C1219 CHANGE TO 138S0580
PAGE 28:
- C2870 CHANGE TO 138S0614
PAGE 37:
- ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE
- TP_RTL8211_CLK125 CHANGE TO RTL8211_CLK125
PAGE 48:
- C4803 CHANGE TO 138S0614
PAGE 66:
- C6605 CHANGE TO HF APN 128S0221
PAGE 70:
- C7040/C7041/C7047 CHANGE TO 138S0614
PAGE 90:
- L9002 CHANGE TO 116S0004(0ohm,5%,0402)
- C9003 CHANGE TO 116S0004(0ohm,5%,0402)
*****2008/10/24*****
PAGE 19:
- R1950/R1951/R1952/1953 CHANGE TO 116s0004 (0 OHM,5%,0402)
PAGE 28:
- R2825/R2826 CHANGE TO 116s0004 (0 OHM,5%,0402)
PAGE 34:
- J3400 516S0635 CHANGE TO HF APN 516S0729
PAGE 52:
- ADD C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 131S1104 (22pF,5%,0402) NO STUFF
- TEXT "ALS" CHANGE TO "MINI-PCIE"
- I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL
- I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA
PAGE 67:
- J6700 514-0604 CHANGE TO HF APN 514-0521
- J6750 514-0603 CHANGE TO HF APN 514-0519
PAGE 69:
- J6950 516S0620 CHANGE TO HF APN 516S0735
02
*****2008/10/25*****
PAGE 52:
- STUFF C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281
*****2008/10/28*****
PAGE 34:
- J3400 516S0729 CHANGE TO 516S0635

*****2008/10/30*****
PAGE 69:
- J6950 516S0735 CHANGE TO 516S0620

SIZE
DRAWING NUMBER
D
APPLE INC.
NOTE: All page numbers are .csa, not PDF.
REV.
051-8089
SCALE
SHT
NONE
See page 1 for .csa -> PDF mapping.

02
OF
5
109
D
1.05V TO 3.3V LEVEL TRANSLATOR (K36B: ON ICT FIXTURE)
=PP3V3_S0_XDP
13 8
To XDP connector
and/or level translator
=PP1V05_S0_CPU
13 12 11 10 8
U1000
CPU
From XDP connector

JTAG_ALLDEV
1
C0601
JTAG_ALLDEV
1
0.1UF
C0602
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
69 13 10 7 6
IN
69 13 10 7
IN
69 13 10 7 6
IN
69 13 10 7 6
IN
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
XDP
R0603
69 10
XDP_TDO
XDP_TDO_CONN
5%
1/16W
MF-LF
402
JTAG_ALLDEV
OUT
7 13
XDP connector
R06011
1
11
10K
5%
1/16W
MF-LF
402 2
From XDP connector

or via level translator
VCCA VCCB
U0600
U1400
MCP
NLSV4T244
69 13 10 7 6
XDP_TCK
NO STUFF
R06021
0
5%
1/16W
MF-LF
402 2
69 13 10 7 6
69 13 10 7 6
XDP_TMS
XDP_TRST_L
2
3
4
5
UQFN
A1
A2
A3
JTAG_ALLDEV
A4
B1
B2
B3
B4
JTAG_MCP_TCK MAKE_BASE=TRUE 7
JTAG_MCP_TDI MAKE_BASE=TRUE 7
JTAG_MCP_TMS MAKE_BASE=TRUE 7
JTAG_MCP_TRST_L
7
10
9
8
7
13 21
XDP
13 21
R0604
13 21
13 21
21
JTAG_MCP_TDO
MAKE_BASE=TRUE
JTAG_LVL_TRANS_EN_L
12
JTAG_MCP_TDO_CONN
5%
1/16W
MF-LF
402
OE*
7 13
XDP connector
GND
OUT
JTAG Scan Chain
SYNC_DATE=08/17//2008

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
6
109
Functional Test Points

# J4501 SATA HD System LED and IR
#J5601 Fan Connectors
TRUE
TRUE
TRUE
TRUE
I12
I15
I16
I157
PP5VRT_S0
FAN_RT_PWM
FAN_RT_TACH
7 8
I284
48
I283
I282
48
GND
I281
I280
#J6950 Battery/Lid Connector
I279
I290
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I292
TRUE
I285
I286
I288
I287
I289
I291
SMC_BS_ALRT_L_F
SMBUS_BATT_SCL_F
SMBUS_BATT_SDA_F
PPVBAT_G3H_CONN_F
SMC_LID_F
GND_SMC_LID_F
56
I278
56
I277
56
I276
56
TRUE
TRUE
TRUE
I274
I275
56
I273
I272
I293
I295
I296
I298
I299
I269
56
I270
56
Need 2 TP
I267
#J9000 INVERTER Connector
I268
TRUE
TRUE
TRUE
TRUE
I297
Need 2 TP
I271
I266
PPBUS_ALL_INV_CONN Need 2 TP 66
INV_GND
66
PP5V_INV_F
66
INV_BKLIGHT_PWM_L Need 4 TP 66
I264
I265
I263
I262
I261
#J9001 LCD + CAMERA CONNECTOR
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I300
I301
I303
I302
I305
I304
I306
I307
I308
I309
I310
I311
I313
I312
I315
I314
PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
LVDS_IG_DDC_CLK
I259
I260
66
66
I316
I317
I318
I320
LVDS_IG_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_CLK_F_N
LVDS_IG_A_CLK_F_P
USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_N
PP5V_S3_CAMERA_F
GND
18 66
I258
18 66 71
I256
18 66 71
I257
18 66 71
I255
18 66 71
I254
18 66 71
I253
18 66 71
I252
66
I251
66
I250
66 72
I248
66 72
I249
I246
66
I247
MIC_LO_CONN
MIC_HI_CONN
MIC_SHLD_CONN
I245
I244
54
I243
54
I242
54 55
I240
I241
SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
I239
53 54
I237
53 54
I235
#J6703 Right SUB SPEAKER CONNECTOR

TRUE
TRUE
TRUE
TRUE
I321
I322
I323
I324
SPKRCONN_SUB_P_OUT
SPKRCONN_SUB_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT
I236
53 54
I234
53 54
I233
53 54
I232
53 54
I230
I231
# J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS

I326
I325
I328
I327
I329
I330
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I198
TPAD_GND_F
CONN_TPAD_ONOFF_FLTR_L
CONN_TPAD_USB_P
CONN_TPAD_USB_N
SMC_LID_LC
PP5V_S3_TPAD_F
I196
71
I197
38
I195
I193
40
I194
I192
I191
I190
I188
PCIE_WAKE_L
17 31
I189
MINI_CLKREQ_L
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
PCIE_MINI_D2R_N
17 31
17 31 71
I186
I187
17 31 71
I185
17 31 71
I183
PCIE_MINI_D2R_P
PCIE_MINI_R2D_N
17 31 71
31 71
PCIE_MINI_R2D_P
31
PP3V3_WLAN
Need 4 TP 31
PP1V5_S0_R
Need 3 TP 7
MINI_RESET
31
PP3V3_S3_AIRPORT_CONN
31
I2C_MINI_PCIE_SCL
31
I2C_MINI_PCIE_SDA
31
USB2_AIRPORT_N
31
USB2_AIRPORT_P
31
Need 6 TP
GND
71
I184
I182
I181
I180
I178
I179
I177
44
I175
44
I176
72
I173
72
I174
I172
I171
I170
I238
TRUE
TRUE
71
71
18 66
#J6702 Left SPEAKER CONNECTOR

I319
I199
# Other Func Test Points
# J6701 MIC CONNECTOR

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
#J1300
71
#J3400 Airport
56
PP3V42_G3H_LIDSWITCH_F
Need 6 TP
GND
PP18V5_DCIN_FUSE
ADAPTER_SENSE
GND
SATA_HDD_R2D_P
38
SATA_HDD_R2D_N
38
SATA_HDD_D2R_C_N
38
SATA_HDD_D2R_C_P
38
PP5V_S0_HDD_FLT Need 4 TP
SYS_LED_ANODE_L
38
IR_RX_OUT
38
PP5V_S3_IR_CONN
38
Need 4 TP
GND
56
#J6900 MagSafe DC Power Jack

I294
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I229
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
ALL_SYS_PWRGD
PPVCORE_S0_CPU
PPCPUVTT_S0
PPVCORE_S0_MCP_R
PPVCORE_S0_MCP
PP0V9_S0
PP1V05_S0
PP1V5_S0_R
PP1V8_S0
PP1V8_S0_R
PP1V05_S0_MCP_PEX_AVDD
PP1V05_S0
PP1V05_S0_MCP_SATA_AVDD
PP1V05_S0
PP5VRT_S0
PP3V3_S0
PP1V0_FW
PP1V8_S3
PP3V3_S3
PP5VLT_S3
PPVTT_S3_DDR_BUF
PP1V05_S5_REG
PP3V3_S5
PP3V42_G3H
PP18V5_G3H
PPBUS_G3H
PPBUS_G3H_CPU_ISNS
PP3V3_ENET_PHY
PP1V2R1V05_ENET
PPVP_FW
26 41 64
I169
I168
7 8
I167
I165
I166
I163
7 8
I164
7 8
I162
I161
I160
8 24
I159
7 8
I158
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
# J5100 LPC+SPI Connector
XDP
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP_PWRGD
XDP_OBS20
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
XDP_TCK
PPCPUVTT_S0
PP3V3_S0
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
JTAG_MCP_TDI
JTAG_MCP_TMS
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
FSB_CLK_ITP_P
FSB_CLK_ITP_N
XDP_CPURST_L
I227
10 13 69
I228
10 13 69
I226
10 13 69
I225
10 13 69
I224
10 13 69
I223
13
I222
13
I221
13
I219
13
I220
13
I217
13
I218
13
I216
13
I215
13 19
I214
6 13 21
I213
13 21 44 72
I212
13 21 44 72
I211
6 10 13 69
I209
7 8
I210
7 8
I207
6 13
I208
6 13 21
I206
13 19 72
I203
13 19 72
I204
13 19 72
I205
13 19 72
I202
6 13 21
I201
6 13 21
I200
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V42_G3H
PP5VRT_S0
LPC_AD<0>
LPC_AD<1>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
7 8
7 8
19 41 43 72
19 41 43 72
43
43
19 41 43 72
19 41 43
41 42 43
26 43
SMC_TDO
41 42 43
SMC_TRST_L
SMC_MD1
SMC_TX_L
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
41 43
41 43
39 41 42 43
26 43 72
19 41 43 72
19 41 43 72
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
43
43
43
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
19 41 43
19 41 43
41 42 43
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
41 42 43
41 42 43
41 43
39 41 42 43
LPCPLUS_GPIO
18 43
Need 2 TP
GND
13 19 72
13 19 72
13 19 72
13 19 72
13 14 69
13 14 69
13 69
XDP_DBRESET_L
XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS
GND
10 13 69
10 13 26
6 13
6 10 13 69
6 10 13 69
6 10 13 69
Need 8 TP
8 24
7 8
7 8
7 8
8
8
8
8
8
8
8
7 8
8
8
8
8
8
8
49
49
49 72
49 72
49
49
#J5520 CPU/MCP Thermal Sensor

I331
I332
I334
I333
TRUE
TRUE
TRUE
TRUE
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
MCPTHMSNS_D2_P
47
47
47
MCPTHMSNS_D2_N
47
#J4810 BLUETOOTH
I335
I336
I337
I338
TRUE
TRUE
TRUE
TRUE
PP3V3_S3_BT_F_CONN
USB2_BT_F_N_CONN
40
40 72
USB2_BT_F_P_CONN
GND_BT_F_CONN
40 72
FUNC TEST
40
#J4500 SATA ODD

I340
I339
I342
I341
I343
I345
I344
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-8089
SCALE
SHT
NONE
SATA_ODD_R2D_UF_P
38 71
SATA_ODD_R2D_UF_N
38 71
SATA_ODD_D2R_C_N
38 71
SATA_ODD_D2R_C_P
38 71
PP3V3_S0
Need 4 TP 7 8
SMC_ODD_DETECT
38 41
GND
Need 6 TP
02
OF
7
109
"S0,S0M" RAILS
"G3H" RAILS
"S3" RAILS
56
=PPVCORE_S0_CPU_REG
60
(CPU VCORE PWR)
PPVCORE_S0_CPU
58
=PP5VRT_S0_REG
45
43
48
PPCPUVTT_S0
=PP5V_S0_ODD
=PP5V_S0_TMDS
=PP5V_S0_LCD
=PP5V_S0_CPUVTTS0
=PP5V_S0_AUDIO
=PP5V_S0_AUDIO_AMP
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_SMC_LS
6 10 11 12 13
14 22 24
=PP1V8_S3_P1V8S0FET
65
=PP1V8_S3_MEM
28 29
60
38
65 21
=PP3V3_S3_FET
PP3V3_S3
62
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_AIRPORT_AUX
=PP3V3_S3_BT
=PP3V3_S3_SMS
52 55
53
42
61
=PPMCPCORE_S0_REG
=PPVCORE_S0_MCP_REG_R
(MCP VCORE REG. OUTPUT)
(MCP VCORE AFTER SENSE RES)
C
59
=PP0V9_S0_REG
PPVCORE_S0_MCP_R
=PP3V3_S0_FET
PP3V3_S0
44
56
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
65
=PP1V05_S0_FET
65
30
PP1V05_S0
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD
=PP1V05_S0_VMON
63
=PP1V5_S0_FET
PP1V5_S0_R
=PP1V5_S0_CPU
=PP1V5_S0_AIRPORT
=PP1V8_S0
(DDR PWR AFTER SENSE RES.)
46
PP1V8_S0
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8R1V5_S0_MCP_MEM
=PP1V8_S0_FET
(DDR PWR REG. OUTPUT)
65
PP1V8_S0_R
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_VMON
=PP1V8_S0_FET_R
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP5VR3V3_S0_MCPCOREISNS
=PPSPD_S0_MEM
=PP3V3_S0_PWRCTL
=PP3V3_S0_VMON
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_CPUVTTISNS
=PP3V3_FW_P1V0FW
=PP3V3_FW_PHY
=PP3V3_FW_FWPHY
8 24
18 25
64
11 12
31
31
44
44
44
48
52 54 55
50
MAKE_BASE=TRUE
127 mA (A01)
57
PPBUS_G3H
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_DVDD0
61
61
59
58
58
61
45
66
36
46
66
65
46
PPBUS_G3H_CPU_ISNS
=PPBUS_G3H_CPU_ISNS
VOLTAGE=12.6V
MAKE_BASE=TRUE
65
42
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
49
59
62
60
"ENET" RAILS
25
24
33
=PP3V3_ENET_FET
PP3V3_ENET_PHY
VOLTAGE=3.3V
MAKE_BASE=TRUE
21 24
42
=PP3V3_ENET_MCP_RMGT
47
47
59 27
=PPVTT_S3_DDR_BUF
PPVTT_S3_DDR_BUF
28 29
=PP3V3_ENET_PHY
VOLTAGE=0.9V
MAKE_BASE=TRUE
46
33
=PP1V05_ENET_FET
"S5" RAILS
46
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_PHY 32
63
37
35 37
=PP1V05_S5_REG
16 24
VOLTAGE=1.05V
MAKE_BASE=TRUE
64
46
18 24
32
PP1V2R1V05_ENET
64
PP1V05_S5_REG
24
18 24
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET
36
PPVP_FW
=PPBUS_S5_FW_FET
VOLTAGE=12.6V
MAKE_BASE=TRUE
22 24
MIN_LINK_WIDTH=0.4 MM
=PPVP_FW_PHY_CPS_FET
33
=PPVP_FW_PORT1
37
37
64
46
58
=PP3V3_S5_REG
=PP1V0_FW_REG
PP1V0_FW
=PP1V0_FW_FWPHY
PP3V3_S5
VOLTAGE=3.3V
MAKE_BASE=TRUE
18 25
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_PWRCTL
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P1V05S5
=PP3V3_FW_LATEVG
35
17
206 mA (A01)
17
17
57 mA (A01)
17
18 20
43 51
66
22 24
26
33
64
33
65
65
Power Aliases
63
36 37
=PP1V05_S0_MCP_SATA_AVDD0
20
=PP1V05_S0_MCP_SATA_DVDD0
20
20
127 mA (A01)
127 mA (A01)
24 8
=PP18V5_G3H_CHGR
38 40
206 mA (A01)
24 7
39
18 19 21
MAKE_BASE=TRUE
26
=PPVIN_S0_MCPCORES0
=PPVIN_S0_MCPREG_VIN
=PPVIN_S5_1V8S3_0V9S0
=PPVIN_S5_3V3S5
=PPVIN_S0_5VRTS0
=PPVIN_S3_5VLTS3
=PPBUS_G3HRS5
=PPBUS_S5_INV
=PPBUS_S5_FWPWRSW
=PPBUS_G3H_CPU_ISNS_R
VOLTAGE=1.05V
MAKE_BASE=TRUE
PEX & SATA AVDD/DVDD aliases
24 8
=PPBUS_G3H
66
VOLTAGE=1.0V
MAKE_BASE=TRUE
206 mA (A01)
41 42 50
43
40
=PP5V_S3_EXTUSB
=PP5V_S3_IR
=PP5V_S3_CAMERA
=PP5V_S3_VTTCLAMP
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD
=PP5V_S3_1V8S3_0V9S0
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
63
63
46
PP18V5_G3H
25
68
PP5VLT_S3
38
"FW" RAILS
24 7
56
VOLTAGE=18.5V
MAKE_BASE=TRUE
31
VOLTAGE=5V
MAKE_BASE=TRUE
25
=PP3V3_S0_TMDS
24
=PP5VLT_S3_REG
21 22 24
60
=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_HDCPROM
24
61
6 13
=PP3V3_S0_IMVP
8 24
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP18V5_DCIN_CONN
27
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP0V9_S3M_MEM_TERM
39
59
45
PPVCORE_S0_MCP
=PPVTT_S0_VTTCLAMP
57
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP0V9_S0
64
44
VOLTAGE=1.05V
MAKE_BASE=TRUE
65 63
=PPVCORE_S0_MCP
44
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPVCORE_S0_MCP_VSENSE
24 22
61 46
42
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_RTC_D
VOLTAGE=3.3V
MAKE_BASE=TRUE
68
66
=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_BMON_ISNS
57
46
PP3V42_G3H
VOLTAGE=3.42V
MAKE_BASE=TRUE
38
=PP5V_S0_CPU_IMVP
=PPCPUVTT_S0_REG
59
PP1V8_S3
=PP3V42_G3H_REG
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT
11 12
D
65 62
=PP1V8_S3_REG
VOLTAGE=5V
MAKE_BASE=TRUE
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VSENSE
PP5VRT_S0
20
43 mA (A01)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
8
109
LVDS ALIASES
PCI-E ALIASES
17
UNUSED GPU LANES

=PEG_D2R_N<15:0>
NC_PEG_D2R_N<15:0>
NO_TEST=TRUE
=PEG_D2R_P<15:0>
NC_PEG_D2R_P<15:0>
17
=PEG_R2D_C_N<15:0>
NC_PEG_R2D_C_N<15:0>
NO_TEST=TRUE
71 18
LVDS_IG_A_DATA_N<3>
NC_LVDS_IG_A_DATA_N3
LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLKP
NO_TEST=TRUE
NC_PEG_R2D_C_P<15:0>
17
PEG_PRSNT_L
TP_PEG_PRSNT_L
17
PEG_CLKREQ_L
NC_LVDS_IG_B_CLKN
71 18
LVDS_IG_B_DATA_P<3:0>
NC_LVDS_IG_B_DATA_P<3:0>
71 18
LVDS_IG_B_DATA_N<3:0>
71 17
PEG_CLK100M_P
PCIE_EXCARD_D2R_N
17
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_PRSNT_L
17
EXCARD_CLKREQ_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATA_N<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
71 17
71 17
NO_TEST=TRUE
TP_PEG_CLKREQ_L
PCIE_EXCARD_D2R_P
71 17
LVDS_IG_B_CLK_N
MAKE_BASE=TRUE
71 17
MAKE_BASE=TRUE
71 18
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
=PEG_R2D_C_P<15:0>
MAKE_BASE=TRUE
71 18
MAKE_BASE=TRUE
17
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PEG_CLK100MP
71 17
PCIE_CLK100M_EXCARD_P
71 17
PCIE_CLK100M_EXCARD_N
PEG_CLK100M_N
EXTGPU_PWR_EN
TP_EXTGPU_PWR_EN
EXTGPU_RESET_L
TP_EXTGPU_RESET_L
MAKE_BASE=TRUE
14
CPU_PECI_MCP
19
GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
19
GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
ETHERNET ALIASES
33
33
32
MCP_MEM_RESET_L
=PP3V3_ENET_PHY_VDDREG
=RTL8211_REGOUT
21
72 20
72 20
72 20
UNUSED ADDRESS PINS

28
29
MEM_A_A<15>
MEM_B_A<15>
72 20
TP_MEM_A_A15
TP_MEM_B_A15
MAKE_BASE=TRUE
266
133
200
(166)
333
100
(400)
(RSVD)
HDA PULL-DOWN
AUD_IPHS_SWITCH_EN
19
R0977
20K
TP_USB_EXTCP
TP_USB_EXTCN
TP_USB_EXTDP
TP_USB_EXTDN
TP_USB_EXCARDP
TP_USB_EXCARDN
31
=USB_MINI_P
USB_MINI_P
31
=USB_MINI_N
USB_MINI_N
5%
1/16W
MF-LF
MAKE_BASE=TRUE
2 402
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LAN ALIASES
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MCP_MII_RXER
MCP_MII_COL
MCP_MII_CRS
18
20 72
MAKE_BASE=TRUE
18
20 72
MAKE_BASE=TRUE
18
R0930
47K
R0932
47K
5%
49
=USB2_TPAD_P
USB_TPAD_P
49
=USB2_TPAD_N
USB_TPAD_N
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
TRACKPAD(WELLSPRING)
5%
R0931
47K
=RTL8211_ENSWREG
20 72
MAKE_BASE=TRUE
20 72
MAKE_BASE=TRUE
DP HOTPLUG PULL-DOWN
BLUETOOTH
FSB MHZ
0
1
0
1
0
1
0
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
32
TP_MCP_MEM_RESET_L
SO-DIMM ALIASES
PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
32
72 20
MAKE_BASE=TRUE
MAKE_BASE=TRUE
14
OUT
0
0
1
1
0
0
1
1
MAKE_BASE=TRUE
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_EXCARD_P
USB_EXCARD_N
72 20
MAKE_BASE=TRUE
16
=MCP_BSEL<0:2>
UNUSED USB PORTS

MAKE_BASE=TRUE
PM_SLP_RMGT_L
CPU_BSEL<0:2>
MAKE_BASE=TRUE
0
0
0
0
1
1
1
1
TP_PCIE_CLK100M_EXCARDP
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARDN
USB ALIASES
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=P3V3ENET_EN
=P1V05ENET_EN
IN
MISC NC MCP79 ALIASES
MAKE_BASE=TRUE
17
69 10
MAKE_BASE=TRUE
TP_PEG_CLK100MN
17
BSEL<2..0>
TP_PCIE_EXCARD_D2RP
MAKE_BASE=TRUE
TP_PCIE_EXCARD_D2RN
MAKE_BASE=TRUE
TP_PCIE_EXCARD_R2D_CP
MAKE_BASE=TRUE
TP_PCIE_EXCARD_R2D_CN
MAKE_BASE=TRUE
TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
TP_EXCARD_CLKREQ_L
MAKE_BASE=TRUE
71 17
CPU FSB FREQUENCY STRAPS
UNUSED EXPRESS CARD LANE
UNUSED LVDS SIGNALS

LVDS_IG_A_DATA_P<3>
NC_LVDS_IG_A_DATA_P3
MAKE_BASE=TRUE
17
NO_TEST=TRUE
71 18
40
=USB2_BT_P
USB_BT_P
40
=USB2_BT_N
USB_BT_N
DP_HOTPLUG_DET
18
20 72
MAKE_BASE=TRUE
R0940
20K
20 72
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
FW PULL-DOWN
CPU HEATSINK STANDOFF SCREW HOLE
Screw Holes
OMIT
OMIT
Z0903
17
Z0904
STDOFF-4.2OD3.95H-5.52R3.37-6B
PCIE_FW_PRSNT_L
STDOFF-4.2OD3.95H-5.52R3.37-7SQB
R0955
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND
Z0906 OMIT
5R2P3-7SQBNP
1
56
SATA,LVDS CONNECTOR CHASSIS GND
=GND_CHASSIS_AUDIO_JACK
28 =GND_CHASSIS_DIPDIMM_LEFT
55 =GND_CHASSIS_AUDIO_MIC
66 =GND_CHASSIS_LVDS
28 =GND_CHASSIS_DIPDIMM_CENTER
29 =GND_CHASSIS_DIPDIMM_RIGHT
34 =GND_CHASSIS_RJ45
68 =GND_CHASSIS_TMDS_UPPER
37 =GND_CHASSIS_FW_UPPER
68 =GND_CHASSIS_TMDS_DOWN
37 =GND_CHASSIS_FW_DOWN
OMIT
6P5R2P6-7SQB
1
29
DIP DIMM CONNECTOR CHASSIS GND

OMIT
Z0910
5R2P3-7SQB
OMIT
OMIT
=GND_BATT_CHGND
54
Z0907
5%
1/16W
MF-LF
2 402
Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

FOR LAYOUT PLACEMENT
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL
STDOFF-4.5OD3.95H-1.1-3.2-TH
STDOFF-4.5OD3.95H-1.1-3.2-TH
R0920
MCP_SPKR
21
SMC_MCP_SAFE_MODE
IN
41
5%
1/16W
MF-LF
402
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
R09411
1
124
OMIT
5R2P3-7SQBNP
1
1%
1/16W
MF-LF
402
OMIT
Z0901
MCP_SAFE_MODE SIGNAL TO SUPPORT

ROM FAILURE OVERRIDE
Z0921
Z0905
Z0912
18 71
C0940
0.01UF
10%
16V
2 CERM
402
STDOFF-4.2OD2.15H-1.2-3.2-TH
DIP DIMM CONNECTOR CHASSIS GND
18 71
OMIT
Z0909
5R2P3-7SQB
1
55 54 53 52
DCIN CONNECTOR CHASSIS GND
OMIT
Z0911
5R2P3-7B
OMIT
Z0902
7X7R2P3-5B
GND_AUDIO_CODEC
MAKE_BASE=TRUE
XW0901
SM
Z0913
STDOFF-4.2OD3.95H-5.52R3.37-6B
=GND_AUDIO_CODEC
OMIT
53
=GND_AUDIO_AMP
GND_AUDIO_AMP
MAKE_BASE=TRUE
XW0902
SM
I/O CONNECTOR CHASSIS GND

OMIT
Z0908
5P0R2P3-7BLB
1
SIGNAL ALIAS
(EMI PAD FOR INVERTER GONNECTOR)
QTY
DESCRIPTION
CRITICAL
BOM OPTION
66
INVT_CHGND
TABLE_5_ITEM
860-0964
THERMAL STANDOFF
Z0903,Z0904,Z0905,Z0921
STANDOFF
860-0723
STANDOFF WIRELESS
Z0912
STANDOFF
860-0749
STANDOFF W/THRU HOLES,WIRELESS
Z0913
STANDOFF
TABLE_5_HEAD
PART#
ZS0920
EMI-SPRING

CLIP-SM-M42
TABLE_5_ITEM

TABLE_5_ITEM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
9
109
OMIT
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
69 14
BI
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
69 14
69 14
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
IN CPU_A20M_L
OUT CPU_FERR_L
IN CPU_IGNNE_L
69 14
IN
69 14
IN
69 14
IN
69 14
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
DEFER*
DRDY*
DBSY*
BR0*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
H5
F21
E1
FSB_BREQ0_L
F1
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
D20
F3
F4
G3
G2
HIT*
HITM*
G6
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
AD4
E4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
69
R1000
6 8 11 12 13
54.9
1%
1/16W
MF-LF
402
14 69
B3
CPU_IERR_L
CPU_INIT_L
IERR*
INIT*
=PP1V05_S0_CPU
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
14 69
14 69
IN
13 14 69
IN
14 69
IN
14 69
IN
14 69
IN
14 69
BI
14 69
BI
14 69
BI
7 13 69
OMIT
BI
7 13 69
BI
7 13 69
BI
7 13 69
BI
R1001
1%
1/16W
MF-LF
402
7 13 69
THERMTRIP*
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
BI
BI
BI
6 10 69
69 14
IN
6 7 10 13 69
69 14
BI
IN
6 7 10 13 69
69 14
BI
69 14
BI
OUT
7 13 26
R1002 1
B25
OUT
47
C7
PM_THRMTRIP_L
OUT
14 42 69
69 14
OUT
14 42 60 69
IN
IN
14 69
BI
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
69 14
BI
1K
CPU JTAG Support
R1090
XDP_TMS
BI
69 14
BI
69 13 10 7 6
69 10 6
XDP_TDI
BI
69 14
BI
69 14
BI
XDP_TDO
R1092
54.9
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
1%
1/16W
MF-LF
2 402
C1014
R1094
XDP_TRST_L
649
BI
69 14
BI
69 14
BI
54.9
1%
1/16W
MF-LF
402
10%
16V
X5R
402
R1010
0
5%
1/16W
MF-LF
402
R1011 1
1K
NO STUFF
1
69 9
69 9
69 9
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
OUT CPU_BSEL<0>
OUT CPU_BSEL<1>
OUT CPU_BSEL<2>
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
FCBGA
2 OF 4
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
69
U26
69
AA1
69
Y1
69
E5
B5
D24
D6
D7
AE6
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
BI
14 69
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
IN
14 60 69
IN
14 69
IN
14 69
IN
13 14 69
IN
14 69
OUT
R1023 1
R1021 1
54.9
1%
1/16W
MF-LF
402
54.9
1%
1/16W
MF-LF
402
60
5%
1/16W
MF-LF
2 402
R1022
R1020
27.4
R1012
1K
5%
1/16W
MF-LF
402 2
0.1uF
NO STUFF
1%
1/16W
MF-LF
402
NO STUFF
69 13 10 7 6
69 14
NO STUFF
R1093
XDP_TCK
BI
R1006
69 13 10 7 6
BI
69 14
2.0K
BI
69 14
69 27
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
BI
69 14
1%
1/16W
MF-LF
402
R1091
54.9
54.9
R1005
BI
69 14
69 14
BI
69 14
69 14
14 69
BI
69 14
69 14
69 13 10 7 6
BI
69 14
OUT
FSB_CLK_CPU_P
FSB_CLK_CPU_N
69 14
6 7 10 13 69
47
A21
BI
IN
OUT
A22
BI
69 14
IN
H CLK
BCLK0
BCLK1
BI
69 14
69 14
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
A24
BI
69 14
7 13 69
BI
5%
1/16W
MF-LF
402
D21
BI
69 14
6 7 10 13 69
THERMAL
PROCHOT*
THERMDA
THERMDC
69 14
69 14
54.9
68
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
G5
DATA GRP 2
BI
1 OF 4
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
H1
E2
DATA GRP 3
BI
69 14
FCBGA
DATA GRP 0
69 14
M3
ADS*
BNR*
BPRI*
PENRYN
DATA GRP 1
BI
K5
U1000
CONTROL
69 14
L4
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
XDP/ITP SIGNALS
BI
L5
ADDR GROUP0
BI
69 14
J4
ADDR GROUP1
BI
69 14
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ICH
69 14
BI
RESERVED
69 14
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
27.4
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
PLACEMENT_NOTE (all 4 resistors):
1%
1/16W
MF-LF
402
Place within 12.7mm of CPU
CPU FSB

SYNC FROM T18

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
10
109
A4
P6
A8
(CPU CORE POWER)
A7
AB20
A9
AB7
OMIT
A10
FCBGA
A15
(SV
(SV
(SV
(LV
Design Target)
HFM)
LFM)
Design Target)
3 OF 4
A14
U1000
A16
PENRYN
R2
R5
FCBGA
A19
R22
4 OF 4
A23
R25
AF2
T1
B6
T4
B8
B11
T26
AC13
B13
U3
AC15
B16
U6
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
AE9
C22
Y3
Y6
VCC
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D15
AF15
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
VCC
AF20
(CPU IO POWER 1.05V)
E14
=PP1V05_S0_CPU
E9
6 8 10 12 13
G21
E10
4500 mA (before VCC stable)

2500 mA (after VCC stable)
VSS
AB8
E16
AB11
E19
AB13
E21
AB16
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
VCCP
F10
N6
F2
AC14
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
AA7
NEED 1.5V POWER SOURCE
G23
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
60 69
J2
AD19
OUT
60 69
J5
AD22
OUT
60 69
J22
AD25
OUT
60 69
J25
AE1
OUT
60 69
K1
AE4
OUT
60 69
K4
AE8
OUT
60 69
(CPU INTERNAL PLL POWER 1.5V)

=PP1V5_S0_CPU
(BR1#)
8 12
B26
AA9
VCCA
AA10
130 mA
C26
AA12
AA13
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AA15
AA17
AA18
AA20
AB9
AC10
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
=PPVCORE_S0_CPU
1
AB14
VCCSENSE
AF7
R1100
CPU_VCCSENSE_P
1%
1/16W
MF-LF
402
OUT
60 69
AB15
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
AB17
AB18
VSSSENSE
AE7
100
AB10
AB12
8 11 12
AB4
VSS
E12
F9
T23
AC12
A18
E7
A
A
A
A
P24
A17
D9
44
41
30.4
23
AC9
PENRYN
A13
8 11 12
AC7
U1000
A12
P21
OMIT
A11
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
R1101
M22
AF8
100
M25
AF11
N1
AF13
OUT
1
K23
60 69
1%
1/16W
MF-LF
402
N4
AF16
N23
AF19
N26
AF21
P3
B1
A25
(Socket-P KEY)
AF25
CPU Power & Ground

SYNC FROM T18

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
REV.
051-8089
02
OF
11
109
CPU VCore HF and Bulk Decoupling

6x 330uF. 32x 22uF 0805 (20 stuffed)
PLACEMENT_NOTE (C1200-C1219):
11 8
=PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
CRITICAL
1
CRITICAL
1
C1200
22UF
CRITICAL
1
22UF
2
20%
6.3V
CERM
805
CRITICAL
C1211
CRITICAL
C1212
C1213
22UF
20%
6.3V
CERM
805
20%
6.3V
CERM
805
CRITICAL
1
C1204
22UF
CRITICAL
1
C1215
CRITICAL
CRITICAL
20%
6.3V
CERM
805
C1216
20%
6.3V
CERM
805
20%
6.3V
CERM
805
CRITICAL
1
22UF
20%
6.3V
CERM
805
C1207
22UF
CRITICAL
1
22UF
20%
6.3V
CERM
805
C1206
22UF
20%
6.3V
CERM
805
CRITICAL
C1214
22UF
C1205
22UF
20%
6.3V
CERM
805
CRITICAL
1
22UF
20%
6.3V
CERM
805
CRITICAL
1
22UF
20%
6.3V
CERM
805
22UF
20%
6.3V
CERM
805
C1203
22UF
20%
6.3V
CERM
805
CRITICAL
C1210
CRITICAL
1
C1202
22UF
20%
6.3V
CERM
805
CRITICAL
1
C1201
C1217
22UF
2
20%
6.3V
CERM
805
20%
6.3V
CERM
805
CRITICAL
C1218
22UF
2
C1209
22UF
20%
6.3V
CERM
805
CRITICAL
22UF
CRITICAL
1
C1208
C1219
22UF
20%
6.3V
CERM
805
20%
6.3V
CERM
805
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side.
CRITICAL
1
CRITICAL
1
C1240
330UF
CRITICAL
1
C1241
330UF
20%
2.0V
POLY-TANT
D2T-SM2
20%
2.0V
POLY-TANT
D2T-SM2
CRITICAL
1
C1242
330UF
20%
2.0V
POLY-TANT
D2T-SM2
C1243
330UF
20%
2.0V
POLY-TANT
D2T-SM2
VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
11 8
=PP1V5_S0_CPU
PLACEMENT_NOTE=PLACE C1250 C1251 NEAR CPU PIN B26.
C1250
C1251
10uF
20%
6.3V
X5R
603
0.01UF
10%
16V
CERM
402
B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13 11 10 8 6
=PP1V05_S0_CPU
PLACEMENT_NOTE=PLACE C1260 BETWEEN CPU & MCP79.
CRITICAL
C1260
330UF
20%
2.0V
POLY-TANT
D2T-SM2
C1261
C1262
C1263
C1264
C1265
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C1266
0.1UF
20%
10V
CERM
402
CPU Decoupling

SYNC FROM T18

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
12
109
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0620 adapter board to support CPU, MCP debugging.
MCP79-specific pinout
8 6
12 11 10 8 6
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP_CONN
J1300
6-1747769-0
CRITICAL
F-ST-SM
XDP
R1315 1
64
54.9
62
1%
1/16W
MF-LF
402 2
69 10 7
69 10 7
69 10 7
69 10 7
XDP_BPM_L<5>
XDP_BPM_L<4>
BI
BI
XDP_BPM_L<3>
XDP_BPM_L<2>
BI
IN
69 10 7
IN
69 10 7
IN
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
OBSDATA_B3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R1399
37
38
1K
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CPU_PWRGD
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
IN
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
69 14 10
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<1>
XDP_BPM_L<0>
7
XDP
OBSFN_A0
OBSFN_A1
XDP_PWRGD
5%
1/16W
MF-LF
402
19 7
21 7 6
IN
OUT
72 44 21 7
BI
72 44 21 7
BI
69 10 7 6
OUT
PM_LATRIGGER_L
JTAG_MCP_TCK
XDP_OBS20
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
OBSDATA_C0
OBSDATA_C1
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
7 19 72
BI
7 19 72
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
7 19 72
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
6 7 21
OUT
6 7 21
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
7 19 72
BI
7 19 72
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
7 19 72
BI
7 19 72
IN
OUT
BI
6 7
6 7 21
7 19 72
IN
7 14 69
IN
7 14 69
OUT
7 10 26
XDP
R1303
1
IN
1K
5%
1/16W
MF-LF
402
FSB_CPURST_L
IN
10 14 69
PLACEMENT_NOTE=Place close to CPU to minimize stub.
6 7
OUT
6 7 10 69
OUT
6 7 10 69
OUT
6 7 10 69
XDP_PRESENT#
XDP
1
61
0.1uF
10%
16V
X5R
402
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
69 7 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO_CONN
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP
C1300
OBSFN_C0
OBSFN_C1
C1301
0.1uF
63
2
516S0625
10%
16V
X5R
402
Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
SYNC_MASTER=M99_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
13
109
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
BI
69 10
BI
69 10
69 10
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
BI
69 10
69 10
R1410 1
R1415 1
54.9
62
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BI
69 10
69 10
=PP1V05_S0_MCP_FSB
BI
BI
69 10
24 22 14 8
BI
69 10
69 10
BI
BI
BI
BI
69 10
BI
69 10
BI
69 10
BI
62
5%
1/16W
MF-LF
402
69 10
69 10
69 10
BI
BI
BI
69
69 42 10
69 10
IN
IN
PM_THRMTRIP_L
CPU_FERR_L
69 10
NO STUFF
R1420
IN
IN
IN
NO STUFF
R1421
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BI
69 10
BI
69 10
BI
69 10
IN
69 10
OUT
OUT
69 60 42 10
OUT
NO STUFF
1
R1422
1K
BI
69 10
T40
U40
V41
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
W39
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
N37
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
M39
W37
V35
L36
N35
M41
J41
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
AC34
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
AE36
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35
AK35
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
BI
69 10
R1416
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
AC38
AA33
AC39
AC33
AC35
FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
AD42
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
CPU_PECI_MCP
CPU_PROCHOT_L
E41
AJ41
AG43
5%
1/16W
MF-LF
402
AH40
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
F42
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
D42
F41
CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#
CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#
CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
FSB
69 10
CPU_ADSTB0#
CPU_ADSTB1#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
AA41
AA40
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
G42
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
AL43
BCLK_OUT_NB_P
BCLK_OUT_NB_N
AL41
69
AK42
69
BCLK_IN_N
BCLK_IN_P
AK41
G41
AL42
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
BI
10 69
FSB_BPRI_L
FSB_DEFER_L
OUT
10 69
OUT
10 69
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
10 69
OUT
10 69
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
7 13 69
OUT
7 13 69
FSB_CLK_MCP_P
FSB_CLK_MCP_N
Loop-back clock for delay matching.
R1430
R1435
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
69 10
OUT
69 10
OUT
69 10
OUT
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
24
69
69
69
R1431 1
69
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
AC42
206
20
29
15
mA
mA
mA
mA
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AG27
AH27
AG28
AH28
AM39
AM40
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AM43
AM42
R1436
49.9
AB41
CPU_RS0#
CPU_RS1#
CPU_RS2#
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
AC41
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
CPU_PWRGD
CPU_RESET#
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AJ40
AF41
AH39
AH42
AF42
AG41
AH41
AH43
H38
AM33
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
10 69
OUT
10 69
OUT
10 69
OUT
10 69
OUT
10 69
OUT
10 69
=PP1V05_S0_MCP_FSB
8 14 22 24
NO STUFF
1
R1440
150
OUT
OUT
10 13 69
OUT
10 69
OUT
10 69
OUT
10 69
OUT
10 69
OUT
10 60 69
MCP CPU Interface
5%
1/16W
MF-LF
402
10 13 69

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
14
109
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
70 28
70 28
BI
BI
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
BI
70 28
OUT
70 28
OUT
70 28
OUT
70 28
OUT
70 28
OUT
70 28
OUT
70 28
OUT
70 28
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
70 28
OMIT
U1400
MRAS0#
MCAS0#
MWE0#
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
AV17
AP17
AR17
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
28 70
70 29
BI
BI
28 70
70 29
BI
BI
28 70
70 29
BI
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
AP23
AP19
AW17
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
28 70
70 29
BI
28 70
70 29
BI
BI
28 70
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
OUT
70 29
BI
OUT
28 30 70
70 29
BI
OUT
28 30 70
70 29
BI
AV33
MCLK0A_1_P
MCLK0A_1_N
BA24
MCLK0A_0_P
MCLK0A_0_N
BB20
MCS0A_1#
MCS0A_0#
AY24
BC20
AR18
BI
70 29
BI
70 29
BI
70 29
BI
28 30 70
70 29
BI
OUT
28 30 70
70 29
BI
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
28 30 70
OUT
28 30 70
OUT
28 30 70
OUT
28 30 70
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
70 29
BI
OUT
28 70
70 29
BI
OUT
28 70
70 29
BI
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
70 29
28 70
BI
OUT
OUT
28 70
70 29
BI
70 29
BI
OUT
28 30 70
70 29
OUT
OUT
28 30 70
70 29
OUT
70 29
MODT0A_1
MODT0A_0
MEM_A_ODT<1>
MEM_A_ODT<0>
AP15
AV15
MEM_A_CKE<1>
MEM_A_CKE<0>
AU23
AT23
OUT
OUT
28 30 70
70 29
OUT
OUT
28 30 70
70 29
OUT
70 29
MCKE0A_1
MCKE0A_0
BI
70 29
28 30 70
OUT
OUT
70 29
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
AT15
BI
70 29
OUT
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
AW33
BI
28 30 70
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
BI
BI
70 29
MBA0_2
MBA0_1
MBA0_0
BI
OUT
OUT
28 30 70
70 29
OUT
OUT
28 30 70
70 29
OUT
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MRAS1#
MCAS1#
MWE1#
AW16
MBA1_2
MBA1_1
MBA1_0
BB29
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BA29
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
BA15
BA16
BB17
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
BI
29 70
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
OUT
29 30 70
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
29 70
OUT
29 70
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
29 70
OUT
29 70
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
29 30 70
OUT
29 30 70
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
29 30 70
OUT
29 30 70
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
29 30 70
OUT
29 30 70
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
BA14
29 70
BI
OUT
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BB18
BI
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
MCLK1A_1_P
MCLK1A_1_N
BB22
MCLK1A_0_P
MCLK1A_0_N
BA19
MCS1A_1#
MCS1A_0#
BB14
MODT1A_1
MODT1A_0
BB13
MCKE1A_1
MCKE1A_0
AY31
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
BB42
BA22
AY19
BB16
AY15
BB30
MCP Memory Interface

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
15
109
OMIT
U1400
MCP79-TOPO-B
BGA
24 16 8
24
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
BA21
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
AU17
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
AN17
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
AV23
BC24
BB21
AR15
AN15
AN25
MCLK0B_1_P
MCLK0B_1_N
MCLK0B_0_P
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MODT0B_0
MODT0B_1
MCKE0B_0
MCKE0B_1
R1610 1
40.2
70
17
12
19
39
mA
mA
mA
mA
T27
U28
U27
T28
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
AN41
AM41
MCLK1B_1_P
MCLK1B_1_N
AY23
MCLK1B_0_P
MCLK1B_0_N
BA20
MCS1B_0#
MCS1B_1#
BC16
MODT1B_0
MODT1B_1
AY16
MCKE1B_0
MCKE1B_1
BA30
MRESET0#
AY32
BB41
BA23
AY20
BA13
BC13
BA31
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MCP_MEM_RESET_L
TP or NC for DDR2.
MEM_COMP_VDD
MEM_COMP_GND
R1611 1
40.2
1%
1/16W
MF-LF
402
BA41
2
70
MCLK1B_2_P
MCLK1B_2_N
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
1%
1/16W
MF-LF
402
AU34
MCLK0B_2_P
MCLK0B_2_N
MEMORY CONTROL 1B
AU33
MEMORY CONTROL 0B
(4 OF 11)
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
AA22
AP12
2
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AM17
8 16 24
4771 MA (A01, DDR2)
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
MCP Memory Misc
T9
U18
U20
U22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
REV.
051-8089
02
OF
16
109
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
9
9
IN
IN
IN
31
IN
35
IN
IN
IN
IN
F7
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
PEG_PRSNT_L
IN
31 7
C9
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
Int PU
PE0_PRSNT_16#
Int PU
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
D5
PEB_CLKREQ#/GPIO_49
D9
PEB_PRSNT# Int PU
FW_CLKREQ_L
PCIE_FW_PRSNT_L
E8
PEC_CLKREQ#/GPIO_50
Int PU
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PEG_CLK100M_P
PEG_CLK100M_N
OUT
9 71
OUT
9 71
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
7 31 71
OUT
7 31 71
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
35 71
OUT
35 71
OUT
9 71
OUT
9 71
PE0_REFCLK_P
PE0_REFCLK_N
E11
PE1_REFCLK_P
PE1_REFCLK_N
G11
PE2_REFCLK_P
PE2_REFCLK_N
J11
PE3_REFCLK_P
PE3_REFCLK_N
G13
PE4_REFCLK_P
PE4_REFCLK_N
J13
PE5_REFCLK_P
PE5_REFCLK_N
L14
PE6_REFCLK_P
PE6_REFCLK_N
N14
M14
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N
D11
F11
PEC_PRSNT# Int PU
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
M15
PED_CLKREQ#/GPIO_51
B10
PED_PRSNT# Int PU
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L
L16
PEE_CLKREQ#/GPIO_16
L18
PEE_PRSNT#/GPIO_46
TP_MCP_GPIO_17
EXTGPU_PWR_EN
M16
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
M17
OUT
PEG_CLKREQ_L
EXTGPU_RESET_L
M19
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
31 7
IN
PCIE_WAKE_L
F17
Int PU
PE_WAKE# Int PU (S5)
PEX_RST0#
K11
PCIE_RESET_L
OUT
26
71 31 7
IN
K9
PE1_TX0_P
PE1_TX0_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
OUT
31 71
IN
PE1_RX0_P
PE1_RX0_N
D8
71 31 7
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
OUT
31 71
71 35
IN
H9
PE1_TX1_P
PE1_TX1_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
35 71
IN
PE1_RX1_P
PE1_RX1_N
B8
71 35
PCIE_FW_D2R_P
PCIE_FW_D2R_N
OUT
35 71
71 9
IN
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
F9
PE1_RX2_P
PE1_RX2_N
PE1_TX2_P
PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
OUT
9 71
OUT
9 71
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
H7
PE1_RX3_P
PE1_RX3_N
PE1_TX3_P
PE1_TX3_N
B6
OUT
IN
71 9
IN
M18
J9
G9
E9
G7
Int PU
Int PU
Int PU
Int PU
J10
C10
IN
IN
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
PCI EXPRESS
F13
H13
Int PU
K14
Int PU
C8
A8
B7
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
C6
T17
W19
U17
V19
W16
W17
W18
U16
T19
PP1V05_S0_MCP_PLL_PEX
24
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
U19
+DVDD1_PEX1
+DVDD1_PEX2
T16
+V_PLL_PEX
A11
PEX_CLK_COMP
84 mA (A01)
71
MCP_PEX_CLK_COMP
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
Y12
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
M13
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
N13
MCP PCIe Interfaces
P13
NO STUFF
2.37K
R1710
1%
1/16W
MF-LF
402

IF PE0 INTERFACE IS NOT USED, GROUND DVDD0_PEX AND AVDD0_PEX.

IF PE1 INTERFACE IS NOT USED, GROUND DVDD1_PEX AND AVDD1_PEX
PLACEMENT_NOTE=Place within 12.7mm of U1400

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
17
109
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
IN
73 32
IN
73 32
IN
73 32
IN
73 32
IN
IN
IN
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
IN
C23
B23
E24
A24
ENET_CLK125M_RXCLK
ENET_RX_CTRL
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
MCP_MII_RXER
MCP_MII_COL
MCP_MII_CRS
F23
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
B26
B22
TP_ENET_INTR_L
R1810 1
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
J22
K24
+V_DUAL_RMGT1
+V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
B24
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
24
Network Interface Select
C24
C25
D25
73
+V_DUAL_MACPLL
C27
MII_COMP_VDD
MII_COMP_GND
B27
24
Interface
OUT
32 73
OUT
32 73
OUT
32 73
OUT
32 73
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
32 73
OUT
32 73
OUT
32 73
RGMII_TXC/MII_TXCLK
D24
C26
RGMII_MDC
RGMII_MDIO
D21
C21
ENET_MDC
ENET_MDIO
RGMII_PWRDWN/GPIO_37
G23
TP_ENET_PWRDWN_L
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
OUT
33 73
MII_RESET#
J23
ENET_RESET_L
OUT
32 73
BI
32 73
=PP3V3_S0_MCP_GPIO
PP3V3_S0_MCP_DAC
+V_RGB_DAC
+V_TV_DAC
J32
DDC_CLK0
DDC_DATA0
B31
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
B39
RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE
A40
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
D36
IFPA_TXC_P
IFPA_TXC_N
B35
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
B32
IFPB_TXC_P
IFPB_TXC_N
L31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J29
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
C30
DDC_CLK3
DDC_DATA3
D31
IFPAB_RSET
IFPAB_VPROBE
E32
49.9
TP_MCP_RGB_DAC_VREF
B38
RGB_DAC_RSET
RGB_DAC_VREF
20 8
71 9
OUT MCP_TV_DAC_RSET
E36
71 9
OUT MCP_TV_DAC_VREF
A35
=PP3V3_S5_MCP_GPIO
R1820
47K
5%
1/16W
MF-LF
402
26
IN
26
OUT
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
43 7
Interface Mode
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
67
IN
66
OUT
66
OUT
66
OUT
67
OUT
67
OUT
67
67
D38
XTALIN_TV
XTALOUT_TV
OUT
OUT
67
OUT
67
OUT
67
OUT
OUT
OUT
IN
67
IN
LPCPLUS_GPIO
DP_IG_CA_DET
E16
GPIO_6/FERR*/IGPU_GPIO_6
B15
GPIO_7/NFERR*/IGPU_GPIO_7
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
G39
LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58
E37
F40
MCP_HDMI_TXC_P
MCP_HDMI_TXC_N
OUT
67
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HOTPLUG_DET.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
C38
TV
C
Y
Comp
/
/
/
/
25
206 mA (A01)
R1860
100K
D35
E35
MCP_HDMI_TXD_P<0>
MCP_HDMI_TXD_N<0>
MCP_HDMI_TXD_P<1>
MCP_HDMI_TXD_N<1>
MCP_HDMI_TXD_P<2>
MCP_HDMI_TXD_N<2>
G35
TP_DP_IG_AUX_CHP
TP_DP_IG_AUX_CHN
D43
F35
F33
G33
J33
H33
C43
DP_HOTPLUG_DET
MCP_HDMI_HPD
C31
F31
M27
190 mA (A01, 1.8V)
M26
PP3V3_S0_MCP_VPLL
25
16 mA (A01)
25 8
71 25
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET2/GPIO_22
HPLUG_DET3
25 8
71 25
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
8 mA
8 mA
M28
M29
+VDD_IFPA
+VDD_IFPB
+V_PLL_IFPAB
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
HDMI_VPROBE
J30
MII
5%
1/16W
MF-LF
402
8 19 21
R1861
100K
5%
1/16W
MF-LF
402
MCP_DDC_CLK0
MCP_DDC_DATA0
A31
NO_TEST=TRUE
NC_MCP_RGB_RED
NC_MCP_RGB_GREEN NO_TEST=TRUE
NO_TEST=TRUE
NC_MCP_RGB_BLUE
A39
B40
NC_MCP_RGB_HSYNC NO_TEST=TRUE
NC_MCP_RGB_VSYNC NO_TEST=TRUE
A41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
A36
B36
C36
C37
OUT
68 71
OUT
68 71
OUT
68 71
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
68 71
OUT
68 71
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
66 71
OUT
66 71
OUT
7 66 71
OUT
7 66 71
OUT
7 66 71
OUT
7 66 71
OUT
7 66 71
OUT
7 66 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
OUT
9 71
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
7 66
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
25 71
OUT
25 71
TV DAC Disable:
BI
TV_DAC_RSET
TV_DAC_VREF
RGB ONLY
C39
DACS
NO_TEST=TRUE NC_MCP_RGB_DAC_RSET
FLAT PANEL
1%
1/16W
MF-LF
402
103 mA
103 mA
K32
R1811
ENET_TXD<0>
RGMII
NOTE: All Apple products set strap to

MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
73
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
IN
RGMII_TXCTL/MII_TXEN
RGMII_INTR/GPIO_35
T23
8 24
131 mA (A01)
V23
49.9
1%
1/16W
MF-LF
402
8 18 24
83 mA (A01)
IN
J24
+3.3V_DUAL_RMGT2
24 18 8
32
73 32
LAN
+3.3V_DUAL_RMGT1
C35
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
A32
D32
C32
D33
C33
B34
C34
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
K31
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
H29
L29
K29
L30
K30
N30
M30
B30
E31
G31
BI
BI
7 66
67
67
R1850
10K
5%
1/16W
MF-LF
402
MCP Ethernet & Graphics

GPIO 57-59 ( IF LCD PANEL IS USED):

IN MCP79 THESE PINS HAVE UNDOCUMENTED PULL HIGH
(~10K TO 3.3V). TO ENSURE PINS ARE LOW
BY DEFAULT, PULL DOWN(1K OR SRONGER) MUST BE USED

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
18
109
OMIT
U1400
21 18 8
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
72 19
72 19
19
9
19
OUT
OUT
IN
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
T2
V9
T3
U9
T4
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R3
U10
R4
U11
P3
19
OUT
OUT
OUT
19
72 19
72 19
19
BI
72 13 7
BI
72 13 7
BI
72 13 7
BI
72 13 7
BI
72 13 7
BI
72 13 7
BI
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_TRDY_L
43 41 7
35
43 41 7
IN
IN
BI
PM_CLKRUN_L
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
P2
N3
N2
N1
Y3
AD11
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AE2
AE1
AE6
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
PCI
BI
72 13 7
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
LPC_DRQ0#
Int PU
LPC_SERIRQ Int PU
PCI_RESET0#
PCI_RESET1#
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AA3
AA6
AA11
W10
Y2
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
OUT
7 13
R10
MEM_VTT_EN_R
TP_PCI_RESET1_L
OUT
26
AA9
Y4
AA10
Y1
AB9
AA7
R11
R6
R7
R8
72
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
8.2K
R1990
8.2K
PCI_REQ1_L
CRTMUX_SEL_TV_L
MCP_RS232_SIN_L
R1991
R1992
R1994
8.2K
8.2K
8.2K
1
1
1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R
PCI_CLKIN
R9
72
PCI_CLK33M_MCP
AE12
LPC_FRAME_R_L
LPC_PWRDWN_L
LPC_RESET0#
AE5
LPC_RESET_L
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
R1910
AD4
AD2
AD1
AD5
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to pin R8
R1960
22
LPC_FRAME_L
2
5%
R1950
R1951
R1952
R1953
0
0
0
0
LPC_CLK0
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
GND
U26
R1989
PCI_REQ0_L
22
1/16W
MF-LF
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
Y26
OUT
7 41 43 72
OUT
7 41 43
OUT
26 72
BI
7 41 43 72
BI
7 41 43 72
BI
7 41 43 72
BI
402
LPC_CLK33M_SMC_R
AE9
U24
19
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_TRDY#
PCI_PME#/GPIO_30
Int PU (S5)
PCI_CLK0
PCI_CLK1
PCI_CLK2
LPC
72 13 7
MCP_RS232_SOUT_L
OUT
7 41 43 72
26 72
R1961
10K
Y27
AB18
2
H34
AB20
5%
1/16W
MF-LF
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
MCP PCI & LPC
AD28
AD33
AD34

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
19
109
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
71 38
71 38
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
OUT
OUT
71 38
IN
71 38
IN
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ7
AJ6
AJ5
AJ4
SATA_A0_TX_P
SATA_A0_TX_N
USB0_P
USB0_N
SATA_A0_RX_N
SATA_A0_RX_P
USB1_P
USB1_N
USB2_P
USB2_N
OUT
71 38
OUT
71 38
71 38
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
IN
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AJ11
AJ10
AJ9
AK9
AK2
AJ3
AJ2
AJ1
AM4
AL3
AL4
AK3
AN1
AM1
AM2
AM3
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
AP3
TP_SATA_F_D2RN
TP_SATA_F_D2RP
AN3
AP2
AN2
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_C0_TX_P
SATA_C0_TX_N
C28
D28
A28
B28
External A
USB_EXTA_P
USB_EXTA_N
BI
39 72
BI
39 72
AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N
BI
9 72
BI
9 72
External D
USB_EXTD_P
USB_EXTD_N
BI
9 72
BI
9 72
USB_CAMERA_P
USB_CAMERA_N
BI
66 72
BI
66 72
USB_IR_P
USB_IR_N
BI
40 72
USB3_P
USB3_N
F29
USB4_P
USB4_N
K27
USB5_P
USB5_N
J26
G29
USB6_P
USB6_N
USB7_P
USB7_N
USB8_P
USB8_N
L27
J27
F27
G27
D27
E27
K25
L25
USB9_P
USB9_N
H25
USB10_P
USB10_N
F25
USB11_P
USB11_N
K23
J25
BI
40 72
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
9 72
BI
9 72
Bluetooth
USB_BT_P
USB_BT_N
BI
9 72
BI
9 72
External B
USB_EXTB_P
USB_EXTB_N
BI
39 72
BI
39 72
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
BI
9 72
BI
9 72
External C
USB_EXTC_P
USB_EXTC_N
BI
9 72
BI
9 72
G25
SATA_C1_RX_N
SATA_C1_RX_P
L21
+V_PLL_USB
L28
1
1
R2051
8 18
R2053
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2052 1
R2050
TP_USB_11P
TP_USB_11N
L23
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
=PP3V3_S5_MCP_GPIO
TP_USB_10P
TP_USB_10N
1
5%
1/16W
MF-LF
402
8.2K
5%
1/16W
MF-LF
402
8.2K
SATA_C0_RX_N
SATA_C0_RX_P
SATA_C1_TX_P
SATA_C1_TX_N
IR
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
D29
Camera
SATA
USB
71 38
C29
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
K21
J21
H21
PP3V3_S0_MCP_PLL_USB
IN
39
IN
39
IN
IN
42
24
19 mA (A01)
USB_RBIAS_GND
A27
72
MCP_USB_RBIAS_GND
R2060 1
TP_MCP_SATALED_L
PP1V05_S0_MCP_PLL_SATA
24
E12
AE16
AF19
AG16
AG17
AG19
AH17
AH19
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
+DVDD1_SATA1
+DVDD1_SATA2
127 mA (A01)
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
+V_PLL_SATA
84 mA (A01)
43 mA (A01)
SATA_LED#
AN14
AL14
AM13
AM14
71
MCP_SATA_TERMP
AE3
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AD35
AD37
AD38
806
1%
1/16W
MF-LF
402
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
R2010
2.49K
1%
1/16W
MF-LF
402
MCP SATA & USB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
20
109
OMIT
U1400
MCP79-TOPO-B
8 21 24
7 mA (A01)
BGA
(9 OF 11)
HDA
+V_DUAL_HDA1
+V_DUAL_HDA2
D
72 52
HDA_SDIN0
IN
G15
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
24 21 8
J14
J15
HDA_SDATA_IN0
Int PD
HDA_SDATA_OUT
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
Int PD
HDA_BITCLK
43
49.9K
1%
1/16W
MF-LF
402
OUT
IN
R2121
49.9K
E15
72 21
22
HDA_RESET*
K15
72 21
L15
72 21
HDA_BIT_CLK
22
1
22
OUT
1%
1/16W
MF-LF
402
41
IN
41
IN
MCP_HDA_PULLDN_COMP
A15
HDA_PULLDN_COMP
OUT
52 72
HDA_SYNC
OUT
52 72
5%
1/16W
MF-LF
402
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
K17
20 mA
17 mA
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
AE18
AE17
SLP_S3*
SLP_RMGT*
SLP_S5*
G17
THERM_DIODE_P
THERM_DIODE_N
B11
+V_PLL_NV_H
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
K13
C18
A20GATE
Int PU
KBRDRSTIN* Int PU
SIO_PME*
Int PU (S5)
EXT_SMI/GPIO_32* Int PU (S5)
SM_INTRUDER_L
B20
INTRUDER*
L13
C19
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
J17
H17
MCP_THMDIODE_P
MCP_THMDIODE_N
C11
IN
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
41
IN
C16
26
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN* Int PU (S5)

RSTBTN* Int PU
RTC_RST_L
C20
RTC_RST*
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
L20
SPKR
C13
LID* Int PU (S5)

LLB* Int PU (S5)
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
L19
OUT
21
IN
21
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
B12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
CPUVDD_EN
D17
MCP_CPUVDD_EN
C14
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
26
IN
E20
26
IN
MCP_CPU_VLD
C17
CPU_VLD
E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST*
JTAG_TCK
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
XTALIN
XTALOUT
SUS_CLK/GPIO_34
BUF_SIO_CLK
D20
13 7 6
IN
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
13 7 6
IN
JTAG_MCP_TCK
G19
26
IN
OUT
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16
26
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19
IN
OUT
F19
J19
JTAG_MCP_TRST_L
J18
SPI0
SPI1
OUT
33 36 41 64
OUT
OUT
41 42 64
OUT
47
OUT
47
OUT
21 61
OUT
21 61
OUT
21 61
NOTE: MCP79 does not support FWH, only

LPC ROMs. So Apple designs will
not use LPC for BootROM override.
=PP3V3_S0_MCP
NOTE: MCP79 rev A01 does not support

SPI1 option.
8 22 24
M20
M21
R2180
5%
1/16W
MF-LF
402
Frequency
MCP_SPKR
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
K19
G21
F21
M23
A12
D12
D13
C15
B14
OUT
BI
OUT
BI
OUT
7 13 44 72
R2181
10K
7 13 44 72
44 72
44 72
HDA_SYNC
24 MHz
14.31818 MHz
5%
1/16W
MF-LF
402
SPI Frequency Select
21 31 33
Frequency
IN
OUT
BUF_SIO_CLK Frequency
10K
SPI_DO
SPI_CLK
42 MHz
25 MHz
1 MHz
21 28 29 41
38
31 MHz
21 42
21
OUT
26
OUT
43 72
OUT
43 72
IN
NOTE: Straps not provided on this page.
43
OUT
43 72
OUT
26 72
R21591
10K
5%
1/16W
MF-LF
402
B16
26
IN
26
OUT
B19
XTALIN_RTC
XTALOUT_RTC
TEST_MODE_EN
PKG_TEST
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
C2170
C2172
10PF
10PF
5%
50V
CERM
402
5%
50V
CERM
402
C2171
MCP_TEST_MODE_EN
=PP3V3_S3_FET
21 72
21 72
R2143
8 65
R2140
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2141
10K
R2146
21 72
R2190
1K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
8 18 19
R2142
5%
1/16W
MF-LF
402
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
MCP_GPIO_4
5%
1/16W
MF-LF
402
AP_PWR_EN
R2163
10K
100K
21 72
L22
10K
=PP3V3_S0_MCP_GPIO
For EMI Reduction on HDA interface
K22
HDA_RST_R_L
HDA_SYNC_R
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
B18
R2150 1
100K
HDA Output Caps

HDA_SDOUT_R
HDA_BIT_CLK_R
AE7
R21221
PCI
BOOT_MODE_USER
PWRGD_SB
PS_PWRGD
IN
LPC_FRAME#
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
PM_RSMRST_L
MCP_PS_PWRGD
13 7 6
M24
HDA_SDOUT
LPC
BOOT_MODE_SAFE
MISC
41
69 60
M25
I/F
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
MCP_GPIO_4
AUD_I2C_INT_L
L17
PP1V05_S0_MCP_PLL_NV
TP_MCP_LID_L
PM_BATLOW_L
41
IN
52 72
HDA_RST_L
13 7 6
52 72
R2172
HDA_RST_R_L
HDA_SYNC_R
OUT
BIOS Boot Select
22
HDA_BIT_CLK_R
HDA_SDOUT
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
Int PD
R2170
HDA_SDOUT_R
5%
1/16W
MF-LF
402
42 41 36 33
72 21
R2173
PP3V3_G3_RTC
F15
5%
1/16W
MF-LF
402
R2171
HDA_SYNC
37 mA (A01)
8.2K
1%
1/16W
MF-LF
402
24
R2120
R2160
R2110
72
26 22
K16
49.9
J16
21
21 28 29 41
MCP HDA & MISC
21 42
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
21
21 31 33
ARB_DETECT
21
21 61
21 61
21 61
2
1
C2173
10PF
10PF
5%
50V
CERM
402
5%
50V
CERM
402
R2147
R2155
R2156
100K
22K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402

R2157
22K
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
21
109
OMIT
U1400
MCP79-TOPO-B
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
61 46 24 8
AV40
BGA
(10 OF 11)
=PPVCORE_S0_MCP
AA25
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
BA1
AC23
BA4
U25
AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
G34
AF23
G4
AF25
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
K10
AG3
K12
AG4
K18
AA21
K26
AG6
K37
AG7
K4
AG8
K40
AG9
K8
AH1
AU1
AH10
L40
AH11
L43
W26
L5
AH2
M10
AA23
M34
W28
M35
AH25
M37
AH21
Y28
AH3
Y33
AH4
Y34
AH5
Y35
AH6
Y37
AH7
Y38
AH9
AB17
AA24
AB16
W21
AN26
W23
AD7
W25
M11
AF12
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
POWER
AH34
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
GND
AH33
OMIT
U1400
MCP79-TOPO-B
BGA
(11 OF 11)
AH26
=PP1V05_S0_MCP_FSB
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
R32
1139 mA
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
+VTT_CPUCLK
AG32
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
26 21
AY13
PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)
P11
A20
+VBAT
8 21 24
450 mA (A01)
AE8
AB10
AD9
Y10
AB11
AA8
Y9
=PP3V3_S5_MCP
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3
T21
16 mA
8 24
266 mA (A01)
H19
J20
K20
250 mA
H27
J28
K28
AA4
AB19
8 14 24
1182 mA (A01)
AC32
8 24
105 mA (A01)
MCP Power & Ground
U21
V21
Y6
T11
V11

Y11
AH16
T22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
22
109
MCP79 A01 Silicon Support

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
24
109
8
MCP Core Power
61 46 22 8
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500
C2501
C2502
C2503
4.7UF
4.7UF
4.7UF
4.7UF
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
C2504
C2506
C2507
C2508
C2509
C2510
C2511
C2512
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
10V
X5R
402-1
10%
10V
X5R
402-1
10%
10V
X5R
402-1
10%
10V
X5R
402-1
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
MCP PCIE (DVDD) Power

8
C2505
1UF
C2513
0.1UF
20%
10V
CERM
402
MCP SATA (DVDD) Power
57 mA (A01)
43 mA (A01)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
C2515
4.7UF
20%
4V
X5R
402
C2516
1UF
C2517
1UF
10%
10V
X5R
402-1
333 mA (A01)
C2518
C2519
0.1uF
10%
10V
X5R
402-1
C2520
0.1uF
20%
10V
CERM
402
20%
4V
X5R
402
MCP 1.05V AUX Power

22 8
4.7UF
20%
10V
CERM
402
C2521
0.1uF
131 mA (A01)
20%
6.3V
CERM
402-LF
C2525
C2526
0.1uF
2
MCP FSB (VTT) Power

22 14 8
C2528
0.1uF
20%
10V
CERM
402
4.7uF
20%
10V
CERM
402
20%
4V
X5R
402
C2529
0.1uF
C2531
C2532
C2533
C2534
C2535
C2536
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
4.7UF
20%
4V
X5R
402
C2540
4.7UF
20%
4V
X5R
402
=PP3V3_S0_MCP
C2574
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
127 mA (A01)
C2576
20%
6.3V
CERM
402-LF
14
270 mA (A01)
C2581
20%
10V
CERM
402
L2582
1
PP1V05_S0_MCP_PLL_PEX
VOLTAGE=1.05V
2
0402
MCP 3.3V Power
0.1UF
30-OHM-1.7A
4771 MA (A01, DDR2)
22 21 8
C2573
2.2UF
20%
6.3V
CERM
402-LF
PP1V05_S0_MCP_PLL_FSB
C2580
MCP Memory Power

16 8
C2572
2.2UF
206 mA (A01)
2.2UF
2
VOLTAGE=1.05V
2
0402
C2530
20%
6.3V
CERM
402-LF
30-OHM-1.7A
562 mA (A01)
20%
6.3V
CERM
402-LF
L2580
8
1182 mA (A01)
C2575
2.2UF
20%
10V
CERM
402
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
2.2UF
2
VOLTAGE=1.05V
2
0603
C2571
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
7 8
L2575
30-OHM-5A
18 8
105 mA (A01)
C2570
2.2UF
20%
10V
CERM
402
MCP 1.05V RMGT Power
7 8
VOLTAGE=1.05V
0603
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
L2570
C2541
C2542
C2543
C2544
C2545
C2546
C2547
C2548
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)
450 mA (A01)
19 mA (A01)
C2551
C2552
C2553
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
C2583
0.1UF
20%
10V
CERM
402
L2584
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_SATA
VOLTAGE=1.05V
19 mA (A01)
0402
C2584
C2555
2.2UF
4.7UF
VOLTAGE=3.3V
2
0402
C2550
C2582
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
20
L2555
30-OHM-1.7A
C2549
0.1UF
17
84 mA (A01)
4.7UF
20%
4V
X5R
402
20
84 mA (A01)
C2585
0.1UF
20%
10V
CERM
402
B
MCP 3.3V AUX/USB Power
22 8
=PP3V3_S5_MCP
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
MCP 3.3V Ethernet Power

24 18 8
266 mA (A01)
21 8
L2586
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_CORE
C2560
C2564
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
C2586
4.7UF
20%
4V
X5R
402
C2587
0.1UF
20%
10V
CERM
402
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
C2562
C2588
2.2UF
24 18 8
4.7UF
MCP79 Ethernet VRef
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
21
VOLTAGE=1.05V
2
0402
7 mA (A01)
87 mA (A01)
L2588
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
16
VOLTAGE=1.05V
2
0402
83 mA (A01)
1
MCP 3.3V/1.5V HDA Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
C2589
0.1UF
2
20%
10V
CERM
402
37 mA (A01)
C2590
0.1UF
20%
10V
CERM
402
R2591 1
MCP Standard Decoupling
1.47K
1%
1/16W
MF-LF
402
L2595
8
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
PP1V05_ENET_MCP_PLL_MAC
VOLTAGE=1.05V
2
0402
C2595
4.7UF
20%
4V
X5R
402
MCP_MII_VREF
OUT
18

5 mA (A01)
R2590 1
C2596
1.47K
1%
1/16W
MF-LF
402 2
20%
10V
CERM
402
18
0.1UF
2
C2591
0.1UF
2
20%
10V
CERM
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
25
109
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
18 8
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
L2650
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A
8
=PP3V3_S0_MCP_DAC_UF
206 mA (A01)
PP3V3_S0_MCP_DAC
VOLTAGE=3.3V
0402
190 mA (A01, 1.8V)

1
18 8
C2610
C2650
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
18
206 mA (A01)
C2651
2.2UF
20%
6.3V
CERM
402-LF
95 mA (A01)
C
C2615
4.7UF
20%
4V
X5R
402
C2616
0.1UF
HDCP ROM
20%
10V
CERM
402
WF: Open question on which packge option(s) nVidia can support.
=PP3V3_S0_HDCPROM
C2690
R2690 1
0.1UF
20%
10V
CERM
402
MCP_HDMI_RSET
MCP_HDMI_VPROBE
71 18
71 18
71 18
71 18
NO STUFF
C2620
R2620
5%
1/16W
MF-LF
402 2
AT24C08
C2630
1%
1/16W
MF-LF
402
10K
NO STUFF
VCC
U2695
A0
A1
3
A2
20%
10V
CERM
402
R2630
1K
0.1UF
2
SOIC
NO STUFF
NO STUFF
1K
0.1UF
20%
10V
CERM
402
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
1%
1/16W
MF-LF
402
SDA
SCL
WP
=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL
25
BI
IN
44
44
HDCPROM_WP
GND
4
NO STUFF
VCC
U2690
AT24C01B
SOT23
25
HDCPROM_WP
SDA
SCL
WP
3
1
GND
2
=PP3V3_S0_MCP_VPLL_UF
16 mA (A01)
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: ???
1
2
PP3V3_S0_MCP_VPLL
18
VOLTAGE=3.3V
0402
C2640
4.7UF
20%
6.3V
CERM
603
16 mA (A01)
C2641
0.1uF
20%
10V
CERM
402
MCP Graphics Support

SYNC FROM T18

REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
26
109
RTC Power Sources
Platform Reset Connections
LPC Reset (Unbuffered)
VIN
R2881
U2870
MIC5232-2.8YD5
72 19
TSOT-23-5
=PP3V42_G3H_RTC_D
3 EN
VOUT
C2870
NC
1UF
10%
10V
2 X5R
402-1
PP3V3_G3_RTC
NC
C2871
0.47UF
10%
10V
2 X5R
402
GND
R2801 C2801
10%
1
100
1%
1/16W
MF-LF
2 402
1UF
6.3V
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
33
5%
1/16W
MF-LF
402
21 22
VOLTAGE=3.3V
DEBUG_RESET_L
OUT
7 43
SMC_LRESET_L
OUT
41
BKLT_PLT_RST_L
OUT
66
MINI_RESET_L
OUT
31
PCA9557D_RESET_L
OUT
27
FW_RESET_L
OUT
35
R2883
33
5%
1/16W
MF-LF
402
PLACE C2872 CLOSE MCP
CERM
402
G3_RTC_L
IN
C2800
0.08F
2%
2 3.3V
XHHG
SM
PCIE Reset (Unbuffered)

R2892
17
RTC Crystal
PCIE_RESET_L
21
12pF
1
R2810
Y2810
18
32.768K
R2821 1
21
MCP 25MHz Crystal
21
OUT
CRITICAL
5%
1/16W
MF-LF
402
Y2820
27MHZ
NC
NC
C2821
12pF
1
MCP_CLK27M_XTALIN
OUT
2
5%
50V
CERM
402
R2870
Y2815
25.0000M
CRITICAL
10M
5%
1/16W
MF-LF
402
MCP_CLK27M_XTALOUT_R
MCP_CLK25M_XTALOUT_R
SM-3.2X2.5MM
NC
NC
R2816
SM-2
5%
50V
CERM
402
5%
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402
2
18
R2815
R2872
1
12pF
1
5%
1/16W
MF-LF
402 2
C2815
MCP_CLK25M_XTALOUT
19
IN
33
MEM_VTT_EN_R
C2816
12pF
1
MCP_CLK25M_XTALIN
2
5%
1/16W
MF-LF
402
MEM_VTT_EN
MAKE_BASE=TRUE
=DDRVTT_EN
72 19
IN
LPC_CLK33M_SMC_R
22
LPC_CLK33M_SMC
5%
1/16W
MF-LF
402
Reset Button
PM_SYSRST_L
IN
XDP_DBRESET_L
0
5%
1/16W
MF-LF
402
LPC_CLK33M_LPCPLUS
1
R2899
R28901
NO STUFF
0
5%
1/16W
MF-LF
402 2
33
10K pull-up to 3.3V S0 inside MCP

72 21
PM_SYSRST_DEBOUNCE_L
IN
1
21
OUT
NO STUFF
5%
1/16W
MF-LF
402
C2899
OUT
7 43 72
C2826
5%
22
PM_CLK32K_SUSCLK_R
41 72
10PF
R2829
R2898
13 10 7
0
5%
1/16W
MF-LF
402
NO STUFF
XDP
OUT
R2826
1
IN
59 65
OUT
R2825
5%
50V
CERM
402
41
5%
1/16W
MF-LF
402
5%
50V
CERM
402
NO STUFF
R2820
10M
IN
R2871
2
5%
50V
CERM
402
NO STUFF
12pF
1
RTC_CLK32K_XTALIN
OUT
MCP_CLK27M_XTALOUT
IN
C2811
7X1.5X1.4-SM
21
12pF
RTC_CLK32K_XTALOUT_R
CRITICAL
5%
1/16W
MF-LF
402
C2820
10M
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
MCP 27MHZ CRYSTAL
5%
50V
CERM
402
5%
1/16W
MF-LF
402
R2891
R2811
C2810
RTC_CLK32K_XTALOUT
IN
IN
2 50V
CERM
402
PM_CLK32K_SUSCLK
OUT
41 72
5%
1/16W
MF-LF
402
1UF
SILK_PART=SYS RST
10%
10V
X5R
402
MCP S0 PWRGD
8
=PP3V3_S5_MCPPWRGD
1
C2850
0.1UF
20%
10V
CERM
402
5 TC7SZ08AFEAPE
64 41 7
60
IN
IN
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
SOT665
U2850Y
MCP_PS_PWRGD
OUT
21
SB Misc
SYNC FROM T18

CHANGE RESET BUTTOM TO RESET PADS
MCP_CPUVDD_EN
REMOVE UNUSED PCIE RESET SIGNALS
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A
CHANGE RTC POWER SOURCE FROM COIN CELL TO SUPER CAPS
ALIAS MEM_VTT_EN TO =DDRVTT_EN
CHANGE Y2810 AND U2850 TO SMALLER PARTS
21
R2853
0
1
IN

MCP_CPU_VLD

OUT
21
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
28
109
Page Notes
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
Voltage divider resistor values at op-amp outputs not yet finalized.

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM OPTION TO SELECT VREF SOURCE

=PPVTT_S3_DDR_BUF
59 8

VREFMRGN AND NO VERFMRGN
10mA max load
R2903
1
B1
C2
C2903
V+
0.1UF
U2902
V-
27
B4
1
R2901
C2901
0.1UF
20%
2 6.3V
CERM
402-LF
20%
2 10V
CERM
402
B1
A2
V+
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
10 A1
VB4
NO_VREFMRGN
MEM_VREF_B
29
R2906
1
VREFMRGN_DQ_SODIMMB_BUF
27
5%
1/16W
MF-LF
402
100
1%
1/16W
MF-LF
402
A4
A3
Place close to J3100.1
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN
Place close to J3200.1
VREFMRGN_DQ_SODIMM
R2902
VOUTB 2
100K
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
NC
5%
1/16W
MF-LF
402
VREFMRGN
44
IN
DAC5574
44
VREFMRGN
MAX4253
UCSP
VREFMRGN A1
VREFMRGN
8 U2900
VDD
MSOP VOUTA 1
5%
1/16W
MF-LF
402
U2902
R2905
1
100K
1
2.2UF
100
1%
1/16W
MF-LF
402
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN
C2900
28
VREFMRGN
VREFMRGN
1
VREFMRGN_DQ_SODIMMA_BUF
C4
C3
MEM_VREF_A
R2904
MAX4253
UCSP
VREFMRGN C1
20%
10V
2 CERM
402
=PP3V3_S3_VREFMRGN
5%
1/16W
MF-LF
402
VREFMRGN
1
NO_VREFMRGN
GND
3
B1
C2
VREFMRGN
1
V+
C2905
U2904
MAX4253
UCSP
C1
VREFMRGN
0.1UF
NC
C4
C3
20%
10V
2 CERM
402
VB4
B
B1
A2
16
C2902
0.1UF
U2901
44
IN
BI
SCL
2 SDA
THRM
17
PAD
NC
27
NC
R2913
VREFMRGN_CPUFSB_EN
10
100K
5%
1/16W
MF-LF
402
VREFMRGN_DQ_SODIMMA_EN
27
11
NC
12
100
1%
1/16W
MF-LF
402
VREFMRGN_CPUFSB_EN
27
A4
VB4
P0
P1
P2
P3
P4
P5
P6
P7
R2914
VREFMRGN_CPUFSB_BUF
VREFMRGN
CPU_GTLREF
OUT
10 69
Place close to U1000.AD26
VREFMRGN
VREFMRGN_DQ_SODIMMB_EN
27
13
NC
NC
14
RESET* 15
TABLE_5_HEAD
PCA9557D_RESET_L
PART#
IN
QTY
DESCRIPTION
CRITICAL
BOM OPTION
26
TABLE_5_ITEM
GND
114S0149
RES, MTL FILM, 200, 1%, 0402, SM, LF
R2903
VREFMRGN
114S0149
RES, MTL FILM, 200, 1%, 0402, SM, LF
R2905
VREFMRGN
44
A0
A1
5 A2
4
UCSP
A1
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
A3
PCA9557
QFN
U2904
MAX4253
VREFMRGN
VCC
20%
2 10V
CERM
402
ADDR=0x30(WR)/0x31(RD)
V+
VREFMRGN
VREFMRGN
1
TABLE_5_ITEM
FSB/DDR2 VREF MARGINING


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
29
109
7
29 28 8
27
=PP1V8_S3_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MEM_VREF_A
1
C3100
C3101
2.2UF
0.1UF
1
20%
4V
2 X5R
402
20%
2 10V
CERM
402
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
MEM_A_DQ<3>
MEM_A_DQ<6>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<7>
MEM_A_DQ<2>
MEM_A_DQ<12>
MEM_A_DQ<8>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<19>
MEM_A_DQ<17>
MEM_A_DM<2>
NC
70 15
MEM_A_DQ<23>
MEM_A_DQ<22>
70 30 15
MEM_A_CKE<0>
70 30 15
MEM_A_BA<2>
70 15
NC
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
70 30 15
MEM_A_CAS_L
MEM_A_CS_L<1>
70 30 15
MEM_A_ODT<1>
70 30 15
70 15
70 15
B
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DM<5>
MEM_A_DQ<47>
MEM_A_DQ<42>
MEM_A_DQ<56>
MEM_A_DQ<60>
NC
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
29 8
70 15
=PPSPD_S0_MEM
1
1 C3131
C3130
2.2UF
0.1UF
20%
2 4V
X5R
402
20%
10V
2 CERM
402
44
44
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQ<59>
MEM_A_DQ<63>
MEM_A_DQ<48>
MEM_A_DQ<53>
MEM_A_DM<6>
MEM_A_DQ<50>
MEM_A_DQ<55>
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS1
DQ0
DQ1
CRITICAL VSS0
F-RT-TH4
VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
CK0
CK0*
VSS12
DQ10
VSS13
DQ14
DQ11
VSS14
DQ15
VSS15
KEY
VSS16
DQ16
VSS17
DQ20
DQ17
VSS18
DQ21
VSS19
DQS2*
NC0
DQS2
VSS21
DM2
VSS22
DQ18
DQ19
VSS23
DQ24
DQ25
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
VSS26
DM3
NC1
DQS3*
DQS3
VSS27
VSS28
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC/A15
NC/A14
VDD3
A11
A7
A6
VDD5
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD10
NC/ODT1
VDD11
NC3
VSS31
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
DQS4*
VSS34
DM4
DQS4
VSS35
VSS36
DQ34
DQ35
VSS38
DQ40
DQ38
DQ39
VSS37
DQ44
DQ45
DQ41
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
DQ42
VSS42
DQ46
DQ43
VSS43
DQ48
DQ49
VSS45
NC_TEST
DQ47
VSS44
DQ52
DQ53
VSS46
CK1
VSS47
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
DQ50
VSS50
DQ54
DQ51
VSS51
DQ56
DQ57
=PP1V8_S3_MEM
8 28 29
29
J3100
DQ55
VSS52
DQ60
DQ61
VSS53
DM7
VSS54
DQS7*
VSS55
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
SDA
DQ63
VSS58
SCL
SA0
VDDSPD
SA1
516-0135
=GND_CHASSIS_DIPDIMM_CENTER 9
5
DIP DIMM CONN201
DDR2-SODIMM-STD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84 NC
86 NC
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120 NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
MEM_A_DQ<4>
MEM_A_DQ<1>
15 70
MEM_A_DM<0>
15 70
MEM_A_DQ<5>
MEM_A_DQ<0>
15 70
MEM_A_DQ<13>
MEM_A_DQ<9>
MEM_A_DM<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_EVENT_L
MEM_A_DM<3>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQ<16>
MEM_A_DQ<20>
15 70
15 70
15 70
15 70
15 70
15 70
15 70
15 70
15 70
15 70
21 29 41
15 70
15 70
15 70
15 70
15 70

- =I2C_MEM_SCL
- =I2C_MEM_SDA
15 70
15 70
MEM_A_A<15>
MEM_A_A<14>
15 30 70
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
15 30 70
MEM_A_ODT<0>
MEM_A_A<13>

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
15 70
15 30 70
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<0>
Page Notes
15 70
MEM_A_CKE<1>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
15 70
DDR2 Bypass Caps
15 30 70
15 30 70
(For return current)

29 28 8
=PP1V8_S3_MEM
15 30 70
15 30 70
15 30 70
4.7uF
15 30 70
15 30 70
15 30 70
15 30 70
C3110
2 10V
CERM
402
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<43>
MEM_A_DQ<46>
MEM_A_DQ<61>
MEM_A_DQ<57>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_DM<7>
MEM_A_DQ<58>
MEM_A_DQ<62>
MEM_A_DQ<52>
MEM_A_DQ<49>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQ<51>
MEM_A_DQ<54>
15 70
C3114
20%
2 10V
CERM
402
C3113
0.1UF
20%
2 10V
CERM
402
C3116
2 10V
CERM
402
15 70
15 70
2 6.3V
CERM
15 70
15 70
C3115
0.1UF
2.2UF
20%
2 10V
CERM
402
20%
2 6.3V
CERM
402-LF
C3119
C3117
2.2UF
20%
2 6.3V
CERM
402-LF
15 70
C3118
20%
15 70
402-LF
2.2UF
C3120
2.2UF
20%
20%
2 6.3V
CERM
2 6.3V
CERM
402-LF
402-LF
15 70
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

when they get cheaper.
15 70
15 70
15 70
15 70
15 70
DDR2-800
15 70
15 70
15 70
28
MEM_A_SA0
R3140
10K
1
DDR2 SO-DIMM Connector A
5%
1/16W
MF-LF
402
15 70
15 70
15 70
28
MEM_A_SA1
R3141
10K
1

5%
1/16W
MF-LF
402
15 70

15 70

15 70
SIZE
MEM_A_SA0
MEM_A_SA1
20%
15 70
2.2UF
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
C3112
15 70
0.1UF
MEM_A_DQ<34>
MEM_A_DQ<35>
0.1UF
20%
2 10V
CERM
402
MEM_A_DM<4>
C3111
0.1UF
20%
DRAWING NUMBER
28
28
APPLE INC.
202=GND_CHASSIS_DIPDIMM_LEFT
REV.
051-8089
SCALE
SHT
NONE
ADDR=0xA0(WR)/0xA1(RD)
C3121
20%
2 6.3V
CERM
603
15 30 70
0.1UF
MEM_A_DQ<32>
MEM_A_DQ<33>

(NONE)
02
OF
31
109
7
29 28 8
27
=PP1V8_S3_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MEM_VREF_B
1
1 C3201
C3200
2.2UF
0.1UF
20%
2 4V
X5R
402
20%
2 10V
CERM
402
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
MEM_B_DQ<5>
MEM_B_DQ<1>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<12>
MEM_B_DQ<14>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQ<11>
MEM_B_DQ<9>
MEM_B_DQ<22>
MEM_B_DQ<19>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQ<18>
MEM_B_DQ<23>
70 15
MEM_B_DQ<24>
MEM_B_DQ<28>
70 15
MEM_B_DM<3>
70 15
NC
70 15
70 15
70 30 15
MEM_B_DQ<29>
MEM_B_DQ<25>
MEM_B_CKE<0>
NC
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 30 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
70 15
MEM_B_BA<2>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_CS_L<1>
MEM_B_ODT<1>
MEM_B_DQ<39>
MEM_B_DQ<34>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQ<37>
MEM_B_DQ<32>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DM<5>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<49>
MEM_B_DQ<53>
NC
70 15
70 15
70 15
70 15
70 15
70 15
70 15
29 28 8
=PPSPD_S0_MEM
70 15
C3230 1 C3231
2.2UF
20%
2 4V
X5R
402
0.1UF
20%
2 10V
CERM
402
70 15
44
44
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DM<7>
MEM_B_DQ<57>
MEM_B_DQ<56>
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS1
DQ0
CRITICAL VSS0
J3200
DQ1
VSS4
F-RT-TH4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
DQS1*
DQS1
CK0
CK0*
VSS12
VSS13
DQ10
DQ11
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
DQ16
VSS17
DQ20
DQ17
DQ21
VSS18
DQS2*
VSS19
NC0
DQS2
DM2
VSS21
DQ18
VSS22
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ28
DQ25
VSS25
DQ29
VSS26
DM3
DQS3*
NC1
VSS27
DQS3
VSS28
DQ26
DQ30
DQ27
VSS29
DQ31
VSS30
CKE0
VDD0
NC/CKE1
VDD1
NC2
NC/A15
BA2
VDD2
NC/A14
VDD3
A12
A11
A9
A8
A7
A6
VDD4
VDD5
A5
A3
A4
A2
A1
VDD6
A0
VDD7
A10/AP
BA1
BA0
WE*
RAS*
S0*
VDD8
VDD9
CAS*
NC/S1*
ODT0
NC/A13
VDD10
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
VSS34
DQS4*
DQS4
DM4
VSS35
VSS36
DQ38
DQ34
DQ35
DQ39
VSS37
VSS38
DQ44
DQ40
DQ41
DQ45
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
VSS42
DQ42
DQ43
DQ46
DQ47
VSS43
VSS44
DQ48
DQ49
DQ52
DQ53
VSS45
VSS46
NC_TEST
VSS47
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
VSS50
DQ50
DQ51
DQ54
DQ55
VSS51
VSS52
DQ56
DQ57
DQ60
DQ61
VSS53
VSS54
DM7
VSS55
DQS7*
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
DQ63
VSS58
SA0
SDA
SCL
VDDSPD
516-0135
=GND_CHASSIS_DIPDIMM_RIGHT 9
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
MEM_B_DQ<0>
MEM_B_DQ<4>
8 28 29
15 70
15 70
MEM_B_DM<0>
15 70
MEM_B_DQ<3>
MEM_B_DQ<2>
15 70
15 70
MEM_B_DQ<8>
MEM_B_DQ<13>
15 70
MEM_B_DM<1>
15 70
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_DQ<10>
MEM_B_DQ<15>
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84 NC
86 NC
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120 NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202=GND_CHASSIS_DIPDIMM_CENTER
=PP1V8_S3_MEM
5
DIP DIMM CONN201
DDR2-SODIMM-STD
MEM_B_DQ<21>
MEM_B_DQ<17>
MEM_EVENT_L
MEM_B_DM<2>
15 70
15 70
15 70
15 70
15 70
15 70
15 70
21 28 41
15 70
MEM_B_DQ<16>
MEM_B_DQ<20>
MEM_B_DQ<30>
MEM_B_DQ<26>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQ<27>
MEM_B_DQ<31>
MEM_B_CKE<1>
MEM_B_A<15>
MEM_B_A<14>
Page Notes
15 70
15 70

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
15 70
15 70

- =I2C_MEM_SCL
- =I2C_MEM_SDA
15 70
15 70

(NONE)
15 70
15 70
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
15 30 70
9
15 30 70
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
DDR2 Bypass Caps
15 30 70
15 30 70
(For return current)
15 30 70
29 28 8
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=PP1V8_S3_MEM
15 30 70
15 30 70
15 30 70
C3221
4.7uF
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_A<13>
20%
2 6.3V
CERM
603
15 30 70
15 30 70
15 30 70
15 30 70
15 30 70
C3210
0.1UF
15 70
MEM_B_DM<4>
15 70
2 10V
CERM
402
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<52>
MEM_B_DQ<48>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
15 70
15 70
C3213
0.1UF
20%
2 10V
CERM
402
C3216
2 10V
CERM
402
C3214
C3215
0.1UF
2.2UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 6.3V
CERM
402-LF
C3217
2.2UF
20%
2 6.3V
CERM
402-LF
15 70
15 70
C3218
20%
2 6.3V
CERM
402-LF
15 70
15 70
C3219
2.2UF
C3220
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
15 70
15 70
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

when they get cheaper.
15 70
15 70
15 70
15 70
29 28 8
MEM_B_DM<6>
20%
B
1
2.2UF
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
C3212
15 70
0.1UF
MEM_B_DQ<33>
MEM_B_DQ<38>
0.1UF
20%
2 10V
CERM
402
MEM_B_DQ<35>
MEM_B_DQ<36>
C3211
0.1UF
20%
=PPSPD_S0_MEM
DDR2-800
R3241
15 70
10K
MEM_B_DQ<54>
MEM_B_DQ<51>
15 70
15 70
MEM_B_SA0
J3201_SA1
29
5%
1/16W
MF-LF
2 402
DDR2 SO-DIMM Connector B

29
MEM_B_DQ<63>
MEM_B_DQ<59>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQ<58>
MEM_B_DQ<62>
15 70
15 70
R3240

10K
5%
1/16W
MF-LF
2 402
15 70
15 70

15 70
15 70
SIZE
MEM_B_SA0
J3201_SA1
9
28
29
DRAWING NUMBER
Resistor prevents pwr-gnd short
APPLE INC.
29
ADDR=0XA2(WR)/0XA3(RD)
SCALE
SHT
NONE
REV.
051-8089
02
OF
32
109
One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it
8
70 28 15
IN
70 28 15
IN
70 29 15
IN
70 29 15
IN
70 28 15
IN
70 28 15
IN
70 29 15
IN
70 29 15
IN
70 28 15
IN
70 28 15
IN
70 29 15
IN
70 29 15
IN
70 28 15
IN
RP3300
R3301
RP3301
RP3302
47
47
47
47
2
1
2
4
7
2
7
5
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
RP3303
RP3304
RP3305
47
47
47
47
1
4
1
1
8
5
8
2
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
RP3300
R3309
RP3301
1
3
2
6
5% 1/16WSM-LF
5% 1/16WMF-LF402
R3311
47
47
47
47
5% 1/16WSM-LF
5% 1/16WMF-LF402
RP3307
RP3308
RP3307
RP3308
RP3307
RP3308
RP3304
RP3307
RP3308
RP3303
RP3309
RP3304
RP3303
R3325
RP3304
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
2
4
1
3
3
2
1
4
1
4
1
2
3
7
5
8
6
6
7
8
5
8
5
8
7
6
1
3
2
6
47
47
47
2
4
2
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
R3327
MEM_A_A<14..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
70 28 15
IN
=PP0V9_S3M_MEM_TERM
MEM_A_BA<2..0>
0
1
2
RP3309
RP3300
RP3303
7
5
7
5% 1/16WSM-LF
5% 1/16WMF-LF402
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WMF-LF402
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
20%
10V
2 CERM
402
C3302
20%
10V
2 CERM
402
C3304
IN
70 28 15
IN
70 28 15
IN
RP3300
RP3309
RP3309
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
47
47
47
3
4
3
6
5
6
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
0.1UF
C3306
0.1UF
C3308
0.1UF
C3310
0.1UF
C3312
C3314
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
70 29 15
IN
MEM_B_A<0>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<10>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<1>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_BA<2..0>
0
1
2
RP3311
RP3310
RP3311
R3335
RP3311
RP3310
RP3306
RP3306
RP3310
RP3305
RP3310
RP3306
RP3305
RP3301
RP3306
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
3
3
2
1
1
2
4
3
1
4
4
2
3
4
1
6
6
7
2
8
7
5
6
8
5
5
7
6
5
8
RP3302
RP3311
RP3305
47
47
47
1
4
2
8
5
7
C3316
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WMF-LF402
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
C3318
C3320
0.1UF
C3322
0.1UF
C3317
0.1UF
20%
10V
2 CERM
402
C3319
0.1UF
20%
2 10V
CERM
402
C3321
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3315
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3313
20%
2 10V
CERM
402
0.1UF
20%
2 10V
CERM
402
C3311
0.1UF
0.1UF
20%
10V
2 CERM
402
LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
TO PP0V9_S0_MEM_TERM
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
0.1UF
C3309
20%
10V
2 CERM
402
0.1UF
20%
2 10V
CERM
402
C3307
20%
10V
2 CERM
402
0.1UF
20%
2 10V
CERM
402
C3305
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3303
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3301
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
70 28 15
0.1UF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WMF-LF402
5% 1/16WSM-LF
C3300
C3323
0.1UF
20%
10V
2 CERM
402
Memory Active Termination
A
70 29 15
IN
70 29 15
IN
70 29 15
IN
RP3301
RP3302
RP3302
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
47
47
47
1
2
3
8
7
6

5% 1/16WSM-LF
5% 1/16WSM-LF
5% 1/16WSM-LF
C3324
0.1UF
20%
10V
2 CERM
402
C3325

0.1UF
20%
10V
2 CERM
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
33
109
AIRPORT
D
Q3450
L3404
31
5 6
PP3V3_WLAN_F
SOT-6
8 31
FDC606P_G
VOLTAGE=3.3 V
MIN_LINK_WIDTH=1 MM
0402-LF
FERR-120-OHM-1.5A
750 mA nominal max

1000 mA peak
C3421
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
0.1uF
C3420
10uF
20%
6.3V
X5R
603
10%
16V
X5R
402
C3450
0.1UF
1
PLACE C3422 NEAR J3400
C3451
PLACE C3420 AND C3421 NEAR Q3450
R3451
10K
0.033UF
C3422
5%
1/16W
MF-LF
R3450
P3V3WLAN_S5
100K
2 402
PM_WLAN_EN_L
=PP1V5_S0_AIRPORT
1
7
C3404
C3405
2 CERM
2 CERM
402
402
C3406
20%
10V
20%
10V
20%
10V
2 CERM
0.1UF
0.1UF
0.1UF
PP3V3_WLAN
MIN_LINE_WIDTH=1 MM
VOLTAGE=3.3 V
33
IN
5%
1/16W
MF-LF
402
10%
16V
X5R
402
402
PP3V3_WLAN_F
31
CRITICAL
17 7
OUT
31
OUT
=PP3V3_S3_WLAN 8
J3400
ASOB226-S45B-7F
PCIE_WAKE_L
MINI_CLKREQ_CONN_L
54
IT IS CO-LAY FUNCTION
U3402
74LVC1G17DRL
1
5
71 17 7
71 17 7
IN
PCIE_CLK100M_MINI_N
IN
PCIE_CLK100M_MINI_P
10
11
12
13
14
15
16
17
71 17 7
OUT
71 17 7
OUT
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
C3431
71 17
IN
71 17
IN
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
1
10%
10%
2
0.1uF
16V
0.1uF
X5R 402
71 7
71 7
PCIE_MINI_R2D_N
PCIE_MINI_R2D_P
16V X5R 402
C3430
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
KEY
MINI_RESET
U3401
SOT-553
4
PP3V3_WLAN_BUF
PP3V3_WLAN_RC
NC
5%
1/16W
MF-LF
402
1
3
NC
C3453
MINI_RESET_L
10%
6.3V
CERM
402
R3454
62K
1UF
26
IN
2
2
5%
1/16W
MF-LF
402
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
TC7SZ08AFEAPE 5
SOT665
R3453
33K
F-ST-SM
PP3V3_S3_AIRPORT_CONN
L3405
275 mA peak
206 mA nominal max
8 31
FERR-120-OHM-1.5A
0402-LF
I2C_MINI_PCIE_SCL
I2C_MINI_PCIE_SDA
72
C3452
IN
BI
0.1uF
7 44
20%
10V
CERM
402
7 44
USB2_AIRPORT_N
7 USB2_AIRPORT_P
B
17
PCIE_MINI_PRSNT_L
MINI_CLKREQ_L
7
17
46
47
48
CRITICAL
Q3401
49
50
L3402
90-OHM
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
51
52
Q3401
DLP0NS
SYM_VER-1
53
=USB_MINI_N
=USB_MINI_P
BI
BI
33 21
31
AP_PWR_EN
MINI_CLKREQ_CONN_L
CONNECT TO M35 MODULE

OLD:516S0406 (FOXCONN ONLY)
NEW:516S0635 (FOXCONN & ACON)
Right Clutch Connector

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
34
109
=PP1V05_ENET_PHY
C3710
C3711
0.1UF
10%
16V
X5R
402
=PP3V3_ENET_PHY
(43mA typ - 1000base-T)
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
0.1UF
10%
16V
X5R
402
(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
CRITICAL
L3715
FERR-120-OHM-1.5A
0402-LF
CRITICAL
L3705
FERR-120-OHM-1.5A
C3700
C3701
C3702
0.1UF
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
PP1V05_ENET_PHYAVDD
C3714
0402-LF
C3715
0.1UF
0.1UF
10%
16V
X5R
402
C3716
10%
16V
X5R
402
VOLTAGE=1.05V
0.1UF
10%
16V
X5R
402
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
C3705
0.1UF
2
C3706
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
=PP3V3_ENET_PHY_VDDREG
If internal switcher is used, must place 1x 22uF &

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
IN
=RTL8211_ENSWREG
39
40
10
36
28
45
44
21
37
OMIT
CRITICAL
5%
1/16W
MF-LF
402
RTL8211CLGR
R3752 1
R3751
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=RTL8211_REGOUT
If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
If internal switcher is not used, VDDREG and REGOUT can float.
U3700
ENSWREG
4.7K
AVDD12
5%
1/16W
MF-LF
402
15
4.7K
FB12
5%
1/16W
MF-LF
402 2
DVDD12
Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.
VDDREG
10K
R3799
DVDD33
AVDD33
NO STUFF
R3720 1
41
R3750 1
REGOUT
48
RXC
19
TQFP
R3796
1
73
PLACE R3796 CLOSE TO U1400, PIN D24
IN
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
IN
ENET_TX_CTRL
73 18
IN
73 18
BI
ENET_MDC
ENET_MDIO
73 18
IN
73 18
IN
73 18
73 18
73 18
WF: Verify that ENET_RESET_L does not assert when WOL is active.
If true, RC and 0-ohm resistor should be removed.
If false, ENET_RESET_L should be removed.
73 18
IN
ENET_RESET_L
22
ENET_CLK125M_TXCLK_R
5%
1/16W
402
MF-LF
IN
23
24
25
26
27
30
31
TXC
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RGMII/MII
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
TXCTL
MDC
MDIO
RXCTL
MANAGEMENT
R3700
1
5%
1/16W
402
MF-LF
RTL8211_PHYRST_L
29
PHYRSTB*
NO STUFF
1
C3727
0.1UF
RESET MEDIA DEPENDENT
RTL8211_RSET
20%
10V
CERM
402
RTL8211_CLK125
R3730 1
REFERENCE
18
13
MDI+[2]
MDI-[2]
MDI+[3]
MDI-[3]
11
R3795
ENET_RXCTL_R
12
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
34 73
BI
34 73
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
34 73
BI
34 73
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
34 73
BI
34 73
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
34 73
BI
34 73
22
22
22
22
22
22
ENET_CLK125M_RXCLK
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
OUT
18 73
OUT
18
OUT
18 73
OUT
18 73
OUT
18 73
OUT
18 73
PHY_AD0/LED0
R3731
5% 33 IN
1/16W
MF-LF
2 402
17
MDI+[1]
MDI-[1]
R3791
R3792
R3793
R3794
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
16
R3790
ENET_CLK125M_RXCLK_R
CLK125
CLOCK
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
42
43
CKXTAL1
CKXTAL2
LED
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
35
38
RXDLY/LED2
GND
7
1%
1/16W
MF-LF
402
32
RSET
22
2.49K
46
73
14
MDI+[0]
MDI-[0]
NO STUFF
C3790
47
ENET_CLK125M_TXCLK
33
IN
20
73 18
10PF
5%
50V
CERM
402
R3755 1
R3756 1
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3757
4.7K
5%
1/16W
MF-LF
402
Reserved for EMI

per RealTek request.
Ethernet PHY (RTL8211CL)
SYNC_MASTER=SUMA

Configuration Settings:
SIZE
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
DRAWING NUMBER
(PHY Address 00001)

(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
37
109
3.3V ENET FET
CRITICAL
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
Q3810
NTR4101P
SOT-23-HF
=PP3V3_ENET_FET
G
1
R3800 1
5%
1/16W
MF-LF
402
R3810
10%
16V
X5R
402
C3810
0.01UF
100K
P3V3ENET_EN_L
Q3801
C3811
0.033UF
10K
P3V3ENET_SS
5%
1/16W
MF-LF
402
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
IN
=P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
31
OUT
Q3805
1.05V ENET FET
Pull-up is with power FET.

6
SSM6N15FEAPE
SOT563
31 21
IN
1.8V Vgs
C3840
AP_PWR_EN
Q3805
Q3801
8
20.0K
SOT563
R3842
IN
20%
10V
CERM
402
R3840
SSM6N15FEAPE
SOT563
IN
1%
1/16W
MF-LF
402
SMC_ADAPTER_EN
Q3840
1
SI2312BDS
G
S
Q3841
=PP1V05_ENET_FET
SOT563
P1V05ENET_EN_L
PM_SLP_S3_L
1
1
1%
1/16W
MF-LF
402
C3841
0.01UF
10K
1
Q3841
SOT23
SSM6N15FEAPE
69.8K
CRITICAL
P1V05ENET_SS
2
1%
1/16W
MF-LF
402
R3841
64 41 36 21
0.1UF
AC_OR_S0_L
SSM6N15FEAPE
42 41 36 21
=PP1V05_ENET_P1V05ENETFET
10%
16V
CERM
402
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
IN
=P1V05ENET_EN
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=SUMA
R3895
73 18
IN
MCP_CLK25M_BUF0_R
22
1
RTL8211_CLK25M_CKXTAL1
OUT

32
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
38
109
- COPY THIS PAGE FROM K36 CSA.39
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1
C3900
0.1UF
C3901
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C3902
C3903
ETHERNET CONNECTOR
0.1UF
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
OMIT
CRITICAL
CRITICAL
73 32
BI
ENET_MDI_P<1>
73 32
BI
ENET_MDI_N<1>
T3901
SM
J3900
12
ENET_MDI_TRAN_P<1>
11
ENET_MDI_TRAN_N<1>
10
RJ45-MG3-K36
F-RT-TH
9
TX
1% 1/16W
1% 1/16W
73 32
73 32
BI
BI
ENET_MDI_P<3>
ENET_MDI_N<3>
MF-LF 402
R3902
2 75
ENET_CENTER_TAP<3> 1
TLA-6T213HF
4
MF-LF
402
SYM_VER-1
R3903
2 75
ENET_MDI_TRAN_P<3>
BI
ENET_MDI_N<2>
73 32
BI
ENET_MDI_P<2>
1% 1/16W
73 32
BI
ENET_MDI_P<0>
ENET_MDI_TRAN_N_2
ENET_MDI_TRAN_P_3
ENET_MDI_TRAN_N_3
MF-LF 402
R3900
2 75
1% 1/16W
ENET_MDI_N<0>
ENET_MDI_TRAN_P_2
ENET_MDI_TRAN_P<2>
10
TX
TLA-6T213HF
BI
ENET_MDI_TRAN_N_1
514-0523
R3901
2 75
73 32
ENET_MDI_TRAN_P_1
ENET_MDI_TRAN_N<2>
12
11
ENET_MDI_TRAN_N_0
10
CRITICAL
73 32
ENET_MDI_TRAN_P_0
ENET_MDI_TRAN_N<3>
RX
T3902
SM
MF-LF 402
ENET_MDI_TRAN_N<0>
ENET_MDI_TRAN_P<0>
7
RX
ENET_BOB_SMITH_CAP
CRITICAL
1
C3910
1000PF
10%
2KV
2 CERM
1206
9
=GND_CHASSIS_RJ45
ETHERNET CONNECTOR
SYNC_MASTER=SUMA

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
39
109
7 mA I/O
1
=PP3V3_FW_FWPHY
8 35 37
138 mA
C4120
C4121
1UF
C4122
1UF
10%
6.3V 2
CERM
402
C4123
1UF
10%
6.3V 2
CERM
402
C4124
1UF
10%
6.3V 2
CERM
402
1UF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
L4130
120-OHM-0.3A-EMI
114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA
1
2
D
C4130 1
C4131 1
1UF
C4132 1
1UF
10%
6.3V 2
CERM
402
VOLTAGE=3.3V
1UF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
L4110
=PP1V0_FW_FWPHY
L4135
120-OHM-0.3A-EMI
1
2
PP1V0_FW_FWPHY_AVDD
25 mA PCIe SerDes
VOLTAGE=1.0V
0402-LF
135 mA
C4110
1UF
10%
2 6.3V
CERM
402
C4100
1UF
10%
2 6.3V
CERM
402
C4101
1UF
10%
2 6.3V
CERM
402
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
C4111
1UF
C4135 1
C4136 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
10%
2 6.3V
CERM
402
110 mA Digital Core

1
0402-LF
VOLTAGE=3.3V
0402-LF
1UF
0 mA VReg PWR
C4102
1UF
10%
2 6.3V
CERM
402
C4103
1UF
10%
2 6.3V
CERM
402
C4104
1UF
C4105
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C4106
C4141 1
1UF
0.1UF
10%
2 6.3V
CERM
402
20%
10V
CERM 2
402
C4140
1UF
10%
2 6.3V
CERM
402
VDD10
=PPVP_FW_PHY_CPS
R41601
390K
5%
1/16W
MF-LF
402 2
C4150
R4150
22PF
2
1
NC
390
5%
1/16W
MF-LF
402
SM-3.2X2.5MM
R41611
2.94K
1%
1/16W
MF-LF
402 2
22PF
Y4150
24.576MHZ
C4151 NC
5%
50V
CERM
402
FW_CLK24P576M_XO
CRITICAL
R4170
191
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
R41621
470K
5%
1/16W
MF-LF
402 2
IN
37
IN
37
IN
74 37
BI
74 37
BI
74 37
BI
74 37
BI
37
BI
37
BI
74 37
BI
74 37
BI
74 37
BI
74 37
BI
37
BI
37
BI
37
BI
37
BI
37
BI
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
F12 DS0
E12 DS1
E13 DS2
B8
A8
B5
A5
B3
A3
B9
A9
B6
A6
B4
A4
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
B7 TPBIAS0
C3 TPBIAS1
A2 TPBIAS2
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
L6
L9
L5
L10
K12
71
71
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-2 (IPU) TRST*
N1
FW643_TRST_L
PCIE_FW_R2D_C_N
IN
17 71
PCIE_FW_R2D_C_P
IN
17 71
C4175
1
10%
2 16V PCIE_FW_D2R_N
OUT 17 71
X5R 402
10%
2 16V PCIE_FW_D2R_P
OUT 17 71
0.1UF X5R 402
PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100
PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100
0.1UF
C4176
1
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
M4
N2
M1
M3
WAKE*
FIXME!!! - TYPO IN SYMBOL REGCTL
REGCLT
POWER MANAGEMENT
VAUX_DETECT
NT-12 (IPD)
VAUX_DISABLE
NT-13
(OD) CLKREQN
IN
17 71
IN
17 71
=PP3V3_FW_FWPHY
C2
D13
E1
D2
L2
8 35 37
FW643_LDO
R41651
FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L
OUT
19
OUT
17
5%
1/16W
MF-LF
402 2
R4166
10K
5%
1/16W
MF-LF
2 402
R4164
10K
NAND_TREE
REXT
XO
XI NT-9
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
M13
N13
J2
L13
D12
D1
A10
H13
K13
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
J12 OCR_CTL_V10
J13 OCR_CTL_V12
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD) SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SERIAL EEPROM
CONTROLLER
NT-7
NT-6
SCL
SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
N12
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
5%
1/16W
MF-LF
2 402
MISCELLANEOUS
CHIP RESET
NT-5
PERST*
IN
26
R4163
10K
5%
1/16W
MF-LF
2 402
(Reserved)
VSS
10%
2 6.3V
CERM-X5R
402
71
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
NT-10 (IPD)
K1
L8
F13
G13
0.33UF
71
10%
2 16V
X5R 402
10%
2 16V
X5R 402
10K
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
NC
A12
D5
D6
D8
1394 PHY
N8
N7
N5
N6
REFCLKN N9
REFCLKP N10
PCI EXPRESS PHY
TEST CONTROLLER
B11 R0
B10 TPCPS
C4162
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
FW643E
BGA
OMIT
0.1UF
C4171
1
VREG_PWR
U4100
FW643_R0
FW643_TPCPS
TP_FW643_OCR10_CTL
1
VP25
CRITICAL
(IPD) NT-19
(IPD) NT-20
(IPD) NT-21
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
VP
VREG_VSS
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
37
37
B13 ATBUSB
A13 ATBUSH
A11 ATBUSN
VDDH
VDD33
L12
NC
NC
NC
C1
C12
F1
G12
J1
L3
L11
M2
A1
B1
B12
C13
E2
E10
H2
H12
K2
L1
M12
N3
N11
PLACEMENT_NOTE=Place C4170 close to U1400

PLACEMENT_NOTE=Place C4171 close to U1400
C4170
1
FireWire LLC/PHY(FW643E)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
41
109
Page Notes
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
FireWire Port Power Switch

(NONE)
CRITICAL

- FW_PORT_FAULT_PU
CRITICAL
R4260
C4260 1
470K
1.5A-24V
8
7
6
5
3
2
1
PWRDI5
F4260
SOI-HF
=PPBUS_S5_FWPWRSW
D4260
CRITICAL
Q4260
NDS9407
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
1812L15024HF
PPBUS_FW_FWPWRSW_D
VOLTAGE=12.6V
=PPBUS_S5_FW_FET
PDS540XF
0.01uF
5%
1/16W
MF-LF
2 402
20%
16V
CERM 2
402
FWPWR_EN_L_DIV
1
R4261
330K
5%
1/16W
MF-LF
2 402
FWPWR_EN_L
Enables port power when machine
is running or on AC.
Q4261 D
SSM6N15FEAPE
Q4261
D 3
SSM6N15FEAPE
SOT563
SOT563
2
42 41 33 21
64 41 33 21
IN
SMC_ADAPTER_EN
IN
PM_SLP_S3_L
S 1
S 4
FW_PORTPWR_EN_FET
C
Q4262
SSM3K15FV
D 3
SOD-VESM-HF
36
S 2
FW_PORTPWR_EN
Late-VG Event Detection

37 8
37
=PP3V3_FW_LATEVG
PP2V4_FW_LATEVG
R42111
10K
5%
1/16W
MF-LF
402 2
R4212
2
4
V+
FWLATEGV_3V_REF
100pF
5%
50V
CERM 2
402
V-
5%
1/16W
MF-LF
2 402
D4219
LATEVG_EVENT_L
SOD-123
2
1
MBR0540XXH
FW_PORTPWR_EN
1
36
C4219
0.33UF
10%
2 10V
CERM-X5R
603
R4213
80.6K
1%
1/16W
MF-LF
2 402
2.0M
LMC7211
C4211 1
R4219
U4210
SM-HF
1
20%
2 10V
CERM
402
1%
1/16W
MF-LF
2 402
P2V4_FWLATEVG_RC
C4210
0.1UF
10K
R4210
1
200K 2
1%
1/16W
MF-LF
402
FWLATEVG_3V_REF Hysteresis:
2.95V when port power is on
2.81V on late Vg event and port power is off
FireWire Port Power


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
42
109
Page Notes
=PP3V3_FW_PHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
R43811
10K
1%
1/16W
MF-LF
402 2
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
R43821
R43801
10K
10K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FireWire PHY Config Straps

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
FWPHY_DS0
=FW_PHY_DS0
35
=FW_PHY_DS2
35
=FW_PHY_DS1
35
MAKE_BASE=TRUE
FWPHY_DS2
MAKE_BASE=TRUE
Configures PHY for:

- 1-port Portable Power Class (0)
FWPHY_DS1
MAKE_BASE=TRUE
OUT

(NONE)
NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
35
35
74 35
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
SOT-363
Place close to FireWire PHY

FW_P1_TPBIAS
0.33UF
35
PPVP_FW_CPS
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS
FW_P0_TPB_N
FW_P0_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
35
Cable Power
5%
1/16W
MF-LF
402 2
C4360
74 35
470K
74 35
35
=PPVP_FW_PHY_CPS_FET
R43111
35
NC_FW0_TPBIAS MAKE_BASE=TRUE
NC_FW2_TPBIAS MAKE_BASE=TRUE
NC_FW0_TPAN MAKE_BASE=TRUE
NC_FW0_TPAP MAKE_BASE=TRUE
NC_FW2_TPAN MAKE_BASE=TRUE
NC_FW2_TPAP MAKE_BASE=TRUE
35
35
Q4300
(SYM-VER2)
Termination
BSS8402DW
74 35
FW_P0_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_N
FW_P0_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
10%
2 6.3V
CERM-X5R
402
CRITICAL
L4310
5%
1/16W
MF-LF
402 2
1
37 36
C4311 1
56.2
0.01uF
1%
1/16W
MF-LF
2 402
Q4300
1%
1/16W
MF-LF
402 2
35 8
=PP3V3_FW_FWPHY
74 35
FW_P1_TPA_P
FW_PORT1_TPA_P
74 35
FW_P1_TPA_N
FW_PORT1_TPA_N
C4310 1
(SYM-VER1)
0.01uF
10%
50V 2
X7R
402
37
37
MAKE_BASE=TRUE
FW_PORT1_TPB_P
FW_P1_TPB_P
37
MAKE_BASE=TRUE
74 35
FW_P1_TPB_N
FW_PORT1_TPB_N
R4362
56.2
1%
1/16W
MF-LF
2 402
37
FW_PORT1_TPA_P
37
FW_PORT1_TPA_N
37
FW_PORT1_TPB_P
37
FW_PORT1_TPB_N
37
MAKE_BASE=TRUE
1
CRITICAL
R4363
56.2
PORT 1
CRITICAL
BAV99DW-X-G
SOT-363
MAKE_BASE=TRUE
74 35
3
4
DP4310
BSS8402DW
SOT-363
5
10%
50V 2
X7R
402
56.2
10%
2 50V
X7R
402
BAV99DW-X-G
C4314
0.01UF
DP4310
PP2V4_FW_LATEVG
CPS_EN_L
R43611
VOLTAGE=33V
"Snapback" & "Late VG" Protection
330K
R4360
=PPVP_FW_PORT1
SM
R43121
FERR-250-OHM NOTE: TRACE PPVP_FW_PORT1 MUST HANDLE UP TO 1A

1
2
PPVP_FW_PORT1_F
CPS_EN_L_DIV
SOT-363
2
FL4320
TCM2010-100-4P
J4300
SM
1394A-MG3-K36
F-RT-TH
74
FW_PORT_A_P
74
FW_PORT_A_N
74
TPA-
FW_PORT_B_P
74
1%
1/16W
MF-LF
402 2
TPA+
FW_PORT_B_N
TPB+
POWER
FW_PORT1_TPB_C
C4316
DP4311
SOT-363
2
1
C4364 R4364
4.99K
220pF
5%
2 25V
CERM
402
1%
1/16W
MF-LF
402 2
0.01uF
10%
50V 2
X7R
402
BAV99DW-X-G
SOT-363
5
10%
50V 2
X7R
402
36 8
=PP3V3_FW_LATEVG
1%
1/16W
MF-LF
402
PP2V4_FWLATEVG needs to be biased

to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail
PP2V4_FW_LATEVG
VOLTAGE=2.4V
3
=GND_CHASSIS_FW_DOWN
Late-VG Protection
Power
R4390
A
=GND_CHASSIS_FW_UPPER
C4313 1
0.01uF
332 2
10%
50V 2
X7R
402
DP4311
6
C4312 1
GROUND
0.01uF
BAV99DW-X-G
1
FireWire Ports
ESD and late-VG rail

for snap-back diodes
D4390
MMBZ5227BLT1H (Common to all ports)
CRITICAL

SOT23

SIZE
DRAWING NUMBER
REV.
051-8089
SCALE
SHT
NONE
SYNC_DATE=(MASTER)
36 37
APPLE INC.
TPB-
02
OF
43
109
CRITICAL
Q4590
6
FDC606P_G
38 8
10K
=PP3V3_S0_ODD
R4595
ODD_PWR_EN_LS5V_L
R45971
Q4596
100K 2
10%
10V
2 CERM
402
C4596
0.01UF
ODD_PWR_SS
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402 2
C4595
0.068UF
5%
1/16W
MF-LF
402 2
D 6
1 2
R45961
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.
ODD Power Control
=PP5V_S0_ODD
SOT-6
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
ODD_PWR_EN
2
D 3
Q4596
S 1
SSM6N15FEAPE
SOT563
5
21
S 4
ODD_PWR_EN_L
IN
SATA ODD Port

CRITICAL
J4500
2-1775184-0
FL4520
90-OHM-100MA
M-ST-SM
NC
38 8
SYM_VER-1
71 7
R45901
33K
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_N
SATA_ODD_R2D_P
5%
1/16W
MF-LF
402 2
41
71
SATA_ODD_D2R_UF_N
10% 16V CERM
71
20 71
SATA_ODD_R2D_C_N
IN
20 71
402
90-OHM-100MA
DLP11S
SYM_VER-1
SATA_ODD_D2R_N
OUT
20 71
SATA_ODD_D2R_P
OUT
20 71
402
SATA_ODD_D2R_UF_P
10% 16V CERM
0.01UF
IN
FL4525
PLACEMENT_NOTE=Place C4525 next to C4526

PLACEMENT_NOTE=Place C4526 close to J4500
C4525
SATA_ODD_R2D_C_P
402
402
CRITICAL
PLACEMENT_NOTE=PLACE FL4525 CLOSE TO J4500
SATA CONNECTOR
C4520
10% 16V CERM
1
2 C4521
SATA_ODD_R2D_UF_N
10% 16V CERM
0.01UF
PLACEMENT_NOTE=Place FL4520 close to J4500
C4526
NC
0.01UF
516S0719
1
SATA_ODD_R2D_UF_P
0.01UF
=PP3V3_S0_ODD
PLACEMENT_NOTE=Place C4521 next to C4520

PLACEMENT_NOTE=Place C4520 close to MCP79
DLP11S
CRITICAL
3
SMC_ODD_DETECT
Indicates disc presence
OUT
PLACE L4501 NEAR J4501

CRITICAL
VALUE=3900PF IN REFERENCE SCHEM

CAPS TO BE SAME DISTANCE
FROM SB WITHIN EACH PAIR
L4501
DLP11S
SATA_HDD_R2D_UF_N
20
SATA_HDD_R2D_C_N
IN
71 20
J4501
20247-019E
F-ST-SM
SATA_HDD_R2D_C_P
C4501
2
0.01UF
402
SATA_HDD_R2D_UF_P
C4503
90-OHM-100MA
1
CRITICAL
518S0390
IN
20 71
0.01UF
402
SYM_VER-1
71 7
SATA_HDD_R2D_P
SATA_HDD_R2D_N
C4500
2
71 7
SATA_HDD_D2R_N
71 7
C4502
L4590 FERR-70-OHM-4A
7
8
9
0.01UF
402
1
PP5V_S0_HDD_FLT
=PP5V_S0_HDD
0603
NC
1
11
12
2
13
C4590
0.1UF
10%
16V
X5R
402
20 71
402
OUT
NO STUFF
NO STUFF
10
SATA_HDD_D2R_P
0.01UF
8
OUT
71 20
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
71 7
C4591
10UF
20%
6.3V
X5R
603
14
15
16
17
18
19
NC
NC
NC
SYSTEM (SLEEP) LED FILTER
21
R4522
10
1
SYS_LED_ANODE_L
1
C4522
0.01UF
10%
16V
CERM
402
SYS_LED_ANODE
42
5%
1/16W
MF-LF
402
SATA Connectors
PLACE R4522 AND C4522 NEAR J4501
IR_RX_OUT
OUT
7 40
R4550
100
(TO IR RECEIVER)
7
PP5V_S3_IR_CONN
C4550
4.7UF
20%
=PP5V_S3_IR

8 40
5%
1/16W
MF-LF
402

PLACE R4550 AND C4550 NEAR J4501
6.3V
CERM
603
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
45
109
Port Power Switch
Left USB Port A

PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
L4605
U4690
FERR-220-OHM-2.5A
TPS2064DGN
8
20
OUT
=PP5V_S3_EXTUSB
USB_EXTA_OC_L
8
3
20
OUT
64
IN
USB_EXTB_OC_L
=USB_PWR_EN
OUT1 7
IN
PP5V_S3_RTUSB_A_ILIM
VOLTAGE=5V
MSOP
OC1*
OUT2
EN1
C4605
PP5V_S3_RTUSB_B_ILIM
0.01uF
VOLTAGE=5V
OC2*
20%
16V
CERM
402
EN2
C4690
10UF
20%
6.3V
X5R
603
CRITICAL
C4695
0.1UF
10UF
20%
10V
CERM
402
J4600
CRITICAL
USB-K36-MG3
F-RT-TH
5
90-OHM
DLP0NS
SYM_VER-1
C4691
OMIT
CRITICAL
L4600
GND TPAD
1
2
PP5V_S3_RTUSB_A_F
VOLTAGE=5V
0603
20%
6.3V
X5R
603
C4696
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
C4617
10UF
20%
6.3V
X5R
603
72
USB2_EXTA_MUXED_N
72 3
USB2_EXTA_F_N
C4616
100UF
72
USB2_EXTA_MUXED_P
72 2
USB2_EXTA_F_P
20%
2 6.3V
POLY-TANT
CASE-B2-SM
VBUS
D-
D+
GND
NC
IO
NC
IO
2
6 VBUS
514-0527
1 GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1
2
0603
USB/SMC Debug Mux
0.01uF
2
C4615
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
VOLTAGE=5V
20%
16V
CERM
402
OMIT
CRITICAL
=PP3V42_G3H_SMCUSBMUX
J4601
SMC_DEBUG_YES
SMC_DEBUG_YES
C4650
10K
0.1UF
F-RT-TH
CRITICAL
L4610
90-OHM
5%
1/16W
MF-LF
2 402
DLP0NS
SYM_VER-1
20%
10V
CERM
402
USB-K36-MG3
R4650
72 20
BI
USB_EXTB_N
72
72
VCC
43 42 41 7
IN
OUT
SMC_RX_L
SMC_TX_L
5 M+SMC_DEBUG_YESY+ 1
4 MY- 2
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
72 20
BI
USB_EXTB_P
U4650
BI
72 20
BI
VBUS
D-
D+
GND
PI3USB102ZLE
72 20
TQFN
6 VBUS
514-0527
NC
IO
NC
IO
43 42 41 7
USB2_EXTB_F_N
USB2_EXTB_F_P
CRITICAL
SEL 10
8 OE*
USB_DEBUGPRT_EN_L
1 GND
IN
41
SEL=0 Choose SMC

SEL=1 Choose USB
D4610
GND
RCLAMP0502N
SLP1210N6
CRITICAL
SMC_DEBUG_NO
R4651
1
0
5%
1/16W
MF-LF
402
Left USB Port B
SMC_DEBUG_NO
R4652
0
1
2
5%
1/16W
MF-LF
402
External USB Connectors

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
46
109
IR CTRL
BLUETOOTH
38 8 =PP5V_S3_IR

1
L4810
PLACE C4810 C4811 NEAR 120-OHM-0.3A-EMI

L4810
C4801
0.1UF
10%
16V
X7R-CERM
402
=PP3V3_S3_BT
0402-LF
1
C4810
10UF
20%
6.3V
2 X5R
C4811
0.1UF
20%
10V
2 CERM
402
16
603
72 20
BI
72 20
BI
NET_SPACING_TYPE=USB
DIFFERENTIAL_PAIR=USB2_IR
NET_PHYSICAL_TYPE=USB_90D
VDD
DIFFERENTIAL_PAIR=USB2_IR
NET_PHYSICAL_TYPE=USB_90D
NET_SPACING_TYPE=USB
USB_IR_P
14
USB_IR_N
15
IR_VREF_FILTER
18
20
C4803
1UF
10%
10V
X5R
402-1
23
24
25
26
P1_0/D+
P1_1/DP1_2/VREG
P1_3/SSEL
P1_4/SCLK
P1_5/SMOSI
P1_6/MISO
P1_7
P0_0
P0_1
P0_2/INT0
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
OMIT
P0_7
J4810
22
P3_0
P3_1
CY7C63833
QFN
P2_0
P2_1
IR_RX_OUT_RC
1
1
10
C4804
DLP0NS
SYM_VER-1
IR_RX_OUT
IN
7 38
9
5%
1/16W
MF-LF
402
=USB2_BT_N
72 7
72 7
0.001UF
8
2
=USB2_BT_P
10%
50V
CERM
402
NC
NC
PP3V3_S3_BT_F_CONN1
2
USB2_BT_F_N_CONN
3
USB2_BT_F_P_CONN
4
7 GND_BT_F_CONN
TO M13D SLOT
518S0521
11
28
29
100
32
SB HAS INTERNAL 15K PULL-DOWNS
R4800
L4812
90-OHM
CRITICAL
P/N 338S0375
27
M-RT-SM
CRITICAL
U4800
21
78171-0004
CRITICAL
12
17
30
19
31
L4811
120-OHM-0.3A-EMI
13
33
THRM_PAD VSS
1
0402-LF
CYPRESS ENCORE II USB CONTROLLER
Front Flex Support

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
48
109
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
42
50 42 8
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
D
C4902
22UF
20%
6.3V
CERM
805
U4900
42
42
OUT
64 26 7
IN
64
IN
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
P10
P11
P12
P13
P14
P15
P16
P17
NC
21
OUT
60
OUT
21
OUT
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
42
OUT
ESTARLDO_EN
SMC_P24
NC
42
SMC_P26
NC
72 43 19 7
BI
72 43 19 7
BI
72 43 19 7
BI
72 43 19 7
BI
72 43 19 7
IN
26
IN
72 26
43 19 7
IN
BI
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
P30
P31
P32
P33
P34
P35
P36
P37
42
44
BI
50
OUT
(OC)
NC
NC
42
OUT
42
OUT
43 42 41 39 7
OUT
43 42 41 39 7
44
IN
BI
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
0.1UF
C4904
C4905
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
0.1UF
0.1UF
20%
10V
CERM
402
C4906
20%
10V
CERM
402
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_PM_G2_EN
64
OUT
NC
NC
NC
SMC_VCL
R4999
1
SMC_ADAPTER_EN
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P80
P81
P82
P83
P84
P85
P86
SMC_WAKE_SCI_L
IN
42
IN
42
IN
46
IN
45
IN
42
IN
42
IN
46
IN
45
IN
46
IN
42
OUT
21
4.7
5%
1/16W
MF-LF
402
21 33 36 42
OUT
NC
P70
P71
P72
P73
P74
P75
P76
P77
P90
P91
P92
P93
P94
P95
P96
P97
P40
P41
P42
P43
P44
P45
P46
P47
NC
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
LGA-HF
(1 OF 3)
OMIT
P20
P21
P22
P23
P24
P25
P26
P27
NC
NC
NC
42
P60
P61
P62
P63
P64
P65
P66
P67
H8S2117
C4903
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
C4907
1
10%
6.3V
CERM-X5R
402
0.1UF
20%
10V
CERM
402
AVCC
VCC
VCL AVREF
NC
42
42
NC
LGA-HF
(3 OF 3)
OMIT
IN
R4909 1
U4900
H8S2117
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12

PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12
43 42 7
0.47UF
C4920
SMC_RESET_L
RES*
SMC_XTAL
SMC_EXTAL
XTAL
EXTAL
MD1
MD2
R4901
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
7 43
SMC_NMI
IN
7 43
SMC_TRST_L
IN
7 43
SMC_KBC_MDE
NMI
NC
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
OUT
7 19 43
IN
7 19 43
OUT
7 39 41 42 43
IN
7 39 41 42 43
ETRST
1
VSS
44
BI
XW4900
SM
42 49
IN
IN
42 56 57
IN
42 56
IN
21 33 36 64
IN
21 42 64
IN
42
IN
26 72
NOTE: P94 and P95 are shorted, P95 could be spare.
NO STUFF
AVSS
R4902
R4998
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
GND_SMC_AVSS
42 45 46
44
BI
P50
P51
P52
(OC)
U4900
21
SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
SMC_PA5
42
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT
21
OUT
(DEBUG_SW_1)
(DEBUG_SW_2)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
42
42
26
39
29 28 21
B
56 42
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
38 7
IN
42
OUT
42
IN
42
IN
42
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_PB3
SMC_EXCARD_CP
NC
48
OUT
42
OUT
42
OUT
42
OUT
48
IN
42
IN
42
IN
42
IN
50
IN
50
IN
50
IN
42
IN
46
IN
46
IN
42
IN
42
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_MCP_CORE_ISENSE
SMC_MCP_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
H8S2117
LGA-HF
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
IN
42
IN
7 42 43
IN
7 42 43
OUT
7 42 43
IN
7 42 43
NC
SMC_SYS_LED
SMC_LID
42
OUT
42 49 56
IN
NC
NC
SMC_MCP_SAFE_MODE
OUT
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
IN
44
BI
44
BI
44
BI
44
BI
44
BI
SMC_PROCHOT
SMC_THRMTRIP
SMC_FWE
ALS_GAIN
42
BI
OUT
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
44
42
OUT
42
IN
42
OUT
42
NC
NC
SMC

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
49
109
7
SMC Reset "Button" / Brownout Detect
41
SMC_FAN_1_CTL
41
SMC_FAN_1_TACH
SMC FSB to 3.3V Level Shifting
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
NO_TEST=TRUE
50 42 41 8 =PP3V3_S5_SMC
SMC_FAN_2_CTL
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
C5000
CRITICAL
20%
10V
CERM
402
NCP303LSN
SOT23-5-HF
5
SMC_MANUAL_RST_L
NO STUFF
1
SILK_PART=SMC_RST
NO STUFF
NC
CD
NC
GND
R5001
R5002
5%
1/10W
MF-LF
603
5%
1/10W
MF-LF
603
C5001
SMC_FAN_2_TACH
41
SMC_FAN_3_CTL
OUT
IN
NC_SMC_FAN_2_TACH
R5060
NO_TEST=TRUE
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
=PP1V05_S0_SMC_LS
5%
NO_TEST=TRUE
1/16W
MF-LF
41
SMC_FAN_3_TACH
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
NO_TEST=TRUE
R5061
SMC_RESET_L
OUT
SMC_GFX_OVERTEMP_L
7 41 43
TP_SMC_GFX_OVERTEMP_L
TO SMC
402
SMC_PROCHOT_3_3_L
3.3K
41
NO_TEST=TRUE
470
1K
U5000
41
MAKE_BASE=TRUE
R5000
0.1uF
=PP3V3_S0_SMC
42 8
41
OUT
41
5%
MAKE_BASE=TRUE
1/16W
MF-LF
41
SMC_GFX_THROTTLE_L
SMC_IG_THROTTLE_L
21
MAKE_BASE=TRUE
402
Q5060
5
CPU_PROCHOT_BUF
3
57 56 42 41
0.01UF
SMC_BC_ACOK
BC847BV-X-F
SOT563-HF
=CHGR_ACOK
MAKE_BASE=TRUE
10%
16V
CERM
402
41
ALS_GAIN
NC_ALS_GAIN
TO CPU
3.3K
69 60 14 10
BI
CPU_PROCHOT_L
R5062
MAKE_BASE=TRUE
SILK_PART=SMC_RST
Q5060
CPU_PROCHOT_L_R
BC847BV-X-F
SOT563-HF
5%
1/16W
PLACE R5015,R5001 ON BOTTOM SIDE

PLACE R5016,R5002 ON TOP SIDE
MF-LF
402
6
41
SMC_PB3
41
SMC_P24
NC_SMC_PB3
Q5059
SSM6N15FEAPE
MAKE_BASE=TRUE
SOT563
TP_SMC_P24
MAKE_BASE=TRUE
SMC Crystal Circuit
41
SMC_P26
41
SMC_P41
Debug Power "Button"
SMC_BMON_MUX_SEL
46
MAKE_BASE=TRUE
1
TP_SMC_P41
MAKE_BASE=TRUE
41
SMC_XTAL
2
5%
1/10W
MF-LF
603
15pF
1
SMC_XTAL_R
Y5010
20.00MHZ
5X3.2-SM
41
SILK_PART=PWR_BTN
15pF
1
SMC_EXTAL
41
ALS_RIGHT
41
ESTARLDO_EN
R5015
R5016
41
SMC_ANALOG_ID
41
SMC_SYS_KBDLED
OUT
41 42 49
SMC_PROCHOT
IN
41
TP_SMC_EXCARD_PWR_EN
5%
1/10W
MF-LF
603
5%
1/10W
MF-LF
603
OUT
PM_THRMTRIP_L
NO_TEST=TRUE
NC_ESTARLDO_EN
MAKE_BASE=TRUE
69 14 10
NC_ALS_RIGHT
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_ANALOG_ID
NO_TEST=TRUE
41
SOT563
NC_SMC_SYS_KBDLED
MAKE_BASE=TRUE NO_TEST=TRUE
=SMC_SMS_INT
Q5059
SSM6N15FEAPE
MAKE_BASE=TRUE
PLACE R5015,R5001 ON BOTTOM SIDE

PLACE R5016,R5002 ON TOP SIDE
SMS_INT_L
50
MAKE_BASE=TRUE
2
5%
50V
CERM
402
SMC_EXCARD_PWR_EN
NO STUFF
SILK_PART=PWR_BTN
SMC_ONOFF_L
NO STUFF
C5011
41
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
5%
50V
CERM
402
CRITICAL
SMC_RSTGATE_L
MAKE_BASE=TRUE
C5010
R5010
41
45
SMC_MCP_VSENSE
SMC_GPU_VSENSE
46
SMC_CPU_FSB_ISENSE
ALS_LEFT
41
41
SMC_THRMTRIP
IN
41
C
=PP3V3_S5_SMC
50 42 41 8
41
SMC_PA0
41
SMC_PA1
R5091
R5092
100K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMC AVREF Supply

CRITICAL
VR5020
49 42 41
SMC_ONOFF_L
SMC_LID
R5070
R5071
10K
56 49 41
100K
41
SMC_FWE
R5072
10K
REF3333
R5095
SOT23-3
=PPVIN_S5_SMCVREF
IN
OUT
PP3V3_S5_AVREF_SMC
41
41
VOLTAGE=3.3V
GND
OUT
SMC_EXCARD_OC_L
EXCARD_OC_L
IN
20
43 41 39 7
5%
1/16W
MF-LF
402
C5026
43 41 39 7
R5073
R5074
SMC_TX_L
SMC_RX_L
10K
100K
2.0K
C5020
C5025
100K
10K
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
ONEWIRE_PU
0.01UF
402
10%
16V
CERM
402
56 41
SYS_ONEWIRE
56 41
SMC_BS_ALRT_L
R5075
R5076
SMC_TMS
R5077
43 41 7
43 41 7
SMC_TDI
R5078
R5079
43 41 7
SMC_TCK
R5080
10K
SMC_BIL_BUTTON_L
R5081
R5087
10K
43 41 7
2
41
GND_SMC_AVSS
SMC_TDO
41 45 46
57 56 42 41
VOLTAGE=0V
SMC_BC_ACOK
10K
10K
470K
R5055
B
41
SMC_NB_MISC_ISENSE
10K
5%
1/16W
MF-LF
402
R5054
System (Sleep) LED Circuit

41
SMC_GPU_ISENSE
=PP5V_S3_SYSLED
41 36 33 21
41
R5031
2.37K
1%
1/16W
MF-LF
402
R5030
41
100
5%
1/16W
MF-LF
402
41
64 41 21
R5085
R5086
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5088
SMC_EXCARD_CP
R5090
PM_SLP_S5_L
10K
5%
1/16W
10K MF-LF
1
402
10K
10K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NEED TO TUNE VALUE FOR POWER SAVING
PM_SLP_S4_L
SYS_LED_ILIM
2
=PP3V3_S0_SMC
42 8
SOD
2SA2154MFV-YAE
SYS_LED_L_VDIV
Q5030
41
R5032
R5089
SMC_PA5
10K
5%
9.09K
SYS_LED_ANODE
1%
1/16W
MF-LF
402 2
OUT
1/16W
MF-LF
402
38
SMC Support
SYS_LED_L
Q5032
SSM3K15FV
SOD-VESM-HF
41
IN

SMC_SYS_LED

1

SIZE
DRAWING NUMBER
ADD NC ALIASES FOR FAN1 SIGNALS
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
50
109
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
43 8
8
72 41 19 7
BI
72 41 19 7
BI
Alternate SPI ROM Support
IN
43 7
72 41 19 7
OUT
42 41 7
OUT
26 7
51 43 8
R5144
IN
OUT
41 7
IN
41 7
OUT
42 41 39 7
=PP3V3_S5_LPCPLUS
=PP3V3_S5_ROM
IN
41 19 7
42 41 7
43 8
OUT
IN
LPC_AD<0>
LPC_AD<1>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
C5144
20%
2 10V
CERM
402
IN
1 Y+
2 Y-
SPI_CLK_R
72 43 21
SPI_MOSI_R
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
BI
BI
7 26 72
7 19 41 72
7 19 41 72
OUT
7 43
IN
7 43
IN
7 43
BI
7 19 41
IN
7 19 41
OUT
7 41 42
OUT
7 41 42
OUT
7 41 42
OUT
7 41
OUT
7 39 41 42
OUT
7 18
516S0573
9
72 43 21
0.1UF
10K
5%
1/16W
MF-LF
402 2
M-ST-SM
31
32
R5164
VCC
LPCPLUS
U5110
M+ 5
M- 4
SPI_ALT_CLK
SPI_ALT_MOSI
OUT
7 43
OUT
7 43
SPI_CLK_MUX
SPI_MOSI_MUX
OUT
43 51 72
OUT
43 51 72
43 8
PI3USB102ZLE
TQFN
10K
5%
1/16W
MF-LF
402 2
43 7
SPIROM_USE_MLB
10 SEL
D+ 7
D- 6
=PP3V3_S5_LPCPLUS
R5140 1
100K
5%
1/16W
MF-LF
402 2
OE* 8
GND
3
43 7
SPIROM_USE_MLB
=SPI_CS1_R_L_USE_MLB
BI
21
MAKE_BASE=TRUE
43 8
=PP3V3_S5_LPCPLUS
1
C5145
0.1UF
20%
10V
402
2 CERM
SPI_ALT_MISO
VCC
43 21
OUT
72 21
IN
1 Y+
2 Y-
SPI_MISO
SPI_CS0_R_L
LPCPLUS
U5120
M+ 5
M- 4
PI3USB102ZLE
TQFN
IN
D+ 7
D- 6
R5166
0
1
2 SPI_ALT_CS_L
5% 1/16W
MF-LF 402
SPI_MISO_MUX
LPCPLUS
SPI_MLB_CS_L_MUX
SPI_ALT_CS_L_MUX
OUT
IN
7 43
43 51 72
R5165
10 SEL
7 43
LPCPLUS
OE* 8
5%
402 1/16W MF-LF
SPI_MLB_CS_L
OUT
51
GND
R51611
20K
5%
1/16W
MF-LF
402 2
LPCPLUS_NO
R5160
1
=PP3V3_S5_ROM
8 43 51
5% 1/16W
MF-LF 402
SPI Bus Series Resistance Option

LPCPLUS_NO
R5156
72 51 43
OUT
33
SPI_CLK_MUX
72 51 43
OUT
R5158
IN
SPI_MISO_MUX
IN
21 43 72
SPI_MOSI_R
IN
21 43 72
R5157
SPI_MOSI_MUX
LPCPLUS_NO
72 51 43
SPI_CLK_R
LPCPLUS_NO
5%
1/16W
MF-LF
402
33
5%
1/16W
MF-LF
402
SPI_MISO
LPC+SPI Debug Connector

OUT
21 43
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
51
109
MCP79 SMBUS "0" CONNECTIONS
SMC "0" SMBus Connections
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
44 8
MCP79
U1400
(MASTER)
72 21 13 7
SMBUS_MCP_0_CLK
72 21 13 7
SMBUS_MCP_0_DATA
=PP3V3_S0_SMBUS_SMC_0_S0
8
R5200
R5201
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SO-DIMM "A"
SMC
J3100
(Write: 0xA0 Read: 0xA1)
U4900
(MASTER)
R5250
=I2C_SODIMMA_SCL
28
41
SMB_0_S0_CLK
75
=I2C_SODIMMA_SDA
28
41
SMB_0_S0_DATA
75
MAKE_BASE=TRUE
R5251
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP Temp
SMC
EMC1403-5: U5535
(Write: 0x98 Read: 0x99)
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
R5270 1
1K
5%
1/16W
MF-LF
402
=I2C_MCPTHMSNS_SCL
47
41
SMB_A_S3_CLK
75
=I2C_MCPTHMSNS_SDA
47
41
SMB_A_S3_DATA
75
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_A_S3
R5271
MINI-PCIE
1K
5%
1/16W
MF-LF
402
J3400
SMBUS_SMC_A_S3_SCL
I2C_MINI_PCIE_SCL
7 31
I2C_MINI_PCIE_SDA
7 31
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SO-DIMM "B"
J3200
(Write: 0xA2 Read: 0xA3)
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
C5250
5%
50V
CERM
402
C5251
5%
2 50V
CERM
402
22PF
29
22PF
C5270
5%
50V
2 CERM
402
22PF
5%
50V
CERM
402
29
C5250,C5251 close to Destination end
C5271
22PF
C5270,C5271 close to destination end
SMC "B" SMBus Connections
SMC "Battery A" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V3_S0_SMBUS_SMC_B_S0
R5280 1
MCP79 SMBUS "1" CONNECTIONS

41
SMB_BSA_CLK
75
R5281
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
1K
SMC
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
Battery
SMC
J6950
(See Table)
U4900
(MASTER)
=SMBUS_BATT_SCL
56
41
SMB_B_S0_CLK
MAKE_BASE=TRUE
44 8
41
SMB_BSA_DATA
75
R5260 1
75
R5261
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPU Temp
EMC1403-5: U5515
SMBUS_SMC_B_S0_SCL
=I2C_CPUTHMSNS_SCL
47
=I2C_CPUTHMSNS_SDA
47
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
=SMBUS_BATT_SDA
56
41
SMB_B_S0_DATA
MAKE_BASE=TRUE
75
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
HDCP ROM
MCP79
U1400
(MASTER?)
72 21
R5230 1
R5231
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_MCP_1_CLK
U2690 OR U2695
(Write: 0xA0-0xAE,
Read: 0xA1-0xAF)
(All 8 addresses used)
=I2C_HDCPROM_SCL
Battery Charger
ISL6258A - U7000
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
25
MAKE_BASE=TRUE
72 21
SMBUS_MCP_1_DATA
=I2C_HDCPROM_SDA
C5280
25
MAKE_BASE=TRUE
Battery Manager - (Write: 0x16 Read: 0x17)

Battery Temp - (Write: 0x90 Read: 0x91)
5%
50V
CERM
402
5%
50V
2 CERM
402
C5260
5%
50V
CERM
402
5%
50V
2 CERM
402
22PF
57
C5281
22PF
Battery
57
22PF
C5261
22PF
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
8
=PP3V3_S3_SMBUS_SMC_MGMT
R5290 1
SMC
4.7K
U4900
(MASTER)
B
41
5%
1/16W
MF-LF
402 2
SMB_MGMT_CLK
75
R5291
Vref DACs
4.7K
U2900
5%
1/16W
MF-LF
2 402
SMBUS_SMC_MGMT_SCL
=I2C_VREFDACS_SCL
27
=I2C_VREFDACS_SDA
27
MAKE_BASE=TRUE
41
SMB_MGMT_DATA
75
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
Margin Control
U2901
=I2C_PCA9557D_SCL
27
=I2C_PCA9557D_SDA
27
SMS
U5930
=I2C_SMS_SCL
=I2C_SMS_SDA
SMBUS CONNECTIONS

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
52
109
CPU Voltage Sense / Filter

XW5309
R5309
SM
8
=PPVCORE_S0_CPU_VSENSE
4.53K
CPUVSENSE_IN
SMC_CPU_VSENSE
PLACEMENT_NOTE=Place near U1000 center
1%
1/16W
MF-LF
402
41
0.22UF
2
OUT
C5309
20%
6.3V
X5R
402
GND_SMC_AVSS
41 42 45 46
Place RC close to SMC
MCP Voltage Sense / Filter

XW5359
R5359
SM
8
=PPVCORE_S0_MCP_VSENSE
MCPVSENSE_IN
4.53K
PLACEMENT_NOTE=Place near U1400 center
1%
1/16W
MF-LF
402
SMC_MCP_VSENSE
OUT
42
C5359
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
41 42 45 46
C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
PBUSVSENS_EN_L
R5316 1
64
IN
=PBUSVSENS_EN
100K
1%
1/16W
MF-LF
402
Enables PBUS VSense

divider when high.
1
3
PPBUS_G3HRS5_VSENSE
VOLTAGE=18.5V
5
8
R5385 1
27.4K
1%
1/16W
MF-LF
402
=PPBUS_G3HRS5
RTHEVENIN = 4573 OHMS
P-CHANNEL
SMC_PBUS_VSENSE
OUT
41
R53151
100K
1%
1/16W
MF-LF
402
R5386
1
1
5.49K
1%
1/16W
MF-LF
402
PBUSVSENS_EN_L_DIV
C5385
0.22UF
2
2
20%
6.3V
X5R
402
GND_SMC_AVSS
41 42 45 46
VOLTAGE SENSING

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
53
109
MCP VCore Current Sense

=PP5VR3V3_S0_MCPCOREISNS
R5490
C5415
0.1uF
0.001
1
IN =PPVCORE_S0_MCP_REG_R
3
10V
2 CERM
61
OUT
U5400
8 22 24 61
5 IN-
ISNS_PVCORES0MCP_N
MCP VCore Current Sense Filter
DC-IN (AMON) CURRENT SENSE
SC70
R5471
R5416
INA213
4 IN+
ISNS_PVCORES0MCP_P
CPU VCORE LOAD SIDE CURRENT SENSOR / FILTER
V+
402
2 =PPVCORE_S0_MCP
4
20%
1%
1W
MF
1206
OUT
4.53K1
SMC_MCP_CORE_ISENSE
MCPCORE_IOUT 2
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402
REF 1
60
OUT
41
IMVP6_IMON
IN
1%
1/16W
MF-LF
402
C5472
0.22UF
GND
2
R5481
6.19K2
SMC_CPU_ISENSE
R5480
17.4K
20%
6.3V
X5R
402
41
57
IN
4.53K2
CHGR_AMON
SMC_DCIN_ISENSEOUT
1%
1/16W
MF-LF
402
C5470
0.22UF
1%
1/16W
MF-LF
402 2
GND_SMC_AVSS
OUT
41
C5487
0.22UF
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
41 42 45 46

GND_SMC_AVSS 41
GND_SMC_AVSS 41
42 45 46
42 45 46
MCP MEM VDD Current Sense

8
1
3
2 10V
CERM
OUT
5 IN4 IN+
ISNS_P1V5S0MCP_P
OUT 6
MCPDDR_IOUT
4.53K1
SMC_MCP_DDR_ISENSE
OUT
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402
REF 1
0.01
R5417
INA210
SC70
=PP3V3_S0_CPUVTTISNS
R5492
U5401
ISNS_P1V5S0MCP_N
MCP MEM VDD Current Sense Filter
V+
402
2 =PP1V8_S0
4
41
8
IN
2
4
=PPBUS_G3H_CPU_ISNS_R
C5435
20%
6.3V
X5R
402
GND_SMC_AVSS
1 =PPBUS_G3H_CPU_ISNS
3
0.22UF
GND
C5417
0.1uF
0.5%
1W
MF
0612
OUT
20%
10V
CERM
402
IN
=PP1V8_S0_FET_R
20%
1%
1/4W
MF
1206
8
C5416
0.1uF
0.002
CPU 1.05V CURRENT SENSE
=PP3V3_S0_MCPDDRISNS
R5491
V+
U5402
ISNS_CPUVTT_N
5 IN-
ISNS_CPUVTT_P
4 IN+
R5418
INA213
SC70
OUT
6CPUVTT_IOUT
4.53K1
SMC_CPU_FSB_ISENSE
1%
1/16W
MF-LF
402
REF 1
C5436
0.22UF
41 42 45 46
GND
20%
6.3V
X5R
402
42
OUT
1
GND_SMC_AVSS
41 42 45 46
CHARGER BMON CURRENT SENSE

8
=PP3V42_G3H_BMON_ISNS
B
1
ENG_BMON
ENG_BMON
C5418
U5413
0.1uF
1 B1
BMON_INAOUT
V+
402
IN
LOAD SIDE
CHGR_CSO_R_P
5 IN-
2 GND
INA213
SC70
SEL 6SMC_BMON_MUX_SEL
IN
OUT
IN
4 IN+
CHGR_CSO_R_N
REGULATOR SIDE
ENG_BMON
42
VCC 5
R5401
0
57
20%
10V
2 CERM
402
U5403
57
SC70
C5459
0.1UF
NC7SB3157P6XG
3
20%
2 10V
CERM
ENG_BMON
1
REF 1
57
IN
CHGR_BMON
4
B0
VER 1
PROD_BMON
GND
2
R5423
R5431
1
BMON_AMUX_OUT
100K
4.53K2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
SMC_BATT_ISENSE
41
C5490
0.22UF
ENG_BMON
OUT
ENG_BMON
1
20%
6.3V
X5R
402
GND_SMC_AVSS
41 42 45 46
STUFF EITHER R5431 OR U5413 DEPENDING ON BMON CURRENT SENSING METHOD
Current Sensing

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
54
109
CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
R5515
8
=PP3V3_S0_CPUTHMSNS
47
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
1
1
VDD
10
CPU_THERMD_P
BI
U5515
C5521
R5517
10K
5%
1/16W
MF-LF
402
DP1
THERM*
CPUTHMSNS_THERM_L
DN1
ALERT*
CPUTHMSNS_ALERT_L
DP2/DN3
SMDATA
CRITICAL
DN2/DP3
SMCLK
GND
=I2C_CPUTHMSNS_SDA
BI
44
10
=I2C_CPUTHMSNS_SCL
BI
44
2
4
CPU_THERMD_N
BI
TSSOP
10K
5%
1/16W
MF-LF
402
20%
10V
CERM
402
0.0022uF
10%
50V
CERM
402
10
R5516 1
0.1uF
EMC1403-1-AIZL
SIGNAL_MODOL=EMPTY
DETECT CPU DIE TEMPERATURE
C5515
CPUTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
1
PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520
0.0022uF
10%
50V
CERM
402
DETECT HEAT-PIPE TEMPERATURE

7
CPUTHMSNS_D2_N
MCP T-Diode Thermal Sensor

J5520
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
78171-0004
M-RT-SM
5
NC
47
PP3V3_S0_MCPTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
1
2
1
1
VDD
3
4
21
MCP_THMDIODE_P
BI
C5522
NC
DETECT MCP DIE TEMPERATURE
EMC1403-1-AIZL
10%
50V
CERM
402
TSSOP
20%
10V
CERM
402
R5537
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
DP1
THERM*
MCPTHMSNS_THERM_L
DN1
ALERT*
MCPTHMSNS_ALERT_L
DP2/DN3
SMDATA
CRITICAL
DN2/DP3
SMCLK
GND
=I2C_MCPTHMSNS_SDA
BI
44
10
=I2C_MCPTHMSNS_SCL
BI
44
2
4
MCP_THMDIODE_N
BI
R5536 1
0.0022uF
518S0521
21
C5535
0.1uF
U5535
SIGNAL_MODOL=EMPTY
R5535
=PP3V3_S0_MCPTHMSNS
MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
C5540
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
10%
50V
CERM
402
DETECT FIN-STACK TEMPERATURE

7
MCPTHMSNS_D2_N
Thermal Sensors

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
55
109
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
R5660 1
J5601
78171-0004
47K
5%
1/16W
MF-LF
402
R5665
41
SMC_FAN_0_TACH
M-RT-SM
NC
1 47K 2
FAN_RT_TACH
5%
1/16W
MF-LF
402
FAN_RT_PWM
5
1
2
3
4
NC
5V DC
TACH
MOTOR CONTROL
GND
R5661 1
518S0521
100K
SMC_FAN_0_CTL
41
5%
1/16W
MF-LF
402
Q5660
SSM3K15FV
SOD-VESM-HF
Fan

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
56
109
- SYNC WITH T18

- COPY THIS PAGE FROM T18 CSA.58
PLACEMENT NOTE
D
PLACE L5800,L5801,L5803 NEAR J5800

PLACE C5800,C5810,C5803 NEAR J5800
PLACE D5800 NEAR J5800
GEYSER
8
IN
L5802
=PP5V_S3_TPAD
VOLTAGE=5V
600-OHM-300MA
0402
1
PP5V_S3_TPAD_F
L5804
600-OHM-300MA
0402
C5860
0.1UF
20%
10V
CERM
402
TPAD_GND_F
VOLTAGE=0V
R5810
42 41
OUT
SMC_ONOFF_L
1
1
C5810
0.1UF
1K
CONN_TPAD_ONOFF_FLTR_L
5%
1/16W
MF-LF
402
20%
10V
2 CERM
402
CRITICAL
J5800
53307-8610
F-ST-SM
CRITICAL
L5801
=USB2_TPAD_N
1
72 7
CONN_TPAD_USB_N
72 7
NC
CONN_TPAD_USB_P
SYM_VER-2
DLP0NS
90-OHM
2
4
10
L5803
NC
NC
600-OHM-300MA
0402
7
SMC_LID_LC
SMC_LID
IN
41 42 56
NC
2 5 3 4
6 VBUS
NC
IO
NC
IO
BI
=USB2_TPAD_P
1
3
BI
(CONN_TPAD_USB_P)
(CONN_TPAD_USB_N)
516S0727
C5803
0.01uF
10%
2 16V
CERM
1 GND
402
D5800
RCLAMP0502N
SLP1210N6
CRITICAL
PLACE D5800 CLOSE J5800
GEYSER

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
58
109
D
42 41 8
=PP3V3_S5_SMC
R59321
10K
5%
1/16W
MF-LF
402
42
SMSINT_L SHOULD BE PULL UP IF NOT USED.

2
SMS_INT_L
ANALOG SMS
8
=PP3V3_S3_SMS
1
1
14
R5920
10K
5%
1/16W
MF-LF
402 2
C5920
0.1uF
2
VDD
U5920
C5926
10UF
20%
10V
CERM
402
20%
6.3V
2 X5R
603
AP344ALH
LGA
41
IN
SMS_ONOFF_L
1 FS
5 PD
2 ST
SMS_PWRDN
MAKE_BASE=TRUE
SMS_SELFTEST
R5921
10K
NC
NC
NC
3 NC
6 NC
9 NC
SMS_X_AXIS
OUT
41
VOUTY 10
SMS_Y_AXIS
OUT
41
VOUTZ 8
SMS_Z_AXIS
OUT
41
CRITICAL
NC 11
NC 13
NC 16
GND
7
5%
1/16W
MF-LF
2 402
NC
15 RES
4 RES
VOUTX 12
NC
NC
NC
C5904
C5905
0.01UF
20%
16V
CERM
402
20%
16V
CERM
402
Desired orientation when
Desired orientation when
placed on board top-side:
placed on board bottom-side:
Package Top
C5906
0.01UF
20%
16V
CERM
402
Top-through View
+Y
0.01UF
+Y
+X
Front of system
+X
+Z (up)
+Z (down)
SMS

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
59
109
43 8
=PP3V3_S5_ROM
NO STUFF
10K
5%
1/16W
MF-LF
402 2
R6101
3.3K
3.3K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
C6100
0.1UF
20%
10V
CERM
402
R61901 R61001
CRITICAL
VCC
OMIT
U6100
PLACEMENT_NOTE=PLACE CLOSE TO U6100

72 43
43
SPI_CLK_MUX
IN
R6152
SOP
SPI_CLK
5%
1/16W
MF-LF
402
SPI_MLB_CS_L
IN
32MBIT
R6150
6 SCLK
SI/SIO0 5
MX25L3205DM2I-12G
1 CE*
SPI_WP_L
SPI_HOLD_L
SPI_MOSI
R6105
7 HOLD*
72
GND
4

SPI_MOSI_MUX
IN
43 72
5%
1/16W
MF-LF
402
SO/SIO1 2
3 WP*/ACC
NO STUFF
1
R6191
10K
SPI_MISO_R 2
33

SPI_MISO_MUX
OUT
43 72
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
MCP79 SPI Frequency Select

Frequency
SPI_MOSI
SPI_CLK
42 MHz
25 MHz
1 MHz
31 MHz
25MHZ IS SECLECTED WITH R5164 AND R5144

ANY FO THE 4 FREQUENCIES CAN BE SELECTED
WITH R6190, R6191, R5164 AND R5144
SPI ROM
SYNC_DATE=081/17/2008

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
61
109
AUDIO CODEC
APPLE P/N 353S1538
L6202
VOLTAGE=4.5V
FERR-220-OHM
PP4V5_AUDIO_ANALOG
D
52
0402
VOLTAGE=3.3V
2
0402
52
CODEC_DVDD
AVDD_ADC_DAC
CRITICAL
CRITICAL
C6200 1
1UF
C6201
0.001UF
10%
0.001UF
10%
2 50V
CERM
402
6.3V
CERM 2
10%
2 50V
CERM
402
72 21
IN
NO STUFF
52
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT
R6204
R6270
100K
72 21
5%
1/16W
MF-LF
2 402
OUT
53
R6271
6
10
5
8
10K
55
5%
1/16W
MF-LF
2 402
55
53
53
HDA_SDIN0
39
CODEC_SDATA_IN
SYNC
SDATA_OUT
SPDIFI/EAPD/MIDI-I/DMIC-R
10%
2 50V
CERM
402
U6200
SDATA_IN
20%
2 50V
CERM
402
AUD_SPDIF_O
48
47
0.001UF
=GND_AUDIO_CODEC
39
9 52 53 54 55
AUD_SPDIF_OUT 54
5%
1/16W
MF-LF
402
13
34
REV B3
GPIO0/DMIC-CLK
GPIO1/DMIC-L
PORT-A-L
PORT-A-R
39
41
PORT-F-L
16 NO_TEST
17 NO_TEST
30 NO_TEST
33
14 NO_TEST
15 NO_TEST
31 NO_TEST
28
21
22
NC_AUD_BI_PORT_F_L
NC_AUD_BI_PORT_F_R
NC_AUD_VREF_PORT_F
29 NO_TEST
32 NO_TEST
NC_AUD_VREF_PORT_C
NC_AUD_VREF_PORT_D
AUD_BI_PORT_C_L
AUD_BI_PORT_C_R
23
24
PORT-C-L
PORT-C-R
AUD_BI_PORT_D_L
AUD_BI_PORT_D_R
35
36
PORT-D-L
PORT-F-VREFO
PORT-A-VREFO/DCVOL
PORT-D-R
PORT-E-L
NO_TEST18
NO_TEST19
NO_TEST20
BEEP
PORT-F-R
CD-L
PORT-E-R
PORT-E-VREFO
CD-GND
CD-R
PORT-B-VREFO
PORT-B-L
12
BEEP
11
RESET*
PORT-B-VREFO2
AUD_SPDIF_I
AUD_SENSE_A
AUD_SENSE_B
CRITICAL
54
55
55
43 NO_TEST
44
PORT-H-L
PORT-H-R
45 NO_TEST
46 NO_TEST
49
AVSS2
VREF
AVSS1
10%
16V
2 X5R
402
JDREF
NC
AUD_VREF_PORT_A
55
AUD_VREF_PORT_B
AUD_BI_PORT_B_L
AUD_BI_PORT_B_R
55
55
55
NC_AUD_BI_PORT_G_L
AUD_BI_PORT_G_R
53
NC_AUD_BI_PORT_H_L
NC_AUD_BI_PORT_H_R
AUD_CODEC_VREF
27
40 AUD_CODEC_JDREF
37 NC_VRP
1
R6209
100K
5%
1/16W
MF-LF
2 402
R6205
NO_TEST
20.0K
1%
1/16W
MF-LF
2 402 CRITICAL
NO STUFF
1
R6201
5%
1/16W
MF-LF
2 402
C6212
0.001UF
C6210
10%
16V
TANT
SMA-HF1
3.3UF
0
=GND_AUDIO_CODEC
55
55
NC_AUD_BI_PORT_E_L
NC_AUD_BI_PORT_E_R
NC_AUD_VREF_PORT_E
26
42
0.1UF
5%
1/16W
MF-LF
2 402
DVSS
C6208
100K
THRM_PAD
R6203
4
7
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R
PORT-G-R
PORT-G-L
HDA_RST_L
55 54 53 52 9
20%
6.3V 2
POLY-TANT
CASE-B2-SM
150UF
SENSE_A
SENSE_B
PORT-C-VREFO
C6207
C6205 1
CRITICAL
PORT-B-R
IN
20%
6.3V 2
POLY-TANT
CASE-B2-SM
0.001UF
QFN
2
3
NC_BAL_IN_L
NC_BAL_IN_COM
NC_BAL_IN_R
72 21
R6206
SPDIFO
ALC885Q-VB3-GR
5%
1/16W
MF-LF
402
AUD_GPIO_0
AUD_GPIO_1
BCLK
AVDD1
IN
DVDD
IN
72 21
DVDD_IO
CODEC_DVDD
72 21
CRITICAL
C6206
C6204 1
150UF
1
9
402
C6203
25
38
55 54 52 8
L6201
FERR-220-OHM
AVDD2
VOLTAGE=3.3V
=PP3V3_S0_AUDIO
10%
50V
2 CERM
402
VOLTAGE=0V
AUDIO 4.5V REGULATOR

APPLE P/N 353S1576
U6201
L6200
FERR-220-OHM
=PP5V_S0_AUDIO
AUD_4V5_REG_IN
1
2
8
0402
R6202
=PP3V3_S0_AUDIO
1K
OUT1
OUT2
NR/FB
GND THRM_PAD
PP4V5_AUDIO_ANALOG
3
4
5
4V5_REG_FB
NC
5%
1/16W
MF-LF
402
R6210
80.6K
AUD_REG_SHDN_L
6
55 54 52 8
LREG_TPS79501DRB
SON
IN1
IN2
EN
1%
1/16W
MF-LF
2 402
55 8
VOLTAGE=5V
52
C6224
15PF
5%
50V
2 CERM
402
CRITICAL
C6221
1
C6220
0.1UF
10%
16V
2 X5R
402
10UF
20%
6.3V 2
X5R
603
C6223
0.001UF
VOUT=1.2246V*[1+(R6210/R6211)]=4.58V
10%
2 50V
CERM
402
R6211
PLACE R6210, R6211, AND C6224 CLOSE TO U6201
AUDIO: CODEC
29.4K
1%
1/16W
MF-LF
2 402
SYNC_MASTER=K36A_MLB

55 54 53 52 9
=GND_AUDIO_CODEC
NO STUFF
R6200
1
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
62
109
SATELLITE
& SUB TWEETER AMPLIFIER
APN:353S1595
SATELLITE
169 HZ < FC < 282 HZ
SUB
GAIN
80 HZ < FC < 132 HZ

12DB
D
53
53 8
VOLTAGE=5V
=PP5V_S0_AUDIO_AMP
5%
1/16W
MF-LF
402
AUD_SPKRAMP_INR_L
10%
6.3V
CERM 2
402
53
1
VDD
MAX9705_R_N
2 IN+
3 IN-
OUTSYNC
5 SHDN*
AUD_SPKRAMP_SHUTDOWN_L
SPKRAMP_R_N_OUT
R6661
2
53
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
53
GND PGND PAD

7
4
11
53
SPKRAMP_L_P_OUT
R6670
2
53
53
=PP5V_S0_AUDIO_AMP
PP5V_S0_AUDIO_F
SPKRAMP_L_N_OUT
CRITICAL
53
10%
6.3V
CERM 2
402
C6620
AUD_SPKRAMP_INL_L
0.047UF
0402
SPKRCONN_L_P_OUT
C
OUT
7 54
1UF
10%
6.3V
CERM 2
402
10
PVDD
U6620
SPKRCONN_L_N_OUT
OUT
7 54
5%
1/16W
MF-LF
402
C6603
47UF
20%
POLY
CASE-B3-SM1
LEFT SATELLITE
2 6.3V
MAX9705
TDFN1
AUD_SPKRAMP_INL
2 IN+
3 IN-
MAX9705_L_N
10%
16V
X7R
402
1
VDD
1uF
R6671
CRITICAL
C6608 1
5%
1/16W
MF-LF
402
SPKRAMP_THERMPLANE
FERR-1000-OHM
7 54
53
=GND_AUDIO_CODEC
AUD_BI_PORT_D_L
OUT
20%
POLY
CASE-B3-SM1
=GND_AUDIO_AMP
IN
SPKRCONN_R_N_OUT
C6601
THRML
CRITICAL
L6620
2 6.3V
8
9
C6604 1
52
7 54
5%
1/16W
MF-LF
402
53
10%
16V
X7R 2
402
53 8
SPKRCONN_R_P_OUT
OUT
47UF
10%
6.3V
CERM 2
402
OUT+
CRITICAL
C6611 1
53 9
TDFN1
10%
16V
X7R
402
1UF
10
PVDD
U6610
0.047UF
55 54 53 52 9
MAX9705
0.047UF AUD_SPKRAMP_INR
0402
RIGHT SATELLITE
C6602
1uF
C6610
FERR-1000-OHM
AUD_BI_PORT_D_R
R6660
CRITICAL
C6607 1
CRITICAL
L6610
PP5V_S0_AUDIO_F
VOLTAGE=5V
R6600
IN
SPKRAMP_R_P_OUT
5%
1/16W
MF-LF
402
53
52
OUT+
OUT-
CRITICAL SYNC
5 SHDN*
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
53
53
THRML
GND PGND PAD
4
11
7
CRITICAL
C6621
0.047UF
10%
16V
X7R 2
402
55 54 53 52 9
=GND_AUDIO_CODEC
53 9
=GND_AUDIO_AMP
53 8
=PP5V_S0_AUDIO_AMP
53
SPKRAMP_THERMPLANE
CRITICAL
C6606
C6609 1
IN
2
0402
L6611
52
IN
AUD_GPIO_0
0.1UF
1
U6630
MAX9705_SUB_N
2 IN+
3 IN-
OUT+
OUTCRITICAL SYNC
5 SHDN*
R6680
2
SPKRCONN_SUB_P_OUT
OUT
7 54
C6605
53
8
9
SPKRAMP_SUB_N_OUT
120UF
R6681
2
SPKRCONN_SUB_N_OUT
OUT
7 54
5%
1/16W
MF-LF
402
20%
POLY-TANT
CASE-B2-SM
2 6.3V
SUB-TWEETER
SPKRAMP_SUB_P_OUT 53
SPKRAMP_SUB_N_OUT 53
THRML
GND PGND PAD
R66101
4
53
11
CRITICAL
C6631 1
10K
5%
1/16W
MF-LF
402 2
53 9
10%
6.3V
CERM 2
402
10
PVDD
MAX9705
0402
55 54 53 52 9
1UF
TDFN1
AUD_SPKRAMP_INSUB
10%
16V
X5R
402
FERR-1000-OHM
1
10%
6.3V
CERM 2
402
C6630
AUD_SPKRAMP_INSUB_L
1
VDD
1uF
CRITICAL
L6630
FERR-1000-OHM
52
SPKRAMP_SUB_P_OUT
5%
1/16W
MF-LF
402
PP5V_S0_AUDIO_F
AUD_BI_PORT_G_R
53
53
0.1UF
10%
16V
X5R 2
402
=GND_AUDIO_CODEC
SPKRAMP_THERMPLANE
53
AUDI0: SPEAKER AMP
=GND_AUDIO_AMP
53 9 =GND_AUDIO_AMP
XW6600
SM
1
SPKRAMP_THERMPLANE

53

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
66
109
MIC CONNECTOR
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX
CRITICAL
APN:518S0392
J6701
48227-0303
L6790
M-RT-SM
4
FERR-220-OHM
55 52 8
=PP3V3_S0_AUDIO
IN
0402
L6700
AUD_CONNJ1_SLEEVE
PP3V3_S0_AUDIO_SPDIF
52
54 7
L6701
FERR-120-OHM-1.5A
54
54 7
FERR-120-OHM-1.5A
AUD_CONNJ1_SLEEVE_F
0402-LF
55 54 7
MIC_LO_CONN
MIC_HI_CONN
MIC_SHLD_CONN
AUD_CONNJ1_TIPDET
F-RT-TH-HF
2
3
SWITCH
4
RIGHT
VCC
GND
VIN
SHLD_PIN
SHLD_PIN
AUD_CONNJ1_TIP
0402
8
9
L6707
AUD_CONNJ1_TIP_F
AUD_CONNJ1_SLEEVEDET
GND_AUDIO_SPDIF_DGND
0405
CRITICAL
6.8V-100PF
R6791
0
NO STUFF
2
CRITICAL
402
DZ6701
DZ6705
6.8V-100PF
6.8V-100PF
402
402
1
0405
2
1
2
BI
78171-0004
55
M-RT-SM
5
10K
AUD_J1_SLEEVEDET_R
OUT
55
53 7
IN
53 7
IN
53 7
IN
53 7
IN
SPKRCONN_SUB_P_OUT
SPKRCONN_SUB_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT
4.7
1
2
3
4
APN:518S0521
AUD_J1_TIPDET_R
OUT
55
5%
1/16W
MF-LF
402
CRITICAL
DZ6703
5.6V-15A
5%
1/16W
MF-LF
402
AUD_PORTA_L
R6701
402
DZ6702
1
DZ6704
6.8V-100PF
5.6V-15A
1UF
SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
5%
1/16W
MF-LF
402
CRITICAL
DZ6700
10%
2 6.3V
CERM
402
IN
J6703
R6700
AUD_CONNJ1_SLEEVEDET_F
NO STUFF
C6700
IN
53 7
CRITICAL
0402
53 7
0402
FERR-1000-OHM
10
55
FERR-1000-OHM
BI
L6706
FERR-1000-OHM
1
7
AUD_PORTA_R
0402
L6705
AUD_CONNJ1_RING
54
0402
APN:514-0604
HF APN:514-0521
54
FERR-1000-OHM
AUD_CONNJ1_RING_F
M-RT-SM
3
APN:518S0519
L6704
FERR-1000-OHM
1
J6702
78171-0002
L6703
DETECT FOR PLUG TYPE
CRITICAL
SPEAKER CONNECTOR
0402
AUDIO-OUT-K36-MG3
GROUND
AUD_CONNJ1_TIPDET_F
J6700
FERR-1000-OHM
OMIT
CRITICAL
0402-LF
L6702
LEFT
AUD_SPDIF_OUT
XW6705
SM
C6705
=GND_CHASSIS_AUDIO_JACK
CHASSIS_AUDIO_JACK_ISOL
54
100PF
5%
2 50V
CERM
402
XW6700
SM
AUD_J1_COM
XW6701
SM
AUD_J2_COM
54
10
AUD_SPDIF_I
OUT
5%
1/16W
MF-LF
402
PP3V3_S0_AUDIO_SPDIF
L6750
CRITICAL
LEFT
RIGHT
GROUND
SHLD_PIN
SHLD_PIN
10
L6754
FERR-1000-OHM
MIC_HI
55
AUD_PORTC_R
BI
OUT
MIC_HI_CONN
7 54
0402
55
0402
CRITICAL
L6755
L6756
FERR-1000-OHM
1
AUD_CONNJ2_TIP_F
0402
AUD_PORTC_L
DZ6770
6.8V-100PF
BI
402
55
CRITICAL
0402
2
L6757
AUD_CONNJ2_SLEEVEDET
AUD_CONNJ2_SLEEVEDET_F
0402
C6750
1UF
10%
2 6.3V
CERM
402
NO STUFF
20%
6.3V
2 X5R
603
GND_AUDIO_SPDIF_DGND
DZ6751
10uF
0405
2
NO STUFF
CRITICAL
CRITICAL
6.8V-100PF
402
1
R6740
0
4.7
AUD_J2_TIPDET_R
OUT
55
54
5%
1/16W
MF-LF
402
402
1
6.8V-100PF
402
0405
2
DZ6755
DZ6754
6.8V-100PF
5.6V-15A
402
DZ6752
DZ6750
CRITICAL
6.8V-100PF
54 55
5%
1/16W
MF-LF
2 402
R6751
CRITICAL
DZ6753
5.6V-15A
MIC_SHLD_CONN 7
402
5%
1/16W
MF-LF
402
C6751
10K
DZ6771
6.8V-100PF
R6750
FERR-1000-OHM
54
7 54
L6772
FERR-1000-OHM
AUD_CONNJ2_RING_F
2
0402
MIC_LO_CONN
0402
FERR-1000-OHM
APN:514-0603
HF APN:514-0519
54
AUD_CONNJ2_TIPDET_F
FERR-1000-OHM
AUD_CONNJ2_RING
5
1
7
6
OUT
0402-LF
L6753
AUD_CONNJ2_TIP
AUD_CONNJ2_TIPDET
8
VCC
GND
MIC_LO
0402
2
4
VOUT
FERR-1000-OHM
FERR-1000-OHM
F-RT-TH-HF
SWITCH
L6752
J6750
AUDIO-IN-MG3-K36
DETECT FOR PLUG TYPE
L6770
FERR-120-OHM-1.5A
0402-LF
OMIT
52
L6751
FERR-120-OHM-1.5A
1
2
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_SLEEVE
9 52 53 55
MIC EMI FILTER
R6749
1
=GND_AUDIO_CODEC
55
AUD_J2_OPT_OUT
C6756
AUDIO: JACK
100PF
5%
2 50V
CERM
402

AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
67
109
CODEC OUTPUT SIGNAL PATHS

FUNCTION
HP OUT
SAT SPKR
SUB SPKR
SPDIF OUT
VOLUME
0X0F (15)
0X26 (38)
0X0E (14)
N/A
CONVERTER
0X05 (5)
0X25 (37)
0X04 (4)
0X06 (6)
PIN COMPLEX
0X15 (21,PORTA)
0X14 (20,PORTD)
0X16 (22,PORTG)
0X1E (30,SPDIF OUT)
MUTE CONTROL
VREF_A(100%)
GPIO 0
GPIO 0
N/A
DET ASSIGNMENT
0X15 (21,PORTA)
N/A
N/A
0X1B (27,PORTE)
CODEC INPUT SIGNAL PATHS

FUNCTION
LINE IN
MIC IN
SPDIF IN
MIXER
0X23 (35)
0X24 (36)
N/A
VOLUME
0X08 (8)
0X07 (7)
N/A
MUTE CONTROL
0X08 (8)
0X07 (7)
N/A
CONVERTER
0X08 (8)
0X07 (7)
0X0A (10)
PIN COMPLEX
0X1A (26,PORTC)
0X18 (24,PORTB)
0X1F (31,SPDIF IN)
VREF
N/A
VREF_B (80%)
N/A
DET ASSIGNMENT
0X1A (26,PORTC)
N/A
N/A
HP/LO DE-POP SWITCH

APN:353S1459
52 8
PORT A HP/LO
=PP5V_S0_AUDIO
CRITICAL
C6830
100UF
1
1
1
52
OUT AUD_SENSE_B
55 52
OUT AUD_SENSE_A
55
PP3V3_S0_AUDIO_F
AUD_OUTJACK_INSERT_L
R6801
5%
1/16W
MF-LF
2 402
Q6801
5
47K
1
39.2K
39.2K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
S 4
NC
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
C6801
MAX9890_OUTL
MAX9890_OUTR
1%
1/16W
MF-LF
402
C6831
100UF
IN
52
8 MAX9890_CEXT
1
1
10%
16V
2 X5R
402
AUD_PORTA_R
OUT
54
6.3V
POLY-TANT
CASE-B2-SM
27.4K
10K
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R6835
R6839
C6835
0.1UF
2
20%
AUD_VREF_PORT_A
D 3
=GND_AUDIO_CODEC
55 54 53 52 9
S 1
S 4
16V
10%
X5R
402
PLACE L6800/C6800 CLOSE TO Q6800
=GND_AUDIO_CODEC
L6800
R6803
1
PP3V3_S0_AUDIO_F
R6861
270K
5%
1/16W
MF-LF
2 402
100K 2
5%
1/16W
MF-LF
402
FERR-1000-OHM
AUD_J1_SLEEVEDET_INV
54 52 8
=PP3V3_S0_AUDIO
PP3V3_S0_AUDIO_F
55
0402
Q6800
D 6
55 54
AUD_J1_SLEEVEDET_R
10%
SOT563
2
55 54 53 52 9
C6800
0.1UF
SSM6N15FEAPE
AUD_J1_SLEEVEDET_R
IN
CEXT
THM
PAD
27.4K
0.1UF
2
55 54
OUTR
54
OUT
AUD_J1_DET_RC
5%
1/16W
MF-LF
402
55
INL
GND
NC
R6834
TDFN
INRCRITICALOUTL
SHDN*
AUD_PORTE_DET_L
Q6801
D 6
6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
R6805
AUD_PORTA_DET_L
SOT563
R6802
AUD_J1_TIPDET_R
SSM6N15FEAPE
IN
AUD_BI_PORT_A_L
AUD_PORTA_L
U6801
R6806
D 3
Q6800
270K
55 54 53 52 9
2 6.3V
CERM
402
52
IN
10%
AUD_BI_PORT_A_R
54
IN
PORT E DETECT(SPDIF DELEGATE)
20%
VCC
1UF
52
PORT A DETECT
MAX9890BETA+
C6836
=GND_AUDIO_CODEC
16V
X5R
402
S 1
PORT C LI
MIC INPUT CIRCUITRY
CRITICAL
1
C6802
R6850
R6855
6.81K
2.2K
0.01UF
10%
16V
2 CERM
VREF_PORT_B_R
AUD_VREF_PORT_B
=GND_AUDIO_CODEC
1%
402
1/16W
MF-LF
5%
402
IN
AUD_PORTC_L
R6836
CRITICAL
C6853
27.4K
4.7UF
1%
1/16W
MF-LF
402
20%
6.3V
2 X5R-CERM
=GND_AUDIO_CODEC
54
IN
MIC_HI
R6813
C6851
5%
1/16W
MF-LF
402 2
R6811
50V
CERM
402
NC
5%
1/16W
MF-LF
2 402
54
IN
MIC_LO
47K
5%
1/16W
MF-LF
402
MIC_SHLD_CONN
C6811
XW6800
50V
CERM
402
IN
3.3UF
2
AUD_PORTC_R
AUD_BI_PORT_C_R
OUT
52
10%
16V
TANT
SMA-HF1
52
NO STUFF
PLACE C6852 NEAR U6200

2
=GND_AUDIO_CODEC
9 52 53 54 55
AUDIO: JACK TRANSLATORS
5%
1/16W
MF-LF
402
S 2
NO STUFF
402
0
2
=GND_AUDIO_CODEC
R6854
16V
1
55 54 53 52 9
5%
IN
0.1UF
10%
X5R
54
R6853
54 7
AUD_BI_PORT_B_R
100PF
AUD_J2_DET_RC
1
52
CRITICAL
C6833
2
NO STUFF
R6812
1
C6852
D 3
SOD-VESM-HF
AUD_J2_TIPDET_R
AUD_BI_PORT_B_L
MAKE_BASE=TRUE
CRITICAL
SM
Q6802
SSM3K15FV
CRITICAL
R6852
100K
10%
AUD_INJACK_INSERT_L
5%
1/16W
MF-LF
402
1
1
680PF
270K
IN
1%
1/16W
MF-LF
402
9 52 53 54 55
27.4K
10% 16V
X5R 402
CRITICAL
10K
PP3V3_S0_AUDIO_F
54
9 52 53 54 55
0.1uF
55
R6837
C6850
52
10%
16V
TANT
SMA-HF1
=GND_AUDIO_CODEC
Line-in (PORT C) DETECT

AUD_SENSE_A
1 AUD_BI_PORT_C_L
OUT
402
55 52
3.3UF
52
54
1/16W
MF-LF
402
55 54 53 52 9
C6832
=GND_CHASSIS_AUDIO_MIC

5%
1/16W
MF-LF
402

NO STUFF
R6856
0
1
SIZE
DRAWING NUMBER
5%
1/16W
MF-LF
402
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
68
109
CRITICAL
J6900
CRITICAL
78048-0573
F6905
M-RT-SM
Q6910 restricts system load to 10K-70K window until

adapter detects system and enables 16.5V output.
6AMP-24V
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
0
ADAPTER_SENSE 1
2
2
5%
1/16W
MF-LF
402
518S0656
Q6910
0.01UF
NTUD3127CXXG
1-Wire OverVoltage Protection
20%
50V
CERM
603
Vgs(max) = 8V
MIN_LINE_WIDTH=0.25mm
VOLTAGE=18.5V
R6928
SOT-963
PP18V5_DCIN_ONEWIRE
C6915
R6917 1
270K
0.1UF
MagSafe DC Power Jack
<Ra>
R6913 1
ADAPTER_SENSE_R
10%
25V
X5R
402
5%
1/16W
MF-LF
402
If ADAPTER_SENSE > Vth

then turn off FET
100K
5%
1/16W
MF-LF
402 2
ONEWIRE_DCIN_DIV
LM397
V+
<Vth>
<Rb>
R6914 1
SOT23-5-HF
4
ONEWIRE_OVERVOLT
Vgs = 7.30V @ 20V DCIN

Vgs = 4.74V @ 13V DCIN
V-
R6918 1
D 3
CRITICAL
Q6915
SSM3K15FV
470K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
S 2
270K
5%
1/16W
MF-LF
402
C6917
CRITICAL
0.001UF
2
2
10%
50V
CERM
402
N-CHN
NTUD3127CXXG
R6920
24.3K
C6910
0.001UF
47
5%
1/8W
MF-LF
805
10%
50V
CERM
402
CRITICAL
SMC_BC_ACOK
IN
41 42 57
5%
1/16W
MF-LF
402
SYS_ONEWIRE_BILAT
SYS_ONEWIRE
41 42
BI
SSM6N15FEAPE
SOT563
SOT563
SSM6N15FEAPE
D6905
R6905
=PP18V5_DCIN_CONN
Q6920
1K
SMC_BC_ACOK_RC
Q6920
1%
1/16W
MF-LF
2 402
R6910
SOT-963
VOLTAGE DIVIDER FROM DCIN ENSURES Q6910

Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure
SYS_ONEWIRE doesnt drive unpowered U6990
CRITICAL
Q6910
D
G
HN2D01JEAPE
3.425V "G3Hot" Supply
SOT665
PPDCIN_S5_P3V42G3H
VOLTAGE=18.5V
Supply needs to guarantee 3.31V delivered to SMC VRef generator

4
3
57 56
R6912 1
270K
ONEWIRE_PWR_EN_L
R6916 1
Vth = Vdcin * (Rb / (Ra + Rb))

Vth = Vdcin / 2
56 8
SOD-VESM-HF
3
ONEWIRE_ESD
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
U6915
5%
1/16W
MF-LF
402
ONEWIRE_PWR_EN_L_DIV
270K
CRITICAL
5
1
180K
ONEWIRE_EN
R6915 1
R6911 1
C6905
8 56
CRITICAL
1206
1
=PP18V5_DCIN_CONN
P-CHN

- DO WE NEED TO CHANGE BATTERY CONNECTOR?
BATT_POS_F
NC
VOLTAGE=12.6V
P3V42G3H_BOOST
PPVIN_G3H_P3V42G3H
NC
VOLTAGE=18.5V
C6990
3
VIN
10uF
10%
25V
X5R
1206-1
6
BOOST
C6994
20%
6.3V
X5R
402
LT3470ETS8
1
TSOT23-8
SHDN*
NC 2 NC
SW
BIAS
FB
CRITICAL
L6995
33UH
SWITCH_NODE=TRUE
GND
4
C6995
<Ra>
R6995 1
348K
22pF
MLB TOP VIEW

2
Vout = 3.425V
200mA max output
(Switcher limit)
CDPH4D19FHF-SM
PIN 1
=PP3V42_G3H_REG
P3V42G3H_SW
CRITICAL
LID HALL EFFECT SENSOR
0.22uF
U6990
1%
1/16W
MF-LF
402 2
5%
50V
CERM
402
C6999
22UF
P3V42G3H_FB
<Rb>
R6996 1
20%
6.3V
CERM
805
200K
1%
1/16W
MF-LF
402 2
BATTERY/LID CONNECTOR
L6901
Vout = 1.25V * (1 + Ra / Rb)
FERR-50-OHM
SM-LF
7
PPVBAT_G3H_CONN_F
BATT_POS_F
56 57
L6902
120-OHM-0.3A-EMI
L6909
600-OHM-300MA
0402
1
PP3V42_G3H_LIDSWITCH_F
NC
L6907
0402
GND_SMC_LID_F
L6908
VOID
10
12
11
14
13
16
15
18
17
20
19
SMBUS_BATT_SCL_F
NC
7
J6950
SMBUS_BATT_SDA_F
C6920
0.01uF
10%
16V
2 CERM
402
0402-LF
SMC_BS_ALRT_L_F
=SMBUS_BATT_SDA
44
L6904
120-OHM-0.3A-EMI
DC-In & Battery Connectors
0402-LF
CRITICAL
D6950
RCLAMP2402B
SMC_BS_ALRT_L
SYNC_MASTER=RAYMOND
41 42
SC-75
C6942
0.001UF
10%
50V
SMC_LID_F
C6921
44
120-OHM-0.3A-EMI
F-ST-SM
=SMBUS_BATT_SCL
L6903
2 CERM
8199-3520-M281
0402
SMC_LID
CRITICAL
600-OHM-300MA
49 42 41
600-OHM-300MA
1
0402-LF
APN:516S0620
HFAPN:516S0735
=PP3V42_G3H_LIDSWITCH
402
C6943
0.001UF
10%
50V
2 CERM
402
C6944
47pF
C6945
47pF
5%
50V

5%
50V
2 CERM
2 CERM
402
402

56 9
=GND_BATT_CHGND
0.01uF
10%
16V
SIZE
402
2 CERM
=GND_BATT_CHGND
APPLE INC.
9 56
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-8089
02
OF
69
109
PBUS SUPPLY / BATTERY CHARGER

Q7001
HAT1127H
LFPAK-SM
Q7000
CRITICAL
HAT1127H
LFPAK-SM
C7063
SOD-723-HF
R7098 1
100K
5%
0.1UF
10%
25V
X5R 2
402
R7010
R7001
62K
CHGR_SGATE
1/16W
MF-LF
402
57
57.6K
VCC
R7061 1
1.82K
57
0.1UF
R70111
57 8
9.31K
1%
2 CHGR_VDD 1
=PP3V42_G3H_CHGR
10V
X5R
402-1
57
CHGR_SCL
CHGR_SDA
NC
CHGR_ACIN
C7044 C7042
10%
16V
402
0.01UF 0.033UF
10%
16V
X5R
402
2 CERM
CHGR_ICOMP 5
CHGR_VCOMP 7
CHGR_VNEG 8
CHGR_CSOP 18
CHGR_CSON 17
1
R7045
ICOMP
VCOMP
VNEG
CSOP
CSON
C7043
56.2K
0.1UF
1%
1/16W
MF-LF
402 2
10%
16V
X5R
402
CHGR_VCOMP_R
C7045 1
1/16W
C7024 1
10%
10V
CERM
402
CHGR_BGATE
CHGR_DCIN 57
BOOT 25
UGATE 24
PHASE 23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
LGATE 21
CHGR_LGATE
5%
1/16W
MF-LF
402
R7020
0.02
XW7021
SM
2 CHGR_CSIN_XW7021 1
0.5%
1W
MF
2 0612
0.1UF
10%
25V
X5R
402
0.1UF
10%
25V
X5R
402
GND_CHGR_SGND 57
C7020
20%
25V
POLY-TANT
CASE-D2-SM
10%
25V
X5R
402
4.7UH-9.5A
1
NO STUFF
R7090
5%
EMI
1/16W
MF-LF
2 402
57
CHGR_VNEG_R
RJK0305DPB
request
57
C7011 1
1UF
C7008
10%
25V
2 X5R
20%
16V
POLY-TANT
CASED2E-SM
603-1
C7028
0.001UF
20%
50V
CERM
402
PWM FREQ. = 400KHZ

MAX CURRENT = 7 A
(??? LIMITED)
C7090
100PF EMI request
5%
1 2 3
LFPAK-HF
2 50V
CERM
402
GND_CHGR_SGND
R7031
10
470PF
(CHGR_CSON)
10
46
5%
1/16W
MF-LF
402
R7047
10%
50V
CERM 2
402
33UF
(CHGR_CSOP)
C7046 1
PPVBAT_G3H_CHGR_OUT
NO STUFF
Q7021
10%
2 50V
X7R
402
2
4
CHGR_PHASE_SNUBBER
CRITICAL
C7026
0.001UF
1
3
F7000
CRITICAL
IHLP4040DZ-SM
TO SYSTEM
=PPBUS_G3H
1206
0.5%
1W
MF
0612
PPVBAT_G3H_CHGR_REG
7AMP
0.01
L7000
1
20%
50V
CERM
402
MAX CURRENT = 7A
PWM FREQ. = 400 KHZ
R7008
CRITICAL
1 2 3
C7027
0.001UF
0.1UF
57
3.01K
1UF
CRITICAL
C7025 1
C7023
10%
25V
X5R
603-1
LFPAK-HF
1%
1/16W
MF-LF
402 2
C7022 1
1UF
10%
25V
X5R
603-1
RJK0305DPB
46
XW7000
SM
22UF
Q7020
R70461
C7021
20%
25V
2
POLY-TANT
CASE-D2-SM
CRITICAL
2.2
46 57
10%
50V
CERM 2
402
22UF
0.001UF
GND_CHGR_SGND
PP18V5_S5_CHGR_SW_R
CRITICAL
CRITICAL
C7061 1 C7062
TRKL* 13 NC
CHGR_AMON
CHGR_BMON
CHGR_ACOK
1CRITICAL
10
R7021
CHGR_AGATE
CHGR_CSIP
CHGR_CSIN
16
57
BGATE
DCIN 2
AMON 9
BMON 15
ACOK 14
XW7020
SM
2 CHGR_CSIP_XW7020 1
402
MF-LF
0.047UF
20
QFN
4 VREF
3 ACIN
29 THRM_PAD
U7000
U7060
R70235% 10
1UF
12 VHST
AGATE 1
11 SCL
CSIP 28
10 SDA CRITICALCSIN 27
ISL6258A
57
CHGR_LOWCURRENT_GATE
SOT23-5
VDDP
26
6 AGND
TL331
C7040
10%
2 10V
X5R
402-1
22 PGND
VDD
57
1UF
10%
10V 2
X5R
402-1
62K
CHGR_VDDP
5%
1/16W
MF-LF
402
1UF
10%
C7047 1
R7040
4.7
C7041
19
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CRITICAL
1%
1/16W
MF-LF
402
2
(CHGR_ACIN)
10%
25V 2
X5R
402
GND
3
CHGR_LOWCURRENT_REF
100K
5%
1/16W
MF-LF
402
2
CHGR_AMON
57 46
R7062 1
10%
25V
X5R
402
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
C7010 1
0.1UF
R7060
R7099
CHGR_LOWCURRENT_GATE_MOS
C7060
30.1K
1%
CHGR_DCIN
=PP3V42_G3H_CHGR
57 8
1/16W
MF-LF
402 2
1SS418
D7010
PPVDCIN_G3H_PRE
PPVDCIN_G3H_PRE2
CRITICAL
=PP18V5_G3H_CHGR
46
CHGR_CSO_R_P
CHGR_CSO_R_N
5%
1/16W
MF-LF
402
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC
57 8
CRITICAL
=PP3V42_G3H_CHGR
Q7070
ACOK pullup/down on SMC page

56 42 41
SMC_BC_ACOK
CHGR_ACOK
R70741
57
MAKE_BASE=TRUE
SSM6N15FEAPE
SOT563
D 6
1M
5%
1/16W
MF-LF
402 2
S 1
1/16W
MF-LF
402
2
Q7052
FDS6681Z
R70751
1M
5%
2 G
CRITICAL
Q7050
NO STUFF
57
PPVBAT_G3H_CHGR_OUT
1
C7050
0.01uF
C7051
0.1UF
10%
2 16V
X5R
402
SO-8
BATT_POS_INRUSH
CHGR_VDD_L
10%
16V
2 X5R
402
D 3
CHGR_BGATE
R7052
1M
5%
1/16W
MF-LF
402
SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008
CHGR_VDD
R7053
5 G
330K
S 4
5%
1/16W
MF-LF
402
1K

R70731
PBUS Supply/Battery Charger
BATT_POS_GATE
57
57
C7052
0.1UF
SSM6N15FEAPE
SOT563
56
Q7070
BATT_POS_F
10%
2 16V
CERM
402
TO BATTERY
FDS6681Z
SO-8
1 2 3
57
BATTERY CHARGING
CHGR_AMON
CHGR_SDA
57 46
5 6 7 8
57
5 6 7 8
CHGR_SCL
=SMBUS_CHGR_SDA
=SMBUS_CHGR_SCL
44
1 2 3
44
5%
1/16W
MF-LF
402 2

SIZE
CHGR_VDD_R
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
70
109
5V_RT/3.3V POWER SUPPLY

D
D
VOUT = (2 * RA / RB) + 2
ROUTING NOTE:
<RA>
<RB>
<RD>
<RC>
R7267
R7268
R7269
R7270
15.0K
10K
10K
6.49K
XW7203
Place XW7203 by Pin1 OF L7260.
5VRT_S0_VFB_XW7203
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
SM
2
VOUT = (2 * RC / RD) + 2
XW7204
1%
1/16W
MF-LF
402
SM
2
3V3S5_VFB_R7270
ROUTING NOTE:
Place XW7204 by Pin 2 of L7220.
58
GND_5VRT3V3S5_SGND
XW7205
2
ROUTING NOTE:
Place XW7205 by C7252.
SM
1
=PPVIN_S0_5VRTS0
58 8
ROUTING NOTE:
XW7202
C7272
1UF
SM
10%
2 25V
X5R
603-1
=PPVIN_S0_5VRTS0
5V3V3S5_REG3
8 58
50V
CERM
402
16V
POLY-TANT
CASED2E-SM
2 X5R
603-1
C7260
0.1UF
10%
16V
X5R
402
CRITICAL
Q7260
SI7110DN
PWRPK-1212-8-HF
L7260
1
0.001UF
20%
2 50V
CERM
402
C7290
10UF
20%
6.3V
2 X5R
603
C7291
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
1
21 DRVH1
2 VFB1
LL2 11
C7294
3 2
100PF
1 ENTRIP1
ENTRIP2 6
5%
50V
2 CERM
C7230
0.001UF
20%
50V
CERM
402
C7241
1UF
10%
2 25V
X5R
603-1
CRITICAL
C7240
33UF
20%
16V
POLY-TANT
CASED2E-SM
CRITICAL
Q7220
FDMS9600S
CRITICAL
MLP
PWM FREQ. = 375 KHZ

MAX CURRENT = 4A
L7220
4.7UH-5.5A
Q1
10
SW
5VRT_S0_VO2
EMI request
NO STUFF
IHLP2525CZ
R7295
2.2
3V3S5_ENTRIP
2
Q2
NC
PGOOD 23
EN0 13
GND THRM_PAD
1/16W
MF-LF
402
3V3S5DRVL
VO2 7
R7271
75K
1%
3V3S5_LL
VFB2 5 3V3S5_VFB
VCLK 18
4
PWRPK-1212-8-HF
DRVH2 10
DRVL2 12
SI7110DN
EMI request
NO STUFF
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
Q7261
5VRT_S0_LL_SNUBBER
C7292
5VRT_S0_ENTRIP
9 4 3 2
3V3S5_DRVH
QFN
10%
16V
X5R
402
3V3S5_VBST
U7200
24 VO1
5VRT_S0_VFB
CRITICAL
VREG3 8
VREG5 17 5V3V3S5_REG5
19 DRVL1
5VRT_S0_VO1
NO STUFF
R7294
C7220
0.1UF
VREF
22 VBST1 CRITICAL VBST2 9
20 LL1
5VRT_S0_DRVL
2.2
EMI request
C7233
5%
1/16W
MF-LF
2 402
CRITICAL
5VRT_S0_VBST
MIN_NECK_WIDTH=0.2 MM 5VRT_S0_LL
IHLP
603
4 TONSEL
CRITICAL
3.3UH
=PP5VRT_S0_REG
VOLTAGE=5V
3 2
402
2 6.3V
X5R
VIN
14 SKIPSEL
10%
2 10V
CERM
MIN_NECK_WIDTH=0.2 MM 5VRT_S0_DRVH
PWM FREQ. = 300 KHZ

MAX CURRENT = 4A
C7271
0.22UF
EMI request
10UF
20%
1
NC
C7273
10UF
20%
2 6.3V
X5R
603
25
0.001UF
20%
C7270
16
C7232
CRITICAL 1 C7281
C7280
1UF
10%
33UF
25V
20%
TPS51125
=PPVIN_S5_3V3S5
5VRTS3_3V3S5_VREF
15
EMI request
EMI request
3V3S5_LL_SNUBBER
1
R7272
EMI request
NO STUFF
75K
1%
2
=PP3V3_S5_REG
5%
1/16W
MF-LF
402
7 6 5
1/16W
MF-LF
402
C7295
100PF
5%
50V
C7231
0.001UF
20%
50V
CERM
402
CRITICAL CRITICAL
1
C7252
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
VOLTAGE=3.3V
C7251
C7250
10UF
20%
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
6.3V
2 X5R
603
2 CERM
402
402
58
GND_5VRT3V3S5_SGND
XW7201
SM
D 6
Q7221
SSM6N15FEAPE
P5V3V3_PGOOD
64
SOT563
ROUTING NOTE:
=P5VRTS0_EN_L
64
S 1
IN
Q7221
D 3
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE
5V/3.3V SUPPLY
SOT563
=P3V3S5_EN_L 5
64
IN
S 4

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
72
109
1.8V/0.9V(DDR2) POWER SUPPLY

D
VOUT = 0.75V * (1 + RA / RB)

NO STUFF
<RB>
1
2
1
2
1V8S3_VDDQSET
R7322
<RA>
C7303
20K
0.1%
100PF
R7321 5%
1/16W
MF
28K
402
27 8
=PPVTT_S3_DDR_BUF
1
1
50V
CERM
402
1%
1/16W
MF-LF
402
2
C7340
0.033UF
10%
16V
X5R
402
20%
2 6.3V
X5R
603
1V8S3_V5FILT
C7300
1UF
C7301
10UF
=PP5V_S3_1V8S3_0V9S0
R7307
C7302
10UF
4.7
5%
1/16W
MF-LF
402
10%
10V
X5R
402-1
20%
6.3V
X5R
603
=PP0V9_S0_REG
1V8S3_VDDQSNS
Place XW7301 by L7320.
R7310
10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
10
11
PGOOD
DRVH
LL
COMP
QFN
CS
ROUTING NOTE:
ROUTING NOTE:
20%
2 6.3V
X5R-CERM
603
C7308
22UF
20%
6.3V
2 X5R-CERM
603
19 1V8S3_DRVL
MODE
THRM_PAD
CS_GND
NC0
NC1
GND
PGND
VTTGND
C7307
22UF
DRVL
CONNECT CS_GND TO
Q7321 PIN1,2.3
USING KEVIN CONNECTION.
18
16
1V8S3_CS
21 1V8S3_DRVH
20 1V8S3_LL
TPS51116
17
SM
13
CRITICAL
25
S3
S5
U7300
SYM (1 OF 2)
1
=DDRREG_EN
XW7303
64
=DDRVTT_EN
5%
1/16W
MF-LF
402
VBST V5IN VDDQSNS VTTSNS
1%
1/16W
MF-LF
2 402
65 26
R7300
15
22
14
24
23
1V8S3_VBST
1V8S3_VBST_RC
ROUTING NOTE:
XW7301
SM
1V5S3_VTTSNS
CRITICAL
CRITICAL
Q7320
C7309
SI7110DN
0.1uF
10%
16V
X5R
402
SM-IHLP-1
1
EMI request
NO STUFF
1
MIN_LINE_WIDTH=1 mm
5
MIN_LINE_WIDTH=1 mm
1UF
33UF
20%
16V
POLY-TANT
CASED2E-SM
10%
2 25V
X5R
603-1
0.001UF
20%
50V
CERM
402
MAX CURRENT = 12A

PWM FREQ. = 400 KHZ
5%
1/16W
MF-LF
2 402
SI7108DN
PWRPK-1212-8-HF
1V8S3_LL_SNUBBER
EMI request
NO STUFF
1
2 3
PUT ONE BULK CAP NEXT TO THE LOAD
=PP1V8_S3_REG
CRITICAL
1
CRITICAL
2.2
20%
16V
POLY-TANT
CASED2E-SM
VOLTAGE=1.8V
2
R7390
CRITICAL
C7330
33UF
CRITICAL
L7320
1.0UH-13A-5.6M-OHM
MIN_LINE_WIDTH=1 mm
PWRPK-1212-8-HF
Q7321
7 NC
12 NC
=PPVIN_S5_1V8S3_0V9S0
CRITICAL
1 C7331
1 C7332
1 C7333
330UF
20%
2 2.5V
POLY-TANT
CASE-C2-SM1
C7341
10UF
20%
2 6.3V
X5R
603
20%
2 2.5V
POLY-TANT
CASE-D2E-SM
C7343
330UF
C7342
C7344
0.001UF
20%
50V
CERM
402
C7390
100PF
5%
50V
2 CERM
402
B
GND_1V8S3_SGND
XW7300
SM
ROUTING NOTE:
PUT 6 VIAS UNDER THE THERMAL PAD
GND_1V8S3_CSGND
R7399
100K
ROUTING NOTE:
Place XW7300 between
Pin 3 and Pin 25
of U7300.
1
XW7302
SM
DDRREG_PGOOD
5%
1/16W
MF-LF
402
2
=PP3V3_S3_PDCISENS
ROUTING NOTE:
Place XW7302 by Q7321.
STATE
PM_SLP_S4_L
PM_SLP_S3_L
PP1V8_S3
PP0V9_S0
S0
HIGH
HIGH
1.8V
0.9V
S3
HIGH
LOW
1.8V
0.0V
S5/G3HOT
LOW
LOW
0.0V
0.0V
1.8V/0.9V DDR2 SUPPLY


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
73
109
=PP5V_S0_CPU_IMVP
60 8
R7412
10
5%
1/16W
MF-LF
402
10%
6.3V
CERM
402
1
R7420
IN
2
8
=PP3V3_S0_IMVP1
0.1uF
69 11
69 11
69 11
2
1
R7445
C7410
499
ERT-J0EV474J
1%
1/16W
MF-LF
2 402
0.01uF
IMVP6_NTC_R
69
NO STUFF
69 11
69 11
69 11
R7447
R7406
46
5%
1/16W
MF-LF
IMVP_VR_ON
OUT VR_PWRGOOD_DELAY
41
IN
26
IMVP6_VR_TT
IMVP6_NTC
R7408
C7405
147K
1%
0.015uF
1/16W
MF-LF
402
10%
16V
X7R
402
60
60
QFN
2 PSI*
3 IMON
(NC)
IMVP6_SOFT
48 3V3
47 CLK_EN*
44 VR_ON
6 NTC
4 RBIAS
IMVP6_VDIFF
60
IMVP6_UGATE1
34
60
IMVP6_PHASE1
32
LGATE1
60
PHASE1
PGND1
60
C7406
R7409
1K
1%
1/16W
MF-LF
2 402
0.001UF
60
NO STUFF
60
R7413
60
1K
IMVP6_VDIFF_RC
1
R7411
60
1%
1/16W
MF-LF
402
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
UGATE2 27
60
IMVP6_UGATE2
PHASE2 28
60
LGATE2 30
60
19
60
VSEN
10 COMP
9 VW
RTN
18
60
16
60
17
60
(IMVP6_PHASE1)
C7413
220PF
5%
25V
CERM
402
R7414
C7407
0.001UF
10%
50V
CERM
402
C7400
20%
50V
CERM
402
R7400
C7403
R7404
0.22uF
1%
1/16W
MF-LF
402
402
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
C
1
C7431
0.068UF
10%
10V
CERM
402
60
1
C7408
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
C7411 1
1UF
10%
25V
X5R
603-1
C7422
0.001UF
20%
50V
CERM
402
R7401
3.65K
1%
1/16W
MF-LF
2 402
NO STUFF
CRITICAL
1
1 2 3
C7416
1
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
R7418 R7417
1K
20%
16V
POLY-TANT
CASED2E-SM
LFPAK-HF
IMVP6_DFB
15
C7401
33UF
8 60
RJK0305DPB
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
4.42K
1%
1/16W
MF-LF
402
C7429
180pF
5%
2 50V
CERM
402
(IMVP6_PHASE2)
RJK0328DPB
13.7K
MPC1055-SM
MPC1055LR36
DCR=0.8MOHM
R7491
LFPAK-HF
5%
1/16W
MF-LF
2 402
3.92K
C7434 1
C7428
10%
10.0V
CERM-X5R 2
402
10%
6.3V
CERM-X5R
402
0.22UF
R7415
11K
1%
1/16W
MF-LF
2 402
20%
50V
CERM
402
10K
R7407
0.22uF
1%
1/16W
MF-LF
402
C7491
C7404
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
100PF
5%
50V
NO STUFF
IMVP6_VO_R
CRITICAL
R7431
NO STUFF
2
2 CERM
C7402
402
0.0022UF
R7452
10K
R7443
3.65K
10%
50V
CERM
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
10KOHM-5%
R7405
EMI request
NO STUFF
1 2 3
1%
1/16W
MF-LF
2 402
C7423
0.001UF
2.2
1%
1/16W
MF-LF
2 402
R7430
0.36UH-30A-0.80MOHM
EMI request
NO STUFF
1
IMVP6_PHASE2_SNUBBER
L7401
CRITICAL
Q7403
R7416
0.12UF
CRITICAL
(IMVP6_VO)
(IMVP6_ISEN2)
0603-LF
2
C7433
(IMVP6_VSUM)
ERT-J1VR103J
0.018UF
97.6K
10K
2 CERM
10%
50V
CERM
402
=PPVIN_S5_CPU_IMVP
CRITICAL
CRITICAL
6.81K
1%
1/16W
MF-LF
2 402
C7490
5%
50V
0.0022UF
C7420
1/16W
MF-LF
402
Q7402
10%
16V
CERM
402
R7410
0.001UF
NO STUFF
R7451
10K
1%
100PF
NO STUFF
1
1
5%
1/16W
MF-LF
402
EMI request
NO STUFF
49
MPC1055LR36
DCR=0.8MOHM
2.2
10%
16V
2 X5R
402
10%
16V
X5R
402
MPC1055-SM
R7490
0.1UF
0.1UF
=PPVCORE_S0_CPU_REG
IMVP6_PHASE1_SNUBBER
C7415
1
C7427
0.36UH-30A-0.80MOHM
RJK0328DPB
IMVP6_ISEN2
C7432
Q7401
1 2 3
0.01UF
1
EMI request
NO STUFF
LFPAK-HF
PWM FREQ. = 300 KHZ

MAX CURRENT = 44A
L7400
CRITICAL
4
20%
50V
CERM
402
CRITICAL
IMVP6_LGATE2
(GND)
NO STUFF
(IMVP6_VW)
IMVP6_COMP_RC
1-PHASE DCM
IMVP6_PHASE2
14
TPAD
GND_IMVP6_SGND
VOLTAGE=0 V
470PF
1%
1/16W
MF-LF
2 402
60
60
10%
50V
CERM
402
20%
16V
POLY-TANT 2
CASED2E-SM
C7419
0.001UF
1 2 3
2
60
21
60
29
ISEN2 23
12 FB2
11 FB
GND
C7414
1UF
(IMVP6_ISEN1)
IMVP6_ISEN1
25 NC
(IMVP6_FB)
1-PHASE DCM
0.001UF
1%
1/16W
MF-LF
2 402
C7418
10%
25V
X5R
603-1
IMVP6_LGATE1
(GND)
60
VO
255
33
5%
1/16W
MF-LF
402
24
ISEN1
DFB
10%
50V
CERM
402
60
VSUM
OCSET 8
7 SOFT
13 VDIFF
60
PGND2
1 PGOOD
5 VR_TT*
IMVP6_RBIAS
26
UGATE1 35
DROOP
LOAD LINE SLOPE = -2.1 MV/A
IMVP6_BOOT1
IMVP6_BOOT2
U7400BOOT2
46 DPRSTP*
45 DPRSLPVR
IMVP6_IMON
FROM SMC
C7417
33UF
LFPAK-HF
2 IMVP6_BOOT2_RC
R7425
PVCC
BOOT1 36
38 VID1
37 VID0
1/16W
MF-LF
402
CPU_PROCHOT_L
1
VDD
31
CRITICAL
41 VID4
40 VID3
39 VID2
0
5%
69 42 14 10
20%
16V
POLY-TANT
CASED2E-SM
CRITICAL
1
1-PHASE CCM
IMVP6_BOOT1_RC
402
1
22
20
43 VID6
42 VID5
CPU_VID<6>
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
IN
OUT
C7409
33UF
5%
1/16W
MF-LF
2.0K
CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
10
IN
69 14 10
69 11
RJK0305DPB
2-PHASE CCM
R7424
VIN
CRITICAL
1
0
1
0
Q7400
2 402
R7426
NO STUFF
10%
16V
X5R
402
470K
402
10%
16V
CERM
402
NO STUFF
R7427
1
1
0
0
OPERATION MODE
PP3V3_S0_IMVP6_3V3
5%
1/16W
MF-LF
402
4.02K
1%
1/16W
MF-LF
402
PSI*
CRITICAL
C7430
R7421
GND_IMVP6_SGND
NO STUFF
0.01UF
10
60
C7496
10%
16V
CERM
402
DPRSTP*
0
0
1
1
20%
6.3V
X5R
603
PPVIN_S5_IMVP6_VIN
5%
1/16W
MF-LF
402
PM_DPRSLPVR
DPRSLPVR
10UF
=PPVIN_S5_CPU_IMVP
10
69 21
C7435
IMVP6_VSEN
60 8
1UF
CRITICAL
VOLTAGE=5V
C7426
IMVP6_RTN
=PPVIN_S5_CPU_IMVP
PP5V_S0_IMVP6_VDD
ISL9504BCRZ
10%
16V
X7R
402
(IMVP6_VO)
(IMVP6_COMP)
1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

OMIT
C7421
10%
6.3V
CERM-X5R
402
5%
1/16W
MF-LF
2 402
0.22uF
XW7400
SM
1
R7423
0
R7422
0
5%
1/16W
MF-LF
2 402
CPU_VCCSENSE_P
CPU_VCCSENSE_N
11 60 69
11 60 69
60
60
IMVP6 CPU VCORE REGULATOR
60
60
60
60
60
60
60
60
60
60
60
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
MIN_LINE_WIDTH
1.5 MM
0.25 MM
1.5 MM
1.5 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
60
60
60
60
60
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
60
60
60
60
60
69 60 11
69 60 11
60
LATEST ISSUE: 2007/01/23

8
60
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_RTN
IMVP6_VSEN
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.50 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.25 MM
IMVP6 CPU VCore Regulator


SIZE
0.25 MM
0.25 MM
0.25 MM
0.25 MM
DRAWING NUMBER
D
APPLE INC.
REV.
051-8089
SCALE
SHT
NONE
02
OF
74
109
- SYNC WITH T18

MCP VCORE/5V_S3 LEFT REGULATOR
=PPVIN_S3_5VLTS3
8
VOLTAGE=12.6V
CRITICAL
C7512
0.001UF
20%
50V
CERM
402
Q7510
SI7110DN
PP5V_S3_MCPREG_LDO
PWRPK-1212-8-HF
61
=PPVIN_S0_MCPREG_VIN
CRITICAL
C7510
C7511
(P5VLTS3_UGATE)
20%
16V 2
POLY-TANT
CASED2E-SM
10%
25V
X5R
603-1
CRITICAL
GATE_NODE=TRUE
1UF
33UF
C7500
C7501
10UF
1UF
10%
25V
X5R
805
10%
6.3V
CERM
402
CRITICAL
PWRPK-1212-8-HF
5
C7560
(Internal 10-ohm path

from PVCC to VCC)
PP5V_S0_MCPREG_VCC
VOLTAGE=5V
SI7110DN
MCPREG_VREF3
(P5VLTS3_LGATE)
L7520
3.3UH
C7514
0.1UF
CRITICAL
10%
50V
SWITCH_NODE=TRUE
X7R
603-1 MIN_LINE_WIDTH=0.6MM
P5VLTS3_BOOT
P5VLTS3_UGATE
P5VLTS3_PHASE
P5VLTS3_LGATE
(P5VLTS3_PHASE)
IHLP
(=PP5VLT_S3_REG)
CRITICAL
0.001UF
20%
50V
CERM
402
C7517
2
10UF
20%
6.3V
POLY-TANT
CASE-B2-SM
20%
10V
X5R
805
(=P5VLTS3_EN)
C7516
150UF
NO STUFF
150UF
20%
6.3V
POLY-TANT
CASE-B2-SM
5%
1/16W
MF-LF
SM
PLACEMENT_NOTE=Place next to C7516
C7520
R7521
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
61
(=P5VLTS3_EN)
PP5V_S0_MCPREG_VCC
NO STUFF
100PF
61.9K
EMI request
2 402
P5VLTS3_PHASE_SNUBBER
P5VLTS3_VSNS
NO STUFF NO STUFF
P5VLTS3_FB
P5VLTS3_ILIM
2.2
XW7501
CRITICAL
C7515
R7595
1UF
4.7UF
10%
6.3V
CERM
402
20%
6.3V
X5R-CERM
402
LDO
LDOREFIN
CRITICAL
VBST2
DRVH2
LL2
QFN
DRVL2
VOUT2
EN2
U7500
7
8
24
26
25
23
30
27
61
Max load 100mA

PP5V_S3_MCPREG_LDO
C7502
(MCPCORES0_UGATE)
GATE_NODE=TRUE
10%
25V
X5R
603-1
0.001UF
20%
50V
CERM
402
MCPCORES0_REFIN
MCPCORES0_ILIM
VREF2 1
PGOOD1 13
PGOOD2 28
PP2V_S0_MCPREG_REF
RJK0305DPB
Vout = See below

MAX CURRENT : 11A
FREQ = 300 KHZ
LFPAK-HF
VOLTAGE=5V
5%
10V
CERM-X7R
603
CRITICAL
L7500
1.0UH-13A-5.6M-OHM
1 2 3
0.22UF
(SGND)
MCPCORES0_BOOT
MCPCORES0_UGATE
MCPCORES0_PHASE
MCPCORES0_LGATE
ISNS_PVCORES0MCP_N
REGULATE TO AFTER SENSE RES
REFIN2 32
TRIP2 31
Q7560
C7564
SM-IHLP-1
1
(MCPCORES0_PHASE)
SWITCH_NODE=TRUE
46
=PPMCPCORE_S0_REG
NO STUFF
R7596
2.2
5%
1/16W
MF-LF
(MCPCORES0_LGATE)
R7570
RJK0328DPB1
LFPAK-HF
402
C7570
0.001UF
10UF
C7596
20%
4V
X5R
603
C7566
10UF
20%
50V
CERM
402
20%
4V
X5R
603
C7565
20%
2 2.5V
POLY-TANT
CASE-C2-SM
C7569
0.0027UF
330UF
2
10%
50V
CERM
402
2 50V
CERM
402
0.1%
1/16W
MF
402 2
2 CERM
C7567
100PF EMI request

5%
48.7K
50V
NO STUFF
Q7565
Max load 50uA
CRITICAL
MCPCORES0_PHASE_SNUBBER
CRITICAL
VOLTAGE=2V
EMI request
2 402
GATE_NODE=TRUE
THRM_PAD GND PGND
C7595
100PF EMI request
5%
VIN
VBST1
DRVH1
LL1
DRVL1
VOUT1
EN1
VSW
VFB1
TRIP1
SKIPSEL
EN_LDO
V5DRV1
TONSEL
33
C7518
6
17
15
16
18
10
14
9
11
12
29
4
20
2
VREF3
(Q7510 LIMIT)
7A MAX OUTPUT
VOUT = 5V
FREQ = 400 KHZ
=PP5VLT_S3_REG
22
21
3 2 1
TDP: 5.2A
V5FILT
10%
6.3V
CERM
402
C7562
1UF
CRITICAL
C7503
1UF
SN0802043
(P5VLTS3_BOOT)
V5DRV
C7504
19
C7561
61
GATE_NODE=TRUE
20%
16V 2
POLY-TANT
CASED2E-SM
Q7511
4
33UF
=PPVIN_S0_MCPCORES0
<Ra>
<Ra>
R7520 1
1
180K
R7522
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
XW7500
SM
1
64
OUT
64
OUT
64
IN
20%
10V
CERM
402
R7571 1
R7581
R7582
54.9K
475K
237K
110K
5%
1/16W
MF-LF
402
0.1%
1/16W
MF
402
0.1%
1/16W
MF
402
0.1%
1/16W
MF
402
0.1%
1/16W
MF
402
<Rb>
<Rc>
<Rd>
MCP_VID0_L
VOLTAGE=0V
B
PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.
<Re>
MCP_VID1_L
MCP_VID2_L
Q7582
=P5VLTS3_EN
Q7580
Vout = 2.0V * Req / (Ra + Req)
MCPCORES0_PGOOD
P5V_LT_S3_PGOOD
=MCPCORES0_EN
R7580
180K
GND_MCPREG_SGND
Vout = 0.7V * (1 + Ra / Rb)

IN
R7530 1
C7530
0.1UF
<Rb>
64
Q7580
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
SSM3K15FV
D 3
=PPVCORE_S0_MCP
SOD-VESM-HF
CRITICAL
S 2
21
21
IN
IN
IN
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
7.5K
20%
5%
1/16W
MF-LF
402
R7591
1
Rev A01
VID<2:0>
Production
Voltage
Voltage
MCP Target
000
+1.224V
+1.060V
+1.05V
001
010
+1.159V
+1.101V
+0.994V
+0.937V
+1.00V
+0.95V
011
+1.049V
+0.885V
+0.90V
100
+0.995V
+0.830V
+0.85V
101
+0.952V
+0.789V
+0.80V
110
+0.913V
+0.752V
+0.75V
111
+0.876V
+0.719V
7.5K
5%
1/16W
MF-LF
402
R7592
7.5K
5%
1/16W
MF-LF
402
2 2.5V
MCP_VID0_RC
MCP_VID1_RC
MCP_VID2_RC
POLY-TANT
CASE-C2-SM
C7590
C7591
C7592
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE

CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE
2
MCP VCORE REGULATOR

M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:
+0.70V
Added C7568 bulk cap on output.

Tied TON to REF.
Changed Q7510 to 376S0674.
C7500 changed to 138S0638.
L7560 changed from T18 MLB inductor to 152S0782.
Changed Q7565 to 376S0637.
Changed R7514 to 280K, R7564 to 180K.

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-8089
SCALE
SHT
NONE
C7568
330UF
R7590
21
8 22 24 46
Req = Rb || Rc || Rd || Re
02
OF
75
109
CPUVTT POWER SUPPLY
=PPVIN_S0_CPUVTTS0
CRITICAL
C7630
20%
16V
POLY-TANT
CASED2E-SM
C7695
1UF
33UF
2
10%
25V
X5R
603-1
C7696
0.001UF
20%
50V
CERM
402
CRITICAL
Q7620
SI7110DN
PWRPK-1212-8-HF
S
=PP5V_S0_CPUVTTS0
L7620
2 3
R7601
PP5V_S0_CPUVTTS0_V5FILT
VOLTAGE=5V
R7603 1
C7601
1UF
10%
10V
X5R
402-1
10
1%
1/16W
MF-LF
402
301
V5FILT
2
187K
C7604
1%
1/16W
MF-LF
402
4.7UF
V5DRV
2
CRITICAL
10%
6.3V
X5R-CERM
603
64
IN
=CPUVTTS0_EN
64
OUT
CPUVTTS0_PGOOD
PGOOD
(=PPCPUVTT_S0_REG)
VOUT
VFB
VBST
CPUVTTS0_TON
14
CPUVTTS0_VBST
DRVH
13
LL
12
CPUVTTS0_DRVH
GATE_NODE=TRUE
CPUVTTS0_VFB
CPUVTTS0_LL
SWITCH_NODE=TRUE
CPUVTTS0_TRIP
11
TRIP
DRVL
CPUVTTS0_DRVL
GATE_NODE=TRUE
THRM_PAD
10%
50V
X7R
603-1
2.2
5%
1/16W
MF-LF
SI7108DN
PWRPK-1212-8-HF
XW7665
2 402
CPUVTTS0_LL_SNUBBER
1
2
2 3
EMI request
NO STUFF
1
C7690
100PF
5%
50V
2 CERM
402
CPUVTTS0_VSNS
NO STUFF
R7670
C7670
8.45K
R7604
XW7600
2
5%
50V
CERM
402
<Ra>
SM
1
100PF
1%
1/16W
MF-LF
2 402
6.65K
1%
1/16W
MF-LF
2 402
SM
0.1UF
R7690
CRITICAL
Q7621
PGND
D
2
15
GND
C7603
SM-IHLP-1
U7600
TPS51117RGY_QFN14
SYM QFN
(2 OF 2)
EN_PSV
TON
EMI request
NO STUFF
(GND)
ROUTING NOTE:
R7671
1%
1/16W
MF-LF
2 402
20%
6.3V
X5R
603
CRITICAL
C7660
C7661
0.001UF
20%
50V
CERM
402
330UF
20%
2.5V 2
POLY-TANT
CASE-C2-SM
B
2
XW7601
ROUTING NOTE:
<Rb>
GND_CPUVTTS0_SGND
C7665
10UF
20.0K
Place XW7600 between Pin 7 and Pin 15 of U7600.
8 65
Vout = 1.052V
8A max output
F = 400 KHZ
SM
PLACEMENT_NOTE=Place XW7665 next to L7620
=PPCPUVTT_S0_REG
1.0UH-13A-5.6M-OHM
2 CRITICAL
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
CPUVTT_VOUT
(=PPCPUVTT_S0_REG)
CPU VTT(1.05V) SUPPLY


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
76
109
FireWire 1.0V (Core) Supply

CRITICAL
L7710
4.7UH-0.8A
1
P1V0FW_SW
CRITICAL
SWITCH_NODE=TRUE
U7780
C7712
=PP3V3_FW_P1V0FW
52.3K
22pF
5%
50V
CERM
402
SC70
8
VIN
SW
RUN
VFB 6
<Rb>
R7713
4.7UF
20%
6.3V
X5R-CERM
402
200K
2
C7715
4.7UF
f = 2.25 MHz
P1V0FW_VFB
GND
C7710
(Switcher limit)
1%
1/16W
MF-LF
2 402
Vout = 1.001V
300mA max output
LTC3410ESC6
4
=PP1V0_FW_REG
<Ra>
R7712
PCAA031B-SM
1%
1/16W
MF-LF
402
20%
6.3V
X5R-CERM
402
Vout = 0.8V * (1 + Ra / Rb)
MCP 1.05V_S5 AUXC SUPPLY
1.5V S0 SWITCH
=PP3V3_S5_P1V05S5
8
CRITICAL
CRITICAL
C7781
CRITICAL SW
OVT
U7750
FB
TPS62510
PG
BQA
1 1V05S5_SW
4 1V05S5_FB
9
=PP1V05_S5_REG
C7782
402
P1V05_S5_PGOOD
OUT
64
=P1V5S0_EN
C7783
FREQ = 1MHZ
C7741
22UF
2
R7781
392K
20%
6.3V
CERM
805
0.1UF
10%
2
MF-LF
402
1V05S5_SGND
VOUT = 0.6V * (1 + Ra / Rb)
CRITICAL
L7740
2.2UH-3.25A
EN
IHLP1616BZ-SM
OVT
CRITICAL SW
1V5S0_SW
U7740 FB
1V5S0_FB
TPS62510
MODE
PG
BQA
<Ra>
C7742
R7740
22PF
301K
16V
X5R
402
5%
50V
CERM
402
1%
1/16W
MF-LF
402
<Rb>
R7741
200K
P1V5_S0_PGOOD
OUT
64
2
MODE_GND
XW7700
SM
=PP1V5_S0_FET
AGND PGND THRM_PAD
1%
1/16W
64
MAX Current = 1.5A
CRITICAL
1%
1/16W
MF-LF
402
<Rb>
1
11
2 16V
X5R
402
0.1UF
10%
Vout = 1.05V
301K
5%
2 50V
CERM
<Ra>
R7780
22PF
8
20%
6.3V
CERM
805
AVINPVIN
8
C7740
22UF
1V5S0_AVIN
AGND PGND THRM_PAD
IHLP1616BZ-SM
EN
MODE
L7720
10
9
6
2.2UH-3.25A
AVINPVIN
=P1V05_S5_EN
64
R7742
5%
1/16W
MF-LF
402
6.3V
CERM
805
10
5%
1/16W
MF-LF
402
1V05S5_AVIN
=PP3V3_S0_FET
22UF
20%
65 8
C7720
11
R7722
VOUT = 0.6V * (1 + Ra / Rb)
VOUT = 1.5V
MAX CURRENT = 1.5A
C7743
22UF
FREQ = 1MHZ
20%
6.3V
CERM
805
1%
1/16W
MF-LF
2 402
1
XW7740
SM
MISC POWER SUPPLIES


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
77
109
3.3V 1.05V S5 ENABLE
Power Control Signals
R7802
64 8
100K
=PP3V42_G3H_PWRCTL
PM_G2_P3V3S5_EN_L
=P3V3S5_EN_L
OUT
58
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
0.068UF
Q7800
SSM3K15FV
D 3
10%
10V
R7813
SMC_PM_G2_EN
IN
CERM
402
SOD-VESM-HF
41
5VLT_S0, 3.3V_S0, 1.8V_S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE
1.5V S0 AND 1.05V S0 ENABLE
NO STUFF
C7802
64 8 =PP3V42_G3H_PWRCTL
68K
PM_SLP_S3_L_INVERT
=P5VRTS0_EN_L
OUT
MAKE_BASE=TRUE
5%
R7800
100K
5%
1/16W
MF-LF
402
1/16W
MF-LF
402
S 2
SSM3K15FV
SOD-VESM-HF
NO STUFF
1
R7801
2
5.1K
1 PM_G2_P1V05S5_EN
OUT
63
2
1
1
S 2
(PM_SLP_S3_L)
C7801
0.47UF
C7813
0.068UF
=P1V05_S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
58
Q7813
D 3
41 36 33 21
10%
6.3V
CERM-X5R
402
IN
10%
10V
CERM
402
PM_SLP_S3_L
R7879
NO STUFF
C7858
64 8 =PP3V3_S5_PWRCTL
0.1UF
100K
5%
1/16W
MF-LF
402
PM_SLP_S3_L_BUF
=P3V3S0_EN
=PBUSVSENS_EN
20%
10V
CERM
402
OUT
MAKE_BASE=TRUE
65
OUT
45
NO STUFF 5 TC7SZ08AFEAPE
2
SOT665
U7859 Y
(PM_SLP_S3_L)
4 (PM_SLP_S3_L_BUF)
R78811
R7880
22K
5%
S3 ENABLE
1/16W
MF-LF
402
R78821
R78831
33K
5.1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
P1V8S0_EN
42 41 21
IN
(PM_S4_STATE_L)
PM_SLP_S4_L
OUT
MCPDDR_EN
CPUVTTS0_EN
R7859
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
DDRREG_EN
=DDRREG_EN
OUT
MAKE_BASE=TRUE
NO STUFF
C7812
R7812
1
=USB_PWR_EN
OUT
100
65
=CPUVTTS0_EN
OUT
62
=MCPCORES0_EN
OUT
61
MAKE_BASE=TRUE
MCPCORES0_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
59
NO STUFF
1
39
0.47UF
63
OUT
MAKE_BASE=TRUE
0.47UF
5.1K
1
100K
5%
1/16W
MF-LF
402
R7811
OUT
=MCPDDR_EN
65
C7810
R7810
=P1V5S0_EN
MAKE_BASE=TRUE
=P3V3S3_EN
MAKE_BASE=TRUE
C7880
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
CERM-X5R
CERM-X5R
402
C7882
0.47UF
402
C7881
0.47UF
C7883
0.47UF
10%
6.3V
CERM-X5R
CERM-X5R
402
402
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
P5VLTS3_EN
=P5VLTS3_EN
MAKE_BASE=TRUE
OUT
61
64 8 =PP3V42_G3H_PWRCTL
OTHER S0 RAILS PGOOD
C7840
1
1
0.1uF
20%
10V
CERM
402
=PP3V3_S5_PWRCTL
64 8
100K
R7820
63
0.1uF
20%
10V
CERM
402
58
IN
IN
U7840
RSMRST_PWRGD
41
P1V05_S5_PGOOD
63
TPS3808G33DBVRG4
CT
4 CT
SOT23-6
MR* 3
TPS3808 MR* HAS INTERNAL PULLUP
GND
2
C7841
P1V5_S0_PGOOD
NEED TO CHANGE SIMBOL
0.001UF
20%
50V
CERM
402
P5V3V3_PGOOD
VCC
RESET* 1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8 =PP3V3_S0_VMON
C7870
5 SENSE
10K
LAYOUT_NOTE: ADD XW IF NEEDS TO SAVE SPACE FOR PIN2,10,1,9
VDD
5.0V (RIGHT AND LEFT), 3.3V AND 1.5V S0 RAILS MONITOR CIRCUIT
R7840
8 =PP3V3_S0_PWRCTL
61
IN
MCPCORES0_PGOOD
62
IN
CPUVTTS0_PGOOD
U7870
LTC2909
=PP1V8_S0_VMON
NC
8
=PP1V05_S0_VMON
SEL
8
7
ADJ1
ADJ2
REF
DFN
RST*
TIE TMR TO GND

TRST = 200MS
61
IN
P5V_LT_S3_PGOOD
ALL_SYS_PWRGD
OUT
7 26 41
MAKE_BASE=TRUE
GND
5
TMR
S0PGOOD_PWROK
(S0PGOOD_PWROK)
POWER SEQUENCING
THRM_PAD
Unused PGOOD signal

LTC2901 THRESHOLD IS 95% (4.75V, 3.136V)
1.5V 1.05V COMPARED TO 0.5V
TP_ENETLV_PGOOD

ENETLV_PGOOD
MAKE_BASE=TRUE

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
78
109
3.3V S3 FET
1.8V S0 FET
CRITICAL
Q7910
(1.8V S0 FET FOR DDR2 MEM)
FDC638P_G
SM
6
3.3V S3 FET
=PP3V3_S3_FET
=PP1V8_S3_P1V8S0FET
8 21
1.8V S0 FET
5
8
=PP3V3_S5_P3V3S3FET
R7912
MOSFET
FDC638P
CHANNEL
P-TYPE
C7911
10K
RDS(ON)
0.033UF
5%
X5R
402
2
C7910
20%
10V
CERM
402
0.182 A (EDP)
P3V3S3_SS
=PP5V_S3_MCPDDRFET
10%
SSM3K15FV
MF-LF
16V
402
CERM
R7903 1
402
D 3
10K
5%
1/16W
MF-LF
402
64
IN
N-TYPE
CRITICAL
RDS(ON)
15 MOHM @4.5V VGS
LOADING
5A (EDP)
FDM6296G
CKT FROM T18
S
D
SSM6N15FEAPE
=PP1V8_S0_FET
SOT563
S 2
MCPDDR_EN_L
47K
1
1
5%
1/16W
MF-LF
402
C7903
0.068UF
2
2
=P3V3S3_EN
Q7971
FDM6296G
CHANNEL
MICROFET3X3
Q7971
R7971
G
MCPDDR_SS
100K
SOD-VESM-HF
Q7901
1%
1/16W
MF-LF
402
5%
1/16W
Q7903
R7901
0.01UF
47K
P3V3S3_EN_L
48 mOhm @4.5V
LOADING
402
R7910
0.1UF
10%
16V
1/16W
MF-LF
C7902
MOSFET
1
10%
10V
CERM
402
MCPDDR_EN_L_RC
SSM6N15FEAPE
SOT563
3.3V S0 FET
64
IN
=MCPDDR_EN
CRITICAL
Q7930
FDC606P_G
100K
C7931
5%
MF-LF
402
2
1
FDC606P
CHANNEL
P-TYPE
10%
16V
R7930
P3V3S0_EN_L
X5R
47K
26 MOHM @4.5V
1.431 A (EDP)
0.01UF
P3V3S0_SS
LOADING
C7930
402
RDS(ON)
0.033UF
1/16W
3.3V S0 FET
8 63
MOSFET
R7932
=PP3V3_S5_P3V3S0FET
=PP3V3_S0_FET
5 6
SOT-6
5%
10%
1/16W
Q7905
SSM3K15FV
16V
MF-LF
CERM
402
402
D 3
SOD-VESM-HF
MCP79 DDRVTT FET

1
64
IN
S 2
=P3V3S0_EN
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.
R7975
8
=PPVTT_S0_VTTCLAMP
R79551
0
VTTCLAMP_L
90mA max load @ 0.9V

81mW max power
CKT FROM T18
=PP5V_S3_VTTCLAMP
Q7975
5%
1/8W
MF-LF
805 2
62 8
10
5%
1/10W
MF-LF
603
=PP1V05_S0_FET 8
SOT563
100K
5%
1/16W
MF-LF
402
SSM6N15FEAPE
R7976 1
=PPCPUVTT_S0_REG
VTTCLAMP_EN
Q7975
NO STUFF
C7976
SSM6N15FEAPE
20%
50V
CERM
402
59 26
IN
0.001UF
SOT563
POWER FETS
=DDRVTT_EN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
79
109
=PP5V_S0_LCD
PP5V_INV
VOLTAGE=5V
R9000
100K
1%
1/16W
MF-LF
2 402
INV_PWREN_F_L
R9001
100K
1
Q9006
SSM3K15FV
D 3
PPBUS_ALL_INV_CONN
VOLTAGE=12.6V
0402-LF
NTK3142PXXH
INV_PWREN_L
Q9005
SOT723-3-HF
1 G
CRITICAL
J9000
5%
1/16W
MF-LF
402
78171-0004
M-RT-SM
5
L9000
1 G
66 18
IN
S 2
120-OHM-0.3A-EMI
C9014
0.0022UF
1
2
LVDS_IG_BKL_ON
PP5V_INV_F
VOLTAGE=5V
0402-LF
10%
50V
CERM
402
1
2
3
4
INV_BKLIGHT_PWM_L
INV_GND
L9001
120-OHM-0.3A-EMI
1
66 8
=PP3V3_S0_LCD
518S0521
0402-LF
1 C9001
CRITICAL
100PF
26
BKLT_PLT_RST_L
5 TC7SZ08AFEAPE
2
1
LVDS_IG_BKL_PWM
66 18
SOT665
U9053Y
C9002
C9003
5%
5%
1/16W
MF-LF
2 402
50V
CERM
402
BKLIGHT_CTL
C9000
100PF
5%
2 50V
CERM
100PF
5%
50V
CERM
402
402
C90591
0.1UF
INVT_CHGND
10%
16V
X5R 2
402
INVERTER CONNECTOR
L9002
1%
1/16W
MF-LF
402
SOD-VESM-HF
L9003
FERR-120-OHM-1.5A
=PPBUS_S5_INV
THIS GND CONECTS TO CHASSIS GND
CRITICAL
Q9003
=PP3V3_S5_LCD
4
1
6
5
2
1
PP3V3_LCDVDD_SW
VOLTAGE=3.3V
R9002
FDC606P_G
SOT-6
100K
5%
1/16W
MF-LF
2 402
LCDVDD_PWREN_L 1
D 3
10K
2
5%
1/16W
MF-LF
402
C9011
0.1UF
R9023
Q9004
SSM3K15FV
LCD + CAMERA
CONNECTOR
C9012
10UF
20%
2 6.3V
X5R
603
10%
2 16V
X5R
402
LCDVDD_PWREN_L_R
CRITICAL
J9001
S-050162B
F-RT-SM
SOD-VESM-HF
25
C9013
0.0033UF
1
1 G
66 18
IN
S 2
66 9
L9004
FERR-120-OHM-1.5A
10%
50V
CERM
402
LVDS_IG_PANEL_PWR
66 8
=PP3V3_S0_LCD
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MIN_NECK_WIDTH=0.20
MM
MM
0402-LF
7 PP3V3_S0_LCD_F
(LVDS DDC POWER)
VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20
MM
MM
L9008
120-OHM-0.3A-EMI
IT IS CO-LAY FUNCTION
2
0402-LF
66 18 7
66 18 7
66 8
71 18 7
CRITICAL
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
71 18 7
L9006
90-OHM-200MA
71 18 7
AMC2012-SM
=PP3V3_S0_LCD
71 18 7
SYM_VER-1
71 18
LVDS_IG_A_CLK_N
71 18 7
71 18 7
R9015 R9016
2.7K
5%
1/16W
MF-LF
2 402
CRITICAL
L9007
2.7K
5%
71 18
LVDS_IG_A_CLK_P
66 18 7
1/16W
MF-LF
2402
USB_CAMERA_P
72 20
USB_CAMERA_N
72 20
LVDS_IG_DDC_CLK
L9005
FERR-120-OHM-1.5A
LVDS_IG_DDC_DATA
=PP5V_S3_CAMERA
72 7
66 18
66 18
AMC2012-SM
66 18
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
1K
5%
1/16W
MF-LF
402 2
C9016
0.001UF
10%
50V
2 CERM
402
R90191 R90181
1K
5%
1/16W
MF-LF
402 2
USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_N
SYM_VER-1
PP5V_S3_CAMERA_F
0402-LF
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_CLK_F_N
LVDS_IG_A_CLK_F_P
90-OHM-200MA
72 7
66 18 7
23
=GND_CHASSIS_LVDS
C9015
0.001UF
10%
50V
2 CERM
402
C9010
NC
NC
VOLTAGE=5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LCD I/F
CAMERA I/F
24
0.001UF
66 9
10%
50V
2 CERM
402
=GND_CHASSIS_LVDS
26
Plexi: 516S0212
*Enclosure: 518S0364
R90121
INVERTER,LVDS
1K
5%
1/16W
MF-LF
402 2
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
90
109
18
=MCP_HDMI_DDC_CLK
DP_IG_DDC_CLK
DP_IG_DDC_DATA
18
68
D9301, D9302, D9303, D9304 PLACE CLOSE TO J9401
MAKE_BASE=TRUE
=MCP_HDMI_DDC_DATA
68
MAKE_BASE=TRUE
CRITICAL
CRITICAL
CRITICAL
CRITICAL
D9301
D9301
D9303
D9303
RCLAMP0524P
RCLAMP0524P
RCLAMP0524P
RCLAMP0524P
SLP2510P8
SLP2510P8
SLP2510P8
SLP2510P8
D
5 IO
IO 4
NC 7
MCP_HDMI_TXC_N
IO 1
NC 10
GND
GND
9 NC
GND
6 NC
2 IO
C9302
0.1UF
20%
10V
CERM
1
18
MCP_HDMI_TXC_P
18
402
IO 4
NC 7
402
2
0.1UF
20%
9 NC
5 IO
C9301
10V
CERM
IO 1
NC 10
GND
6 NC
2 IO
TMDS_TX_CLK_P
68
TMDS_TX_CLK_N
68
TMDS_TX_P<0>
68
TMDS_TX_N<0>
68
TMDS_TX_P<1>
68
TMDS_TX_N<1>
68
C9303
MCP_HDMI_TXD_N<0>
C9304
0.1UF
20%
10V
CERM
1
18
402
2
MCP_HDMI_TXD_P<0>
18
402
2
0.1UF
20%
10V
CERM
C9305
MCP_HDMI_TXD_N<1>
C9306
0.1UF
20%
10V
CERM
1
18
402
2
MCP_HDMI_TXD_P<1>
18
402
2
0.1UF
20%
10V
CERM
C9307
C9308
0.1UF
20%
402
68
TMDS_TX_N<2>
68
R9305
2
1
R9307
1%
1/16W
MF-LF
402
R9308
499
499
499
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
499
1%
1/16W
MF-LF
402
2
1
R9303
TMDS_TX_P<2>
R9306
499
1%
1/16W
MF-LF
402
1
1%
1/16W
MF-LF
402
1
1%
1/16W
MF-LF
402
R9304
499
R9302
499
R9301
499
10V
CERM
1
MCP_HDMI_TXD_N<2>
MCP_HDMI_TXD_P<2>
18
18
402
0.1UF
20%
10V
CERM
18
1.00K2
MCP_HDMI_HPD
600-OHM-300MA
HDMI_HPD_R
18
1M
C9321
5%
1/16W
MF-LF
402
180PF
100K
DP_IG_CA_DET
68
R93701
C9320 R9322
100PF
5%
50V
2 CERM
402
TMDS_HTPLG
2
0402
0.1%
1/16W
MF
402
1
Interface Mode Setting
L9320
R9321
5%
50V
2 CERM
402
1%
1/16W
MF-LF
402
TMDS ALIASES

R9322, C9320 PLEASE PLACE CLOSE TO MCP79
R9321, L9320, C9321 PLEASE PLACE CLOSE TO J9401

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
93
109
Video Connectors EXTERNAL VIDEO (VGA) INTERFACE

D
D
Isolation required for DVI power switch
TMDS(MINI DVI) INTERFACE

NEED CHANGE SYMBOL
CRITICAL
F9404
VOLTAGE=5V
600-OHM-300MA
1SS418
PP5V_S0_TMDS_FUSE
L9444
D9401
0.5AMP-13.2V
=PP5V_S0_TMDS
PP5V_S0_DVIPORT
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 MM SOD-723-HF
SM-HF
0402
1
C9408
0.047UF
10%
16V
X7R
402
C9409
0.047UF
10%
16V
X7R
402
C9404
0.1UF
PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR J9401
68
VOLTAGE=5V
=PP3V3_S0_TMDS
20%
2 10V
CERM
402
C9409 PLACE CLOSE TO Z0912
8 68
C9460
0.1UF
=GND_CHASSIS_TMDS_UPPER
20%
2 10V
CERM
402
CRITICAL
9 68
U9404
CRT_IG_HSYNC
71 18
C9408 PLACE CLOSE TO F9404
R9460
0
1
8 SN74LVC2G125DCU
5%
1/16W
MF-LF
402
PP5V_S0_DVIPORT_D
R9470
US
VCC
5 A
CRT_HSYNC_LS_R
125
CRT_HSYNC_LS 1 39
VGA_HSYNC
5%
1/16W
MF-LF
402
GND
68
NO STUFF
1
C9442
47PF
5%
DVI power DIODE on page 95 (D9500)
2 50V
CERM
1
R9462
2.7K
R9463
2.7K
5%
1/16W
MF-LF
4022
67
5%
1/16W
MF-LF
2402
71 18
CRT_IG_VSYNC
R9461
0
1
8 U9404
SN74LVC2G125DCU
TMDS_HTPLG
R9471
39
US
VCC
2 A
CRT_VSYNC_LS_R
5%
1/16W
MF-LF
402
125
CRT_VSYNC_LS 1
R94221
1/16W
MF-LF
4022
1/16W
MF-LF
402 2
2 50V
CERM
C9410
402
NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT
C9411
Q9401
SSM6N15FEAPE
5%
2 25V
CERM
402
CRITICAL
220PF
SOT563
3
S
4
67
GPU_CRT_DDC_CLK
SOT563
DP_IG_DDC_DATA
SSM6N15FEAPE
5
BI
2.7K
5%
BI
DP_IG_DDC_CLK
L9405
90-OHM-100MA
1210-4SM1
OMIT
GPU_CRT_DDC_DATA
J9401
C9412
220PF
NC
NC
B
CRITICAL
D9400
SC70-6-1
68
VGA_B
VGA_HSYNC
26
18
27
19
28
20
29
RCLAMP0504F
68
VGA_G
VGA_VSYNC
VG signal trace, we need follow NVs recommendation. So we need change the segment impedance base on NV design guide.
A segment: 37.5 ohm from MCP to 150 ohm PD res: Top/bottom layer width is 0.18 mm
B segment: 50 ohm B/W 2 150 PF res. inner layer width is 0.09 mm top/bottom layer width is 0.115 mm
C segment: 75 ohm from FL to connector, top/bottom layer width is 0.076 mm.
VGA_R
30
22
31
32
24
TMDS_TX_CONN_P<2>
67
L9407
90-OHM-100MA
1210-4SM1
TMDS_TX_CONN_N<2>
TMDS_TX_CONN_P<1>
1
TMDS_TX_CONN_N<1>
67
TMDS_TX_N<1>
67
4
SYM_VER-1
CRITICAL
TMDS_TX_CONN_P<0>
TMDS_TX_CONN_N<0>
TMDS_TX_P<1>
L9406
90-OHM-100MA
1210-4SM1
2
TMDS_TX_P<0>
67
TMDS_TX_N<0>
67
TMDS_TX_CONN_CLK_P
TMDS_TX_CONN_CLK_N
4
SYM_VER-1
CRITICAL
L9404
33
34
35
36
300-OHM-100MA
1210-4SM
2
68 9
FL9400
210MHZ
=GND_CHASSIS_TMDS_UPPER
=GND_CHASSIS_TMDS_DOWN
TMDS_TX_CLK_P
67
TMDS_TX_CLK_N
67
4
SYM_VER-1
MEA2010P-SM
MINI-DVI CONNECTOR
71 18
CRT_IG_B_COMP_PB
R9491
150
1%
1/16W
MF-LF
402
R9492
150
1%
1/16W
MF-LF
402
CRITICAL

R9490
150
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R9495
150
R9494
150
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R9493
150
71 18
CRT_IG_G_Y_Y
CRT_IG_R_C_PR
71 18
TMDS_TX_N<2>
4
CRITICAL
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
16
25
PP5V_S0_DVIPORT 17
67
SYM_VER-1
F-RT-TH-HF
68
TMDS_TX_P<2>
MINI-DVI-M42-MG3
5%
2 25V
CERM
402
CRITICAL
for
for
for
for
C9443
47PF
10%
2 50V
CERM
402
Q9401
67
68
NO STUFF
0.001UF
R94211
2.7K
5%
VGA_VSYNC
5%
1/16W
MF-LF
402
GND
5%
=PP3V3_S0_TMDS
68 8
402
PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR THE CONNECTOR
CRITICAL

SIZE
R9493, R9494, R9495 PLACE CLOSE TO U1400
DRAWING NUMBER
R9490, R9491, R9492 PLACE CLOSE TO FL9400
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
94
109
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
FSB_DATA
LAYER
*
=2x_DIELECTRIC
FSB_DSTB
=3x_DIELECTRIC
FSB_ADDR
=STANDARD
SPACING_RULE_SET
WEIGHT
FSB_DATA
TOP,BOTTOM
LAYER
=4x_DIELECTRIC
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
FSB_ADSTB
=2x_DIELECTRIC
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_1X
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
LAYER
WEIGHT
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
CPU_AGTL
CPU_AGTL
TOP,BOTTOM
CPU_8MIL
8 MIL
?
CPU_COMP
25 MIL
?
CPU_GTLREF
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred
?
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
CPU_GTLREF
CPU_50S
CPU_GTLREF
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LAYER
WEIGHT
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO1
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
CPU_50S
CPU_8MIL
CPU_27P4S
CPU_VCCSENSE
SPACING_RULE_SET
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
=100_OHM_DIFF
SPACING_RULE_SET
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 13 14
10 14
10 14
10 14
9 10
10 14
10 14
10 14
10 14
10 14
10 14 42 60
10 13 14
10 14
10 14
10 14 42
10 14
10 14
10 14 60
10 14
14
14
14
14
10 14
10 14
7 13 14
7 13 14
14
14
10
PM_DPRSLPVR
IMVP_DPRSLPVR
21 60
60
DIFFPAIR NECK GAP

CLK_FSB_100D
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
10 27
10
10
10
10
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
6 7 10 13
6 10
6 7 10 13
6 7 10 13
6 7 10 13
7 10 13
7 10 13
7 13
11 60
CPU/FSB Constraints
11 60
11 60

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
100
109
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
DQ signals should be matched within 5 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MCP MEM COMP Signal Constraints
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_40S_VDD
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
15 28
15 28
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=4:1_SPACING
MEM_CLK2MEM
MEM_CTRL2CTRL
=2:1_SPACING
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
15 28 30
15 28 30
15 28 30
15 28 30
15 28 30
15 28 30
15 28 30
15 28 30
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
MEM_CMD2MEM
=3:1_SPACING
?
MEM_DATA2DATA
=1.5:1_SPACING
?
MEM_DATA2MEM
=3:1_SPACING
?
MEM_DQS2MEM
=3:1_SPACING
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
MEM_2OTHER
25 MIL
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_2OTHER
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DATA
MEM_DQS
MEM_DQS2MEM
MEM_DQS
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
8 MIL
15 28
15 28
15 28
15 28
15 28
15 28
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 29
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
15 29
15 29 30
15 29 30
15 29 30
MEM_2OTHER
MEM_DQS
15 28
MEM_DQS
15 28
NET_SPACING_TYPE1
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
15 29 30
15 29 30
15 29 30
15 29 30
15 29 30
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
Memory Constraints
15 29
15 29
15 29
15 29
15 29

16
16

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
101
109
PCI-Express
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
PCIE_90D
PCIE
PCIE_90D
PCIE
PEG_R2D
PCIE_90D
PCIE
PEG_R2D
PCIE_90D
PCIE
PEG_D2R
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
SPACING_RULE_SET
LAYER
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PCIE
=3X_DIELECTRIC
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
CLK_PCIE
20 MIL
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
MCP_PEX_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCIE_MINI_R2D
Analog Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PCIE_MINI_D2R
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
7 31
7 31
17 31
17 31
7 17 31
7 17 31
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT
=4:1_SPACING
PCIE_FW_R2D
CRT
CRT
CRT_2CRT
PCIE_FW_D2R
CRT_2CRT
=STANDARD
?
CRT_2CLK
50 MIL
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
35
35
17 35
17 35
17 35
17 35
35
35
CRT_2SWITCHER
250 MIL
?
CRT_SYNC
16 MIL
MCP_DAC_COMP
=2:1_SPACING
PCIE_EXCARD_R2D
CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
PCIE_EXCARD_D2R
MCP_PE0_REFCLK
MCP_PE1_REFCLK
MCP_PE2_REFCLK
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_PE3_REFCLK
DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
MCP_PEX_CLK_COMP
MCP_PEX_COMP
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_PEX_CLK_COMP
9 17
9 17
9 17
9 17
9 17
9 17
7 17 31
7 17 31
17 35
17 35
9 17
9 17
17
CRT_RED
CRT_MCP_P
CRT
CRT_GREEN
CRT_MCP_P
CRT
CRT_BLUE
CRT_MCP_P
CRT
CRT_SYNC
CRT_50S
CRT_SYNC
CRT_SYNC
CRT_50S
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
DISPLAYPORT
TOP,BOTTOM
LVDS
=3x_DIELECTRIC
CRT_SYNC
DISPLAYPORT
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
MCP_DAC_RSET
MCP_DAC_COMP
MCP_DAC_VREF
MCP_DAC_COMP
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
18 68
18 68
18 68
18 68
18 68
9 18
9 18
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
MCP_IFPAB_RSET
MCP_DV_COMP
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
TP_DP_IG_AUX_CH_P
TP_DP_IG_AUX_CH_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
18 25
18 25
SATA_100D_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SATA
SATA
TOP,BOTTOM
SATA_TERMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D
SATA
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
18 66
18 66
7 18 66
7 18 66
9 18
9 18
9 18
9 18
9 18
9 18
9 18
9 18
18 25
18 25
20 38
20 38
7 38
7 38
38
38
20 38
20 38
7 38
7 38
MCP Constraints 1
SATA_ODD_R2D
SATA_ODD_D2R
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_TERMP
MCP_SATA_TERMP
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
20 38
38
38

7 38
7 38

20 38

20 38

7 38
SIZE
7 38
DRAWING NUMBER
38
38
APPLE INC.
MCP_SATA_TERMP
20 38
SCALE
SHT
20
NONE
REV.
051-8089
02
OF
102
109
PCI Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_DEBUG
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_REQ0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_INTW_L
PCI_55S
PCI
PCI_INTX_L
PCI_55S
PCI
PCI_INTY_L
PCI_55S
PCI
PCI_INTZ_L
PCI_55S
PCI
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_FRAME_L0
LPC_55S
LPC
LPC_RESET_L
LPC_55S
LPC
MCP_LPC_CLK
CLK_LPC_55S
CLK_LPC
MCP_LPC_CLK
CLK_LPC_55S
CLK_LPC
MCP_LPC_CLK
CLK_LPC_55S
CLK_LPC
USB_EXTA
USB_90D
USB
USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTA
USB_90D
USB
USB_90D
USB
CLK_PCI_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
PCI
=STANDARD
?
CLK_PCI
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
6 MIL
LPC
CLK_LPC
8 MIL
USB 2.0 Interface Constraints

LAYER
ALLOW ROUTE
ON LAYER?
7 13 19
D
19
19
PHYSICAL_RULE_SET
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
19
19
7 19 41 43
7 19 41 43
19 26
MCP_USB_RBIAS
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
USB
=2x_DIELECTRIC
USB
TOP,BOTTOM
=4x_DIELECTRIC
I188
I185
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
I190
I189
USB_MINI
USB_90D
USB
USB_90D
USB
USB_90D
USB_90D
USB
USB
USB_90D
USB
USB_90D
USB
USB_CAMERA
USB_90D
USB
USB_CAMERA
USB_90D
USB
USB_CAMERA
USB_90D
USB
USB_CAMERA
USB_90D
USB
USB_IR
USB_90D
USB
USB_IR
USB_90D
USB
USB_EXTD
LAYER
USB
USB
USB
USB_MINI
USB_MINI
USB_MINI
SPACING_RULE_SET
USB_90D
USB_90D
USB_90D
WEIGHT
SMB
=2x_DIELECTRIC
I183
HD Audio Interface Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_90D
USB
USB_TPAD
USB_TPAD
USB_90D
USB_90D
USB
USB
CONN_TPAD_USB_P
CONN_TPAD_USB_N
USB_BT
USB_90D
USB
USB_BT
USB_90D
USB
USB_BT_P
USB_BT_N
USB_BT
USB_BT
USB_90D
USB_90D
USB
USB
USB2_BT_F_P_CONN
USB2_BT_F_N_CONN
USB_EXTB
USB_90D
USB
USB_90D
USB
USB_90D
USB_90D
USB
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_TPAD
I186
USB_MINI_P
USB_MINI_N
USB2_AIRPORT_P
USB2_AIRPORT_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_N
USB_TPAD
USB_90D
I187
USB_EXTA_P
USB_EXTA_N
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_EXTA_F_P
USB2_EXTA_F_N
USB_IR_P
USB_IR_N
USB_TPAD_P
USB_TPAD_N
PHYSICAL_RULE_SET
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB
19 26
26 41
7 26 43
20 39
20 39
39
39
39
39
9 20
9 20
7 31
7 31
9 20
9 20
20 66
20 66
7 66
7 66
20 40
20 40
9 20
9 20
7 49
7 49
SPACING_RULE_SET
LAYER
WEIGHT
HDA
=2x_DIELECTRIC
MCP_HDA_COMP
8 MIL
I194
I193
SIO Signal Constraints
I192
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
I191
USB_EXTB
USB_EXTB
USB_EXTB
9 20
9 20
USB_EXTB_P
USB_EXTB_N
USB2_EXTB_F_P
USB2_EXTB_F_N
7 40
7 40
20 39
20 39
39
39
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_EXCARD
USB_EXCARD_P
USB_EXCARD_N
9 20
9 20
SPACING_RULE_SET
LAYER
WEIGHT
USB_EXTC
CLK_SLOW
8 MIL
I184
USB_EXTC_P
USB_EXTC_N
9 20
9 20
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
HDA_BIT_CLK
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
20
SPI Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
HDA_SYNC
WEIGHT
SPI
8 MIL
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
MCP_HDA_PULLDN_COMP
MCP_HDA_COMP
MCP_SUS_CLK
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW_55S
CLK_SLOW
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_PULLDN_COMP
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_CLK_R
SPI_CLK_MUX
SPI_MOSI_R
SPI_MOSI_MUX
SPI_MISO_MUX
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
7 13 21 44
7 13 21 44
21 44
21 44
21 52
21
21 52
21
21
21 52
21 52
21 52
21
MCP Constraints 2
21
21 26
26 41

21 43
43 51
21 43

43 51
43 51
51
SIZE
DRAWING NUMBER
D
APPLE INC.
051-8089
SCALE
SHT
NONE
REV.
21 43
02
OF
103
109
MCP RGMII (Ethernet) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_MII_COMP
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_INTR_L
ENET_MII_55S
ENET_MII
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_RXCLK
ENET_MII_55S
ENET_MII
ENET_MII_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_CLK25M_BUF0_R
MCP_CLK25M_BUF0
18
18
18 33
MCP_BUF0_CLK
=3:1_SPACING
ENET_MII
12 MIL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_MII_55S
ENET_MII
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_CLK125M_RXCLK
ENET_CLK125M_RXCLK_R
ENET_RXD<3..1>
ENET_RX_CTRL
18 32
18 32
18 32
32
18 32
18 32
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK
ENET_CLK125M_TXCLK_R
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI
25 MIL

ENET_MDI
18 32
32
18 32
18 32
18 32
18 32
32 34
32 34
Ethernet Constraints

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
104
109
FireWire Interface Constraints
FireWire Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
FW_PORT_A_P
FW_PORT_A_N
FW_PORT_B_P
FW_PORT_B_N
35 37
35 37
35 37
35 37
35 37
35 37
35 37
35 37
37
37
37
37
Port 2 Not Used
FireWire Constraints

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
105
109
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
PHYSICAL
SPACING
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
44
44
44
44
44
44
44
44
44
44
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
SMC Constraints

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
106
109
K36B BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
DEFAULT
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
BGA_P2MM
=DEFAULT
BGA_P1MM
=50_OHM_SE
=50_OHM_SE
30 MM
0 MM
0 MM
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
BGA_P1MM
BGA_P2MM
CLK_FSB
BGA_P1MM
BGA_P2MM
CLK_LPC
BGA_P1MM
BGA_P2MM
BGA_P3MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=DEFAULT
WEIGHT
TOP,BOTTOM
MEM_40S_VDD
BGA_P1MM
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCI
BGA_P1MM
BGA_P2MM
CLK_PCIE
BGA_P1MM
BGA_P2MM
CLK_SLOW
BGA_P1MM
BGA_P2MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
SPACING_RULE_SET
55_OHM_SE
STANDARD
MINIMUM LINE WIDTH
BGA_P1MM
ALLOW ROUTE
ON LAYER?
MEM_40S
BGA_P1MM
MEM_CLK
DEFAULT
LAYER
PHYSICAL_RULE_SET
DIFFPAIR NECK GAP
STANDARD
PHYSICAL_RULE_SET
AREA_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
SPACING_RULE_SET
0.090 MM
LAYER
0.090 MM
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
1.5:1_SPACING
0.15 MM
2:1_SPACING
0.2 MM
=STANDARD
FSB_DSTB
FSB_DSTB
BGA_P1MM
BGA_P3MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
50_OHM_SE
TOP,BOTTOM
0.115 MM
0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
2.5:1_SPACING
0.25 MM
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
WEIGHT
50_OHM_SE
0.090 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
40_OHM_SE
TOP,BOTTOM
0.165 MM
0.165 MM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
2X_DIELECTRIC
0.152 MM
3X_DIELECTRIC
0.228 MM
4X_DIELECTRIC
0.304 MM
5X_DIELECTRIC
0.380 MM
40_OHM_SE
0.145 MM
0.145 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
0.310 MM
0.310 MM
27P4_OHM_SE
0.275 MM
0.275 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
0.175 MM
0.175 MM
0.200 MM
0.200 MM
70_OHM_DIFF
TOP,BOTTOM
0.185 MM
0.185 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
0.109 MM
0.109 MM
0.220 MM
0.220 MM
90_OHM_DIFF
TOP,BOTTOM
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
0.089 MM
0.089 MM
0.230 MM
0.230 MM
100_OHM_DIFF
TOP,BOTTOM
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF_HDD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF_HDD
0.095 MM
0.095 MM
0.400 MM
0.400 MM
100_OHM_DIFF_HDD
TOP,BOTTOM
0.095 MM
0.095 MM
0.400 MM
0.400 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
0.075 MM
0.075 MM
0.330 MM
0.330 MM
110_OHM_DIFF
TOP,BOTTOM
0.077 MM
0.077 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
1:1_DIFFPAIR
=STANDARD
=STANDARD
0.330 MM
0.330 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
0.1 MM
0.1 MM
K36B RULE DEFINITIONS

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8089
02
OF
109
109

Apple Macbook A1181 (K36C MLB)

Încărcat de

Informații document

Descriere originală:

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Apple Macbook A1181 (K36C MLB)

Încărcat de

Drepturi de autor:

Formate disponibile

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

K36C MLB SCHEMATIC

System Block Diagram

Power Block Diagram

JTAG Scan Chain

CPU Power & Ground

eXtended Debug Port(MiniXDP)

MCP CPU Interface

MCP Memory Interface

MCP Memory Misc

MCP PCIe Interfaces

MCP Ethernet & Graphics

MCP PCI & LPC

MCP SATA & USB

MCP HDA & MISC

MCP Power & Ground

MCP79 A01 Silicon Support

MCP Standard Decoupling

MCP Graphics Support

FSB/DDR2 VREF MARGINING

DDR2 SO-DIMM Connector A

DDR2 SO-DIMM Connector B

Memory Active Termination

Right Clutch Connector

Ethernet PHY (RTL8211CL)

Ethernet & AirPort Support

FireWire Port Power

External USB Connectors

Front Flex Support

LPC+SPI Debug Connector

AUDI0: SPEAKER AMP

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

PBUS Supply/Battery Charger

1.8V/0.9V DDR2 SUPPLY

IMVP6 CPU VCore Regulator

MCP VCORE REGULATOR

CPU VTT(1.05V) SUPPLY

MISC POWER SUPPLIES

K36B RULE DEFINITIONS

DIMENSIONS ARE IN MILLIMETERS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

2.X OR 3.X GHZ

FAN CONN AND CONTROL

(UP TO FOUR PORTS)

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

K36B POWER SYSTEM ARCHITECTURE

(4A MAX CURRENT)

(4A MAX CURRENT)

Power Block Diagram

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

(23A MAX CURRENT)

NOTICE OF PROPRIETARY PROPERTY