Conformal Ref

Encounter
Conformal
Equivalence Checking Reference Manual

Conformal ASIC, Conformal Ultra, and Conformal Custom
Product Version 7.2
May 2008
1997 2008 Cadence Design Systems, Inc. All rights reserved.
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Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA
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Encounter Conformal Equivalence Checking Reference Manual
May 2008 3 Product Version 7.2
Contents
About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
Command Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Using UNIX Commands with Conformal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ABSTRACT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ADD ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADD BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ADD CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ADD COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ADD CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ADD DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ADD ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ADD ECO LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ADD ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ADD ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ADD IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ADD IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ADD IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ADD INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ADD INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADD INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ADD LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ADD MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ADD MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADD MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ADD NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADD NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADD NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADD NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADD NOTRANSLATE LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADD NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADD OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADD OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADD PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADD PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADD PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ADD PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADD PRIMARY INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADD PRIMARY OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADD RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADD RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADD SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADD SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADD TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ANALYZE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ANALYZE DATAPATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ANALYZE ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ANALYZE IMPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
ANALYZE MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
ANALYZE NONEQUIVALENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ANALYZE POWER ASSOCIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ANALYZE RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ANALYZE SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
APPLY PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ASSIGN PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
BACKWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
CHANGE GATE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
CHANGE NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CHECK LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CHANGE NET TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
CLOSE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
COMMIT CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
COPY MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
DELETE ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
DELETE BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DELETE CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DELETE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DELETE CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DELETE DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DELETE ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DELETE ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DELETE ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DELETE IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DELETE IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DELETE IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
DELETE INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DELETE INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DELETE INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
DELETE LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DELETE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DELETE MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
DELETE MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
DELETE NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DELETE NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
DELETE NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
DELETE NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
DELETE NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
DELETE OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DELETE OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
DELETE PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
DELETE PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
DELETE PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
DELETE PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DELETE PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
DELETE PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DELETE RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DELETE RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
DELETE SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DELETE TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DIAGNOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ELABORATE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
FLATTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
FORWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
GENERATE ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
INVERT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
LICENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MAP ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
MAP KEY POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MOS2BUFIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
MOVE INSTANCE DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
OPEN SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
OPTIMIZE PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
PRINTENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
PROVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
READ CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
READ DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
READ FSM ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
READ LEF FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
READ LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
READ MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
READ MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
READ ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
READ RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
READ PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
REDUCE MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
REMODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
REMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
REPORT ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
REPORT ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
REPORT BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
REPORT CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
REPORT COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
REPORT COMPARE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
REPORT COMPARE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
REPORT COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
REPORT CPF LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
REPORT CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
REPORT DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
REPORT DATAPATH RESOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
REPORT DESIGN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
REPORT DESIGN SIMILARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
REPORT DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
REPORT ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
REPORT ECO CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
REPORT ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
REPORT ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
REPORT FLOATING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
REPORT GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
REPORT HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
REPORT IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
REPORT IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
REPORT INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
REPORT INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
REPORT INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
REPORT KEY POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
REPORT LIBRARY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
REPORT LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
REPORT LOWPOWER DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
REPORT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
REPORT MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
REPORT MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
REPORT MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
REPORT MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
REPORT MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
REPORT NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
REPORT NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
REPORT NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
REPORT NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
REPORT NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
REPORT OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
REPORT OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
REPORT PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
REPORT PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
REPORT PARTITION RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
REPORT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
REPORT PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
REPORT PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
REPORT PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
REPORT PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
REPORT PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
REPORT PULSE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
REPORT REMOVED INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
REPORT RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
REPORT RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
REPORT RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
REPORT SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
REPORT STATISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
REPORT TESTCASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
REPORT TEST VECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
REPORT TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
REPORT UNMAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
REPORT VERIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
RESET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
RESET HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
RESOLVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
RESTORE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
RUN HIER_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
RUN PARALLEL COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
RUN PARTITION_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
SAVE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
SAVE HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
SAVE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
SET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
SET ANALYZE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
SET_ATTR INPUT_PRAGMA_KEYWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
SET CASE SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
SET COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
SET COMPARE EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
SET COMPARE OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
SET CPU LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
SET DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
SET DIRECTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
SET DOFILE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
SET EXIT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
SET FLATTEN MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
SET FPGA TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
SET GATE REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
SET GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
SET HDL DIAGNOSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
SET HDL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
SET IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
SET LOG FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
SET LOWPOWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
SET MAPPING METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
SET MOS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
SET MULTIPLIER IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
SET MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
SET NAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
SET PARALLEL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
SET RETIMING OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
SET ROOT MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
SET RULE FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
SET RULE HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
SET SCREEN DISPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
SET SPICE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
SET STATETABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
SET SYNTHESIS_OFF_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
SET SYNTHESIS_ON_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
SET SYSTEM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
SET UDP PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
SET UNDEFINED CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
SET UNDEFINED PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
SET UNDRIVEN SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
SET WIRE RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
SET X CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
SET XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
SETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
SUBSTITUTE BLACKBOX MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
SUBSTITUTE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
TCLMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
TEST RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
UNIQUIFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
VALIDATE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
VALIDATE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
VPXMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
WRITE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
WRITE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
WRITE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
WRITE ECO DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
WRITE HIER_COMPARE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
WRITE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
WRITE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
WRITE MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
WRITE PARTITION DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
WRITE RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
3
HDL Rule Check Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
DIR1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
DIR1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
DIR1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
DIR2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
DIR2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
DIR3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
DIR3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
DIR4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
DIR4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
DIR4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
DIR4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
DIR5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
DIR5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
DIR5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
DIR5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
DIR6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
DIR6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
DIR7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
DIR7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
DIR8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
DIR9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
DIR9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
DIR9.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
FIL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
HRC1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
HRC1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
HRC1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
HRC1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
HRC1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
HRC2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
HRC2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
HRC2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
HRC2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
HRC2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
HRC3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
HRC3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
HRC3.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
HRC3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
HRC3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
HRC3.4a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
HRC3.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
HRC3.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
HRC3.5c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
HRC3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
HRC3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
HRC3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
HRC3.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
HRC3.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
HRC3.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
HRC3.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
HRC3.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
HRC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
HRC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
HRC6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
HRC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
IGN1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
IGN1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
IGN2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
IGN2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
IGN2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
IGN3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
IGN3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
IGN3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
IGN3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
IGN3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
IGN3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
IGN5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
IGN5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
IGN5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
IGN6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
IGN6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
IGN7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Register Transfer Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
RTL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
RTL1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
RTL1.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
RTL1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
RTL1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
RTL1.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
RTL1.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
RTL1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
RTL1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
RTL1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
RTL1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
RTL1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
RTL1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
RTL1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
RTL1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
RTL2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
RTL2.1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
RTL2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
RTL2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
RTL2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
RTL2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
RTL2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
RTL2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
RTL2.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
RTL2.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
RTL2.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
RTL2.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
RTL2.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
RTL2.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
RTL3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
RTL3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
RTL3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
RTL3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
RTL3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
RTL4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
RTL4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
RTL4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
RTL4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
RTL5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
RTL5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
RTL5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
RTL5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
RTL6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
RTL6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
RTL6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
RTL6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
RTL6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
RTL6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
RTL7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
RTL7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
RTL7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
RTL7.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
RTL7.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
RTL7.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
RTL7.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
RTL7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
RTL7.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
RTL7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
RTL7.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
RTL7.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
RTL7.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
RTL7.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
RTL7.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
RTL7.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
RTL7.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
RTL7.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
RTL7.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
RTL7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
RTL7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
RTL8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
RTL8.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
RTL8.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
RTL8.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
RTL8.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
RTL9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
RTL9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
RTL9.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
RTL9.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
RTL9.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
RTL9.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
RTL9.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
RTL9.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
RTL9.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
RTL9.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
RTL9.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
RTL9.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
RTL9.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
RTL10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
RTL11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
RTL12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
RTL12.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
RTL13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
RTL13.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
RTL13.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
RTL14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
RTL14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
RTL15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
RTL15.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
RTL15.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
RTL16.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
RTL16.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
RTL17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
RTL17.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
RTL18.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
RTL18.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
RTL18.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
RTL18.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
RTL19.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
RTL20.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
RTL20.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
RTL20.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
SPICE Netlist Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
SPI1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
SPI1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
SPI1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
SPI1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
SPI3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
SPI4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
SPI4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
SPI5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
SPI5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
SPI7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
SPI7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
SPI8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
System Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
SV1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
SV1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
SV1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
SV1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
SV1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
SV1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
SV1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
SV1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
SV1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
SV1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
SV1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
SV1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
SV1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
SV1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
SV1.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
SV2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
SV2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
SV3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
User-Dened Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
UDP1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
UDP1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
UDP1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
UDP2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
UDP2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
UDP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
UDP3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
UDP3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
UDP4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
UDP4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
VLG1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
VLG1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
VLG1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
VLG1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
VLG2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
VLG2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
VLG2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
VLG3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
VLG3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
VLG3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
VLG3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
VLG3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
VLG3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
VLG3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
VLG4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
VLG4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
VLG4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
VLG4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
VLG5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
VLG5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
VLG5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
VLG5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
VLG5.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
VLG5.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
VLG6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
VLG6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
VLG6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
VLG6.3a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
VLG6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
VLG6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
VLG6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
VLG6.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
VLG6.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
VLG6.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
VLG6.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
VLG6.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
VLG6.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
VLG6.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
VLG6.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
VLG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
VLG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
VLG9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
VLG9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
VLG9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
VLG9.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
VLG10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
VLG10.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
VLG10.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
VLG10.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
VLG11.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
VLG11.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
VLG12.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
VLG13.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
VLG13.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
VLG13.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
VLG14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
VLG15.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
VLG16.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
4
Modeling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
F11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
F12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
F13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
F14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
F14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
F16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
F17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
F18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
F19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
F21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
F23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
F25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
F26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
F27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
F28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
F30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
F32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
F34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
F34.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
F34.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
F34.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
F36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
F39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
F41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
F42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
F43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
5
Tcl Command Entry Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
get_compare_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
get_compare_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
get_exit_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
get_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_fanins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_gate_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_gate_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_gate_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
get_handle_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
get_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
get_keypoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
get_map_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
get_module_denition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
get_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
get_parent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
get_primitive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
get_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
get_root_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
get_unmap_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
set_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
echo_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
get_license_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
get_version_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
objtype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
About This Manual
This manual documents commands, HDL rule checking messages, and modeling messages
for the following Encounter
Conformal
Equivalence Checking solutions:

I Conformal Extended Checks
Conformal Extended Checks has equivalency checking capabilities with functional
checks for ASIC design ows.
I Conformal Ultra
Conformal Ultra includes Extended Checks and extends equivalency checking
capabilities to datapath synthesis and layout.
I Conformal Custom
Conformal Custom includes Conformal Ultra and extends equivalency checking
capabilities to digital custom logic and custom memories.
I Conformal LowPower
Conformal LowPower enables low power equivalence and functional checks for isolation
cells, level-shifter cells, and retention-register cells.
Audience
This manual is written for experienced designers of digital integrated circuits who must be
familiar with RTL, synthesis, and design verication; as well as having a solid understanding
of UNIX and Tcl/Tk programming.
Related Documents
For more information about the Conformal family of products, see the following documents.
You can access these and other Cadence documents with the CDSDoc online documentation
system. For a complete list of documents provided with this release, see the CDSDoc library.
About This Manual
I Encounter Conformal Equivalence Checking User Guide
Describes how to install, congure, and use Conformal to verify RTL, gate, or transistor-
level designs.
Conventions
Convention Denition
Bold Case Indicates the command name.
UPPERCASE Indicates the required minimum character entry.
< > Indicates required arguments. Do not type the angle brackets.
[ ] Indicates optional arguments. Do not type the square brackets.
| Indicates a choice among alternatives. Do not type the vertical
bar.
\ The backslash character (\) at the end of a line indicates that the
command you are typing continues on the next line.
Indicates multiple entries of an argument.
* Indicates that LEC lets the wildcard (*) represent zero or more
characters.
2
Command Reference
This chapter describes the Encounter
Conformal
commands. The commands are

presented in alphabetical order.
This chapter also includes the following sections:
I Command Syntax on page 26
I Wildcards on page 28
I Using UNIX Commands with Conformal on page 30
Command Reference
Command Syntax
I Conformal commands are not case sensitive.
I For every Conformal ADD command, there are corresponding DELETE and REPORT
commands. For example:
ADD OUTPUT EQUIVALENCES
DELETE OUTPUT EQUIVALENCES
REPORT OUTPUT EQUIVALENCES
I Conformal commands adhere to the 3-2-1 rule, which reduces the number of
characters you must type.
3: Type the leading three characters of the rst term.
2: Then type the leading two characters of the second term.
1: End with the leading character of the third term.
In some cases, you must use more characters to resolve ambiguity. In this manual, the
minimal sets of characters you must type are shown as uppercase letters in the syntax.
When you use the 3-2-1 rule in conjunction with the syntax guide to resolve any possible
ambiguity, you reduce the number of characters in a command, as the following example
shows:
ADD OUtput Equivalences
becomes
add ou e
I Reduce the number of characters you type for command options to the characters shown
in uppercase in the syntax, as the following example shows:
add output equivalences out10 out20 -module sub_mod1 -revised
becomes
add ou e out10 out20 -m sub_mod1 -r
Command Reference
Searching the Help Database for Specied Strings
Use the SEARCH command to search s the Help database of commands and options for
matches to strings you specify.
Viewing TCLmode Help Information
The HELP command also displays a list of Conformal TCLmode commands. While in
TCLmode, use the following syntax:
HELp
To view command usage for a specic command, use the HELP command followed by the
command name.
HELp [command_name]
System prompt and command example:
TCL_SETUP> help set_current_module
Viewing Conformal UNIX-Style Man Pages
Conformal includes a man directory housed in: <install_dir>/doc/mann/.
Important
Observe the following requirements for viewing UNIX-style man pages:
You must type the entire command name.
Do not apply the 3-2-1 rule (described below).
Do replace each space in the command name with an underscore ( _ ).
1. To access this resource from your UNIX shell, add the following variable:
% setenv MANPATH <install_dir>/doc:$MANPATH
2. Type the following:
man command_name
For example:
man read_design
man set_system_mode
Command Reference
Wildcards
On an as-needed basis, Cadence adds wildcard pattern-matching support to Conformal
commands. The syntax convention that alerts you to wildcard support is the asterisk (*).
If you use a pattern where a lename or design object is expected, Conformal Equivalence
Checker expands the pattern using the same conventions as in the UNIX shell.
I Triggering pattern matching for lenames
To trigger pattern matching for lenames, a string must include at least one asterisk (*),
question mark (?), or a pair of square brackets ( [ ] ).
I Triggering pattern matching for design objects
To trigger pattern matching for design objects, a string must include at least one asterisk
(*) or question mark (?).
In arguments that are considered patterns, the following characters have special meaning: ^,
{, }, [, ], ?, *. The dash (-) also has special meaning when it falls between square brackets.
Note: When you use wildcards for design objects, a wildcard can match a string that includes
the hierarchical delimiter (/). For example, the pattern *[10] matches the design object
a/b/c[10].
When you use wildcards for lenames, every wildcard applies to part of a single directory or
lename (this convention is the normal UNIX convention). For example, the pattern *.v does
not match the lename a/b/c.v.
Special Characters for Filename and Design Object Pattern-Matching
Wildcard
Character
Denition Example
? Match any single character. a?c matches:
aac, abc, a4c, a?c
* Match any (possibly empty) string. a*c matches the following:
ac, abc, a*c
Command Reference
[ ]
That is, [
followed by
characters and
]
Match any single character listed
between the square brackets: [
and ].
If the rst character is ^,
Conformal Equivalence Checker
matches any single character not
listed between the brackets.
If the list shown between the
brackets includes x-y, Conformal
Equivalence Checker matches all
characters in the range xy.
To match square brackets, you must
include the escape character
immediately preceding the square
bracket.
To be matched, the characters -
and ] must appear rst in the list
(possibly after ^).
Note: For design objects, recall that
a string triggers pattern matching
with an asterisk or question mark. In
those cases, this convention applies.
For lenames:
a[145] matches the following:
a1
a4
a5
For design objects:
a*[145] matches the following:
ab1
a34
at5
a*\[145\] matches the following:
ab[145]
a3[145]
at[145]
^ At the beginning of the pattern, the
character ^ negates the result of
the match:
â* matches any name that does
not begin with a.
\ Matches only the character that
follows the \ character.
a\[10] matches the following:
a[10]
But it does not match:
a1
a0
Wildcard
Character
Denition Example
Command Reference
Using UNIX Commands with Conformal
To execute a UNIX command from within LEC or an LEC command script, start the line with
an exclamation point ! or with the SYSTEM command. When you execute commands in this
way, they display to the standard output, and LEC records them in a log le, if one is active.
Using the -all Option
This option applies within the given defaults. For example, the syntax for the ADD OUTPUT
EQUIVALENCES command is as follows:
<primary_pin primary_pin*...>
[-Invert <primary_pin*...>]
[-ROot | -Module <name*> | -All]
[-Golden | -Revised | -Both]
In the above syntax, -golden is a default. Therefore, if you type the command with primary
pin names and the -all option, but no other option, this command species output pin
equivalences on all output boundary module pins in the Golden design.
{p1,p2,} Matches any string matched by any
of the sub-patterns listed.
design/{top,sub{5,11}}/*.v
matches the following:
design/top/a.v
design/sub5/b.v
design/sub11/c.v
Braces can nest.
a/{d{e,f},g{h,i}}_0 matches
the following:
a/de_0
a/df_0
a/gh_0
a/gi_0
Wildcard
Character
Denition Example
Command Reference
Using the -both Option
When you use this option in conjunction with a specic name (for example, a pin name), that
name must appear in both designs. Otherwise, LEC returns an error message. For example,
the syntax for the ADD PIN EQUIVALENCES command is as follows:
ADD PIn Equivalences
<primary_pin primary_pin*...>
[-Invert <primary_pin*...>]
[-ROot | -Module <name*> |-All]
[-User | -Hier]
[-Golden | -REvised | -Both]
Notice -both in the above syntax. If you specify three primary pins (for example, a1, a2, and
a) and the -both option; all three pin names must exist in both the Golden and Revised
designs. If they do not, LEC returns an error message.
If you specify a1, a2, a and include the -revised option; LEC applies equivalence to the
pins in the Revised design only (even if these three pins also exist in the Golden design).
Saving the Commands Output to a File
To save the commands output to a le, Cadence recommends using the command line >
operator. This works for all Conformal commands.
For example, to save the default output of the REPORT GATE command to a le named
gate.out, you would run the following:
report gate > gate.out
You can also use the >> operator to append output text to an existing le.
Note: Although some commands include a -file <filename> type option to save the
commands output to a le, Cadence recommends using the command line > operator.
Command Reference
ABSTRACT LOGIC
ABSTract LOGic
[-MODule <name>]
[-All]
[-PURE]
[-AUTO | -NOAUTO]
[-Golden | -Revised]
[-ASM | -NOASM]
[-TEST_VIEW]
(Setup Mode)
Note: This is a Conformal Custom command. Use this instead of the pre-5.0 EXTRACT
command.
Performs functional analysis on circuit netlists, which can contain different devices, including
transistors, gates, and state elements. The analysis abstracts a logically-correct gate and a
state primitive model. Use the logic model and compare it to the RTL model for complete
functional verication. You can also write out the logic model and use it during
high-performance simulation or fault grading.
Note: If neither the -all nor -module option is specied, Conformal abstracts the current
root module and any modules that are instantiated under it.
Parameters
-MODule name Abstracts logic information fromthe specied module and its
hierarchy.
-All Abstracts logic information from all cells in the database,
including cells that are not used by the current root module.
-Pure Performs basic gate abstraction, which is useful for
debugging.
-AUTO Enables propagation of constants, pin constraints,
non-inverted and inverted pin relationships across module
boundaries. This is the default.
-NOAUTO Does not invoke hierarchical analysis.
-Golden Abstracts logic from the Golden design. This is the
default.
-Revised Abstracts logic from the Revised design.
Command Reference
Related Commands
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
ASSIGN PIN DIRECTION
DELETE CLOCK
DELETE MOS DIRECTION
DELETE NET ATTRIBUTE
MOS2BUFIF
READ PATTERN
REPORT ABSTRACT MODEL
REPORT CLOCK
REPORT MOS DIRECTION
-ASM Enables the Advanced State-element Modeling (ASM)
algorithm. This helps to analyze loop structure to produce
better modeling of state elements, such as D-Latch, DFF,
and bus-keeping I/O logic. This is the default.
-NOASM Disables the Advanced State-element Modeling (ASM)
algorithm.
Tip
If there are any unexpected results, you can use this
option to revert back to the functionality of the 6.2
release and earlier.
-TEST_VIEW Performs structurally accurate abstraction. With this option,
only limited boolean simplication is done for abstraction. As
a result, the gate-level structure of the original logic is
preserved as much as possible after abstraction.
Command Reference
REPORT NET ATTRIBUTE
REPORT PIN DIRECTION
RESET ABSTRACT MODEL
RESOLVE
SET ABSTRACT MODEL
Command Reference
ADD ALIAS
ADD ALias
<name> <string>
(Setup / LEC Mode)
Adds alias names for quick command entry. Assign an alias to long command names and
arguments to minimize typing and character entry.
If you add an alias with an alias name that already exists, Conformal accepts the new alias
and returns a warning as shown in the following example:
//Warning: Alias myread is already defined, will be replaced by the new definition
For the greatest benet, create aliases at the start of a Conformal session. Also, add aliases
to an initial command le: .conformal_lec.
The CONFORMAL_RC Environment Variable
Conformal checks for the CONFORMAL_RC environment variable. If this variable is set,
Conformal uses the le this variable refers to and does not search for other les.
If the CONFORMAL_RC variable is not set, Conformal continues the search as follows:
I First, the installation directory:
<install_dir>/share/cfm/lec/.conformal_lec
I Second, the users home directory: ~/.conformal_lec
I Third, the current working directory: ./.conformal_lec
If one or more of these initial command les exist, Conformal runs them in the order noted
above. This process offers exibility in the way you choose to use the initial command le. You
can set up initial command les for any or all of the following purposes:
I A global initial command le for all users
I A global initial command le for an individual user
I An initial command le for a test case
Parameters
name Species the name of the alias.
Command Reference
Related Commands
DELETE ALIAS
REPORT ALIAS
string Species the command that the alias represents.
Command Reference
ADD BLACK BOX
ADD BLack Box
[<[-Module | -Instance] [name*] [-File <filename>]> | -All]
[ | -Design | -Library]>
(Setup Mode)
Species modules or instances that will be dened as blackboxes. These newly dened
blackboxes are classied in the User class of blackboxes. Blackboxes already contained in
the original design are classied in the System class of blackboxes.
Note: The wildcard (*) represents any zero or more characters in blackbox names.
Parameters
-Module Denes this list of module names as blackboxes. This is the
default.
-Instance Denes this list of instance names as blackboxes.
name ... Denes the list of names of modules or instances.
Note: Wildcard names are only supported for the module
names. The wildcard (*) represents any zero or more characters
in the blackbox module names.
-File <filename> Species the name of the blackbox le. This le must contain
only names of modules or instances, it is not a Verilog le. The
names in the le are added to the [name...] list.
-All Blackboxes all modules except the top module. -All applies
within the given defaults.
-Design (Used with the -all option only) Blackboxes all modules in the
design.
If you do not specify either -design or -library, blackboxing
applies to both the library and the design.
-Library (Used with the -all option only) Blackboxes all modules in the
library.
If you do not specify either -design or -library, blackboxing
applies to both the library and the design.
-Golden Blackboxing applies to the Golden design only. This is the
default.
Command Reference
Related Commands
DELETE BLACK BOX
REPORT BLACK BOX
-Revised Blackboxing applies to the Revised design only.
-Both Blackboxing applies to both the Golden and Revised designs.
Command Reference
ADD CLOCK
ADD CLock
<0 | 1>
<primary_pin> [-Module <name>]
(Setup Mode)
Denes a clock state where data can change. You can use this command to dene:
I Pre-charge clock states for domino style circuits
I Stable nets for clock-gating modeling
Caution
When using the ADD CLOCK command with set flatten model
-gated_clock, there is an assumption that the ENABLE signal going into
the AND gate of the clock cone is stable. Use with caution.
Parameters
Related Commands
ABSTRACT LOGIC
ADD MOS DIRECTION
ADD NET ATTRIBUTE
0 Species that the off-state of the clock pin is 0. This means that
when the pin is low, pre-charge occurs.
1 Species that the off-state of the clock pin is 1.
primary_pin Denes the listed primary input pins as clocks in pre-charged
transistor-MOS.
-Module name Species that the dened clock pin is located in this module.
-Golden Species that the clock is in the Golden design. This is the
default.
-Revised Species that the clock is in the Revised design.
Command Reference
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
SET ABSTRACT MODEL
Command Reference
ADD COMPARED POINTS
ADD COmpared Points
<-All |<gate_id ... | instance_pathname* ... | pin_pathname* ...
[-FRONTier]
>
>
(LEC Mode)
Adds mapped points to the compare list. You can add compare points for all mapped points,
or for a list of the gate ID numbers, instance paths, or pin paths.
If you add a compare point to the Golden design, the Conformal software also adds its
mapped compare point from the Revised design. Alternately, if you add a compare point to
the Revised design, the software also adds its mapped compare point in the Golden design.
Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths.
Parameters
-All Adds all mapped points, excluding primary inputs, as compare
points. -All applies within the given defaults.
gate_id Adds the specied gate ID numbers as compare points.
Note: ID numbers can differ from one version of Conformal to
another. Always use the full path in doles and any time you
rerun a design with a different Conformal version.
instance_pathname* Adds the specied instance paths as compare points.
pin_pathname* Adds the specied pin paths as compare points.
-FRONTier Adds the specied key points and its frontier to the compare list.
If no key points are specied, the frontier is computed from the
existing compare points, and added to the compare list. No key
points are added to the compare list if the frontier contains any
unmapped key points.
-Golden The gate ID numbers, instance paths, or pin paths are in the
Golden design. This is the default.
-Revised The gate ID numbers, instance paths, or pin paths are in the
Revised design.
Command Reference
Examples
For a set of sample commands that shows this and related commands in context, see the
example for the COMPARE command.
Related Commands
DELETE COMPARED POINTS
REPORT COMPARED POINTS
Command Reference
ADD CUT POINT
ADD CUt Point
<pathname>
[-Net | -Pin]
(Setup Mode)
Adds a cut point to the specied net or pin path. This overrides automatic feedback loop cuts,
which Conformal otherwise establishes on entering the LEC mode.
Parameters
Related Commands
DELETE CUT POINT
REPORT CUT POINT
REPORT PATH
pathname Species the path that is the cut point of the feedback loop.
-Net Species that the path is a net. This is the default.
-Pin Species that the path is a pin.
-Golden Applies the cut point to the Golden design. This is the default.
-Revised Applies the cut point to the Revised design.
-Both Applies the cut point to both the Golden and Revised designs.
Command Reference
ADD DYNAMIC CONSTRAINTS
ADD DYnamic Constraints
<0 | 1>
<identifier>
[-INStance | -Pin | -Net | -ID]
(LEC Mode)
Adds dynamic constraints for use with the PROVE command. Place constraints on the
following:
I Hierarchical instance paths
I Hierarchical pin paths
I Hierarchical net paths
I Gate identication numbers
These constraints are either a 0-state or 1-state. Use this command as you diagnose and
debug logic cones to help prove gate equivalence.
Parameters
0 Constrains the identier to a 0-state.
1 Constrains the identier to a 1-state.
identifier If you do not specify one of the following options, Conformal
automatically determines if the identier is a number or a path.
In the case of a number, Conformal uses the -id option;
otherwise, Conformal searches for the gate with the
-instance, -pin, or -net option; in this respective order.
-INStance Hierarchical instance path
This is the default.
-Pin Pin path, which is the module instance name
concatenated with the pin name.
-Net Net path, which is the instance name
concatenated with the net name.
Command Reference
Examples
Related Commands
DELETE DYNAMIC CONSTRAINTS
PROVE
REPORT DYNAMIC CONSTRAINTS
-ID Identication number (ID) of a gate.
The identication number is an integer
assigned automatically by Conformal.
Note: IDnumbers can differ fromone version
of Conformal to another. Always use the full
path in doles and any time you rerun a
design with a different Conformal version.
-Golden Adds the dynamic constraints to the Golden design only. This
is the default.
-Revised Adds the dynamic constraints to the Revised design only.
-Both Adds the dynamic constraints to both the Golden and Revised
designs.
Command Reference
ADD ECO CELL
ADD ECo Cell
[-DEFfile <filename>]
[-FReedcell]
[-SParecell <cell_name*>]
(Setup Mode)
Adds the spare cells or freed cells as the available cells for the MAP ECO PATCH command.
Parameters
Related Commands
DELETE ECO CELL
MAP ECO PATCH
REPORT ECO CELL
-DEFfile <filename> Species the DEF le name. If specied, the spare cell will be
searched in DEF le. Otherwise, the spare cell will be searched
in current hierarchy.
-FReedcell Species that freed cells will be used for mapping.
-SParecell Species the spare cells to be added.
Command Reference
ADD ECO LIBRARY
ADD ECo Library
[<library_name> | -ALL]
(Setup Mode)
Adds the library to the library list used by the by the MAP ECO PATCH command.
Parameters
Related Commands
MAP ECO PATCH
<library_name> Species the name of the library.
-ALL Adds all the libraries in Golden or Revised.
-Golden Species that the library is in the Golden library. This is the
default.
-Revised Species that the library is in the Revised library.
Command Reference
ADD ECO PATCH
ADD ECo PAtch
<module_under_ECO_name>
<patch_module_name>
[-PATH <hierarchy-path>]
(Setup Mode)
Species the ECO patch and adds the patch module to be mapped by the MAP ECO PATCH
command.
Parameters
Examples
In the following command sequence, the ECOs dened in the G1_eco and G2_eco patch
modules will be applied to the design and mapped to the spare cells and freed cells, and will
write out the new mapped patch modules to the map.v le.
add eco patch G1 G1_eco -path /U1/U1
add eco patch G2 G2_eco -path /U1/U2
add eco library typical
add eco cell -def layout.def -freed -spare *spare*
map eco patch map.v -replace
Related Commands
ADD ECO CELL
ADD ECO LIBRARY
Species the name of the module being changed for ECO.
<patch_module_name> Species the name of the patch module that contains the ECO
changes.
[-PATH <hierarchy-path>]
Species the hierarchy path to the module under ECO. This is
for the ADD ECO CELL command to locate the freed cell
locations in DEF le.
Command Reference
DELETE ECO PATCH
MAP ECO PATCH
REPORT ECO PATCH
Command Reference
ADD ECO PIN
ADD ECo PIn
<module_name>
<pin_name> | <bus_name <size>> ...
[-INput | -OUTput | -IO]
[-FORce]
(Setup Mode)
Adds a pin to a module. If the Revised module has extra ports, you can use this command to
add newpins to the Golden module. Cadence recommends that you add the extra pins before
running the WRITE HIER_COMPARE DOFILE command.
Parameters
Examples
I The following command adds wr_req input port and data[15:0] input bus to module
mod_A
add eco pin mod_A wr_req data[15:0] -input -golden
I This example shows how the commands -force option affects the following design:
module top(x,y);
<module_name> Species the name of the module.
<pin_name> Species the name of the pin(s).
<bus_name <size>> Species the name of the bus(es), where <size> is
[msb:lsb], for example, [16:0].
You must include the braces in the command. See the
Examples section.
-INput Species that the pin is an input pin. This is the default.
-OUTput Species that the pin is a output pin.
-IO Species that the pin is an input/output pin.
-FORce Renames the signal if it conicts with the port name. See the
Examples section.
-Golden Applies to the Golden design. This is the default.
-Revised Applies to the Revised design.
Command Reference
wire z;
endmodule
The following command will error out because there is a conict between the net z
and the new port z:
add eco pin -output top z
The following command will not error out and net z will be renamed z_1:
add eco pin -output top z -FORce
Related Commands
ANALYZE ECO
DELETE ECO PIN
WRITE HIER_COMPARE DOFILE
Command Reference
ADD IGNORE RTLCHECK
ADD IGnore Rtlcheck
<-All | -Module <name*>>
(Setup Mode)
Ignores RTL (HDL) rule checking for all or specied modules. Run this command before the
READ LIBRARY and READ DESIGN commands.
Refer to the Encounter Conformal Equivalence Checking User Guide for additional
information about specic rules.
Tip
When using the -module option, ensure that you have entered the module name
correctly. If you enter a nonexistent module name, Conformal conducts the checks
and issues messages as usual.
Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace
previous commands. In the following example, Conformal ultimately enables RTL rule
checking for all modules, including module abc.
add ignore rtlcheck -module abc
delete ignore rtlcheck -all
Wildcard: The wildcard (*) represent any zero or more characters in module names.
Parameters
Related Commands
DELETE IGNORE RTLCHECK
REPORT RULE CHECK
-All Ignores RTL rule checking for all modules.
-Module name* Ignores RTL rule checking for the specied modules.
Command Reference
ADD IGNORED INPUTS
ADD IGnored Inputs
<primary_pin*>
(Setup Mode)
Species which input pins Conformal ignores during comparison. You can use this command
when the input pins are part of a blackboxed module.
Note: Specied pins must be boundary module pins. Although boundary module pins are
generally not compared points, they are compared points when the corresponding module
becomes a blackbox.
For example, when Conformal compares two blackboxes and one of them has extra input
pins, such as scan in and scan enable pins, use this command to tell Conformal to ignore
these extra input pins during comparison.
Wildcard: The wildcard (*) represent any zero or more characters in ignored inputs and
module names.
Parameters
primary_pin* Ignores this list of primary input pins (associated with the root
module or the specied submodule).
-ROot Ignores the specied input pins in the root module. This is the
default.
-Module name* Ignores the specied input pins in this module.
-All Ignores the specied input pins in all the modules, including
the root module. -All applies within the given defaults.
-Golden Ignores the specied input pins in the Golden design. This is
the default.
-REvised Ignores the specied input pins in the Revised design.
-Both Ignores the specied input pins in both the Golden and Revised
designs.
Command Reference
Related Commands
DELETE IGNORED INPUTS
REPORT IGNORED INPUTS
Command Reference
ADD IGNORED OUTPUTS
ADD IGnored Outputs
<primary_pin*>
[-Module <name*> |-All]
[-Golden |-REvised |-Both]
[-EQuivalences]
(Setup Mode)
Species which output pins Conformal ignores during comparison.
Note: Specied pins are boundary module pins. For example, when Conformal compares
two modules and one of themhas extra outputs, such as scan out pins, use this command to
tell Conformal to ignore these extra output pins during comparison.
Wildcard: The wildcard (*) represents any zero or more characters in ignored outputs and
module names.
Parameters
Related Commands
primary_pin* Ignores this list of primary output pins (associated with the root
module or the specied submodule).
-Module name* Ignores the output pins in the specied module. The default is
the root module.
-All Ignores the specied output pins in all the modules, including
the root module. -All applies within the given defaults.
-Golden Ignores the specied output pins in the Golden design. This is
the default.
-REvised Ignores the specied output pins in the Revised design.
-Both Ignores the specied output pins in both the Golden and
Revised designs.
-EQuivalences Ignores the specied output pins and their equivalences. The
equivalences of a pin must be specied by the ADD OUTPUT
EQUIVALENCES command prior to using this option.
Equivalences created after using this option will not be ignored.
Command Reference
DELETE IGNORED OUTPUTS
REPORT IGNORED OUTPUTS
Command Reference
ADD INSTANCE ATTRIBUTE
ADD INstance Attribute
<module_name> <instance_name>
[<WEAK> | <DELETE>]
(Setup Mode)
Species how to treat an attribute for a gate or transistor primitive. Attributes can either be
WEAK or deleted from the database for the purposes of a complete abstraction and
comparison. However, newer abstraction capabilities can make the WEAK feature
unnecessary.
Parameters
module_name Applies the instance attribute to the specied module, which
contains the instance.
instance_name Applies the instance attribute to the specied instance.
WEAK Note: This option applies to Conformal Custom.
Species drive strength of WEAK on an attribute.
In the case of multiple drivers,
I First, the state of the node is determined by devices that are
not WEAK (STRONG).
I Then, if there are none, or if all of the STRONG devices are
disabled, the WEAK devices impact the nets function.
This option affects extraction behavior and loop handling.
DELETE Removes the specied device from the circuit.
Note: This option applies to Conformal Custom.
Tip
The preferred method is to use the REMOVE command.
-Golden Applies the instance attribute to the Golden design. This is the
default.
-Revised Applies the instance attribute to the Revised design.
Command Reference
Related Commands
DELETE INSTANCE ATTRIBUTE
REMOVE
REPORT INSTANCE ATTRIBUTE
Command Reference
ADD INSTANCE CONSTRAINTS
ADD INstance Constraints
<0 | 1>
<instance_pathname* | name -Module name*>
[-REPlace]
[-Golden |-Revised |-Both]
(Setup Mode)
Places constraints on specied instance paths in either the Golden or Revised design. You
can only place 0-state or 1-state constraints on the outputs of instances. You can only apply
instance constraints to D ip-ops and D-latches inside the specied instance paths.
Wildcard: The wildcard (*) represents any zero or more characters in instance and module
names.
Parameters
Examples
add instance constraints 0 /U1/U2/U3 -revised
add instance constraints 1 /U6/U5 /U7/U8 -golden
add instance constraints 0 /U6/U5 /U7/U8 -replace -golden
0 Constrains the specied instance paths to a 0-state.
1 Constrains the specied instance paths to a 1-state
instance_pathname* Places the constraints on these instance paths.
Note: The instances are either DFFs or D-latches.
name -Module name*
Applies the constraint to the specied module(s).
-REPlace Changes the previously specied instance constraint.
-Golden Applies the instance constraints to the Golden design. This is
the default.
-Revised Applies the instance constraints to the Revised design.
-Both Applies the instance constraints to both the Golden and
Revised designs.
Command Reference
Related Commands
DELETE INSTANCE CONSTRAINTS
REPORT INSTANCE CONSTRAINTS
Command Reference
ADD INSTANCE EQUIVALENCES
ADD INstance Equivalences
<instance_pathname*>
[-Invert <instance_pathname*>]
(Setup Mode)
Denes D-latches and D ip-ops as equivalent or inverted equivalences. This command is
useful in mapping and its output is veried during the comparison. Use this command when
you have one state element in a design that corresponds to two or more state elements in
another design.
Note: Only apply instance equivalences to D ip-ops and D-latches.
Effects on Comparison
This command affects comparisons when you use add compared points -all. In that
situation, Conformal merges the instances specied with the ADD INSTANCE
EQUIVALENCES command and then veries them at the end of the comparison.
Wildcard: The wildcard (*) represents any zero or more characters in instance names.
Parameters
instance_pathname* Denes the group of instances that are equivalent. The rst
instance is the representative instance. The following instances
are equivalent to the representative instance.
The wildcard (*) is supported.
-Invert instance_pathname*
Denes a group of instances that is an inverted equivalence of
the group that is equivalent.
-Golden Applies instance equivalences to the Golden design. This is
the default.
-Revised Applies instance equivalences to the Revised design.
Command Reference
Related Commands
ADD COMPARED POINTS
DELETE INSTANCE EQUIVALENCES
REPORT INSTANCE EQUIVALENCES
SET FLATTEN MODEL
-Both Applies instance equivalences to both the Golden and Revised
designs.
Command Reference
ADD LOWPOWER CELLS
ADD LOwpower Cells
<module_name*>
[-isolation | -level_shifter
| [-retention -attribute <attribute_name>] ]
[-Both | -Golden| -Revised]
(Setup Mode)
Note: This is a Conformal Low Power command.
Denes the low power attribute for specied modules.
Parameters
Examples
I The following command assigns cell fdf1a1 as a state retention cell with a CLK_LOW
attribute:
add lowpower cells fdf1a1 -retention -attribute CLK_LOW -revised
module_name Applies the low power cell attribute to the specied
module(s). Wildcards are accepted.
-isolation Species the module as isolation cell. This is equivalent to
the attribute is_isolation_cell : true in the liberty
library.
-level_shifter Species the module as level shifter cell. This is equivalent
to the attribute is_level_shifter : true in the liberty
library.
-retention -attribute <attribute_name>
Species the module as a state retention cell with its
associated power gate cell attribute. This is equivalent to the
attribute power_gating_cell : ATTRIBUTE in the
liberty library.
-Both Applies the low power cell attribute to both the Golden and
Revised designs. This is the default.
-Golden Applies the low power cell attribute to the Golden design.
-Revised Applies the low power cell attribute to the Revised design.
Command Reference
I The following command assigns cell and2b1 as an isolation cell:
add lowpower cells and2b1 -iso -revised
Related Commands
CHECK LOWPOWER CELLS
DELETE LOWPOWER CELLS
REPORT LOWPOWER CELLS
REPORT LOWPOWER DATA
SET LOWPOWER OPTION
Command Reference
ADD MAPPED POINTS
ADD MApped Points
<<<gate_id | instance_pathname | pin_pathname>
<gate_id | instance_pathname | pin_pathname>>
|<-NET <net> <net>>
|<-RULE <pattern> <substitution>>>
[-INSTance | -NET]
[-OUTput_pin <Golden_pin> <Revised_pin>]
[-INPut_pin <Golden_pin> <Revised_pin>]
[-GOLden | -REVised]
[-NOINVert | -INVert]
(LEC Mode)
When Conformal moves from Setup to LEC system mode, it automatically maps key points
and places them in the System class of mapped points. If any additional mapped points are
necessary, use this command, and Conformal will place them in the User class of mapped
points.
Note: If you attempt to add mapped points that were already mapped, Conformal returns a
warning message.
In the syntax shown below, the rst gate_id, instance_pathname, or pin_pathname
refers to the Golden design; the second argument refers to the Revised design.
The -invert option makes one mapped point inverted with respect to the other mapped
point. The (-) sign represents an inverted-mapped point. The (+) sign represents a
non-inverted mapped point.
Parameters
gate_id Adds this gate (identied by number) as a mapped point.
instance_pathname Adds this instance path as a mapped point.
pin_pathname Adds this pin path as a mapped point.
-NET net net Uses the specied Golden and Revised net names to map key
points together.
-RULE pattern substitution
Command Reference
Examples
In the following two commands, A1 is the instance path of a blackbox:
add mapped points A1 A1 -input_pin in1[0] inA[0] -input_pin in1[1] inA[1]
add mapped points A1 A1 -output_pin out1[0] outA[0] -output_pin out1[1] outA[1]
Related Commands
DELETE MAPPED POINTS
Uses the instance or net renaming rule with the specied
original pattern and substitution pattern to map key points
together.
-INSTance Species that the rule is an instance renaming rule. This is the
default.
-NET Species that the rule is a net renaming rule.
-OUTput_pin Golden_pin Revised_pin
Maps the specied Golden and Revised blackboxed output
pins. Multiples are permitted. However, you must list Golden
and Revised pins in pairs and you must precede each pair with
the -output_pin option. (See the example below. For each
pair that is listed, the rst output pin is from the Golden design
and the second output pin is from the Revised design.)
-INPut_pin Golden_pin Revised_pin
Maps the specied Golden and Revised blackboxed input pins.
Multiples are permitted. However, you must list Golden and
Revised pins in pairs and you must precede each pair with the
-input_pin option. (See the example below. For each pair
that is listed, the rst input pin is from the Golden design and
the second input pin is from the Revised design.)
-GOLden Applies this rule pattern substitution to the Golden design. This
is the default.
-REVised Applies this rule pattern substitution to the Revised design.
-NOINVert Does not invert the two mapped points with respect to one
another. This is the default.
-INVert Inverts the two mapped points with respect to one another.
Command Reference
INVERT MAPPED POINTS
MAP KEY POINTS
READ MAPPED POINTS
REPORT MAPPED POINTS
REPORT UNMAPPED POINTS
SET MAPPING METHOD
SET NAMING RULE
Command Reference
ADD MODULE ATTRIBUTE
ADD MOdule Attribute
<module_name*>
<-PIPELINE_Retime [-DFF2Buffer]
| -COMPARE_Effort < Low | Medium | High | AUto | None>
| -CPU_Limit # >
[-Golden |-Revised]
[-ECO_module]
[-HIER_Compare <hier_compare_script>]
(Setup Mode)
Denes the attributes for specied modules.
Parameters
module_name* Applies the attribute to the specied modules. The wildcard (*)
is supported.
-PIPELINE_Retime Checks the specied modules for pipeline retiming (and
remodel if pipeline retiming is detected).
This option requires Conformal to check the module and
remodel it if the Golden and Revised designs have
pipeline-retiming.
-DFF2Buffer Changes registers to buffers.This option lets you compare
models with no registers to those with pipeline registers
inserted.
-COMPARE_Effort Assigns a specied comparison effort level to the module. This
option is generally applied to hierarchical comparisons where
some modules need a higher compare effort than others.
For advanced pipeline retiming, see ANALYZE RETIMING.
Low Applies minimal effort to equivalency
checking for the specied module. This is
the default.
Medium Applies greater effort to equivalency
checking for the specied module.
High Applies the maximum effort to equivalency
Command Reference
Example
In the following command sequence, the hierarchical dole script hier.do that is generated
with the write hier_compare dofile command contains the commands add
partition points -all, set compare effort high, add compared points
-all, and compare for module modA, instead of the default add compared points
-all and compare command sequence:
add module attribute modA -hier_compare "add partition points -all; set compare
effort high; add compared points -all; compare"
write hier_compare dofile hier.do -constraints
Related Commands
ANALYZE RETIMING
DELETE MODULE ATTRIBUTE
REPORT MODULE ATTRIBUTE
AUto Starts with low effort and automatically
increases the compare effort when abort
points are in the specied module.
None Applies no compare effort to equivalency
-CPU_Limit # Species a number of seconds for each module during
hierarchical compare.This option decreases the amount of time
Conformal spends comparing a particular module.
-Golden Species that the module attribute applies to the Golden
design. This is the default.
-Revised Species that the module attribute applies to the Revised
design.
-HIER_Compare <hier_compare_script>
For the specied module, replaces the default add compared
points -all and compare commands in the hierarchical
script generated using the write hier_compare dofile
command with the specied <hier_compare_script>.
Command Reference
ADD MOS DIRECTION
ADD MOs Direction
<module_name instance_name net_name | <-Module <name> | -All>
[-FROM_Source_pin | -FROM_Drain_pin]>
>
(Setup Mode)
Note: This is a Conformal Custom command.
Adds unidirection to bidirectional MOS devices. This can change a tranif0 into a PMOS,
or change a tranif1 to an NMOS.
Use the REPORT MOS DIRECTION command to display the list of all unidirectional and
bidirectional transistor-MOS instances and their source and drain ports.
Use this command to resolve bidirectional transistor-MOS instances, when the ABSTRACT
command is not able to fully resolve all bidirectional transistor-MOS instances not supported
for comparison.
Parameters
module_name Adds unidirection to the specied module.
instance_name Adds unidirection to the specied instance.
net_name Species the source net name, which is the input pin of the
MOS device.
-Module name Adds unidirection to all bidirectional MOS devices in this
module.
-All Adds unidirection to all bidirectional MOS devices. -All
applies within the given defaults.
-FROM_Source_pin Species that all source pins are inputs. This is the default.
-FROM_Drain_pin Species that all drain pins are inputs.
-Golden Applies the MOS direction to the Golden design. This is the
default.
-Revised Applies the MOS direction to the Revised design.
Command Reference
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
ADD NET ATTRIBUTE
ADD NEt Attribute
<VDD | GND | CLOCK0 | CLOCK1 | DYNSTate>
<net_name>
[-Module <name>]
(Setup Mode)
Denes pre-charge nets; power and ground; or with DYNSTate, denes a dynamic latch
state.
If you do not use the -module option with this command, Conformal applies the attribute to
every module on the specied side (Golden or Revised).
Parameters
VDD Species that the net has a VDD attribute.
GND Species that the net has a GND attribute.
CLOCK0 Species that the net has a Clock-0 attribute. This option
places an off-state of 0 at the specied net.
The off-state is dened as the value at which the clock port
is inactive.
CLOCK1 Species that the net has a Clock-1 attribute. This option
places an off-state of 1 at the specied net.
The off-state is dened as the value at which the clock port
is inactive.
DYNSTate Species that the net is a dynamic state point, which
Conformal Custom will abstract as a latch.
net_name Species the transistor-MOS net name.
-Module name Species that the specied module contains the
transistor-MOS. If you do not use the -module option with
this command, Conformal applies the attribute to every
module on the specied side (Golden or Revised).
-Golden Applies the net attribute to the Golden design. This is the
default.
Command Reference
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
SET ABSTRACT MODEL
-Revised Applies the net attribute to the Revised design.
Command Reference
ADD NET CONSTRAINTS
ADD NEt Constraints
<ONE_Hot | ONE_Cold | ZERO_ONE_Hot | ZERO_ONE_Cold>
<net_pathname>
(Setup Mode)
Adds one-hot or one-cold constraints on specied net paths. The one-hot constraint lets only
one net be at a 1-state and the remaining nets be at a 0-state. The one-cold constraint lets
only one net be at a 0-state and the remaining nets be at a 1-state.
Parameters
Related Commands
DELETE NET CONSTRAINTS
REPORT NET CONSTRAINTS
ONE_Hot Places one-hot constraints on the specied net paths.
ONE_Cold Places one-cold constraints on the specied net paths.
ZERO_ONE_Hot Places zero-one-hot constraints on the specied net paths.
ZERO_ONE_Cold Places zero-one-cold constraints on the specied net paths.
net_pathname Places constraints on the listed net paths.
-Golden Applies the net constraints to the Golden design. This is the
default.
-Revised Applies the net constraints to the Revised design.
-Both Applies the net constraints to both the Golden and Revised
designs.
Command Reference
ADD NOBLACK BOX
ADD NOblack Box
<module_name* | All>
(Setup Mode)
Species the modules that are excluded from the hierarchical dole script generation.
(Execute it before the WRITE HIER_COMPARE DOFILE command.)
Wildcard: The wildcard (*) represents any zero or more characters in module names.
Parameters
Related Commands
DELETE NOBLACK BOX
REPORT NOBLACK BOX
module_name* Does not include the listed modules in the hierarchical dole
script generation.
All Does not include any instances or modules in the hierarchical
dole script generation except the top module.
All applies within the given defaults.
-Golden Does not include the specied modules in the Golden design.
-Revised Does not include the specied modules in the Revised design.
-Both Does not include the specied modules in either the Golden or
Revised designs.
Command Reference
ADD NOTRANSLATE FILEPATHNAMES
ADD NOtranslate Filepathnames
<filepath_names*>
[ | -Library | -Design]
[-Both | -Golden | -Revised]
(Setup Mode)
Species library or design les, where modules dened in these les will not be translated
when running the READ LIBRARY or READ DESIGN command. These modules will
automatically become blackboxes.
This command is applied during initial parsing, so name matching applies only to original
module names. For parameterized or VHDL generic modules whose names are determined
and applied by the Conformal software after parsing and preprocessing, you must use the
ADD BLACK BOX command.
The following are examples of modules that should not be compiled:
I RAM models
I Analog blocks
I Modules that contain non synthesizable RTL constructs
Parameters
filepath_names* Species the lepath name, which can be directory names
and Verilog lenames.The wildcard (*) and search path is
supported.
-Library Does not translate the modules in the specied library. If you
do not specify -library or -design, Conformal applies
this command to both the library and design modules.
-Design Does not translate the modules in the specied design. If you
do not specify -library or -design, Conformal applies
this command to both the library and design modules.
-Both Does not translate the specied modules in either the Golden
or Revised libraries and designs. This is the default.
-Golden Does not translate the specied modules in the Golden library
or design.
Command Reference
Related Commands
ADD NOTRANSLATE MODULES
ADD SEARCH PATH
DELETE NOTRANSLATE FILEPATHNAMES
DELETE NOTRANSLATE MODULES
REPORT NOTRANSLATE FILEPATHNAMES
REPORT NOTRANSLATE MODULES
-Revised Does not translate the specied modules in the Revised
library or design.
Command Reference
ADD NOTRANSLATE LINES
ADD NOtranslated Lines
<filename>
<[start:end | line] ... >
(Setup Mode)
Species lines to skip in a Verilog or VHDL le. This has the same effect as commenting out
the lines in the le. With this command, you can instruct the Conformal software to skip
certain lines in the design le without having to modify the le.
Parameters
Example
The following commands skip lines 6 through 8 and line 17 in the foo.v le when reading in
the design:
add notranslated lines foo.v 6:8 17
read dessign foo.v
As a result, lines 6, 7, 8 and 17 are skipped in the foo.v le:
(1) module test(clk, rst, set, d, z);
(2) input clk, set, rst, d;
(3) output z;
(4) reg z;
(5)
(6) garbage 1...........
(7) initial begin end
(8) garbage 2...........
(9)
(10) always @(negedge clk or negedge set or negedge rst) begin
(11) if (!rst) z <= 1b0;
(12) else if (!set) z <= 1b1;
(13) else z <= d;
(14) end
(15)
(17) garbage 3....
(18)
(19)endmodule
filename Species the Verilog or VHDL le.
start:end Species the a line number range to skip. For example, 6:8
would skip lines 6, 7, and 8.
line Species a line number to skip.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
Command Reference
ADD NOtranslate Modules
<module_name*>
(Setup Mode)
Species library or design modules that are parsed, but will not be translated when running
the READ LIBRARY or READ DESIGN command. These modules automatically become
blackboxes.
Note: The ADD NOTRANSLATE MODULES command is applied during initial parsing, so
name matching applies only to original module names. For parameterized or VHDL generic
modules whose names are determined and applied by Conformal after parsing and
preprocessing, you must use the ADD BLACK BOX command.
Examples of modules that should not be compiled include:
I RAM models
I Analog blocks
I Modules that contain non-synthesizable RTL constructs
Parameters
module_name* Does not compile the listed library or design modules. The
wildcard (*) is supported.
-Library Does not compile the specied library modules. If you do not
specify -library or -design, Conformal applies this
command to both the library and design modules.
-Design Does not compile the specied design modules. If you do not
specify -library or -design, Conformal applies this
command to both the library and design modules.
-Both Does not compile the specied modules in either the Golden or
Revised libraries and designs. This is the default.
-Golden Does not compile the specied modules in the Golden library or
design.
Command Reference
Related Commands
ADD BLACK BOX
READ DESIGN
READ LIBRARY
-Revised Does not compile the specied modules in the Revised library
or design.
Command Reference
<primary_pin primary_pin*>
[-Invert <primary_pin*>]
[-ROot | -Module < name*> | -All]
(Setup Mode)
Species output pin equivalences or inverted pin equivalences on output boundary module
pins. Conformal uses the equivalences when the parent module is being compared and the
subsequent module is a blackbox. The rst specied output pin is the representative pin. The
remaining primary output pins refer to the representative pin in that added equivalence group.
Effects on Comparison
This command affects comparisons when you use add compared points -all. In that
situation, Conformal merges the output pins specied with the ADD OUTPUT EQUIVALENCES
command and then veries them at the end of the comparison.
Wildcard: The wildcard (*) represents any zero or more characters in output boundary
module pin and module names.
Parameters
primary_pin primary_pin*
Species a list of output boundary module pins that are
equivalent. The rst output pin is classied as the
representative pin.
The wildcard (*) is supported for the second pin.
-Invert primary_pin*
Species a list of output boundary module pins that have
inverted equivalences with respect to the representative pin.
These inverted output pins are identied as (-) with the REPORT
OUTPUT EQUIVALENCES command.
-ROot Adds output equivalences to the root module output pins. This
is the default.
-Module name* Adds output equivalences to the specied module output pins.
Command Reference
Related Commands
ADD COMPARED POINTS
-All Adds output equivalences to all modules. -All applies within
the given defaults.
-Golden Adds output equivalences to the Golden design. This is the
default.
-Revised Adds output equivalences to the Revised design.
-Both Adds output equivalences to both the Golden and Revised
designs.
Command Reference
ADD OUTPUT STUCK_AT
ADD OUtput Stuck_at
<0 | 1>
<primary_pin*>
(Setup Mode)
Places values at the output boundary module pins. This value has no effect on the current
specied module comparison. However, Conformal uses the value when it compares the
parent (or higher) module.
Note: This command is limited to blackboxes. For a at run, if the module is not blackboxed,
all applied constraints will not take effect.
Wildcard: The wildcard (*) represents any zero or more characters in boundary module pin
and module names.
Parameters
0 Species that the output stuck_at value is 0.
1 Species that the output stuck_at value is 1.
primary_pin* Applies the stuck_at value to this list of output boundary
module pins. The wildcard (*) is supported.
-ROot Applies the output stuck_at value to the root module
boundary pin. This is the default.
-Module name* Applies the output stuck_at value to the specied module
boundary pin. The wildcard (*) is supported.
-All Applies the output stuck_at value to all output boundary
module pins.
-Golden Applies the output stuck_at value to the Golden design. This
is the default.
-Revised Applies the output stuck_at value to the Revised design.
-Both Applies the output stuck_at value to both the Golden and
Revised designs.
Command Reference
Related Commands
DELETE OUTPUT STUCK_AT
REPORT OUTPUT STUCK_AT
Command Reference
ADD PARTITION KEY_POINT
ADD PArtition Key_point
[-Pin |-Instance]
< name [-Golden |-Revised]]
|gname0 rname0 gname1 rname1 -Pair>
[-ALL_pattern | -ONE_Hot | -ONE_Cold]
(Setup Mode)
Species the pin or instance names that partition the design into different compare iterations
when the normal comparison process cannot nish. Execute this command before the WRITE
PARTITION DOFILE command.
I The -all_pattern option creates all possible binary combinations for n key points
specied.
I The -one_hot option creates all combinations where only one key point has a 1-state
and the rest have a 0-state.
I The -one_cold option creates combinations where only one key point has a 0-state
and the rest have a 1-state.
Important
A maximum of 14 partition points can be added. If you try to add more than 14
partition points, then only the rst 14 will be taken.
Parameters
-Pin Species that the partition key point names are pin names.
-Instance Species that the partition key point names are instance
names.
name Species a list of partition pin or instance key point names.
-Golden Species that the partition key points are in the Golden design.
-Revised Species that the partition key points are in the Revised design.
gname0 rname0 gname1 rname1 -Pair
Individually species that the Golden and Revised partition key
point names when the names differ between the Golden and
Revised designs.
Command Reference
Related Commands
DELETE PARTITION KEY_POINT
REPORT PARTITION KEY_POINT
WRITE PARTITION DOFILE
-ALL_pattern Applies all possible combinations of constraints to the partition
key point names. This is the default.
-ONE_Hot Applies a one-hot constraint to the partition key point names.
-ONE_Cold Applies a one-cold constraint to the partition key point names.
Command Reference
ADD PARTITION POINTS
ADD PARtition Points
< [-Net | -Pin | -GAte_instance | -ID] identifier... [-Pair]
| -MODule <module_name* ...>
| -INstance <instance_pathname* ...>
| -Datapath | -OUTPUT_TRIstate
| -ALL
>
[-OUTPUT_port | -INPUT_port | -INTRA_operator]
[-NAME]
[-ABORT_cone [compare point ...] ]
[-Cut | -NOCut]
[-EFFORT <Low | Medium | High>]
[-Verbose]
(LEC Mode)
Note: This is a Conformal Ultra command.
Adds partition (cut) points to the design. If a location in one design is specied, the Conformal
software will attempt to nd the corresponding point in the other design. If found, it adds a cut
point to both the Golden and Revised designs. These cut points are automatically mapped.
This command automatically handles inverted points.
In the cases where the added cut points are not equivalent, you will need to diagnose them.
If the non-equivalency is caused by the cut point, then you will need to delete that pair of cut
points with the DELETE PARTITION POINTS command.
After adding the partition points, you would normally run the ADD COMPARED POINTS -all
command to add the cut points to the compare list.
Note: If a cut point has already been added to a location, a second cut point cannot be added
to the same location. If a specied point has more than one corresponding point in the design,
the software will not add a cut point.
Caution
Adding cut points in LEC mode causes flattened netlists to change. As a
result, all the gate IDs are subjected to change. Adding cut points does
not affect the existing compare points list; however, all the compare data
is invalidated after adding cut points.
Command Reference
Parameters
-Net Species that the identier is a net pathname.
-Pin Species that the identier is a pin pathname.
-GAte_instance Species that the identier is a gate-instance pathname.
-ID Species that the identier is a gate identication number.
This number is an integer assigned automatically by
Conformal.
ID numbers can differ from one version of Conformal to
identifier Species the identier for adding the partition point.
If you do not specify -Net, -Pin, -GAte_instance, or
-ID, the Conformal software automatically determines if the
identier is a gate-identication number, pin pathname, net
pathname, or a gate-instance pathname.
-Pair Allows specication of multiple pairs of identiers, where the
rst identier in each pair refers to the Golden design and
the second identier in each pair refers to the Revised
design.
-MODule <module_name* ...>
Adds partition points to all the instances of the specied
module(s).
-INstance <instance_pathname* ...>
Species the module instance pathname. By default, the
partition points are all the output pins of the specied
instance.
Note: If an instance is removed during the Conformal
attening and modeling process, you cannot add partition
points to the instance.
-Datapath Adds partition points to all module instances containing
datapath operators. The datapath operator is the multiplier
(including the merged operator) in the Golden design.
By default, the partition points are all the output pins of the
datapath operator(s).
Command Reference
-OUTPUT_TRIstate Species the partition points as the tri-state buffer at the
primary output.
-ALL Adds partition points to all possible locations. This is useful
when resolving aborts.
-OUTPUT_port Species the partition points as all the output pins of the
module instance or datapath operator. This is the default.
-INPUT_port Species the partition points as all the input pins of the
module instance or datapath operator.
-INTRA_operator Species the partition points as the gates inside the
datapath operator.
-NAME Adds partition points around instances using a name-based
algorithm. This is faster than the default algorithm which
adds partition points based on function.
To perform a at run with hierarchical partitioning, add
partition points to all module instances using the following
command:
add partition points -instance * -name -input -output
To get better datapath quality, add partition points to all
module instances containing datapath operators using the
following command:
add partition points -datapath -name -input -output
-ABORT_cone [compare point ...]
Adds the specied partition points only in the fan-in logic
cone of the specied compare points. If no compare point is
specied, by default, the partition points are added in the
fanin logic cone of all the compare points with abort or
unknown results.
Note: You must add compare points rst to use this option.
-CUT Generates the cut gates in the attened netlists for the
feasible partition points in Golden and Revised design. This
is the default.
-NOCUT Does not generate any cut gates in attened netlists.
-Golden Species that the partition points are from the Golden
Command Reference
Examples
I The following commands specify partition points in Golden and Revised design by pin
pathnames:
add partition points -pin i0_gold/sum[17] i0_rev/z[17] -pair
add compared points -all
I The following commands specify the partition points in the Golden design. The
commands will automatically nd the corresponding gates in the Revised design, and if
found, will physically add the cut gate pair in the attened netlist.
add partition points -pin i0/sum[17] i0/sum[16] -golden
I The following commands specify the partition points from the output pins of multiplier
operators in the Golden design. The commands will automatically nd the
correspondence gates in the Revised design, and add partition point pairs as cut gates
in the attened netlists.
add partition points -datapath
I The following command species an instance of datapath operator in the Golden design
and add some gates inside the operator as partition points:
add partition points -instance i0 -intra_operator
I The following command species all the datapath operators in the Golden design and
add some gates inside the operators as partition points:
add partition points -datapath -intra_operator
-Revised Species that the partition points are from the Revised
design.
-EFFORT <Low | Medium | High>
Species the effort level for adding partition points.
Increasing the effort level from Low to High will improve the
quality of partition points being added, but will result in
increased time.
The default effort level is Medium.
-Verbose Reports the partition points with correspondences in the
other design.
Command Reference
I The following command adds partition points for all the tri-state buffers at the primary
outputs:
add partition points -output_tristate
I The following command adds partition points to all instances of the DW_ module:
add partition points -module DW_*
I The following commands add partition points at all the possible locations in the fan-in
logic cone of the compare points with abort or unknown compare results:
add partition points -all -abort_cone
Related Commands
ADD COMPARED POINTS
DELETE PARTITION POINTS
REPORT PARTITION POINTS
Command Reference
ADD PIN CONSTRAINTS
ADD PIn Constraints
<0 | 1 | ONE_Hot | ONE_Cold | ZERO_ONE_Hot | ZERO_ONE_Cold>
<primary_pin*>
[-REPlace] [-ROot | -Module <name*> | -All]
(Setup Mode)
Constrains pins to a logic value or relationship. You can use this command on primary input
pins, or compare two different designs under certain input constraints. The supported
constraints are:
I 0-state
I 1-state
I One-hot
I One-cold
I Zero-one-hot
I Zero-one-cold
The one-hot constraint lets only one pin be at a 1-state and the remaining pins be at a 0-state.
The one-cold constraint lets only one pin be at a 0-state and the remaining pins be at a
1-state.
Wildcard: The wildcard (*) represents any zero or more characters in primary input and
module names.
Parameters
0 | 1 Constrains pins to a constant 0 or 1 value.
ONE_Hot Species that only one of the pins can have a high value.
ONE_Cold Species that only one of the pins can have a low value.
ZERO_ONE_Hot Species that all pins can have a low value, but only one can
have a high value.
ZERO_ONE_Cold Species that all pins can have a high value, but only one can
have a low value.
Command Reference
Related Commands
DELETE PIN CONSTRAINTS
REPORT PIN CONSTRAINTS
primary_pin* Species that a list of primary input names that will be
constrained to a certain state. (These primary inputs are from
either the Golden or Revised design.) The wildcard (*) is
supported.
-REPlace Changes the previously specied pin constraint.
-ROot Applies the constraints to the root module(s). This is the
default.
-Module name* Applies the constraints to the specied module(s). The wildcard
(*) is supported.
-All Applies pin constraints to all modules. -All applies within the
given defaults.
-Golden Species that the primary input names are from the Golden
-Revised Species that the primary input names are from the Revised
design.
-Both Species that the primary input names are from both the
Golden and Revised designs.
Command Reference
ADD PIN EQUIVALENCES
ADD PIn Equivalences
< primary_pin primary_pin*>
[-Invert <primary_pin*>]
[-INPUT_OUTPUT]
[-User | -Hier]
(Setup Mode)
Denes the relationship between pins; species whether module pins are equal or inverted.
Use this command to complete logic abstraction or to resolve differences in logic during
comparisons.
Note: Pin equivalences are considered only when the pin equivalences are on a root module.
If a submodule has black-box pin equivalences, the Conformal Equivalence Checker checks
to see if they are true when you use the ADD COMPARE POINT -all command.
Wildcard: The wildcard (*) represents any zero or more characters in primary input and
module names. Wildcards are not valid for buses.
Parameters
primary_pin primary_pin*
Species a list of primary input pins that are equivalent. The
rst input pin is classied as the representative pin.
The wildcard (*) is supported for the second pin.
-Invert primary_pin*
Species that the primary pins are inverted with respect to
the referenced primary pin. Use the REPORT PIN
EQUIVALENCES command to identify the inverted primary
input pins. The (-) denotes inverted pins.
-ROot Applies the pin equivalences to the root module. This is the
default.
-Module name* Applies the pin equivalences to the specied module. The
default is the root module.
You can also use this command on buses, by dening the
bus range using <name[msb:lsb]>.
Command Reference
Example
The following example implies that p1, p2, and p3 are equivalent and are inverted to p4, p5,
and p6.
add pin equivalences p1 p2 p3 -inv p4 p5 p6
Related Commands
DELETE PIN EQUIVALENCES
REPORT PIN EQUIVALENCES
-All Applies the pin equivalences to all the modules. -All
-INPUT_OUTPUT Enables the handling of internal signals that pass in and out
of the same module. With this option, you can also constrain
an output pin of a blackbox to be equivalent to an input pin.
Note: The representative pin should always be driving all the
equivalent pins.
-User When you use this option, Conformal includes these added
pin equivalences in the comparison, when the
corresponding module is a blackbox. (This option does not
apply to primary inputs.) This is the default.
-Hier When you use this option, Conformal does not do the
additional check associated with the -user option.
-Golden Species that the pin equivalences are from the Golden
-Revised Species that the pin equivalences are from the Revised
design.
-Both Species that the pins specied as equivalent exist in both
the Golden and Revised designs.
Note: If you use the -both option, every primary input pin
you list must exist in both designs (Golden and Revised).
Otherwise, Conformal returns an error message.
Command Reference
ADD PRIMARY INPUT
ADD PRimary Input
< pathname* [-Net] | pathname -Pin>
[-Cut | -NOCut]
(Setup Mode)
Adds a new primary input pin to a specied net or pin name. This new primary input pin is
classied in the User class of primary inputs. (The original primary inputs of the design are
classied in the System class of primary inputs.) Use the -cut option if the added primary
input is the only driver to the net or pin. Otherwise, along with the other original drivers, the
net becomes a wired net.
Wildcard: The wildcard (*) represents any zero or more characters in net paths.
Parameters
Related Commands
DELETE PRIMARY INPUTS
REPORT PRIMARY INPUTS
pathname* -Net Adds the primary input to the specied net path. -Net is the
default.
pathname -Pin Adds the primary input to the specied pin path.
-Cut Cuts the other original drivers of the specied path and allow
only the newly added primary input as the driver of the net or
pin. This is the default.
-NOCut Does not cut the other original drivers of the specied net or pin
name. This option makes the new net a wired net.
-Golden Adds the new primary input in the Golden design. This is the
default.
-Revised Adds the new primary input in the Revised design.
-Both Adds the new primary input in both the Golden and Revised
designs.
Command Reference
ADD PRIMARY OUTPUT
ADD PRimary Output
<net_pathname*>
(Setup Mode)
Adds a new primary output pin to a specied net name. This new primary output pin is
classied in the User class of primary outputs. (The original primary outputs of the design are
classied in the System class of primary outputs.) This command is used for diagnosis when
an internal value can be observed at a primary output.
Wildcard: The wildcard (*) represents any zero or more characters in net paths.
Parameters
Related Commands
DELETE PRIMARY OUTPUTS
REPORT PRIMARY OUTPUTS
net_pathname* Adds the primary output to the specied net path.
-Golden Adds the new primary output in the Golden design. This is the
default.
-Revised Adds the new primary output in the Revised design.
-Both Adds the new primary output in both the Golden and Revised
designs.
Command Reference
ADD RENAMING RULE
ADD REnaming Rule
[[-PIN_MULTIDIM_TO_1DIM]
[-ADD | -NOADD]
[-NOASCEND | -ASCEND]
[-VERBOSE] ]
[<rule_name> <string> <string>
[[ -MAp ]
[-TYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>
|-NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>]
|-MOdule
|-PIn [-BBox <module_name>]
]
[-REPlace]
[-Golden | -Revised | -BOth] ]
(Setup / LEC Mode)
Species renaming rules for key point mapping, module renaming (when reading in the library
and designs for hierarchical comparisons), and pin renaming for blackboxes
Use the REPORT RENAMING RULE command to display the list of all renaming rules.
Conformal applies renaming rules sequentially, in the order they were added.
Key Point Mapping
When you dene renaming rules in the Setup system mode, they guide the automatic
mapping process that occurs during the system mode switch from Setup to LEC. When you
are in the LEC system mode, and nd that the key point mapping is not complete, dene
additional renaming rules and repeat key point mapping to improve the mapping results. The
automatic mapping process refers to the naming specied by the nal renaming rules.
Module Renaming
You must use this command before the READ LIBRARY and READ DESIGN commands. It
helps map modules together for hierarchical comparisons.
Pin Renaming
This command applies to the specied blackbox or to all blackboxes, which is the default.
Command Reference
Renaming Rule Structure
When dening renaming rules, the rst string species the pattern to be matched; the second
string species howConformal is to rename or make substitutions. The rst string can contain
expressions of the following types:
Any character can be preceded by the escape character \ to cancel any special meaning it
has. Use the escape character whenever any of the following special characters represents
a simple character.
% . * + ^ $ | ( ) [ ] \
The second string can contain expressions of the following types:
%d Matches one or more digits, [0-9]+
%a Matches one or more alphabetical characters, [a-zA-Z]+
%s Matches one or more digits or alphabetical characters,
[0-9a-zA-Z]+
%u Matches one or more alphabetical characters or underscores,
[a-zA-Z_]+
%w Matches one or more digits or alphabetical characters or
underscores, [0-9a-zA-Z_]+
x Matches character x
abc Matches string abc
. Matches any single character
* Matches zero or more repetitions of the preceding expression
+ Matches one or more repetitions of the preceding expression
^bol Matches bol only when it occurs at the beginning of a string
eol$ Matches eol only when it occurs at the end of a string
x|abc Matches x or abc
[oz!] Matches o, z, or !
(pattern) Matches anything that is matched by pattern and renders it
referable (through @n) in the substitution string
abc Replaces string abc for each matched string
Command Reference
The following table shows implementation examples for various pattern-matching and
substitution strings. For pattern-matching strings, use parentheses to group individual
patterns into a single pattern, as demonstrated in the example (ab|de)*.
@n Replaces the string that matches the nth %d, %a, %s, or a
pattern enclosed in parentheses.
The n is a digit other than 0, and you can use @{nn} to refer to
further matches (that is, 1099)
#(expr) Where expr is an arbitrary expression that can only contain
constant integers, @n expressions, and the operators +,-,*, /
and ( )
First String Second String Source Result
%a%d @1[@2] xyz123 xyz[123]
%a_%d @1[@2] arr_5 arr[5]
_z_ / _z_top_z_inst /top/inst
âbc XYZ abcabc XYZabc
abc$ XYZ abcabc abcXYZ
âbc$ XYZ abcabc abcabc
âbc$ XYZ abc XYZ
[oz!] $ aaoaazaa!aa aa$aa$aa$aa
\%d\%s AA %a%d%s%b %aAA%b
\(ab ZZ xx(abcd xxZZcd
%s\.%d @1[@2] xx.123 xx[123]
(x|abc) YY abcx abcx YYYY YYYY
(ab|de)* YY ababdeab YY
%s%d @1[#(7-@2)] abc3 abc[4]
%s%d @1[#(2*@2)] abc5 abc[10]
reg%d\[%d\] reg[@2] reg2[5] reg[5]
Command Reference
Important
Do not include the forward slash, /, at the top level for either the rst or second
string.
For example, express /top_module/adder/reg[5] as
top_module/adder/reg[5].
Parameters
-PIN_MULTIDIM_TO_1DIM
Allows you to create renaming rules to map multidimensional
array pins to one-dimensional array pins.
-ADD Shows the pins found when adding the rules into the system.
-NOADD Shows the pins found without adding the rules.
-NOASCEND Renames the pins in an descending order. This is the default.
-ASCEND Renames the pins in an ascending order.
-VERBOSE Shows the renaming patterns.
rule_name Species a rule identication name assigned to a specic
renaming rule.
<string> <string> The rst string represents the pattern to be matched.
The second string represents the substitution pattern.
-MAp Species that the renaming rule applies to key point mapping.
-TYpe keypoint_type
Renames all key points with the specied type. The available
types are as follows:
PI Primary Inputs
E TIE-E gates
Z TIE-Z gates
DFF D ip-ops
DLAT D-latches
Command Reference
CUT Articial gates for breaking combinational
feedback loops
BBOX Blackboxes
PO Primary Outputs
-NOTYpe keypoint_type
Renames all key points except the specied types. The
available types are as follows:
PI Primary Inputs
E TIE-E gates
Z TIE-Z gates
DFF D ip-ops
DLAT D-latches
feedback loops
BBOX Blackboxes
PO Primary Outputs
-MOdule Species that the renaming rule applies to module renaming
when the library and design are read in.
-PIn Species that the renaming rule applies to pin names of
blackboxes.
-BBox module_name Species that the pin renaming rules apply to the specied
blackbox module.
-REPlace Allows the redenition of an existing renaming rule.
Tip
The difference between using add renaming rule
-replace as opposed to using delete renaming
rule followed by add renaming rule is that
renaming rules that are redened remain in the same
position in the list of renaming rules. By deleting and
adding a rule, the new denition will appear at the end
of the list. In some cases, the order in which renaming
rules are applied might affect the result.
Command Reference
Example
In the following command, y2[1:0][2:0] in module test2 is renamed y2[5:0]:
add renaming rule -pin_multidim_to_1dim
// Rule created for (test2) y2[1:0][2:0]
// Rule created for (test1) y1[1:0][1:0]
// Rule created for (top) y2[1:0][2:0]
// Rule created for (top) y1[1:0][1:0]
// Rule created for (top) ym[2:3][2:0][1:0]
// 5 rules created. Rules for top module must be manually validated.
You can use the REPORT RENAMING RULE command to view the added rules.
Related Commands
CHANGE NAME
DELETE RENAMING RULE
MAP KEY POINTS
READ DESIGN
READ LIBRARY
REPORT RENAMING RULE
SET MAPPING METHOD
SET NAMING RULE
TEST RENAMING RULE
-Golden Species that the renaming rule applies to the Golden design.
-Revised Species that the renaming rule applies to the Revised design.
-BOth Species that the renaming rule applies to both the Golden and
Revised designs.
Command Reference
ADD RETENTION MAPPING
ADD REtention Mapping
<rule_name>
<-Module <module_name*> | -Instance <instance_pathname*>
|-NOTag | -Tag <tag_name1*> -Tag <tag_name2*> ... >
<-NOAttribute | -Attribute <attribute name>>
[-TYpe <ALL | DFF | DLAT>]
(Setup / LEC Mode)
Adds the state retention mapping rules for validation of technology mapping of the sequential
elements (DFFs or DLATs) from RTL to gate-level, gate-level to gate-level, or RTL to RTL.
For a description of the default rules that are added by the system, see CHECK LOWPOWER
CELLS on page 143.
Parameters
rule_name Species a rule identication name assigned to a specic
retention mapping rule.
-Module Species the module name in the Golden design. All the
DFFs or DLATs under the named module will be subjected
to this rule.
-Instance Species the instance pathname in the Golden design. Here
instance pathname refers to only DFF or DLAT instances.
The named DFF or DLAT instance(s) would be subjected to
this rule.
Wildcards (*) are supported for the instance pathname.
When using a wildcard, it might point to multiple instances.
-Tag Species the tag name in the RTL golden side. The tag
name refers to the label names used with a) process
blocks in the VHDL RTL and b) always blocks in the Verilog
RTL. All the DFFs or DLATs under the tag-named block will
be subjected to this rule.
Wildcards (*) are supported.
Command Reference
Examples
I The following command veries that all registers with a tag label lp_sel* are
implemented with a state retention cell whose power_gating_cell attribute is
LPRET_DFF1:
add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1
I The following command veries that all registers in module blockA are implemented
with a state retention cell whose power_gating_cell attribute is LPRET_DFF1:
add retention mapping R1 -module dma -attribute LPRET_DFF1
-NOTag When the Golden side is an RTL design, this implies that all
the DFFs or DLATs which do not have any tag-name
associated with their process or always block will be
subjected to this rule.
-Attribute Species the power gating cell attribute for the DFFs or
DLATs in the Revised netlist. Different power gating cell
attributes are dened for different sets of retention cells in
the Synopsys library (liberty format). When synthesized
(technology mapped), the DFFs or DLATs in the Golden
design (specied using module-name, instance-name, or
tag-name) should have the named attribute in Revised
netlist.
-NOAttribute Species that, when synthesized (technology mapped), the
DFFs or DLATs in the Golden design (specied using
module-name, instance-name, or tag-name) should not
have any attribute (power gating cell attribute) in Revised
netlist. In other words, the specied DFFs or DLATs should
be technology mapped as ordinary or non-retention cells.
-TYpe <ALL | DFF | DLAT>
Indicates the sequential element type on which to apply the
retention mapping rule.
ALL applies the retention mapping rule to all sequential
elements (both DFF and DLAT type). This is the command
default when you do not specify the -TYpe option.
DFF applies the retention mapping rule to DFFs only, and
DLAT applies the retention mapping rule to DLATs only.
Command Reference
I The following command veries that all registers with instance name
/U0/*/fifo_dma* are implemented with a state retention cell whose
power_gating_cell attribute is LPRET_DFF2:
add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2
Related Commands
DELETE RETENTION MAPPING
REPORT RETENTION MAPPING
Command Reference
ADD SEARCH PATH
ADD SEarch Path
<pathname>
[ |-Design | -Library]
(Setup Mode)
Denes additional search paths outside the current directory for lenames you use in the
READ DESIGN and READ LIBRARY commands. This command is necessary because the
default is to search for lenames in the current directory; but your design or library can include
lenames that are housed in other directories.
When you add multiple search paths to the list, Conformal does the search in the order paths
were added to the list.
Use the REPORT SEARCH PATH command to display all search paths. Use the tilde character
(~) to shorten the specied path.
Parameters
pathname Species the search path for lenames used in the READ
DESIGN and READ LIBRARY commands.
-Design The READ DESIGN command uses the specied search path.
If you do not specify -library or -design, Conformal
applies this command to both the READ DESIGN and READ
LIBRARY commands.
-Library The READ LIBRARY command uses the specied search path.
If you do not specify -library or -design, Conformal
applies this command to both the READ DESIGN and READ
LIBRARY commands.
-Both Species that the search path applies to both the Golden and
-Golden Species that the search path applies to the Golden design and
library.
-Revised Species that the search path applies to the Revised design
and library.
Command Reference
Related Commands
DELETE SEARCH PATH
READ DESIGN
READ LIBRARY
REPORT SEARCH PATH
Command Reference
ADD SUPPLY
ADD SUpply
<-power | -ground>
[-port [-root | -Module <name>] | -global] <name ...>
(Setup Mode)
Denes power/ground ports of a module or the global power/ground signals for the entire
design.
Parameters
Examples
Instead of specifying .global in a spice netlist, the following commands command have the
same effect:
add supply -power VDD
add supply -ground GND
-power Species that the listed names have a VDD attribute.
-ground Species that the listed names have a GND attribute.
-port Species that the listed names are module ports.
-root Species that the listed names reside in the root
module. By default, all modules will be applied.
-Module <name> Species that the listed names reside in the specied
module. By default, all modules will be applied.
-global Species that the listed names are global signals.
<name> ... Species that a list of net/port names that will be
specied as VDD or GND.
-Golden Species that the listed names are from the Golden
design.
-Revised Species that the listed names are from the Revised
design.
Command Reference
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
SET ABSTRACT MODEL
Command Reference
ADD TIED SIGNALS
ADD TIed Signals
<0 | 1>
<name*>
[-Net | -Pin]
[ |-Design |-Library]
(Setup Mode)
Assigns the specied oating nets or pins to a 0-state or a 1-state in the Golden or Revised
design. These tied signals are classied in the User class of tied signals. The original tied
signals of the design are classied in the System class of tied signals.
Wildcard: The wildcard (*) represents any zero or more characters in net, pin, and module
names.
Parameters
0 Ties the oating nets or pins to a 0-state.
1 Ties the oating nets or pins to a 1-state.
name* Species a list of names that correspond to either oating nets or
oating pins where you intend to add the tied signal.
-Net Species that the listed names are net names. This is the
default.
-Pin Species that the listed names are pin names.
-ROot Species that the oating net or pin resides in the current root
module. This is the default.
-Module name* Species that the oating net or pin resides in the specied
module. The default is the root module.
-All Applies the tied signals to all the modules. -All applies within
the given defaults.
-Design Applies the tied signals to the design.
If you do not specify -design or -library, Conformal applies
tied signals to both designs and libraries.
Command Reference
Related Commands
DELETE TIED SIGNALS
REPORT FLOATING SIGNALS
REPORT TIED SIGNALS
-Library Applies the tied signals to the library.
If you do not specify -design or -library, Conformal applies
tied signals to both designs and libraries.
-Golden Adds the tied signals to the Golden design. This is the default.
-Revised Adds the tied signals to the Revised design.
-Both Adds the tied signals to both the Golden and Revised designs.
Command Reference
ANALYZE ABORT
ANAlyze ABort
[-All | <<gate_id | instance_pathname | pin_pathname> ...
[-Golden | -Revised]> | -Number <number>]
[-Summary | -Verbose | -COmpare]
[-CLass <Abort | Notcompared>]
(LEC Mode)
Analyzes abort points and recommends actions to help solve the abort points. This command
can also provide useful information for further abort investigation.
Parameters
-ALL Analyzes all abort points. This is the default.
gate_id Species the gate ID for abort analysis.
instance_pathname Species the instance pathname for abort analysis.
pin_pathname Species the pin pathname for abort analysis.
-Golden Species whether the gate ID or pathname is in the Golden
-Revised Species whether the gate ID or pathname is in the Revised
design.
-Number <number> Species the number of abort points to analyze.
-Summary Prints out the summary count of the abort points. This is the
default.
-Verbose Prints out additional information, such as RTL statistics.
-COmpare Automatically compares the aborted points. Cadence
recommends using this option when running the ANALYZE
ABORT command.
-CLass <Abort | Notcompared>
Species the class of points to analyze. Select Abort to
analyze abort points, or Notcompared to analyze
not-compared points.
Command Reference
Example
The following commands run abort analysis after the initial compare:
compare
analyze abort -compare
Related Commands
COMPARE
RUN HIER_COMPARE
SET ANALYZE OPTION
Command Reference
ANALYZE DATAPATH
ANAlyze DAtapath
[-MODULE [-RESOURCEFILE <filename>]]
[-MERGE | -NOMERGE]
[-NOSHARE | -SHARE]
[-EFFort <MEDium | HIgh>]
[-SHARE_OPerator <r1 r2 [.. rN]> ]
[-NOADDERTREE | -ADDERTREE]
[-Verbose]
(LEC Mode)
Analyzes datapath modules. Based on the results of the analysis, Conformal can
automatically resolve multipliers, operator merging, and resource sharing problems.
Note: You cannot run datapath analysis without rst mapping the Revised design keypoints
to the Golden design keypoints.
Parameters
-MODULE Applies analysis on the datapath modules. The default is in the
Revised design netlist.
-RESOURCEFILE <filename>
Species the resource lename to analyze the datapath
modules.
-MERGE Applies the operator merging technique. This is the default.
-NOMERGE Does not apply the operator merging technique.
-NOSHARE Does not apply the resource sharing technique. This is the
default.
-SHARE Analyzes the design for datapath resource sharing.
-SHARE_OPerator Shares the specied operators. See the example for the
recommended ow.
Note: If this option is specied, only the sharing is performed,
and does not run datapath analysis.
Command Reference
Example
I The following commands show an example of the recommended ow when using the
-SHARE_OPerator option:
analyze datapath -verbose -share_operator mult_30 mult_31
// Note: mult_30: shared
analyze datapath -verbose -share_operator mult_32 mult_33
// Note: mult_32: shared
analyze datapath -verbose
// Note: add_2(clustered): quality evaluated 70% success
// Note: mult_30: quality evaluated 80% success
// Note: mult_32: quality evaluated 100% success
I The following commands apply datapath module-based analysis followed by the
datapath operator-level analysis:
analyze datapath -verbose -module -resourcefile resourcefile.name
analyze datapath -verbose
Related Commands
ANALYZE MULTIPLIER
REPORT DATAPATH OPTION
REPORT DATAPATH RESOURCE
REPORT MULTIPLIER OPTION
SET DATAPATH OPTION
-EFFort <MEDium | HIgh>
Species the effort level. Choose MEDium (the default), or HIgh
to help provide better analysis of some multipliers, but might
increase the analysis runtime.
-NOADDERTREE Does not automatically add parentheses to the input operands
of adder trees. This is the default.
-ADDERTREE Automatically adds parentheses to the input operands of adder
trees.
-Verbose Provides additional information.
Command Reference
SET MULTIPLIER IMPLEMENTATION
SET MULTIPLIER OPTION
Command Reference
ANALYZE ECO
ANAlyze ECo
<patch_filename>
[-REPlace]
[-EFFort <HIGH | LOW | MEDIUM | SUPER | ULTRA>]
[-PRESERVE_clock]
(LEC Mode)
Analyzes the ECOchange in the Revised root module comparing to the Golden root module.
The logic change is written to the specied patch le, which contains the Verilog module with
the port names corresponding to the nets in the Golden design.
Note: Only the logic cone under Non-EQ points are analyzed by the command.
Parameters
Examples
In the following commands, module G1 contains the placed and routed netlist, and module G2
contains the synthesized netlist frommodied RTL. The two netlist will be compared rst, then
the ANALYZE ECO command will analyze the change implemented by G2 and generates a
patch le, which contains a single Verilog module G1_eco. The patch can then can be read
back and applied to G1 with the APPLY PATCH command, such that the G1 will be equivalent
to G2, meaning that G1 implements the ECO change in G2.
Note: The patch can be remapped or optimized by other tools before it is read back.
SETUP> set root module G1 -golden
SETUP> set root module G2 -revised
SETUP> set system mode lec
LEC> add compare point -all
LEC> compare
LEC> analyze eco patch.v -replace
<patch_filename> Species the name of the patch le.
-REPlace Replaces the existing le.
[-EFFort <HIGH | LOW | MEDIUM | SUPER | ULTRA>]
Species the analysis effort level. The command default is
HIGH.
-PRESERVE_clock Attempts to minimize the changes to the clock network.
Command Reference
SETUP> set system mode setup
SETUP> read design patch.v -append
SETUP> apply patch G1 G1_eco
Related Commands
ADD ECO PATCH
APPLY PATCH
COMPARE
Command Reference
ANALYZE IMPLICATION
ANAlyze IMplication
[-ONE | -1 <GateID...>]
[-ZERO | -0 <GateID...>]
[-ADD <-ONE | -1 | -ZERO | -0> <GateID...>]
[-DELete <GateID...>]
[-CHECK_Redundancy <GateID...>]
[-CHECK_Constant <GateID...> ]
[-Block <GateID...>]
[-DEPTH <depth>]
(LEC Mode)
Analyzes implication values on the design. If you assign value(s) on certain gate(s), this
command shows what the necessary values are on other gates to satisfy the assignment. It
can also show if a gate has redundant fanin and if a gate is a constant gate.
The results are displayed in the schematic view with the following colors:
I Blue: initial assignments
I Green: current implication values
I Red: gates on the conict path
I Purple: location where conict occurred
In the schematic view, you can also right click the gate and set a value. Holding the mouse
pointer on a gate, an information box will show if this gate has redundant fanin and if it is a
constant gate.
Parameters
-ONE | -1 Species that the following gate(s) will be assigned one.
-ZERO | -0 Species that the following gate(s) will be assigned zero.
-ADD Species that the following assignment(s) will be added into
previous assignment(s).
-DELete Species that the following gate(s) will be removed from
previous assignment(s).
-CHECK_Redundacy Checks the specied gate to see if it has redundant fanins.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
-CHECK_Constant Checks the specied gate to see if it is constant gate.
-Block Blocks the gate(s) so that implication will not go across it.
-DEPTH Species the logic depth beyond which implication will not be
performed. The default value is 10.
-Golden Species that the gate IDs are from the Golden design. This is
the default.
-Revised Species that the gate IDs are from the Revised design.
Command Reference
ANALYZE MULTIPLIER
ANAlyze MUltiplier
[-NOCDP_INFO | -CDP_INFO]
(LEC Mode)
Initiates an analysis of multiplier modules. Based on the results of the analysis, Conformal
can automatically resolve architecture mismatches and operand swapping problems.
Additionally, use the -cdp_info option if you want Conformal to let you know when
Conformal Ultra will be helpful.
Use this command after switching from Setup to LEC mode:
set system mode lec
analyze multiplier -cdp_info

compare
Parameters
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
SET DATAPATH OPTION
-NOCDP_INFO Does not display a message when Conformal Ultra can
enhance multiplier analysis. This is the default.
-CDP_INFO Displays a message when Conformal Ultra can enhance
multiplier analysis.
Command Reference
ANALYZE NONEQUIVALENT
ANAlyze NOnequivalent
[ | <gate_id> | <instance_pathname*> ...
[-Golden | -Revised] ]
[-Summary | -Verbose]
(LEC Mode)
Helps identify the possible causes of non-equivalent compared points.
Parameters
Examples
The following shows an example of a report when running the ANALYZE NONEQUIVALENT
command. The lines in bold indicate the cause of the problems:
LEC> analyze noneq 213
//Command analyze noneq 213
Analyzing non-equivalent compared points:
(G) + 213 DFF /wbs/hvlen_reg[28]
(R) + 6277 DFF /wbs/hvlen_reg[28]/U$1
The clock of DFF in Golden is not gated.
The clock of DFF in Revised is gated.
Analysis of non-equivalent compared points:
<gate_id> Analyzes non-equivalent compared points for the specied
gate.
<instance_pathname*> ...
Analyzes non-equivalent compared points for the specied
instance.
-Golden Analyzes non-equivalent compared points in the Golden
-Revised Analyzes non-equivalent compared points in the Revised
design.
-Summary Provides a summary of the analysis. This is the default.
-Verbose Provides additional information for each individual
non-equivalent compared point.
Command Reference
Gated clock of of DFF or DLAT. (Occurrence: 1)
Unknown reason. (Occurrence: 1)
LEC> analyze noneq 170 -revised
//Command analyze noneq 170 -revised
Analyzing non-equivalent compared points:
(G) + 167 PO /wbm_sel_o[0]
(R) + 170 PO /wbm_sel_o[0]
Following constraints may be necessary:
Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]
Analysis of non-equivalent compared points:
Sequential constant. (Occurrence: 1)
Unknown reason. (Occurrence: 1)
Clock Gating
You can x the rst problem in the report:
The clock of DFF in Golden is not gated.
The clock of DFF in Revised is gated.
by running the following command in Setup mode:
set analyze option -auto
or the following command in LEC mode:
analyze setup
Sequential Constant
You can x the second problem in the report:
Following constraints may be necessary:
Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]
by running auto analysis in Setup mode with the following commands:
set analyze option -auto
set flatten model -seq_constant
or the following command in LEC mode:
remodel -seq_constant
Related Command
ANALYZE SETUP
Command Reference
ANALYZE POWER ASSOCIATION
ANAlyze POwer Association
[-Module <module_name*>...>]
[-OUT_Dofile <dofile_name> | -OUT_CPF <filename>]
[-REPlace]
(Setup / Verify Mode)
Analyzes the modules SPICE netlist and identies the power/ground pin for each input and
output pin with which it is associated.
Notes:
I The power/ground pin denition can come from LEF or SPICE.
I Run the SET SPICE OPTION -NOBULK command before reading in the SPICE design
to maintain the connectivity of power/ground ports.
I Each input or output pin can have only one associated power/ground pin. Multiple
power/ground pin association are ignored.
Parameters
-Golden Analyze the Golden design. This is the default.
-Revised Analyze the Revised design.
-Module <module_name*> ...>
Species the module(s) to be analyzed. Without this option, all
modules in the design are analyzed. This accepts wildcards.
-OUT_Dofile <dofile_name>
Species the le to output the ADD POWER ASSOCIATION
command.
-OUT_CPF <filename>
Species the output CPF le.
-REPlace Replaces the specied -OUT_Dofile or -OUT_CPF le if it
already exists.
Command Reference
Related Commands
READ DESIGN -spice
SET SPICE OPTION
Command Reference
ANALYZE RETIMING
ANAlyze REtiming
[-COMBinational_identical]
[-PIPELINE [<identifier* ...>] [-BACKWARD] ]
[-GENERAL]
[-MERGE | -NOMERGE]
[-DIAGNOSIS <identifier> [-BACKWARD] ]
[-VERBose]
[-BOth | -GOLden | -REVised]
(LEC Mode)
Initiates pipeline retiming, retiming for RC synthesized netlist, or retiming for designs that are
combinationally equivalent. Normally, you use this command to retime a Revised design to
match a referenced Golden design. If this command is successful, you can use the COMPARE
command to ensure that the two designs are equivalent. If this command is unsuccessful,
then the original retiming you performed is incorrect.
For more guidelines and examples, see Conformal Ultra: Advanced LEC Capabilities in the
Encounter Conformal Equivalence Checking User Guide.
Parameters
-COMBinational_identical Use this option on combinationally equivalent designs.
Use option when you have retimed a design and want to
conrmthat it is equivalent to another design. Conformal
retimes its registers to match their position in the
reference design.
Note: If you specify this option, it must be the rst option
in the command line.
Tip
If you can replace the DFF -> Q connections
with buffers and your designs are still identical,
then your Golden and Revised designs are
considered combinationally equivalent.
Command Reference
-PIPELINE <identifier* ...> -BACKWARD
Moves all registers to the primary output side of the
design as much as possible, or use the <identifier>
option to specify one or more registers, separated by a
space. The wildcard (*) is accepted.
-BACKWARD moves registers backward to the primary
input side of the design as much as possible. With this
option, pipeline backward retiming can be performed on
either all registers or a selected set of registers.
-GENERAL Retimes the Revised design to match the registers on
the Golden side. Registers in the Golden design will not
be retimed.
-MERGE Species that equivalent registers are merged after
registers are moved, including inverted-equivalent
registers. This helps to reduce the unmapped register
keypoints and the resulting false non-equivalences. This
is the default.
-NOMERGE Disables the merging of equivalent registers after they
are moved.
-DIAGNOSIS <identifier> -BACKWARD
Checks that a register can be retimed a step forward or
backward. If the retime movement cannot succeed, the
reason for the failure is reported. By default, this
diagnoses the forward retiming step.
Note: This option will not change the netlist, it only
provides information about the specied retiming step.
-BACKWARD species that the backward retiming step is
diagnosed.
-VERbose Prints additional information, including a list of current
tasks and statistics.
-BOTh Executes this command on both the Golden and Revised
designs. This is the default.
-REVised Executes this command on the Revised design and uses
the Golden design as the reference design.
-GOLden Executes this command on the Golden design and uses
the Revised design as the reference design.
Command Reference
Examples
The following command initiates backward pipeline retiming for register r1 and registers
whose identiers begin with r2, such as r2a and r21, in the Revised design:
analyze retiming -pipeline r1 r2* \
-revised -backward
The following demonstrates how to use the ANALYZE RETIMING -comb_identical
command with other commands.
1. Read in your library.
SETUP> read lib -lib matrox_test1.lib
// Parsing file matrox_test1.lib ...
// Note: Read Liberty library successfully
2. Read in your Golden and Revised designs.
SETUP> read design -golden matrox_test1_brt.v
// Parsing file matrox_test1_brt.v ...
// Golden root module is set to hst_ssurfdes
// Note: Read VERILOG design successfully
SETUP> read design -revised matrox_test1_art.v
// Parsing file matrox_test1_art.v ...
// Revised root module is set to hst_ssurfdes
// Note: Read VERILOG design successfully
3. Switch to LEC mode.
SETUP> set system mode LEC
// Processing Golden ...
// Modeling Golden ...
// Processing Revised ...
// Modeling Revised ...
// Mapping key points ...
.
.
.
4. Use the ANALYZE RETIMING -comb_identical command and attempt to retime the
Revised design to match the Golden design.
LEC> analyze retiming -combinational_identical
// Retimed successfully 859 registers in Revised as 141 registers
// All comparison points have been deleted
// All key points have been unmapped
// Mapping key points ...
===========================================================================
Mapped points: SYSTEM class
---------------------------------------------------------------------------
Mapped points PI PO DFF Total
---------------------------------------------------------------------------
Golden 1632 29 147 1808
---------------------------------------------------------------------------
Revised 1632 29 147 1808
===========================================================================
Command Reference
5. Add all mapped points, excluding primary inputs, as compare points.
LEC> add comp points -all
// 176 compared points added to compare list
6. Use the COMPARE command to start the equivalency checking comparison.
LEC> compare
===========================================================================
Compared points PO DFF Total
---------------------------------------------------------------------------
Equivalent 29 147 176
===========================================================================
Related Commands
ADD COMPARED POINTS
COMPARE
Command Reference
ANALYZE SETUP
ANAlyze SEtup
[-NOCUT | -CUT]
[-NOLIBRARY_VERIFICATION | -LIBRARY_VERIFICATION]
[-VERBose]
(LEC Mode)
Automatically resolves the setup related issues so that non-equivalency due to incorrect
setup can be prevented or resolved.
Note: To resolve sequential constant optimization with this command, you must use the
following command:
Parameters
Related Commands
ANALYZE NONEQUIVALENT
SET ANALYZE OPTION
-NOCUT Does not analyze loop cutting. This is the default.
-CUT Analyzes loop cutting. When creating attened netlists, the
Conformal software breaks all loops by inserting CUT gates,
which could cause false non-equivalences. With this option, you
can resolve these false non-equivalences.
-NOLIBRARY_VERIFICATION
Does not performsetup analysis for library cell verication. This
is the default.
-LIBRARY_VERIFICATION
Performs setup analysis for library cell verication.
-VERBose Provides additional information.
Command Reference
APPLY PATCH
APPly PAtch
<patch_module_name>
[-KEEPHierarchy]
[-NETnaming <format_string>]
[-INStancenaming <format_string>]
[-SEQuentialnaming <format_string>]
(Setup Mode)
Applies the ECO change specied in the patch module, generated by the ANALYZE ECO
command, to the module under ECO. The patched module can be written out with the WRITE
DESIGN command.
Note: The patch generated by the ANALYZE ECO command can contain unmapped
primitives. You can use the synthesis tool or the MAP ECO PATCH command to map the patch.
Parameters
Species the name of the module being changed for ECO.
<patch_module_name> Species the name of the patch module containing the ECO
changes.
-KEEPHierarchy Species that the ECO changes will be put in a submodule.
-NETnaming <format_string>
Species the net naming format of the ECO nets. For example,
for eco_net_%d, the %d will be an integer that makes the net
name unique.
-INStancenaming <format_string>
Species the instance naming format of the ECO combinational
cells. For example, for eco_instance_%d, the %d will be an
integer that makes the instance name unique.
-SEQuentialnaming <format_string>
Species the instance naming format of the ECO registers and
latches. For example, eco_%s, where %s is the original register
name.
Command Reference
Examples
For a set of sample commands that shows this command and related commands in context,
see the example for ADD BLACK BOX on page 37.
Related Commands
MAP ECO PATCH
OPTIMIZE PATCH
Command Reference
ASSign PIn Direction
<IN | OUT | IO>
<module_name>
<pin_name*>
[-FROM_DIr <IN | OUT | IO>]
(Setup Mode)
Denes a module pins direction. SPICE netlist ports do not have direction, unless you supply
*.pininfo <pin>:<direction> as a CDL comment and read it in as an inout.
Abstraction analyzes the circuit and assigns pin directionwhen determinable. In some
cases, you need to assign pin direction manually to complete abstraction.
Note: You can use this command instead of the ADD MOS DIRECTION command to assist
abstraction.
Wildcard: The wildcard (*) represents any zero or more characters in pin names.
Parameters
Examples
assign pin direction in mux2p sela -revised
assign pin direction out mux4p y -golden
IN Species that the assigned pin direction is input.
OUT Species that the assigned pin direction is output.
IO Species that the assigned pin direction is I/O.
module_name Species that the pin resides in the specied module.
pin_name* Assigns a direction to the specied pin.
-Golden Assigns the pin direction to the Golden design. This is the
default.
-Revised Assigns the pin direction to the Revised design.
-Both Assigns the pin direction to both the Golden and Revised
designs.
-FROM_DIr Only pins which have the direction specied by this options
argument will be redirected.
Command Reference
assign pin direction in mux2p sela y -both
//Assigns direction to pins sela and y.
assign pin direction IN mod pin_* -from_type IO
//Changes all IO pins whose name matches pin_* in
//module mod to IN pins on the golden side.
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
BACKWARD
BACkward
[integer]
(LEC Mode)
Reports fanin gate information from the currently displayed attened gate information. The
fanin gate you choose with this command becomes the current attened gate. Use this
command to trace gates in place of repeatedly using the REPORT GATE command.
Note: This command does not report gates at the design level.
Parameters
Related Commands
FORWARD
REPORT GATE
integer Species which fanin gate is reported. The value 1 denotes the
rst fanin. The default value is 1.
Command Reference
BREAK
BREak
(Setup / LEC Mode)
Terminates the dole script and returns you to the system mode prompt.
Related Commands
CONTINUE
DOFILE
SET DOFILE ABORT
Command Reference
CHANGE GATE TYPE
CHAnge GAte Type
<identifier>
-Type <gate_type>
[-help]
(LEC Mode)
Changes the gate type of a selected object in the schematic viewer.
Note: You cannot use this command on pins and nets.
Note: If you invoke the Flatten Schematics window for a candidate gate (such as
Corresponding Supports and Compared Points) fromthe Diagnosis Manager, you cannot
change its gate type.
Parameters
identifier Species the gate ID or instance pathname.
If you do not specify one of the following options, Conformal
-Type <gate_type> Changes the specied gate type, where <gate_type> could be
one of the following:
I AND
I NAND
I OR
I NOR
I XOR
I XNOR
I BUF
I INV
Note: Not all types are available for all objects
Command Reference
Related Commands
REPORT GATE
-help Returns a list of potential candidate gate types that can be
applied.
-Golden Species that the identier is in the Golden design. This is the
default.
-Revised Species that the identier is in the Revised design.
Command Reference
CHANGE NAME
CHAnge NAme
<filename>
[-Summary |-Verbose]
[-Golden |-Revised |-Both]
(Setup Mode)
Converts netlist net names, port names, and cell names back to their original names. Thus,
Conformal does key point mapping faster and more efciently. The most common use of this
command is to change the names in a post synthesis netlist back to their original,
presynthesis forms.
After Conformal reads in the le containing the original names and new names, it makes the
conversion. Generally, the synthesis tool you have used generates the le describing the
changes. Consult the specic vendors tool documentation for additional change name
information.
The format of the change name le is as follows:
I The change name information is preceded by dashes.
Note the dashes in the example below that separate column headers and the change
name information. Conformal recognizes this le as a change name le format when it
detects the dashes.
I The Design column consists of module names.
For example, see mod0_module in the sample Change Name le below.
I The Type column consists of elements that belong to the specied design (that is, cell,
port, and net).
I The Object is the original name. Conformal will change the name back from the New
Name to the original name.
I The New Name is the name assigned by the synthesis tool
Sample Change Name File
Design Type Object New Name
----------------------------------------------------------
mod0_module port port0_input1 port0_1
mod0_module net net0_output net0_t
mod1_module port port1_input1a port_1a
mod1_module cell net1_subinstantiation net1_n
Command Reference
Parameters
Related Commands
ADD RENAMING RULE
filename Species the le that contains name changes.
-Summary Prints out the summary count of the number of name changes.
-Verbose Prints out a message for each name change.
-Golden Changes names in the Golden design. This is the default.
-Revised Changes names in the Revised design.
-Both Changes names in both the Golden and Revised designs.
Command Reference
CHEck LOwpower Cells
(LEC Mode)
Performs low power checks for low power cell types that were specied with the SET
LOWPOWER OPTION command. This check consists of the state retention technology
mapping check, isolation and level-shifter cell check, and the power domain consistency
check. These checks are described as follows:
State Retention Cells
For state retention cells, this command does the technology mapping check to ensure that
the sequential elements (DFFs or DLATs) are technology mapped in accordance with the
retention mapping rules during synthesis. These retention mapping rules include all the user
rules added with the ADD RETENTION MAPPING command and the default rule added by
the system.
The following three default rules are added by the system:
Note: For any sequential pairs, only one of the default rules take effect.
I Default: Checks that the tag name used in the Golden design is mapped to a non-state
retention cell in the Revised design. A non-state retention cell is a cell that does not have
a power_gating_cell attribute. This rule is normally applied during RTL to gate-level
checks.
I Default1: Checks that the power_gating_cell attribute in the Golden design is
exactly the same as the power_gating_cell in the Revised design. This check
ensures that non-state retention cells (regular DFFs or DLATs) are mapped to non-state
retention cells, or state retention cells are mapped to state retention cells. This rule is
normally applied during gate-level to gate-level checks.
I Default2: Checks that the tag name used in the Golden design is exactly the same as
the tag name used in the Revised design. This rule is normally applied during RTL to RTL
checks.
Command Reference
Isolation Cells and Level-Shifter Cells
For isolation cells and level-shifter cells, this command does the technology mapping check
and equivalence check.
The technology mapping check ensures that for each low power cell (isolation cell or
level-shifter cell) in the Golden design, there is a corresponding low power cell in the Revised
design. To establish the correspondence, the Conformal software inserts key points (cut
gates) at the output of low power cells and performs name-based mapping. If it does not nd
mapping for a low power cut gate, it sets the status of the corresponding low power cell to
FAIL; otherwise, the status is set to PASS.
The equivalence check (EC) ensures that for the mapped lowpower cell pair, the logic feeding
them is equivalent in both the Golden and Revised designs. To perform EC, the Conformal
software adds the low power cut gates as compare points and these are proven equivalent or
non-equivalent during compare (when running the COMPARE command).
Note: The CHECK LOWPOWER CELLS command performs only the technology mapping
check for isolation cells and level-shifter cells. The EC checking results are received after
running the COMPARE command.
After performing the low power check, a status summary is printed for all low power cells.
Power Domain Consistency Check
Power domain consistency checking is available in the CPF ow. This checks whether the
sequential mapped pair resides in the same power domain between the Golden and Revised
designs. You can perform this check after reading in the CPF les for both the Golden and
Revised designs. For RTL and synthesized gate netlists, the power domain of key-points can
only be obtained from the CPF specication. For the physical netlist, the power domain can
be obtained either from the CPF specication or by tracing the power and ground pins.
The power domain consistency check sets the status of the mapped pair to FAIL if the power
domains of the Golden and Revised sequential points in the mapped pair are different. In the
case of merged sequential points, if the power domains of any of the merged elements are
different, the power domain consistency check will set the status of the corresponding pair to
FAIL.
Note: The power domain consistency check is only enabled for sequential compare points.
Note: Use the SET MAPPING METHOD -unreach command to allowmapping and checking
the consistency of power domains for unreachable key-points.
Command Reference
If the power domain cannot be obtained for sequential element in the mapped pair, the power
domain consistency check sets the mapped pair status to NOT-CHECKED. The following are
the scenarios where power domains cannot be obtained for a sequential element:
I CPF is not read in.
I CPF specication is incomplete.
For example, no default power domain is specied or CPF does not have the denition
of internal power and ground nets.
I LEF le is not read in.
I Power and Ground pins are oating in the physical netlist.
Related Commands
ADD LOWPOWER CELLS
COMPARE
SET LOWPOWER OPTION
Command Reference
CHANGE NET TYPE
CHAnge NEt Type
<TRI | TRI0 | TRI1 | TRIREG | TRIAND | TRIOR>
<net_name>
|-Module <name>]
(Setup Mode)
Modies the database so that it appears that the changed net types were declared in the
original Verilog netlist.
Parameters
Related Command
ADD NET ATTRIBUTE
TRI Species a tristate net type. This is the default.
TRI0 Species a net of type TRI0.
TRI1 Species a net of type TRI1.
TRIREG Species a net of type TRIREG.
TRIAND Species a net of type TRIAND.
TRIOR Species a net of type TRIOR.
-Module <name> Species the module name of the net to be changed. By default, this
command changes the net in the root module.
Command Reference
CLOSE SCHEMATICS
CLOse SChematics
(Setup / LEC Mode)
Closes all schematic viewer windows.
Note: You cannot use this command in non-GUI mode.
Related Command
OPEN SCHEMATICS
Command Reference
COMMIT CPF
COMmit CPf
[-INSERT]
[-GOLden | -REVised | -BOTH]
(Setup Mode)
Applies CPF low power cell information. When performing insertion, the cell types can be
level shifter cells, isolation cells, and state retention cells. These low power cells can either
be dened in .lib or dened in CPF les. You can only run this command after successfully
reading in the CPF les.
Parameters
Examples
The following commands show an example of the CPF equivalency checking ow, which
performs low power cell insertion on the Golden side, and performs equivalency checks with
physical implementation in two CPF les named rtl.cpf and my_library.cpf:
read lef file my_library.lef
read library -liberty my_library.lib -both
read design rtl.v -verilog -golden
read cpf rtl.cpf my_library.cpf
commit cpf -insert
read design physical.v -verilog -revised
add compare point -all
compare
-INSERT Inserts low power cells, which include level shifter, isolation,
and state retention cells, into the original design.
-GOLden Inserts low power cells in the Golden design. This is the
default.
-REVised Inserts low power cells in the Revised design.
-BOTH Inserts low power cells in both the Golden and Revised
designs.
Command Reference
Related Command
READ CPF
REPORT CPF LOGIC
Command Reference
COMPARE
COMpare
[-NONEQ_Stop <integer>]
[-ABORT_Stop <integer>]
[-NONEQ_Print]
[-ABORT_Print]
[-PARALLEL <machine_file>]
[-GATE_TO_GATE]
[-SIngle]
[-NOREPORT_BBOX_INPUT | -REPORT_BBOX_INPUT]
[-NOREPORT_SINGLE_LINE_SUMMARY | -REPORT_SINGLE_LINE_SUMMARY]
(LEC Mode)
Starts the equivalency checking comparison between the Golden and Revised designs on the
added compared points. During the comparison, the following information is displayed:
I Progress percentile number, which displays the completion rate
I Running count, which displays the number of key points that have been compared along
with the total number of non-equivalent key points
Each compared point results in a status drawn from the following ve possibilities:
I Equivalent
I Inverted equivalent
I Nonequivalent
I Abort
I Not compared
When Conformal completes the comparison, it displays a summary table of the number of
equivalent and non-equivalent compared points.
Note: If you must interrupt the comparison, the Control-C keys stop the process.
Parameters
-NONEQ_Stop <integer> Stops the comparison after nding the specied number of
non-equivalent points.
-ABORT_Stop <integer> Stops the comparison after nding the specied number of
abort points.
-NONEQ_Print Displays the non-equivalent points as they are found.
Command Reference
Examples
The following is a set of sample commands that shows this and related commands in context.
The following set of commands assumes that you have read in your library, design, and have
switched to the LEC mode.
-ABORT_Print Displays the abort points as they are found.
-PARALLEL <machine_file>
Note: This is a Conformal Ultra feature.
Runs a comparison on multiple machines.
Tip
You can use the USAGE command to display the
total CPU time used for all processes.
For more information on creating a machine_file, see
Parallel Processing in the Encounter Conformal
Equivalence Checking User Guide.
-GATE_TO_GATE Enables an algorithm that might improve the run time of
large gate-to-gate netlist comparisons.
-SIngle Compares each key point as a single point. By default, the
COMPARE command compares by key point groups.
-NOREPORT_BBOX_INPUT Does not report the blackbox input pins in the compare
report results. This is the default.
-REPORT_BBOX_INPUT Reports the blackbox input pins in the compare report
results (Equivalent, Non-equivalent, Abort, and
Not-compared).
-NOREPORT_SINGLE_LINE_SUMMARY
Does not print a single line summary of the compare results.
-REPORT_SINGLE_LINE_SUMMARY
Prints a single line summary of the compare results.
Command Reference
1. Use the ADD COMPARED POINTS command to add mapped points to the compare list.
LEC> add compare point -all
//2 compared points added to compare list
2. Use the COMPARE command to start the equivalency comparison between the Golden
and Revised designs.
LEC> compare
============================================================================
Compared points PO Total
----------------------------------------------------------------------------
Equivalent 1 1
----------------------------------------------------------------------------
Non-equivalent 1 1
============================================================================
3. Use the REPORT COMPARE DATA command to report the non-equivalent points.
LEC> rep comp data -noneq
Compared points are: Non-equivalent
+ 11 PO /x + 11 PO /x
1 compared point(s) reported
============================================================================
Compared points PO Total
----------------------------------------------------------------------------
Equivalent 1 1
----------------------------------------------------------------------------
Non-equivalent 1 1
============================================================================
4. Use the ADD DYNAMIC CONSTRAINT command to add a dynamic constraint to the
design.
LEC> add dyn con 0 /c -gold
LEC> add dyn con 0 /c -rev
5. Use the REPORT DYNAMIC CONSTRAINTS to report the dynamic constraints in the
design.
LEC> report dynamic constraints
============================================================================
Design ID Type Value Name
----------------------------------------------------------------------------
Golden 3 PI 0 /c
Revised 3 PI 0 /c
============================================================================
6. Use the PROVE command to show whether the specied gates are equivalent or not
equivalent.
LEC> prove /x /x
//Compared points are: Non-equivalent
//(G) + 11 PO /x
//(R) + 11 PO /x
Command Reference
7. Use the DIAGNOSE command to diagnose the non-equivalent points.
LEC> diag /x
//Diagnosis for Non-equivalent key points:
//(G) + 11 PO /x
//(R) + 11 PO /x
The diagnosis point can be corrected by changing the following gates:
============================================================================
Correction ID (R) Type Name
----------------------------------------------------------------------------
DEL_INVERTER 24 INV /gextra
Related Commands
ADD COMPARED POINTS
DIAGNOSE
PROVE
REPORT COMPARE DATA
RUN PARALLEL COMPARE
SET COMPARE EFFORT
USAGE
Command Reference
CONTINUE
CONTinue
(Setup / LEC Mode)
Used in conjunction with the BREAK command in a dole, when a dole executes the BREAK
command, Conformal issues a warning and prompts you to use the CONTINUE command.
The CONTINUE command has no effect if you type it without being prompted by Conformal.
The CONTINUE command supports mixed GUI and non-GUI mode. For example, you can run
a dole in non-GUI mode, encounter a break in the dole, issue set gui on, and run
continue from the GUI. The same applies when you break in the GUI mode: switch to
command mode and enter continue.
Conformal also supports nested breaks inside doles, working in a stack fashion. For
example, when you type in continue from a lower-level dole, Conformal proceeds until it
encounters the next BREAK command.
Example
//Warning: Break dofile my_dofile at line 32. Use continue command to continue.
% continue
Related Commands
BREAK
DOFILE
SET DOFILE ABORT
Command Reference
COPY MODULE
COPy MOdule
<[-Golden | -Revised] source_module_name
[-Revised | -Golden] target_module_name>
[-LOGIC | -PINDIR]
[-USE_RENAME_RULE | -NOUSE_RENAME_RULE]
(Setup Mode)
Copies the logic or pin direction froma source module in one design to a target module in the
other design. If you must copy both the logic and the pin direction, use two separate
commands.
Parameters
-Golden Species that the source module is located in the Golden
-Revised Species that the source module is located in the Revised
design.
source_module_name Species the name of the source module to be copied.
-Revised Species that the target module is located in the Revised
-Golden Species that the target module is located in the Golden
design.
target_module_name Species the name of the target module for the copy operation.
-LOGIC Copies the logic fromthe source module into the target module.
If you must copy both logic and pin direction, use two separate
COPY MODULE commands.
-PINDIR Copies the pin direction from the source module into the target
module. If you must copy both logic and pin direction, use two
separate Copy Module commands.
-USE_RENAME_RULE Uses renaming rules for matching pin and module names. This
is the default.
-NOUSE_RENAME_RULE Does not use renaming rules for matching pin and module
names.
Command Reference
Related Command
Command Reference
DELETE ALIAS
DELete ALias
<name*>
(Setup / LEC Mode)
Deletes aliases created with the ADD ALIAS command. Use the REPORT ALIAS command
to display a list of all aliases.
Wildcard: The wildcard (*) represents any zero or more characters in alias names.
Parameters
Related Commands
ADD ALIAS
REPORT ALIAS
name* Deletes the specied aliases.
Command Reference
DELETE BLACK BOX
DELete BLack Box
<name* [-Module] | name -Instance | -All>
(Setup Mode)
Deletes specied blackboxes fromthe design. These blackboxes were either created with the
ADD BLACK BOX command or were a part of the original design.
Use the REPORT BLACK BOX command to display a list of all blackboxes.
Parameters
Related Commands
ADD BLACK BOX
REPORT BLACK BOX
name* -Module Deletes blackboxes specied by this list. -module is the
default.
name -Instance Species that the blackbox names are instance names.
-All Deletes all dened blackboxes. -All applies within the
given defaults.
-Golden Deletes blackboxes from the Golden design. This is the
default.
-Revised Deletes blackboxes from the Revised design.
-Both Deletes blackboxes from both the Golden and Revised
designs.
Command Reference
DELETE CLOCK
DELete CLock
<-ALL_Pin | primary_pin>
[-Golden |-Revised]
(Setup Mode)
Deletes clocks added with the ADD CLOCK command.
Use the REPORT CLOCK command to display a list of all aliases.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
READ PATTERN
REPORT CLOCK
-ALL_Pin Deletes all the dened clocks. -All applies within the given
defaults.
primary_pin Deletes the primary input pins that were dened as clocks and
specied in this list.
-Golden Deletes the clock(s) from the Golden design. This is the
default.
-Revised Deletes the clock(s) from the Revised design.
Command Reference
RESOLVE
Command Reference
DELete COmpared Points
< -All |<<gate_id | instance_pathname* | pin_pathname*>
[-Golden |-Revised]>
>
(LEC Mode)
Deletes compared points originally added with the ADD COMPARED POINTS command. If the
compared point is deleted from the Golden design, Conformal also deletes its mapped
compared point from the Revised design. Alternately, if the compared point is deleted from
the Revised design, Conformal also deletes its mapped compared point from the Golden
design.
Use the REPORT COMPARED POINTS command to display a list of all added compared
points.
Wildcard: The wildcard (*) represents any zero or more characters in instance and pin paths.
Parameters
Related Commands
ADD COMPARED POINTS
COMPARE
-All Deletes all compare points. -All applies within the given
defaults.
gate_id Deletes the specied gates as compare points.
instance_pathname*
Deletes the specied instance paths as compare points.
pin_pathname* Deletes the specied pin paths as compare points.
-Golden Deletes the compare points from the Golden design. This is
the default.
-Revised Deletes the compare points from the Revised design.
Command Reference
Command Reference
DELETE CUT POINT
DELete CUt Point
<-All | pathname>
[-Net | -Pin]
(Setup Mode)
Deletes cut points originally added with the ADD CUT POINT command.
Use the REPORT CUT POINT command to display a list of all added cut points.
Parameters
Related Commands
ADD CUT POINT
REPORT CUT POINT
REPORT PATH
-All Deletes all cut points. -All applies within the given defaults.
pathname Deletes cut points from the specied paths.
-Net Species that the named path is a net. This is the default.
-Pin Species that the named path is a pin.
-Golden Deletes the cut points from the Golden design. This is the
default.
-Revised Deletes the cut points from the Revised design.
-Both Deletes the cut points from both the Golden and Revised
designs.
Command Reference
DELete DYnamic Constraints
<-All | identifier>
(LEC Mode)
Deletes dynamic constraints originally added with the ADD DYNAMIC CONSTRAINTS
command.
Use the REPORT DYNAMIC CONSTRAINTS command to display a list of all added dynamic
constraints.
Parameters
-All Deletes all dynamic constraints. -All applies within the given
defaults.
identifier Deletes dynamic constraints from the specied identier. If you
do not specify one of the following options, Conformal
-INStance Species the hierarchical instance path
-Pin Species the pin path, which is the module
instance name concatenated with the pin
name.
-Net Species the net path, which is the instance
name concatenated with the net name.
-ID Species the identication number (ID) of a
gate.
Command Reference
Related Commands
PROVE
-Golden Deletes dynamic constraints from the Golden design. This is
the default.
-Revised Deletes dynamic constraints from the Revised design.
-Both Deletes dynamic constraints from both the Golden and Revised
designs.
Command Reference
DELETE ECO CELL
DELete ECo Cell
[-FReedcell <cell_name*>]
[-SParecell <cell_name*>]
[-ALL]
(Setup Mode)
Deletes the spare cells or freed cells from the available cells for the MAP ECO PATCH
command.
Parameters
Related Commands
ADD ECO CELL
MAP ECO PATCH
REPORT ECO CELL
-FReedcell Species the name(s) of the freed cell(s) to be deleted. This
supports wildcards.
-SParecell Species the name(s) of the spare cell(s) to be deleted. This
supports wildcards.
-ALL Deletes all the cells.
Command Reference
DELETE ECO PATCH
DELete ECo PAtch
[-ALL| <module_under_ECO_name> [<patch_module_name>] ]
(Setup Mode)
Deletes the ECOpatch fromthe module list to be mapped by the MAP ECO PATCH command.
Parameters
Related Commands
ADD ECO PATCH
MAP ECO PATCH
REPORT ECO PATCH
-ALL Deletes all the added ECO patches.
Species the name of the module to delete
<patch_module_name> Species the name of the patch module that contains the ECO
changes.
Command Reference
DELETE ECO PIN
DELete ECo PIn
<module_name>
<pin_name> | <bus_name> ...
[-REPort <filename>]
(Setup Mode)
Deletes the pins from the module that were added with the ADD ECO PIN command.
Parameters
Related Commands
ADD ECO PIN
MAP ECO PATCH
<module_name> Species the name of the module.
<pin_name> Species the name of the pin(s).
<bus_name> Species the name of the bus(es).
Note: You cannot delete only partial bits. For example, if there
is a bus port OUT[1:0], the command should be:
delete eco pin top OUT
not
delete eco pin top OUT[1:0]
-REPort <filename> Species the name of the report.
Command Reference
DELETE IGNORE RTLCHECK
DELete IGnore Rtlcheck
<-All | -Module <name*>>
(Setup Mode)
Re-enables RTL (HDL) rule checking for all or specied modules. By default, rule checking is
enabled. Thus, you will only use the DELETE IGNORE RTLCHECK command to reverse the
effects of the ADD IGNORE RTLCHECK command.
information about specic rules.
Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace
previous commands. In the following example, Conformal enables RTL rule checking for all
modules, including module abc.
add ignore rtlcheck -module abc
delete ignore rtlcheck -all
Parameters
Related Commands
ADD IGNORE RTLCHECK
REPORT RULE CHECK
-All Enables RTL rule checking for all modules.
-Module* name Enables RTL rule checking for the specied modules.
Command Reference
DELete IGnored Inputs
<-ALL_Pin | primary_pin*>
[-ROot |-Module <name> | -ALL_Module]
(Setup Mode)
Deletes input pins originally added as ignored inputs in the Golden or Revised design with
the ADD IGNORED INPUTS command.
Use the REPORT IGNORED INPUTS command to display a list of all added ignored input pins.
Wildcard: The wildcard (*) represents any zero or more characters in ignored input names.
Parameters
Related Commands
ADD IGNORED INPUTS
-ALL_Pin Deletes all previously added ignored inputs within the given
defaults.
primary_pin* Deletes the specied pins as ignored inputs. The wildcard (*) is
accepted.
-ROot Deletes the ignored inputs in the root module. This is the
default.
-Module name Deletes the ignored inputs from the specied module.
-ALL_Module Deletes the ignored inputs fromall of the modules, including the
root module.
-Golden Deletes the specied ignored inputs from the Golden design.
-REvised Deletes the specied ignored inputs from the Revised design.
-Both Deletes the specied ignored inputs from both the Golden and
Revised designs.
Command Reference
DELete IGnored Outputs
[-ROot | -Module <name> | -ALL_Module]
(Setup Mode)
Deletes output or I/O pins originally added as ignored outputs with the ADD IGNORED
OUTPUTS command.
Use the REPORT IGNORED OUTPUTS command to display a list of all added ignored output
or I/O pins.
Wildcard: The wildcard (*) represents any zero or more characters in ignored output names.
Parameters
Related Commands
ADD IGNORED OUTPUTS
-ALL_Pin Deletes all added ignored outputs.
primary_pin* Deletes the specied pins as ignored outputs.
-ROot Deletes the ignored outputs in the root module. This is the
default.
-Module name Deletes the ignored outputs from the specied module.
-ALL_Module Deletes the ignored outputs from all modules, including the root
module.
-Golden Deletes the specied ignored outputs from the Golden design.
-REvised Deletes the specied ignored outputs from the Revised design.
-Both Deletes the specied ignored outputs fromboth the Golden and
Revised designs.
Command Reference
DELete INstance Attribute
<module_name> <instance_name> <WEAK>
(Setup Mode)
Deletes instance attributes originally added with the ADD INSTANCE ATTRIBUTE command.
Use the REPORT INSTANCE ATTRIBUTE command to display a list of all added instance
attributes.
Parameters
Related Commands
module_name Deletes the instance attribute from the specied module.
instance_name Deletes the instance attribute from the specied instance.
WEAK Species drive strength.
Note: This option applies to Conformal Custom.
-Golden Deletes the instance attribute from the Golden design. This is
the default.
-Revised Deletes the instance attribute from the Revised design.
Command Reference
DELete INstance Constraints
<<name> [-Module name*] | -All>
[-Golden | -Revised | -BOTH]
(Setup Mode)
Deletes instance constraints originally added with the ADD INSTANCE CONSTRAINTS
command.
Use the REPORT INSTANCE CONSTRAINTS command to display a list of all added instance
constraints.
Parameters
Related Commands
name Deletes constraints on the specied instance paths.
Note: The names are either DFFs or D-latches.
-Module name* Deletes the constraints from the specied module(s). The
wildcard (*) is supported.
-All Deletes all instance constraints. -All applies within the given
defaults.
-Golden Deletes instance constraints in the Golden design. This is the
default.
-Revised Deletes instance constraints in the Revised design.
-BOTH Deletes instance constraints in both the Golden and Revised
designs.
Command Reference
DELete INstance Equivalences
<instance_pathname| -All>
(Setup Mode)
Deletes instance equivalences originally added with the ADD INSTANCE EQUIVALENCES
command.
Use the REPORT INSTANCE EQUIVALENCES command to display a list of all added instance
equivalences.
Parameters
Related Commands
instance_pathname Deletes equivalences on the specied instance paths.
-All Deletes all instance equivalences. -All applies within the
given defaults.
-Golden Deletes instance equivalences in the Golden design. This is
the default.
-Revised Deletes instance equivalences in the Revised design.
Command Reference
DELete LOwpower Cells
<module_name* | -All>
(Setup Mode)
Deletes low power cells that were originally dened for modules with the ADD LOWPOWER
CELLS command.
Use the REPORT LOWPOWER CELLS command to display a list of the low power cells used
in the design.
Parameters
Related Commands
ADD LOWPOWER CELLS
SET LOWPOWER OPTION
module_name Deletes previously added low power cells from the specied
modules. This supports wildcards.
-ALL Deletes previously added low power cells from all modules.
-Both Deletes the low power cells in the Golden and Revised designs.
-Golden Deletes the low power cells in the Golden design.
-Revised Deletes the low power cells in the Revised design.
Command Reference
DELete MApped Points
<-All [-Class <Full | User | System>]
|<<gate_id | instance_pathname* | pin_pathname*>
[-Golden | -Revised]>
|[-NONEQ]
|[-UNREACH]
>
(LEC Mode)
Deletes mapped points that were one of the following:
I Automatically identied
I Added with the ADD MAPPED POINTS command.
Additionally, Conformal deletes all compared points associated with the added mapped
points.
Use the REPORT MAPPED POINTS command to display a list of all mapped points in the User
and System classes of the Golden and Revised designs.
Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths
of mapped points.
Parameters
-All Deletes all mapped points. -All applies within the given
defaults.
-Class Deletes the specied class of mapped points.
Full The Full class includes mapped points from both
the User and System classes. This is the
default.
User The User class includes mapped points that were
previously added with the ADD MAPPED POINTS
command.
System The System class includes mapped points that
were automatically identied when Conformal
exited the Setup system mode or were mapped
with the MAP KEY POINTS command.
Command Reference
Related Commands
ADD MAPPED POINTS
MAP KEY POINTS
SET MAPPING METHOD
SET NAMING RULE
gate_id Deletes mapped points with these gate ID numbers.
ID numbers can differ fromone version of Conformal to another.
Always use the full path in doles and any time you rerun a
instance_pathname* Deletes mapped points from the specied instance paths.
pin_pathname* Deletes mapped points from the specied pin paths.
-Golden Delete the mapped points from the Golden design. This is the
default.
-Revised Deletes the mapped points from the Revised design.
-NONEQ Deletes all non-equivalent mapped points.
-UNREACH Deletes all unreachable mapped points. An unreachable
mapped point is one where both the Golden and Revised key
points are unreachable.
If the key point is the representative of the equivalence group or
sequential merge group, it is considered unreachable only if all
the member key points in the group are unreachable.
Command Reference
DELete MOdule Attribute
<module_name | -All>
<-PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit >
(Setup Mode)
Deletes attributes originally assigned to modules with the ADD MODULE ATTRIBUTE
command.
Use the REPORT MODULE ATTRIBUTE command to display a list of all added module
attributes.
Parameters
Related Commands
module_name Deletes previously added attributes from the specied modules.
-ALL Deletes previously added attributes from all modules within
the given defaults.
-PIPELINE_Retime Deletes attributes previously added for pipeline-retiming.
-COMPARE_Effort Deletes compare effort levels previously added to modules.
-CPU_Limit Deletes the CPU time limit imposed with the ADD MODULE
ATTRIBUTE command.
-Golden Deletes the specied module attributes in the Golden design.
-Revised Deletes the specied module attributes in the Revised design.
Command Reference
DELete MOs Direction
<module_name> <instance_name>
(Setup Mode)
Deletes the unidirection that was placed on transistor-MOS instances with the ADD MOS
DIRECTION command.
Use the REPORT MOS DIRECTION command to display a list of all transistor-MOS direction
instances.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
REPORT CLOCK
module_name Deletes MOS direction for the specied module.
instance_name Deletes MOS direction for the specied instance.
-Golden Deletes MOS direction from the Golden design. This is the
default.
-Revised Deletes MOS direction from the Revised design.
Command Reference
RESOLVE
Command Reference
DELete NEt Attribute
<-ALL_Net | net_name>
(Setup Mode)
Deletes attributes that were placed on transistor-MOS nets with the ADD NET ATTRIBUTE
command.
Use the REPORT NET ATTRIBUTE command to display a list of all attributes placed on
transistor-MOS nets.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
-ALL_Net Deletes all net attributes within the given defaults.
net_name Deletes the specied transistor-MOS net attributes.
-ROot Deletes net attributes associated with the root module, which
contains the transistor-MOS. This is the default.
-Module name Deletes net attributes associated with the specied module,
which contains the transistor-MOS.
-ALL_Module Deletes a specied net attribute for all modules, or delete all net
attributes for all modules. (Refer to -all_net and
-net_name to understand the two choices.)
-Golden Deletes net attributes from the Golden design. This is the
default.
-Revised Deletes net attributes from the Revised design.
-Both Deletes net attributes from both the Golden and Revised
designs.
Command Reference
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
DELete NEt Constraints
(Setup Mode)
Deletes either the Golden or Revised design net constraints originally added with the ADD
NET CONSTRAINTS command.
Use the REPORT NET CONSTRAINTS command to display a list of all added net constraints.
Parameters
Related Commands
ADD NET CONSTRAINTS
-Golden Deletes net constraints from the Golden design. This is the
default.
-Revised Deletes net constraints from the Revised design.
-Both Deletes net constraints from both the Golden and Revised
designs.
Command Reference
DELETE NOBLACK BOX
DELete NOblack Box
(Setup Mode)
Deletes the specied module names originally added with the ADD NOBLACK BOX command.
Use the REPORT NOBLACK BOX command to display a list of all of the modules that will be
resolved (attened) to their parents modules during hierarchical dole script generation.
Parameters
Related Commands
ADD NOBLACK BOX
REPORT NOBLACK BOX
module_name* Deletes the previously added noblackbox modules.
-All Deletes all previously added noblackboxes. -All applies
-Golden Deletes the specied Golden module names. This is the
default.
-Revised Deletes the specied Revised module names.
-Both Deletes all of the specied modules from both the Golden and
Revised designs.
Command Reference
ADD NOtranslate Filepathnames
<filepath_names* | -All>
(Setup Mode)
Deletes the specied le pathnames originally added with the ADD NOTRANSLATE
FILEPATHNAMES command.
Use the REPORT NOTRANSLATE FILEPATHNAMES command to display a list of all of the
library and design le pathnames.
Parameters
Related Commands
filepath_name* Deletes the listed notranslate le pathnames.
-All Deletes all previously added notranslate le pathnames.
-All applies within the given defaults.
-Library Deletes the specied library le pathnames. This is the
default.
-Design Deletes the specied design le pathnames.
-Both Deletes the specied le pathnames from both the Golden
and Revised designs. This is the default.
-Golden Deletes the specied Golden le pathnames.
-Revised Deletes the specied Revised le pathnames.
Command Reference
DELete NOtranslate Modules
[-Library | -Design]
(Setup Mode)
Deletes the specied module names originally added with the ADD NOTRANSLATE MODULES
command.
Use the REPORT NOTRANSLATE MODULES command to display a list of all of the library and
design module names that will not be compiled.
Parameters
Related Commands
READ DESIGN
READ LIBRARY
module_name* Deletes the listed modules.
-All Deletes all previously added notranslate module names. -All
-Library Deletes the specied library module names. This is the
default.
-Design Deletes the specied design module names.
-Both Deletes the specied modules from both the Golden and
-Golden Deletes the specied Golden module names.
-Revised Deletes the specied Revised module names.
Command Reference
DELete OUtput Equivalences
(Setup Mode)
Deletes the output pin equivalences placed on output boundary module pins with the ADD
OUTPUT EQUIVALENCES command.
Use the REPORT OUTPUT EQUIVALENCES command to display a list of all added output pin
equivalences.
Wildcard: The wildcard (*) represents any zero or more characters in output boundary
module pin names.
Parameters
Related Commands
-ALL_Pin Deletes all output pin equivalences within the given defaults.
primary_pin* Deletes output pin equivalences from the listed output
boundary module pins.
-ROot Deletes the output pin equivalences from the root module.
-Module name Deletes the output pin equivalences from the specied module.
-ALL_Module Deletes the output pin equivalences from all modules.
-Golden Deletes the specied output pin equivalences in the Golden
-Revised Deletes the specied output pin equivalences in the Revised
design.
-Both Deletes the specied output pin equivalences in both the
Command Reference
DELete OUtput Stuck_at
<-ALL_Pin | primary_pin>
[-Module <name>]
[-Golden |-Revised]
Deletes the output stuck_at values placed on output boundary module pins with the ADD
OUTPUT STUCK_AT command.
Use the REPORT OUTPUT STUCK_AT command to display a list of all added output
stuck_at values and their pin names.
Parameters
Related Commands
ADD OUTPUT STUCK_AT
-ALL_Pin Deletes all output stuck_at values within the given defaults.
primary_pin Deletes the output stuck_at values associated with the listed
output boundary module pins.
-Module name Deletes the output stuck_at values in the specied module.
-Golden Deletes the output stuck_at values in the Golden design.
-Revised Deletes the output stuck_at values in the Revised design.
Command Reference
DELete PArtition Key_point
(Setup Mode)
Deletes all of the specied partition key points originally added with the ADD PARTITION
KEY_POINT command.
Use the REPORT PARTITION KEY_POINT command to display a list of all added partition
key points.
Related Commands
Command Reference
DELete PARtition Points
<pathname | -All | -BAD_cuts [-EFFORT <Low | Medium | High]>
[-NONequivalent]
[-NOVerbose | -Verbose]
(LEC Mode)
Deletes the partition points that were created with the ADD PARTITION POINTS command.
Note: Partition points are always deleted in pairs.
Tip
You can get the pathname of the partition point with the REPORT PARTITION
POINT command.
Caution
Deleting partition (CUT) points in LEC mode causes flattened netlists to
change. As a result, all the gate-ids are subjected to change. Deleting cut
points does not affect the existing compare points list; however, all the
compare data is invalidated after deleting cut points.
Parameters
pathname Species the name of the path for the partition points to be
deleted.
-All Species that all the existing partition points will be deleted.
-BAD_cuts Automatically deletes the bad set of partition points causing
false non-equivalence.
-EFFORT <Low | Medium | High>
Command Reference
Related Commands
Species the effort level for deleting the bad set of partition
points.
Increasing the effort level from Low to High will intelligently
delete more partition points decreasing the probability of false
non-equivalence. However, increasing the effort will result in
increased time as well.
The default effort level is Low.
-NONequivalent Deletes partition cut points that caused false non-equivalent
points.
-Golden Species that the partition point is in the Golden design. This is
the default.
-Revised Species that the partition point is in the revised design.
-NOVerbose Does not provide additional information. This is the default.
Command Reference
DELete PIn Constraints
[-Module <name>]
(Setup Mode)
Deletes constraints originally placed on named primary input pins with the ADD PIN
CONSTRAINTS command.
Use the REPORT PIN CONSTRAINTS command to display a list of all added pin constraints.
Wildcard: The wildcard (*) represents any zero or more characters in primary input names.
Parameters
Related Commands
ADD PIN CONSTRAINTS
-ALL_Pin Deletes all constraints placed on primary input pins within the
given defaults.
primary_pin* Deletes constraints from the listed primary inputs.
-Module name Deletes pin constraints from the specied module.
-Golden Deletes the specied pin constraints from the Golden design.
-Revised Deletes the specied pin constraints from the Revised design.
-Both Deletes the specied pin constraints from both the Golden and
Revised designs.
Command Reference
DELete PIn Equivalences
(Setup Mode)
Deletes the added pin equivalences from the specied primary input pins. These
equivalences were placed on primary input pins with the ADD PIN EQUIVALENCE command.
Use the REPORT PIN EQUIVALENCES command to display a list of all of the added pin
equivalences.
Wildcard: The wildcard (*) represents any zero or more characters in primary input names.
Parameters
Related Commands
-ALL_Pin Deletes all added pin equivalences within the given defaults.
primary_pin* Deletes pin equivalences fromthe listed primary input pins. (Pin
equivalence was originally added with the ADD PIN
EQUIVALENCE command.)
-ROot Deletes pin equivalences from the root module.
-Module name Deletes pin equivalences from the specied module.
-ALL_Module Deletes pin equivalences from all modules.
-Golden Deletes the specied pin equivalences from the Golden design.
-REvised Deletes the specied pin equivalences from the Revised
design.
-Both Deletes the specied pin equivalences from both the Golden
Command Reference
DELete PRimary Inputs
<-All | pathname*>
(Setup Mode)
Deletes specied primary inputs that were originally added with the ADD PRIMARY INPUT
command. After you delete the primary input pins from either the Golden or Revised design,
the associated nets become oating nets, unless there are other net drivers.
Use the REPORT PRIMARY INPUTS command to display a list of all primary inputs.
Wildcard: The wildcard (*) represents any zero or more characters in paths of primary
inputs.
Parameters
Related Commands
ADD PRIMARY INPUT
-All Deletes all primary inputs within the given defaults.
pathname* Deletes the specied primary inputs.
-Golden Deletes the specied primary inputs from the Golden design.
-Revised Deletes the specied primary inputs from the Revised design.
-Both Deletes the specied primary inputs from both the Golden and
Revised designs.
Command Reference
DELete PRimary Outputs
<-All | pathname*>
(Setup Mode)
Deletes primary outputs that were originally added with the ADD PRIMARY OUTPUT
command. When you delete the primary output pins from the Golden or Revised design, the
nets become oating nets, unless there are other net drivers.
Use the REPORT PRIMARY OUTPUTS command to display a list of all primary outputs.
Wildcard: The wildcard (*) represents any zero or more characters in paths of primary
outputs.
Parameters
Related Commands
ADD PRIMARY OUTPUT
-All Deletes all primary outputs within the given defaults.
pathname* Deletes the specied primary outputs.
-Golden Deletes primary outputs from the Golden design. This is the
default.
-Revised Deletes primary outputs from the Revised design.
-Both Deletes primary outputs from both the Golden and Revised
designs.
Command Reference
DELete REnaming Rule
<-All | <rule_name>>
[-MAp | -MOdule | -PIn]
(Setup / LEC Mode)
Deletes renaming rules originally added with the ADD RENAMING RULE command.
Use the REPORT RENAMING RULE command to display a list of all of the renaming rules and
their rule numbers.
Parameters
Related Commands
ADD RENAMING RULE
CHANGE NAME
MAP KEY POINTS
READ DESIGN
READ LIBRARY
-All Deletes all previously added renaming rules in one of the
following three categories:
I Map
I Module
I Pin
If you do not specify a category, Conformal deletes all
previously added renaming rules from the Map category.
rule_name Deletes the specied renaming rule.
-MAp Deletes map renaming rules. This is the default.
-MOdule Deletes module renaming rules.
-PIn Deletes pin renaming rules.
Command Reference
SET MAPPING METHOD
SET NAMING RULE
TEST RENAMING RULE
Command Reference
DELete REtention Mapping
<-All | <rule_name>>
(Setup / LEC Mode)
Deletes the state retention mapping rules added using the ADD REtention_register
Mapping command.
Note: Use the REPORT RETENTION MAPPING command to display a list of all the state
retention mapping rules. Note that the default rule added by the systemcan never be deleted.
CELLS on page 143.
Parameters
Related Commands
-All Deletes all the state retention register mapping rules added
using the ADD RETENTION MAPPING Mapping command.
This option does not delete the default rule added by the
system.
rule_name Deletes the specied state retention mapping rule.
Note: The default rule added by the system cannot be deleted.
Command Reference
DELETE SEARCH PATH
DELete SEarch Path
<-All | pathname>
[-Design | -Library]
(Setup Mode)
Deletes search paths Conformal uses for the READ DESIGN and READ LIBRARY commands.
Use the REPORT SEARCH PATH command to display a list of all search paths.
Parameters
Related Commands
ADD SEARCH PATH
READ DESIGN
READ LIBRARY
REPORT SEARCH PATH
-All Deletes all previously added search paths within the given
defaults.
pathname Deletes the specied search paths.
-Design Deletes search paths used by the READ DESIGN command.
-Library Deletes search paths used by the READ LIBRARY command.
-Golden Deletes search paths used by the Golden design or library.
-Revised Deletes search paths used by the Revised design or library.
Command Reference
DELETE TIED SIGNALS
DELete TIed Signals
<-All | name>
[-Net |-Pin]
[-Module <name>]
[-Class <Full | User | System>]
[-Golden |-Revised]
(Setup Mode)
Deletes specied tied signals from the Golden or Revised design.
Use the REPORT TIED SIGNALS command to display a list of all of the tied signals.
Parameters
Related Commands
ADD TIED SIGNALS
-All Deletes all tied signals within the given defaults.
name Deletes the specied tied signals.
-Net Species that the deleted tied signal is a net. This is the
default.
-Pin Species that the deleted tied signal is a pin.
-Module name Species the name of the module where the oating net or pin
resides.
-Class Deletes tied signals of this class.
Full Tied signals from both the User and System
classes. This is the default.
User Tied signals the user previously added with
the ADD TIED SIGNALS command.
System Tied signals from the original design.
-Golden Deletes tied signals from the Golden design. This is the
default.
-Revised Deletes tied signals from the Revised design.
Command Reference
REPORT TIED SIGNALS
Command Reference
DIAGNOSE
DIAgnose
< < gate_id | instance_pathname | pin_pathname>
[-Golden |-Revised][-SUPport]
[-NUm <integer>]
| -SUMmary [integer][-SOrt <SUpport | SIze>]
|[-NOneq]>
(LEC Mode)
Performs diagnosis on a specied compared point. Specify the compared point by its gate
identication number, instance path, or a pin path. Use this command to determine why the
software identied non-equivalence between compared points.
The diagnosis displays all of the non-corresponding support key points with a list of all likely
error candidates from the Revised design. The list organizes likelihood in descending order
with 1.00 being the greatest possible error candidate.
Use the REPORT ENVIRONMENT command to display the maximum diagnosis candidates
setting.
Parameters
gate_id Diagnoses the specied gate.
instance_pathname Diagnoses the specied instance path.
pin_pathname Diagnoses the specied pin path.
-Golden Diagnoses the Golden design. This is the default.
-Revised Diagnoses the Revised design.
-SUPport Displays the list of corresponding and non-corresponding
support points.
-NUm integer Lists the specied number of error candidates. By default,
Conformal lists all error candidates.
Command Reference
Examples
Related Commands
PROVE
REPORT COMPARE DATA
REPORT ENVIRONMENT
REPORT TEST VECTOR
-SUMmary integer Displays a table of the non-equivalent points with their
corresponding support size, non-corresponding support size,
and cone size.
The integer represents the number of nonequivalent points you
wish to display in the table. By default, Conformal displays
all nonequivalent points.
-SOrt Sorts the summary table results by one of the following.
SUpport Sorts by corresponding support size
SIze Sorts by cone size
-NOneq Diagnoses every nonequivalent point.
Command Reference
DOFILE
DOFile
< <filename> [-FORCE] | -SHOW_STACK>
(Setup / LEC Mode)
Executes a set of commands contained in a specied le. If there is an error while the
Conformal software is executing the dole script, it terminates the dole execution and returns
to the system mode prompt.
Use the SET DOFILE ABORT command to specify how you want the Conformal software to
respond when an error message occurs. You can choose to terminate, continue, or exit the
session.
Use the BREAK command in a dole script to terminate the dole script and return to the
system mode prompt.
Parameters
Related Commands
BREAK
CONTINUE
SET DOFILE ABORT
filename Species a le containing a set of commands the Conformal
software executes one at a time.
-FORCE Allows a dole to be executed multiple times, up to a limit of 16.
Without this option, you will get an error if you attempt to run a
dole multiple times.
-SHOW_STACK Species that if the current execution is stopped because of a
break in one or more doles, it will display the current dole
execution stack. For example:
1: dofile_2
break (line:2)
2: dofile_1
dofile dofile_2 (line:5)
Command Reference
ELABORATE DESIGN
ELAborate DEsign
[-ROot <module_name>]
[-ROOTConfig <configuration_name>]
[-PARAmeter [-INT | -STR | -ENUM] <name> <value>]
[-RAngeconstraint]
[-GOlden | -REvised]
(Setup Mode)
Completes the READ DESIGN command specied with the -noelaborate option. During
this step, modules are synthesized and the complete design hierarchy is created.
This command is typically used for mixed design ows where the Verilog modules and VHDL
entity or architectures are read in separately. Then they can be elaborated using this
command.
Parameters
-ROot <module_name> Species the root module to be elaborated. If this option is not
specied, the Conformal software automatically select a root
module.
-ROOTConfig <configuration_name>
Species that the design includes the specied conguration for
the top-level module.
Note: This option applies to only VHDL designs.
Use this option when the design includes multiple
congurations for the top-level module. When you use the
-rootconfig option, you must also use the -root
module_name option (above).
Command Reference
-PARAmeter [-INT | -STR | -ENUM] <name> <value>
Assigns design parameters or replace existing design
parameters. To specify multiple parameters, use the
-parameter option for each parameter you want to set. For
example:
read design filename -parameter parm1 value1 \
-parameter -int parm2 value2
This option applies to both Verilog and VHDL les. (Combine
with -root.)
When using the -parameter -int <name> <value>
command, the <value> will be converted to integer value,
which can be a positive integer (1), negative integer (-1), an
integer value recognized as a string ("1"/"-1"), or a Verilog
style integer ("16h0001"). When using a Verilog style integer,
the value must be specied between double-quotes (" ").
When using the -parameter -str <name> <value>
command, the <value> will be saved as a string.
When using the -parameter -enum <name> <value>
command, the <value> will be converted to a VHDL
enumeration literal. For example, the following command sets
the parameter P4 to VHDL enumeration literal GREEN:
read design -root mod1 filename \
-parameter -enum P4 GREEN
Note: Any value that is not recognized as an unsigned decimal
integer value is interpreted as string value.
Note: If -int or -str is not specied, then the parameter value
will be interpreted as an integer if it is not between
double-quotes (" "), and as a string if it is between
double-quotes. Therefore, if you want to specify a Verilog format
value, it must be between double-quotes and used with the -int
option.
-RAngeconstraint Applies range constraints during verication. If this option is not
specied, all range constraints are ignored.
-Golden Species to elaborate the Golden design. This is the default.
-Revised Species to elaborate the Revised design.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
Command Reference
EXIT
EXIt
[-Force]
(Setup / LEC Mode)
Ends the existing Conformal session and returns you to the operating system.
Exit Status Codes
On exiting, Conformal returns a status code. Anonzero status code means there is a potential
error; that is, either no comparison was done or unmapped, abort, or nonequivalent points
exist. The exit status code consists of ags that represent different conditions.
Saving GUI Settings
By default, Conformal does not automatically save GUI settings for future sessions. To save
your preferred settings, use the GUI exit window and click the Save GUI settings check box.
information about exit status codes and the procedure to save GUI settings.
Parameters
-Force Exits without conrmation.
Command Reference
FLATTEN
FLAtten
<-MODule <name> | -ALL>
[-Force | -NOForce]
(Setup Mode)
Removes all hierarchy on a specied module or for all modules in the database. If you do not
specify one or all modules, Conformal attens the root module by default. Thus, this
command expands all of the gate primitive or transistor primitive devices into the cell that is
being attened.
The following example illustrates the effects of this command:
A cell that is to be attened contains three cells. One cell has 25 gates and the other two are
the same, each with 33 gates. After attening, the cell now contains 0 cells and 91 gates (1 *
25 + 2 * 33 = 91).
Parameters
Related Command
RESOLVE
-MODule name Flattens the specied module. The default is to flatten the
root module.
-ALL Flattens all modules within the given defaults.
-Force Forces attening of specied modules in the Golden or Revised
design even if those modules have not been attened in the
complementing design. (For example, force attening for
Golden modules when the Revised have not been attened.)
-NOForce Does not force attening when those modules have not been
attened in the complementing design.
-Golden Flattens the specied module(s) from the Golden design. This
is the default.
-Revised Flattens the specied module(s) from the Revised design.
Command Reference
FORWARD
FORward
[integer]
(LEC Mode)
Reports fan-out gate information from the currently displayed atten gate information. The
fan-out gate you choose with this command becomes the current attened gate. Use this
command to trace gates in place of repeatedly using the REPORT GATE command.
Note: This command does not report gates at the design level.
Parameters
Related Commands
BACKWARD
REPORT GATE
integer Reports the specied fan-out gate. The value 1 denotes the rst
fan-out. The default is 1.
Command Reference
GENERATE ROM PRIMITIVE
GENerate ROm Primitive
<-SIM <outfile>>
<-CODE_FILE <codefilename>>
[-MOD <modulename>]
[-CODE_FILE_FORMAT [BIN | HEX]]
[-NO_ACCESS_OUT_LOW | -NO_ACCESS_OUT_HIGH]
(Setup Mode)
Generates a ROM primitive model that you can use to verify against a valid ROM circuit.
Conformal generates a ROM primitive that has the following interface:
I AddrAddress bus for accessing ROM data.
I DoutOutput data from ROM.
I REControl clock for the output latch or ip-op, when you set the -outstate option to
dlat or dff. When RE is high, ROM data is sampled.
I CKAddress decode clock for ROM read operations. ROM is read when the clock is
high.
This command reads in a code le that initializes the ROM. This code le should contain one
number per line, in binary format. The number of entries in the code le should match the
number of words in the memory. As Conformal reads the code le, it assigns each entry to a
successive word element in the memory.
The following illustrates sample contents for a code le called rom.code, which initializes a
4 X 4 ROM:
0000
1111
1010
0111
Note: To perform simulation, you must dene the macro SIM.
Parameters
-SIM <outfile> Species the output le for the ROM primitive.
-CODE_FILE <codefilename>
Command Reference
Related Command
READ ROM PRIMITIVE
Examples
The following command generates a ROM model with a code le called rom.code.
generate rom primitive -sim VROM.v -code_file rom.code -mod VROM /
-code_file_format bin -no_access_out_low
Species the code le that will initialize the ROM. This
code le should contain initialization data in binary format.
-MOD <modulename> Species the module name of the ROM primitive that is
created.
-CODE_FILE_FORMAT [BIN | HEX]
Species the output le format for the ROM primitive.
-NO_ACCESS_OUT_LOW Fills the memory address with 0 when it is not initialized.
-NO_ACCESS_OUT_HIGH Fills the memory address with 1 when it is not initialized.
Command Reference
GROUP
GROUP
<-Module <name> >
<-Instance <instance_name* > >
<-NEWModule <name> >
<-NEWInstance <name> >
[-net_to_pin_name]
(Setup Mode)
Groups dened instances together so that they become a new submodule. This command is
the opposite of the RESOLVE command; it applies to submodules, latches, registers, gates,
and transistors. By default, this command assigns unique and arbitrary submodule pin
names.
Wildcard: The wildcard (*) represents any zero or more characters in existing instance
names.
Parameters
Related Command
RESOLVE
-Module name Species a module for which to apply the grouping.
-Instance instance_name*
Species the instances to group. This accepts wildcards.
-NEWModule name Species the name of the new module.
-NEWInstance name Species the instance name for the new module.
-net_to_pin_name Species that the pin names of the new modules will be the
same as the nets connected to them, and not unique and
arbitrary.
-Golden Applies this command to modules and instances in the
-Revised Applies this command to modules and instances in the
Revised design.
Command Reference
HELP
HELp
[<command_name> | <message_name> | -message] [-Verbose]
[-NOSHOW_ERROR_ID | -SHOW_ERROR_ID]
[-NOSHOW_EXTENDED_HELP | -SHOW_EXTENDED_HELP]
[-COLOR | -NOCOLOR]
[-PAGE | -NOPAGE]
[<error_id>]
(Setup / LEC Mode)
Displays the Conformal commands and their command syntax. To display a group or set of
commands, use a keyword such as ADD, DELETE, REPORT, or SET.
While in the Tcl mode, the HELP command displays a list of all available Conformal Tcl mode
commands.
Parameters
<command_name> Displays the command syntax for a given command name. If
you do not specify a command name, the Conformal
Equivalence Checker displays all of the commands.
<message_name> Displays help for the corresponding rule check message.
-message Displays all rule check messages.
-Verbose Expands information about the command, including
descriptions of the parameters and related commands.
-NOSHOW_ERROR_ID Does not display the error ID. This is the default.
-SHOW_ERROR_ID Displays the error ID.
-NOSHOW_EXTENDED_HELP
Does not display the extended help. This is the default.
-SHOW_EXTENDED_HELP
Displays the extended help only. This does not include error
IDs.
-COLOR Displays the help text with color highlights. This is the default.
Note: This option has no effect if the terminal is not an xterm,
as determined by the environmental variable TERM, or when
running HELP in the GUI window.
Command Reference
Example
The following is an example of the Tcl mode system prompt and the HELP command:
TCL_SETUP> help set_current_module
Related Command
SEARCH
-NOCOLOR Disables the help text with color highlight display. Use this if the
text terminal does not support color.
-PAGE Displays the help text one screenful at a time. This is the
default. The output is paused for input after one screenful of
text is displayed, where you can continue by pressing the
following:
I spacebardisplays the next page
I h-keydisplays a complete list of options
I q-keyquits from the pager
Note: Output displayed with the pager is not saved to the log le
specied by SET LOG FILE command.
Note: The pager is not enabled if the help text is less than a
screenful, when output is redirected to a le, or when running
HELP in the GUI window.
-NOPAGE Disables the help text paging display feature.
<error_id> Displays the error message of the specied message ID.
Command Reference
INVERT MAPPED POINTS
INVert MApped Points
<gate_id | instance_pathname | pin_pathname>
[-Golden |-Revised]
(LEC Mode)
When switching the system from Setup mode to LEC mode, Conformal automatically maps
key points and places them in the System class of mapped points. Use this command to
invert the mapping phase for any mapped points. This command also places the points in the
User class of mapped points.
In the GUI Mapping Manager and in reports, a (-) sign represents an inverted-mapped point.
A (+) sign represents a non-inverted mapped point.
Parameters
Related Commands
ADD MAPPED POINTS
MAP KEY POINTS
gate_id Inverts the mapping phase for the specied gates (identied by
number).
instance_pathname Inverts the mapping phase for the specied instances.
pin_pathname Inverts the mapping phase for the specied pins.
-Golden Species that the point identier refers to the Golden design.
-Revised Species that the point identier refers to the Revised design.
Command Reference
SET MAPPING METHOD
SET NAMING RULE
Command Reference
LICENSE
LICense
[<license_string>]
(Setup / LEC Mode)
Displays information about the currently installed Conformal license. By default, this
command displays all available Conformal licenses.
Parameters
<license_string> Displays information for a specic license. You can select one of
the following:
I conformal_explorer
I conformal_asic
I conformal_ultra
I conformal_custom
I conformal_low_power
I conformal_low_power_gxl
I conformal_eco
I rtl_compiler_verification
Command Reference
MAP ECO PATCH
MAP ECo Patch
<filename>
[-NOConstraint]
[-REPlace]
(Setup Mode)
Maps the ECO patch(es), specied by the ADD ECO PATCH command, to the available ECO
cells.
The available ECO cells are specied by the ADD ECO CELL command. The target
technology libraries are specied by the ADD ECO LIBRARY command.
Parameters
Related Commands
ADD ECO CELL
ADD ECO LIBRARY
ADD ECO PATCH
OPTIMIZE PATCH
<filename> Species the le name for the mapped netlist.
-NOConstraint Species that the mapping process will use the cells in the ECO
library to implement the patch. Use this option for a pre-mask
ECO.
Command Reference
MAP KEY POINTS
MAP KEy Points
(LEC Mode)
Automatically maps all key points, then displays a summary of the mapped points in the
Golden and Revised designs. In addition, if there are any unmapped points, Conformal
displays a summary of the unmapped points in the Golden and Revised designs. Conformal
automatically executes this command the rst time you exit the Setup systemmode and when
the attened gate model changes.
Related Commands
ADD MAPPED POINTS
ADD RENAMING RULE
SET MAPPING METHOD
SET NAMING RULE
TEST RENAMING RULE
Command Reference
MOS2BUFIF
MOS2BUFIF
[-MODule mod1 mod2 modn | -ALL]
[-FORce | -DRIVENmos | -INStance ins1 ins2 insn]
(Setup Mode)
After abstraction for emulation and test support, this transforms all of the unidirectional NMOS
devices to BUFIF1 and unidirectional PMOS devices to BUFIF0.
Parameters
-MODule mod1 mod2 modn
Transforms the specied list of modules.
Note: If you do not specify modules, Conformal transforms the
current root module.
-ALL Transforms all modules.
-FORce Converts all [r]nmos to buf1, [r]pmos to buf0, [r]cmos to a
buf0 buf1 pair. This is the default.
-DRIVENmos Converts only those MOS devices that are driven by a logic
gate or a primary input.
-INStance ins1 ins2 insn
Transforms the specied instances. You can only use this option
when you have specied a single module. (Refer to the
-module denition.)
Note: The following options are mutually exclusive. That is, you
can only use one of these options in the command:
I -force
I -drivenmos
I -instance
Conformal issues a warning when the specied instances do
not exist or they are not unidirectional.
Command Reference
Example
Sample Netlist Transformation:
The following is the original netlist:
nmos (out, in, ctl) ;
pmos (out, in, ctl) ;
The MOS2BUFIF command transforms the netlist to the following:
bufif1 (out, in, ctl) ;
bufif0 (out, in, ctl) ;
Related Command
ABSTRACT LOGIC
-Golden Applies transformation in the Golden design. This is the
default.
-Revised Applies transformation in the Revised design.
Command Reference
MOVE INSTANCE DOWN
MOVe INstance Down
-MODule <module_name>
-From <from_instance>
-TO <to_instance_list>
(Setup Mode)
Moves instances in the same parent module.
Parameters
Species the parent module
-From <from_instance>
Species the instance that is to be moved.
-TO <to_instance>
Species the destination instance or list of instances.
-Golden Applies in the Golden design. This is the default.
-Revised Applies in the Revised design.
Command Reference
OPEN SCHEMATICS
OPEn SChematics
[full pathname]
(Setup / LEC Mode)
Opens the schematic viewer and displays the root module schematics. This command cannot
be used in the non-graphic mode.
Parameters
Related Commands
CLOSE SCHEMATICS
DIAGNOSE
REPORT GATE
-Golden Species that the path is in the Golden design.
-Revised Species that the path is in the Revised design.
full pathname Opens a schematic for the specied path.
Command Reference
OPTIMIZE PATCH
OPTimize PAtch
-WORKdir <working_directory>
-LIBrary <library_file_list>
[-RCExec <rc_executable>]
[-SDC <sdc_filename>]
[-VERbose]
[-KEEPHierarchy]
[-CLEANUP]
[-AVOID <cell_name>*]
[-USE <cell_name>*]
[-POSTLIBscript <script_name>]
[-POSTSYNscript <script_name>]
[-PRESYNscript <script_name]
[-NETnaming <format_string>]
[-INStancenaming <format_string>]
[-SEQuentialnaming <format_string>]
(Setup Mode)
Writes out an RTL Compiler script (run_rc.tcl) in the working directory that will optimize
the patches and execute the script.
After OPTIMIZE PATCH successfully completes, the ECO design will be in memory and can
be written out. The optimized patches will be in the working directory.
Important
Before running this command, you must run the APPLY PATCH -keephierarchy
command.
Parameters
-WORKdir <working_directory>
Species the name of the working directory for the optimized
patches.
-LIBrary <library_file_list>
Species the name of the library les.
If the library name contains a relative path, the path should be
relative to the directory declared in -workdir.
Command Reference
-RCExec <rc executable>
Species the path to the RTL Compiler executable. If this is not
specied, the software will use the rc command in your search
path.
-SDC <sdc_filename> Species the name of the SDC le.
If the SDC lename contains a relative path, the path should be
relative to the directory declared in -workdir.
-VERbose Outputs all RTL Compiler messages. By default, the command
only outputs error messages.
-KEEPHierarchy Species that the ECO changes will be put in a submodule.
-CLEANUP Deletes the generated les.
-AVOID <cell_name>* Avoids the specied library cells. This accepts wildcards.
-USE <cell_name>* Uses the specied library cells. This accepts wildcards.
Note: The order that you specify the -AVOID and -USE options
is signicant. For example:
-avoid * -use NAND2 INV2
avoids all the library cell types except NAND2 and INV2. If these
options are specied in the following order:
-use NAND2 INV2 -avoid *
then no cell types will be available for mapping.
-POSTLIBscript <script_name>
Species the script to run after reading in the libraries.
-POSTSYNscript <script_name>
Species the script to run after each patch is synthesized.
-PRESYNscript <script_name>
Species the script to run before each patch is synthesized.
-NETnaming <format_string>
Species the net naming format of the ECO nets. For example,
for eco_net_%d, the %d will be an integer that makes the net
name unique.
Command Reference
Example
The following script reads in the original netlist and patch, then runs OPTIMIZE PATCH to
map and optimize the ECO changes:
read library typical.lib -liberty
read design top.gv patch1.v
apply patch mod1 mod1_eco -keephierarchy
optimize patch -workdir rc_work -library ../typical.lib
write design top.eco.gv -replace
Related Commands
APPLY PATCH
-INStancenaming <format_string>
Species the instance naming format of the ECO combinational
cells. For example, for eco_instance_%d, the %d will be an
integer that makes the instance name unique.
-SEQuentialnaming <format_string>
Species the instance naming format of the ECO registers and
latches. For example, eco_%s, where %s is the original register
name.
Command Reference
PIN GROUP
PIN GRoup
[-DEScend | -ASCend]
[-ADDEXPression <string> <string>]
[-ADDList <name>[#:#] "<net> <net> ..."]
[-ALL | -Module "<name> <name> ..."]
(Setup Mode)
Combines a group of single nets or pins into a bus. The Conformal software uses the following
two default patterns to group pins or nets into busses:
I Name[#]
I Name<#>
For example, nets blb[3] blb[4] blb[5] will be grouped into bus blb[5:3], and pins
wladd<1> wladd<2> wladd<3> will be grouped into bus wladd[3:1].
Parameters
-DEScend Denes the bus in descending numerical order. This is the
default.
-ASCend Denes the bus in ascending numerical order.
-ADDEXPression <string> <string>
Command Reference
Related Command
GROUP
Species expression(s) for rules on signals to bus. You can
specify your own renaming mapping of specic names to two
default patterns, so that it recognizes those names as buses also.
For example:
-ADDexpression "mybus_%d_bar" "mybus_bar[@1]"
maps the following names into the rst default bus name:
mybus_12_bar mybus_13_bar mybus_14_bar => mybus_bar[12]
mybus_bar[13] mybus_bar[14]
then the renamed names will be further grouped into bus
mybus_bar[14:12]
The renaming mapping syntax:
mybus_%d_bar" "mybus_bar[@1]"
is dened in the ADD RENAMING RULE command.
-AddList <name>[#:#] <net> <net>
Allows you to bus random signals. These nets can be single nets
or mixed single nets and complete busses. The number of nets
dened must be equal to the bus range. If a bus range more than
the number of nets is dened a "-" character is used as a
placeholder for that bit position.
-ALL Species that when pins of a module are converted to a bus, all
instantiations of that module need to be updated. This is the
default.
-Module <name> <name>
Species the module that needs to be updated pins of that
module are converted to a bus.
Command Reference
PRINTENV
PRINTENV
[<variable>]
(Setup / LEC Mode)
Displays environment variable values.
Parameters
Related Command
SETENV
<variable> Prints the value of the specied variable. If you do not specify a
variable, this command displays the value of every environment
variable.
Command Reference
PROVE
PROve
<[-Golden | -Revised] identifier>
<-ONe |-ZEro | [-Revised | -Golden] identifier>
[-NOInvert | -Invert | -Both]
(LEC Mode)
Starts a process that shows whether the specied gates are equivalent or nonequivalent. The
proof process checks equivalency for one of the following pairs:
I One gate in each of the Golden and Revised designs
I Two gates in the Golden design
I Two gates in the Revised design.
Use the ADD DYNAMIC CONSTRAINTS command to specify constraints you want to use
during this proof process.
Parameters
-Golden Species that the rst prove point is in the Golden design. This
is the default.
-Revised Species that the rst prove point is in the Revised design.
identifier Uses this gate fromthe specied design as the rst prove point.
The identifier will be one of the following:
I Gate identication number
I Instance path
I Pin path
-ONe Proves whether the specied gate is equal to a one value.
-ZEro Proves whether the specied gate is equal to a zero value.
-Revised Species that the second prove point is in the Revised design.
-Golden Species that the second prove point is in the Golden design.
Command Reference
Examples
Related Commands
DIAGNOSE
REPORT COMPARE DATA
-NOInvert Proves for equivalence. This is the default.
-Invert Proves for inverted equivalence.
-Both Proves for either non inverted or inverted equivalence.
Command Reference
READ CPF
REAd CPf
<filename.cpf ...>
[-GOLden | -REVised | -BOTH]
[-VERbose]
(Setup Mode)
Reads in the Common Power Format (CPF) les.
Cadence recommends reading in all the CPF les at once with this command. Any susequent
runs will replace all the low power information issued by the previous READ CPF command.
All READ DESIGN and READ LIBRARY commands should be run before running this
command.
Parameters
Example
The following command reads the lib.cpf and design.cpf les and checks that they are
specied correctly:
read cpf lib.cpf design.cpf
Related Commands
COMMIT CPF
REPORT CPF LOGIC
<filename.cpf ...> Species the name of the Common Power Format le(s).
-GOLden Reads in the CPF les for the Golden design. This is the
default.
-REVised Reads in the CPF les for the Revised design.
-BOTH Reads in the CPF les for both the Golden and Revised
designs.
-VERBose Displays additional messages during execution.
Command Reference
READ DESIGN
REAd DEsign
<filename>
[-ROot <module_name>]
[-CONFiguration | -NOCONFiguration]
[-ROOTConfig <configuration_name>]
[-VErilog | -VERILOG2K | -SYStemverilog
| -VHdl [93 | 87] | -SPice | -Ndl | -EDIF
|-LIBErty]
[-File <command_filename>]
[ | -REPlace | -APPend]
[-Define <name>]
[-Map <library_name> <library_path>]
[-MAPRecursive <library_name> <library_path>]
[-MAPFile <library_name> <filename>]
[-LIBRary <library_name> <library_path>]
(this option is the same as -Map)
[-STATEtable | -NOSTATEtable]
[-BBOXUNResolve]
[-BLAST_inst_port]
[-RAngeconstraint | -NORAngeconstraint]
[-INITial_value]
[-VHDLESCaped_to_verilog]
[-CONTINUOUSASSIGNment <BIdirectional | UNIdirectional>]
[-NOZPUSHing | -ZPUSHing]
[-ENUMConstraint]
[-VMEM_LIB]
[-VMEM_ULTRA]
[-SUPPLY | -NOSUPPLY]
[-UNCompress <zip_file_name>]
[-UNZip <zip_file_name ...>]
[-PARAmeter [-INT | -STR | -ENUM] <name> <value>]
(combined with -ROot option)
[-ARchitecture <architecture_name>]
[-FUnctiondefault [0 | 1 | x]]
[-NOKeep_unreach | -Keep_unreach]
[-SEnsitive | -NOSEnsitive]
[-NOELaborate]
[-EXClude <exclude_file_name*>]
[-VERBose]
[-OPTimize | -NOOPTimize]
[-LAstmod]
[-MErge BBox]
[-Golden | -REVised]
(Setup Mode)
Command Reference
Reads in the Golden and Revised designs.
Important
Review these important reminders before using the READ DESIGN command:
I Use the SET NAMING RULE command rst if you intend to read in an RTL design that
requires specic naming conventions.
I Use the SET UNDEFINED CELL command before the READ DESIGN command if your
design includes undened cells that should be treated as blackboxes.
Note:
I If your design includes duplicate modules, Conformal uses the rst module and ignores
later ones. However, you can use the -lastmod option to specify that Conformal use the
last module and ignore the earlier ones.
I Use the tilde character (~) to shorten the path of the le.
I Use the backslash character (\) at the end of a line to show that the command you are
entering continues on the next line.
Supported Options
The following Verilog and VHDL considerations are offered:
I Use the -file option with a Verilog Command le list. However, only the -v, -y,
+incdir, +libext, and +define options are supported. Additionally, use the -yd
option to treat library modules as design modules.
I The VHDL option supports all VHDL constructs and all standard and IEEE packages,
including synthesis packages. It has an elaboration engine and RTL logic generation that
support most RTL VHDL synthesis subset constructs (see below for details). For most
non-synthesizable VHDL constructs, Conformal displays warning messages.
VHDL and Verilog 2001 Library Mapping
You can specify how VHDL and Verilog 2001 libraries are mapped using the READ DESIGN
commands -map, -mapfile, or -library options.
The -map and -library options work the same in that they map logical library names to
physical directories. You can use multiple -map commands to map multiple physical
directories to one logical library. Use the -mapfile option for more specic library mapping,
Command Reference
such as specifying that a list of les must be compiled into a specied library. If you read in a
le without specifying its library mapping, that le is stored in a default library called work.
Note: You can map a le into more than one library. In this case, the le is stored in each
library for which it is mapped.
See the VHDL Support and Verilog Support appendices in the Encounter Conformal
Equivalence Checking User Guide for additional information, including examples on
library mapping.
Parameters
<filename> Reads in the specied le. (Required.)
-ROot module_name The specied module is the top root module.
-CONFiguration Supports VHDL conguration constructs. This is the default.
-NOCONFiguration Does not interpret VHDL conguration.
-ROOTConfig <configuration_name>
The design includes the specied conguration for the
top-level module.
Note: This option applies to only VHDL designs.
Use this option when the design includes multiple
congurations for the top-level module. When you use the
-rootconfig option, you must also use the -root
module_name option (above).
-VErilog Species that this design is a Verilog design. (Use this option
for Verilog designs that comply with IEEE 1364-1995.) This is
the default.
-VERILOG2K Species that this design is a Verilog2K design (Use this
option for Verilog designs that comply with IEEE 1365-2001).
-SYStemverilog Species that this design is a SystemVerilog design.
-VHdl Species that this design is written in VHDL with the specied
standard:
93 VHDL-93 (Use this option for VHDL
designs that comply with IEEE Std
1076-1993.) This is the default.
Command Reference
87 VHDL-87 (Use this option for VHDL
designs that comply with IEEE Std
1076-1987.)
Note: The Conformal software supports multiple uses the
-vhdl 93 and -vhdl 87 options. See the example.
-SPice Species that the design is a SPICE netlist design.
-Ndl Species that the design is an NDL design.
-EDIF Species that the design is an EDIF design.
-LIBErty Species that the design has a Liberty library format type.
(Use this option to qualify the library as Liberty.)
-File <command_filename>
Reads in the specied command le as a design.
Note: This option is for Verilog or VHDL command le lists.
The options for <command_filename> are described in
Table 2-1 on page 244 for Verilog and Table 2-2 on page 245
for VHDL.
-REPlace Removes all designs that were previously read in, and
replaces them with the specied design.
-APPend Appends the design to the one that was previously read.
For example, you can use this option to x a top module and
then read it in again without parsing the entire design le
again:
read design top.v -append -lastmod
Note: The top module cannot pass parameters to modules
that are read in previously.
-Define <name> Denes ìfdef variable names in Verilog.
-Map <library_name> <library_path>
Reads in les for the specied <library_name> from
<library_path>.
Use this option to read in all of the VHDL or Verilog les in the
specied library path for the given library name. You can also
map multiple directories to a single library. For example:
read design -vhdl top.vhd -map mylib /design/path1 \
-map mylib /design/path2
Command Reference
-MAPRecursive <library_name> <library_path>
This option has the same function as -Map, but it searches for
all VHDL or Verilog les recursively down to the subdirectories
of the <library_path>.
-Map searches VHDL or Verilog les under the
<library_path> and will not search any VHDL les under
the subdirectories of <library_path>.
-MAPFile <library_name> <file_name >
Reads in the specied <file_name > and includes themin
the <library_name>.
Use this option to specify the les that belong to a given
library. The le list terminates with the next option or the end
of the READ DESIGN command.
You can also use multiple -mapfile options to specify
multiple les in a library.
For example, the following two commands are the same:
read design -vhdl top.vhd -mapfile \
mylib x1.vhd -mapfile mylib x2.vhd
read design -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd
-LIBRary <library_name> <library_path>
Reads in the specied le in the given library and path for
user-dened VHDL libraries. (This option is the same as
-map.)
-STATEtable Enables support for Synopsys Liberty state tables. This is
the default.
Note: This option supersedes the SET STATETABLE
command.
-NOSTATEtable Disables support for Synopsys Liberty state tables.
-BBOXUNResolve Species that unresolved semantics as unsupported
constructs (in VHDL) will be blackboxed instead of erroring
out.
Command Reference
-BLAST_inst_port Allows the cell model to have a bus pin while the instantiation
is bit-blasted.
By default, instantiations that contain bit-blasted connections
are errored out. The Verilog standard does not allow these
connections.
-RAngeconstraint When a variable is of type integer with a value range, a value
check is made against the range. If a value is out of range, it
will be interpreted as dont care. This is the default.
For example:
variable v : integer range 3 to 5;
With -RAngeconstraint, v will be interpreted as:
((v>=3 && v<=5)? v : 3bx).
Note: This option applies only to VHDL designs.
-NORAngeconstraint Species that no value check is made against the integer
value range.
-INITial_value Species that the variables initial value will not be ignored.
-VHDLESCaped_to_verilog
Species that if the content between \ pairs does not contain
any white space, the new name is the escaped content.
For example, \A_B_C_\ changes to \A_B_C_. In all other
cases, the VHDL escaped name is unchanged. For example,
\1 2\ is unchanged.
-CONTINUOUSASSIGNment <BIdirectional | UNIdirectional>
Species that continuous assignment in the design should be
interpreted as uni-directional or bi-directional assignment.
-NOZPUSHing Does not pushes tristate toward module output. This is the
default.
-ZPUSHing Pushes tristate toward module output.
Command Reference
-ENUMConstraint When a variable is of type of enumeration, a value check is
made against the enumeration range. If a value is out of
range, it will be interpreted as dont care. For example:
variable v : day;
Where day is an enumeration of {sun, mon, tue}
With -ENumconstraint, v will be interpreted as:
((v>=sun && v<=tue)? v : 2bx).
-VMEM_LIB Reads in the RTL model containing the Conformal Memory
Primitive.
This option is a Conformal Custom option.
Note: Without the -vmem_lib option, Conformal does not
recognize the Conformal Memory Primitive.
-VMEM_ULTRA Reads in the RTL model containing the Conformal Memory
Primitive for checking by Conformal Ultra. To use this option,
you must have a Conformal Ultra license.
This option is a Conformal Ultra option.
Note: When you use this option, no debugging is allowed. Use
the -vmem_lib option for memory verication.
-SUPPLY Keeps all Verilog supply0 and supply1 type nets
unchanged. This is the default.
-NOSUPPLY Converts the Verilog supply0 and supply1 type nets to
Verilog wire type nets.
Command Reference
-UNCompress <zip_file_name>
Reads in the specied compressed le. By default, the
Conformal software uses gunzip to unzip the le into the /tmp
directory.
You can control the tool and directory used with UNIX
variables CONFORMAL_UNCOMPRESS and CONFORMAL_TMP.
-UNZip <zip_file_name ...>
This option has the same function as -UNCompress except
that it can include a list of lenames. For example:
read design fileABC -UNZ zip1 zip2 zip3
The list of lenames end when a subsequent option is
specied, or if it is at the end of the command line.
Note: Specifying -uncompress or -unzip is optional for
gunzipped les because the Conformal software can
automatically recognize this le type.
Command Reference
-PARAmeter [-INT | -STR | -ENUM] <name> <value>
Assigns design parameters or replace existing design
parameters. To specify multiple parameters, use the
-parameter option for each parameter you want to set. For
example:
read design filename -parameter parm1 value1 \
-parameter -int parm2 value2
This option applies to both Verilog and VHDL les. (Combine
with -root.)
When using the -parameter -int <name> <value>
command, the <value> will be converted to integer value,
which can be a positive integer (1), negative integer (-1), an
integer value recognized as a string ("1"/"-1"), or a Verilog
style integer ("16h0001"). When using a Verilog style
integer, the value must be specied between double-quotes ("
").
When using the -parameter -str <name> <value>
command, the <value> will be saved as a string.
When using the -parameter -enum <name> <value>
command, the <value> will be converted to a VHDL
enumeration literal. For example, the following command sets
the parameter P4 to VHDL enumeration literal GREEN:
read design -root mod1 filename \
-parameter -enum P4 GREEN
Note: Any value that is not recognized as an unsigned decimal
integer value is interpreted as string value.
Note: If -int or -str is not specied, then the parameter
value will be interpreted as an integer if it is not between
double-quotes (" "), and as a string if it is between
double-quotes. Therefore, if you want to specify a Verilog
format value, it must be between double-quotes and used with
the -int option.
Command Reference
-ARchitecture architecture_name
Reads in les with the specied architecture.
Use this option when multiple architectures of the same root
design are compiled.
This option is associated with the -configuration option,
otherwise only one architecture is kept for each entity.
-FUnctiondefault Species the default return value for unspecied or
incompletely specied functions.
0 Returns zero.
1 Returns one.
x Returns x.
-NOKeep_unreach Remove any unreachable DFF or D-Latch in a module during
RTL synthesis. This is the default.
-Keep_unreach Keeps any unreachable DFF or D-Latch in a module during
RTL synthesis.
-SEnsitive Species that the design is case sensitive. This is the
default.
-NOSEnsitive Species that the design is not case sensitive.
-NOELaborate Reads in multiple les of different languages.
-EXClude <exclude_file_name*>
Species les to exclude when reading in the design. This
accepts the wildcard.
Note: You cannot use multiple wildcards with this option.
-VERBose Displays the verbose messages of parsing and translating
each design module.
-OPTimize Optimizes redundant logic (in library cells) that can affect the
way Conformal interprets the design. This is the default.
Note: Using this option does not always optimize all redundant
logic.
See the following example:
read design file1 file2 file3 -nooptimize \
-optimize -nooptimize -replace
Command Reference
Table 2-1 Supported Verilog Command-Line Options
The following table lists the Verilog command options that Conformal supports.
-NOOPTimize Preserves redundant logic in Library cells.
See the example listed above (-optimize).
-LAstmod If duplicate modules exist, the Conformal software uses the
rst module and ignores the later ones by default. Use this
option to specify that Conformal use the last module and
ignore earlier ones.
-MErge BBox Replaces all blackboxed modules in the design space with
modules in the library space.
-Golden Designates this design Golden. This is the default.
-REVised Designates this design Revised.
Supported:
<file> (Design data le) A list of the design les.
-v <file> (Library le) A list of library les.
-y <directory> (Library directory) A list of library directories.
Conformal searches for modules
not dened in the design les.
Conformal reads in these modules
as library modules.
+incdir+<dirname> (Include directories) A list of include directories
containing design les.
This option is similar to the ADD
SEARCH PATH command.
+libext+<extension>
(Library extensions) A list of library extensions you can

include when using the -y option.
The default is .v.
+define+<name> (Dene macros) A list of macro names you can
include in the `define statement
Command Reference
Table 2-2 Supported VHDL Command-Line Options
The following table lists the VHDL command options that Conformal supports.
Examples
The following example demonstrates how to use the backslash character to show that your
command continues on the next line.
read design tran1.spi tran2.spi tran3.spi \
-spice -revised
In the following example, only ent2.vhdl and arch2.vhdl will be parsed according to
VHDL 87 syntax rules. All the other les will be parsed according to VHDL 93 syntax rules.
read design ent0.vhdl arch0.vhdl \
-vhdl 93 ent1.vhdl arch1.vhdl \
-vhdl 87 ent2.vhdl arch2.vhdl \
-vhdl ent3.vhdl arch3.vhdl
Related Commands
-yd <directory> (Design directory) A list of directories.
Conformal searches for modules
that are not dened in the design
les.
Conformal reads these modules in
as design modules.
-f <file> (another command le)
Supported:
<file> Individual design le
-map <libname> <dirname> Map logical library name to a directory
-mapfile <libname> <filename ...> Map logical library name to a list of les
-library <libname> <dirname> Map logical library name to a directory
Command Reference
ADD RENAMING RULE
ADD SEARCH PATH
DELETE SEARCH PATH
READ LIBRARY
REPORT DESIGN DATA
REPORT MESSAGES
REPORT MODULES
REPORT RULE CHECK
REPORT SEARCH PATH
SET DIRECTIVE
SET NAMING RULE
SET ROOT MODULE
SET RULE HANDLING
SET STATETABLE
SET UNDEFINED CELL
WRITE DESIGN
Command Reference
READ FSM ENCODING
REAd FSm Encoding
<filename>
(Setup Mode)
Directs Conformal to read in a le that denes new Finite State Machine (FSM) encoding.
By default, Conformal reads binary encoding when building an FSM. Therefore, if your gate
netlist uses different encoding (for example, one-hot), you must use the READ FSM
ENCODING command to specify the correct encoding. See the example of an FSM encoding
le below.
Parameters
Examples
The following example shows the need for the READ FSM ENCODING command. In this case,
the user was alerted to encoding differences during mapping. The Golden design showed two
registers, while the Revised showed four registers. The following is an example of an FSM
encoding le that replaces the binary encoding with one-hot encoding:
.fromstates current_state_reg[1] current_state_reg[0]
.tostates current_state_reg[3] current_state_reg[2] current_state_reg[1]
current_state_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end
In this example, between .begin and .end:
I .fromstates are the left-hand side states
<filename> Reads in the specied le. This option is a required lename
that contains the encoding differences.
-Golden Uses this library with the Golden design. This is the default.
-Revised Uses this library with the Revised design.
Command Reference
I .tostates are the right-hand side states
Command Reference
READ LEF FILE
REAd LEf File
<filename>
(Setup Mode)
Reads in the LEF le. For each cell in the LEF database with matching library cell, this
command will do the following:
I Report library cell with ports that are not in the LEF le
I Report non-power or ground ports in the LEF le and not in library
I Add all ports in the LEF le, and not in library to library cell
Parameters
<filename> Species the name of the LEF le.
-Golden Reads in the LEF le for the Golden design. This is the
default.
-Revised Reads in the LEF le for the Revised design.
Command Reference
READ LIBRARY
REAd LIbrary
<filename*>
[-VErilog | -VERILOG2K | -SYStemverilog | -VHdl [93|87] | -Liberty]
[-EXtract]
[ | -REPlace | -APPend]
[-Define <name>]
[-Map <library_name> <library_path>]
[-MAPRecursive <library_name> <library_path>]
[-MAPFile <library_name> <filename ...>]
[-CONFiguration | -NOCONFiguration]
[-VERBose]
[-SUPPLY | -NOSUPPLY]
[-UNCompress <zip_file_name>]
[-UNZip <zip_file_name ...>]
[-OPTimize | -NOOPTimize]
[-STATEtable | -NOSTATEtable]
[-LAstmod]
[-MULTIPLE_LIBraries]
[-NOShare]
[-NOELaborate]
[-EXClude <exclude_file_name*>]
(Setup Mode)
Reads in the library model descriptions for Verilog, VHDL, or Liberty designs. The library is
either a Verilog simulation library or a Synopsys Liberty library. It is read for the Golden,
Revised, or both designs.
Note: For RTL to gate formal equivalence checking, use simulation libraries instead of
synthesis libraries because design verication signoff happens for simulation librariesnot
for synthesis libraries.
The READ LIBRARY command must be used before the READ DESIGN command if the
design is Verilog, VHDL, or Liberty.
Note: Library in this context refers to the technology library, such as ASIC cell and memory
denitions. See READ DESIGN for information on reading VHDL libraries and packages.
Important
I If there are duplicate modules, the Conformal software uses the rst module and ignores
later ones. However, you can use the -lastmod option to specify that Conformal use the
last module and ignore earlier ones.
Command Reference
I Use the backslash character (\) at the end of a line to show that the command you are
entering continues on the next line.
I Use the tilde character (~) to shorten the path of the le.
Parameters
<filename* ...> Reads in the specied le(s). This option is a required lename
that contains the Verilog simulation library or the Synopsys
Liberty library. This accepts wildcards.
-VErilog Contains the Verilog library model descriptions. This is the
default.
Note: This supports NC-Protect and Cadence encryption.
-VERILOG2K Contains Verilog2k library model descriptions.
-SYStemverilog Contains SystemVerilog library model descriptions.
-VHdl Species that the library is written in VHDL. The VHDL le is of
the specied standard:
93 VHDL-93 (Use this option for VHDL designs
that comply with IEEE Std 1076-1993.) This
is the default.
87 VHDL-87 (Use this option for VHDL designs
that comply with IEEE Std 1076-1987.)
Note: The VITAL format is unsupported.
Note: This supports NC-Protect and Cadence encryption.
-Liberty Species that the library lename is in the Synopsys Liberty
format.
Note: This supports Cadence encryption.
-SEnsitive Species that the library models descriptions are case
sensitive. This is the default.
-NOSEnsitive This library models descriptions are not case sensitive.
-EXtract Abstracts the gate information from any transistor library
models.
Note: This option requires a Conformal Custom license.
-REPlace Replaces the existing library. The designs are also deleted.
Command Reference
-APPend Appends this library to the one that was previously read.
For example, you can use this option to x a top module and
then read it in again without parsing the entire library le again:
read library top.v -append -lastmod
Note: The top module cannot pass parameters to modules that
are read in previously.
-Define <name> Denes ìfdef variable names in Verilog.
-Map <library_name> <library_path>
Reads in les for the specied library_name from
library_path.
Use this option to read in all of the VHDL or Verilog les in the
specied library path for the given library name. You can also
map multiple directories to a single library. For example:
read library -vhdl top.vhd -map mylib /design/path1 \
-map mylib /design/path2
-MAPRecursive <library_name> <library_path>
This option has same function as -Map, but it searches for all
VHDL or Verilog les recursively down to the subdirectories of
the <library_path>.
-Map searches VHDL or Verilog les under the
<library_path> and will not search any VHDL or Verilog
les under the subdirectories of <library_path>.
-MAPFile <library_name> <file_name >
Reads in the specied les (file_name) and include themin
the library (library_name).
Use this option to specify the les that belong to a given library.
The le list terminates with the next option or the end of the
READ LIBRARY command.
You can also use multiple -mapfile options to specify multiple
les in a library.
For example, the following two commands are the same:
read library -vhdl top.vhd -mapfile
\ mylib x1.vhd -mapfile mylib x2.vhd
read library -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd
-CONFiguration Supports VHDL conguration constructs. This is the default.
Command Reference
-NOCONFiguration Does not interpret VHDL conguration.
-VERBose Displays the verbose messages of parsing and translating each
library module.
-SUPPLY Keeps all Verilog supply0 and supply1 type nets unchanged.
-NOSUPPLY Converts the Verilog supply0 and supply1 type nets to
Verilog wire type nets.
-UNCompress <zip_file_name>
Reads in the specied compressed le. By default, the
Conformal software uses gunzip to unzip the le into the /tmp
directory.
You can control the tool and directory used with UNIX variables
CONFORMAL_UNCOMPRESS and CONFORMAL_TMP.
-UNZip <zip_file_name ...>
This option has the same function as -UNCompress except
that it can include a list of lenames. For example:
read design fileABC -UNZ zip1 zip2 zip3
The list of lenames end when a subsequent option is
specied, or if it is at the end of the command line.
Note: Specifying -uncompress or -unzip is optional for
gunzipped les because the Conformal software can
automatically recognize this le type.
-OPTimize Removes redundant buffers in library cells. This is the default.
Note: Using this option does not always optimize all redundant
logic.
See the following example:
read library file1 file2 file3 -nooptimize -optimize \
-nooptimize -replace
-NOOPTimize Preserves redundant buffers in library cells.
See the example listed above (-optimize).
Command Reference
-STATEtable Enables support for Synopsys Liberty state tables. This is the
default.
Note: This option supersedes the SET STATETABLE
command.
-NOSTATEtable Disables support for Synopsys Liberty state tables.
-LAstmod If duplicate modules exist, Conformal uses the rst module and
ignores the later ones by default. Use this option to specify that
Conformal use the last module and ignore earlier ones.
-MULTIPLE_LIBraries If duplicate modules exist, Conformal uses the rst modules
and ignores the later ones by default. Use this option to specify
that Conformal store duplicated liberty modules if they are in a
different library.
-Both Uses this library for both the Golden and Revised designs. This
is the default.
-Golden Uses this library with the Golden design.
-Revised Uses this library with the Revised design.
-NOShare Does not share the library les for both the Golden and Revised
designs, and appends the library les to both designs.
When this option is used together with the default -Both
option, this is the equivalent of running the following two
commands:
read library -golden <filenames>
read library -revised <filenames>
By default, the Conformal software shares the library les for
both the Golden and Revised designs, and does not append the
library les to either design.
-NOELaborate Reads in multiple les of different languages. With this option,
you can defer the binding of entity or module instantiations.
This is for cases when you have mixed library les in VHDL and
Verilog languages, where a VHDL entity in one library le
instantiates a Verilog module, and a Verilog module in another
library le instantiates a VHDL entity.
Command Reference
Related Commands
ADD RENAMING RULE
ADD SEARCH PATH
DELETE SEARCH PATH
READ DESIGN
REPORT DESIGN DATA
REPORT MESSAGES
REPORT MODULES
REPORT RULE CHECK
REPORT SEARCH PATH
SET DIRECTIVE
SET RULE HANDLING
SET STATETABLE
SET UNDEFINED CELL
-EXClude <exclude_file_name*>
Species les to exclude when reading in the library. This
accepts the wildcard.
Note: You cannot use multiple wildcards with this option.
Command Reference
WRITE LIBRARY
Command Reference
READ MAPPED POINTS
REAd MApped Points
<filename>
[-GOLDen_prefix <string>]
[-REVIsed_prefix <string>]
[-EXACT_name]
(LEC Mode)
Reads in the mapped point information you created with the WRITE MAPPED POINTS
command. By default, Conformal automatically maps key points during the transition from
Setup to LEC mode. And if the key points are already mapped, Conformal ignores any
mapped point information in the le. Thus, to prevent Conformal fromautomatically mapping
key points during the transition from Setup to LEC mode and enable Conformal to read in
mapped point information completely from the le, do one of the following:
I Use the set flatten model -nomap command before you set the system mode to
LEC.
I Use the set system mode lec -nomap command to suppress automatic mapping
during the transition to LEC mode.
Use the tilde character (~) to shorten the les path.
Note: Use the Golden and Revised prex options to specify the hierarchy of the instance
name. If a hierarchical submodules map point information is written to a le, it can be read in
at a higher level module or the top root module with the specied hierarchical prex string.
Parameters
<filename> Reads mapped point information from the specied le.
-GOLDen_prefix string
Appends this Golden prex string to the instance names.
This option lets Conformal read the mapped point le for a
higher-level module containing hierarchy.
-REVIsed_prefix string
Appends this revised prex string to the instance names.
This option lets Conformal read the mapped point le for a
higher-level module containing hierarchy.
Command Reference
Related Commands
SET FLATTEN MODEL
WRITE MAPPED POINTS
-EXACT_name Species an exact match for the names specied in the le.
This can help speed up the process of reading les where many
names are incorrect.
Command Reference
READ MEMORY PRIMITIVE
REAd MEmory Primitive
<filename1 filename2>
(Setup Mode)
Reads in Verilog memory primitive simulation models that were created using the Conformal
memory primitive generator. This command creates a memory-friendly, synthesized viewthat
you can use for comparison with a memory circuit.
Important
Read in designs that use the memory primitive after you use this command.
Parameters
Related Command
READ DESIGN
<filename1 filename2...> Species the les to read in.
Command Reference
READ ROM PRIMITIVE
REAd ROm Primitive
<filename>
[-CODE_FILE <codefilename>]
[-CODE_FILE_FORMAT <BIN | HEX>]
(Setup Mode)
Reads in Verilog ROM primitive simulation models that were created using the Conformal
ROM primitive generator.
Parameters
Related Command
READ DESIGN
<filename> Species the le to read in.
-CODE_FILE <codefilename>
Species the code le that will initialize the ROM.
-CODE_FILE_FORMAT <BIN | HEX>
Species the format of the code le.
If you do not specify the -code_file_format option, the
software uses the format selected during primitive
generation.
Command Reference
READ RULE CHECK
REAd RUle Check
<filename> <-EXClude |-INClude>
[-Design | -Library]
(Setup Mode)
Performs incremental rule checks. The rst time you run a session, write the rule violations
into a rule le using the write rule check <filename> -golden (or
-revised) command. For later runs, exclude the violations already agged with the read
rule check -exclude <filename> command.
Use the tilde character (~) to shorten the path of the le.
Parameters
<filename> Species the name of the le that contains rule violations from
a previous session.
-EXClude Excludes checks for violations noted in the specied le.This
option works as a lter; therefore, use it after the READ
DESIGN command.
-INClude Includes checks for violations noted in the specied le. This
option lets you reinstate violations that were previously
excluded.
-DEsign Reads only design rule check violations. If you do not specify
-design or -library, Conformal reads rule check violations
from both designs and libraries.
-LIbrary Reads only library rule check violations. If you do not specify
-design or -library, Conformal reads rule check violations
-Golden Applies this command to the Golden design. This is the
default.
-Revised Applies this command to the Revised design.
Command Reference
Examples
In the following example, the second report rule check will not report any rules.
read design g.v -golden
read design r.v -revised
write rule check rule.g -golden -replace
write rule check rule.r -revised -replace
read design g.v -golden -replace
read design r.v -revised -replace
report rule check -verbose -both
read rule check rule.g -exclude -golden
read rule check rule.r -exclude -revised
Related Command
WRITE RULE CHECK
Command Reference
READ PATTERN
REAd PAttern
<filename>
[-Verilog | -SPice ]
[-LAstmod]
(Setup Mode)
Reads in the transistor description from a le that Conformal Custom applies to the Golden
and Revised designs. (The le format type is either Verilog or SPICE.)
The transistor description represents a pattern that Conformal Custom seeks during
abstraction. When Conformal Custom detects a pattern, it substitutes a user-specied
functional model. Before this command can be executed correctly, you must provide the
user-specied functional model using the READ LIBRARY command. The transistor
description le and functional model have the same module and port names; port direction
can be different, but, neither the transistor description le nor the library database can contain
submodulesevery cell must be at.
Parameters
<filename> A required lename. It contains the transistor abstraction
information.
-Verilog The transistor description le format is Verilog. This is the
default.
-SPice The transistor description le format is SPICE.
-Golden Applies the les sub-circuit information to the Golden design.
-Revised Applies the les sub-circuit information to the Revised design.
-Both Applies the les sub-circuit information to both the Golden and
Revised designs.
-SEnsitive The transistor description le is case-sensitive. This is the
default.
-NOSEnsitive The transistor description le is not case-sensitive.
Command Reference
Examples
read pattern DLTCH1.v -verilog -revised
read pattern DLT2.v -verilog -both
read pattern xtran.spi -spice -golden
// Functional description of the transistor
// pattern
read library lib.v -verilog -golden
// Transistor pattern description
read pattern pattern.v -golden
read design design.v -golden
abstract logic -golden
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
REPORT CLOCK
-LAstmod If duplicate modules exist, Conformal uses the rst module and
ignores the later ones by default. Use this option to specify that
Conformal use the last module and ignore earlier ones.
Command Reference
RESOLVE
Command Reference
REDUCE MOS
REDuce MOs
[-ALL | -MODule <module name> ...]
[-MERGE_TRAN]
[-SD_GND]
[-SD_VDD]
[-DIODE]
[-PARALLEL]
[-GATE_ON]
[-GATE_OFF]
[-NOVERbose]
(Setup Mode)
Performs varieties of reduction on MOS transistor(s) from the circuit.
Parameters
-All Reduces transistor logic from all modules. This is the
default.
-MODule <module name> ...
Species the module(s) to reduce transistor logic.
-Golden Reduces transistor logic from the Golden design. This is
the default.
-Revised Reduces transistor logic from the Revised design.
-MERGE_TRAN Collapses the tran or rtran device into the wire.
-SD_GND Removes MOS devices with source and drain on GND.
-SD_VDD Remove MOS devices with the source and drain on VDD.
-DIODE Collapses [PN]mos into the wire if the source is on
[VDD|GND] and the gate and drain are on the same net.
-PARALLEL Collapses parallel-connected MOS devices into one MOS.
-GATE_ON Collapses non-weak MOS devices into the wire if the gate is
a constant that causes current to ow.
-GATE_OFF Removes non-weak MOS devices if the gate is a constant
that does not cause the current to ow.
Command Reference
Related Commands
ABSTRACT LOGIC
READ DESIGN -spice
-NOVERbose Does not report detailed statistical information.
Command Reference
REMODEL
REMODEL
<-SEQ_MERGE | -SEQ_CONSTant | -DFF_CONST_ASYNC | -UNFOLD_DFF
| -BBOX_MERGE | -RED_DLAT | -GATED_CLOCK | -REVERSE_SEQ_REDundant
| -SEQ2BUFfer | -SEQ_CONSTANT_GROUP | -UNREACH>
<-UNMAPPED | -MAPPED | -ALL | gate_id ... | instance_pathname ...>
[-MAX_UNMAP <number_of_keypoints>]
[-BOTH | -GOLden | -REVised]
[-REPEAT]
[-VERBose]
(LEC Mode)
Used in LEC mode and after mapping, this takes a set of key points and attempts to remodel
them. Use this command in conjunction with the SET FLATTEN MODEL command to resolve
mis-compares due to key point issues.
When you use this command, the Conformal software invalidates compare results (if they
exist), closes schematics, and updates the Mapping Manager.
Parameters
-SEQ_MERGE Merges common groups of sequential elements into one
sequential element in a logic cone of a key point.
Note: This modeling can only be applied to unmapped DFFs or
D-latches.
-SEQ_CONSTant Converts a DFF or D-latch to a ONE or ZERO gate.
Note: This modeling can only be applied to unmapped DFFs or
D-latches.
-DFF_CONST_ASYNC Converts a DFF to a ZERO or ONE gate due to its
asynchronous set or reset condition. This can be applied to
both unmapped or mapped DFFs.
-UNFOLD_DFF Converts a DFF to 2 D-latches with a master/slave
conguration.
Note: For latch-based custom logic comparisons, this option
might work better than set flatten model -latch_fold.
-BBOX_MERGE Performs automatic blackbox merging.
Command Reference
-RED_DLAT Collapses serial D-latches (even when there is logic between
them) into the last latch on that clock phase. You cannot use
this option with latches that have set or reset pins.
-GATED_CLOCK Transforms the gated clock of DFF to a MUX feedback loop.
-REVERSE_SEQ_REDundant
Restores the sequential redundancy to the outputs of the
specied DFFs or DLATs.
-SEQ2BUFfer Remodels a DFF or DLAT to a buffer or inverter due to
asynchronous connections.
-SEQ_CONSTANT_GROUP Validates and remodels a group of registers to ZERO and ONE
gates, which are dependent upon each other.
Note: You must specify a correct group of registers for this
modeling to be effective; otherwise, any non-constant register in
the group will prevent the true constant group from being
recognized.
-UNREACH Determines if the specied mapped key points are functionally
unreachable to primary outputs. After the key point is proved to
be functionally unreachable, the fan-out nets from this key point
are tied to constant zero. This analysis is useful to subsequently
remove the functionally unreachable non-equivalent compared
points from the compare and mapping lists.
Note: This remodeling can only be performed on mapped key
points and should be used after running the COMPARE
command.
Note: Use the DELETE MAPPED POINTS -unreach
command to delete unreachable mapped points.
-UNMAPPED | -MAPPED | -ALL | gate_id | instance_pathname
Applies the specied remodeling to all unmapped key points, all
mapped key points, all key points, or the specied gate or
instance. By default, Conformal remodels all unmapped
points.
Note: -ALL only applies to the options: -gated_clock,
-reverse_seq_redundant, -seq2buffer, and
-seq_constant_group.
Command Reference
Example
remodel seq_constant Q1_reg
Sample Implementation for the REMODEL Command:
In the following example, the design can be mapped almost completely by name, but there
are key points that have not been merged. To remodel replicated registers into a single
register, use the REMODEL command. Then Conformal can remap key points and compare.
set flatten model -seq_merge

set map method -name only
set system mode lec
remodel -seq_merge -both -unmapped
set map method -name first
map key points
add compare points -all
compare
Related Commands
COMPARE
-MAX_UNMAP <number_of_keypoints>
Species an upper limit of unmapped keypoints to be
remodeled.
-BOTH Applies the specied remodeling to the Golden and Revised
-GOLden Applies the specied remodeling to the Golden design only.
-REVised Applies the specied remodeling to the Revised design only.
-REPEAT Repeats until no further modeling is possible. Except for
sequential constant modeling, by default, the Conformal
software attempts to remodel once.
Note: Use Ctrl-C to interrupt remodeling.
-VERBose Provides additional information.
Command Reference
MAP KEY POINTS
SET FLATTEN MODEL
Command Reference
REMOVE
REMove
<name* ...>
[-INSTance | -INS_Module]
[-MODule <mod_name*> | -ALL]
(Setup Mode)
Removes instances from the database.
Tip
To report instances removed with this command, run the REPORT REMOVED
INSTANCE command.
Parameters
name* ... Species the name(s) of the instance(s) to remove. This
accepts wildcards.
-Golden Removes instances from the Golden design. This is the
default.
-Revised Removes instances from the Revised design.
-INSTance Indicates that the <name* ...> species the instance
names. This species to remove all instances whose instance
names match <name* ...>. This is the default.
-INS_Module Indicates that the <name* ...> species the module names.
This species to remove all instances whose module names
match <name* ...>.
-MODule <mod_name*> <mod_name*> species the module names. This accepts
wildcards. This species to remove the specied instances
from only the specied modules in <mod_name*>.
Note: If you do not specify <mod_name*>, the REMOVE
command removes the specied instances from only the root
module.
-ALL Removes the specied instances from all modules in the
design.
Command Reference
Example
For these lines:
module top (...);
mod1 u01 (...); // inst1
mod2 u02 (...); // inst2
mod3 u03 (...); // inst3
endmodule
module mod3 (...);
mod1 u01 (...); // inst4
mod2 u02 (...); // inst5
endmodule
I The following command removes u01 from the root module top:
remove u01 -ALL // remove inst1, inst4
I The following command removes u01 from module mod3:
remove u01 -MODULE mod3 // remove inst4
I The following command removes all mod1 instances from the root module top:
remove mod1 -INS_Module // remove inst1
I The following command removes all mod1 instances from all modules:
remove mod1 -INS_Module -ALL // remove inst1, inst4
Related Commands
REPORT REMOVED INSTANCE
Command Reference
REPort ABSTract Model
[-ALL | -MODule <module_name>]
(Setup / LEC Mode)
If you used SET ABSTRACT MODEL command to abstract transistor logic from particular
modules, this reports their abstraction conditions.
Parameters
Related Commands
ABSTRACT LOGIC
SET ABSTRACT MODEL
-All Reports abstraction conditions for all modules.
-MODule module_name
Reports abstraction conditions for the specied modules.
-Both Reports abstraction conditions for both the Golden and Revised
-Golden Reports abstraction conditions for the Golden design.
-Revised Reports abstraction conditions for the Revised design.
Command Reference
REPORT ALIAS
REPort ALias
[name*]
(Setup / LEC Mode)
Displays a list of all or specied aliases you created with the ADD ALIAS command.
Wildcard: The wildcard (*) represents any zero or more characters in alias names.
Parameters
Related Commands
ADD ALIAS
DELETE ALIAS
name* Reports the specied alias.
Command Reference
REPORT BLACK BOX
REPort BLack Box
[-Module |-Instance]
[-DETail]
[-Class <Full | User | System | UNDefined | UNSupported | EMPty | NOTranslate>]
[-HIER | -NOHIER]
[-HIDden | -NOHIDden]
(Setup / LEC Mode)
Displays blackboxes from the Golden and Revised designs. The blackboxes either already
existed in the design, or you previously added them with the ADD BLACK BOX command.
Parameters
-Module Reports only the blackbox modules. This is the default.
-Instance Reports only the blackbox instances.
-DEtail Displays details about blackboxes, where:
I USERIndicates that the blackbox was added by the
ADD BLACK BOX command.
I SYSTEM (undefined)Indicates that the blackbox was added
by the SET UNDEFINED CELL blackbox command.
I SYSTEM (unsupported)Indicates that the module contains
unsupported statements.
I SYSTEM (empty)Indicates that the module contains no logic.
I SYSTEM (notranslate)Indicates that the blackbox was
added by the ADD NOTRANSLATE MODULES command.
-Class Displays the specied class of blackboxes.
Full Blackboxes from both the User and System
classes. This is the default.
User Blackboxes previously added with the ADD
BLACK BOX command.
System Blackboxes included in the original design.
UNDefined Blackboxes for undened modules.
UNSupported Blackboxes for unsupported modules.
Command Reference
Related Commands
ADD BLACK BOX
DELETE BLACK BOX
EMPty Blackboxes for empty modules.
NOTranslate Blackboxes for notranslate modules.
-HIER Displays the hierarchical blackboxes. This is the default.
-NOHIER Does not display the hierarchical blackboxes.
-HIDden Displays all blackbox instances in the design hierarchy including
those contained within other blackboxes. This is the default.
-NOHIDden Does not display blackbox instances that are contained within other
blackboxes.
-Both Displays blackboxes from both the Golden and Revised designs.
-Golden Displays blackboxes from the Golden design.
-Revised Displays blackboxes from the Revised design.
Command Reference
REPORT CLOCK
REPort CLock
(Setup / LEC Mode)
Reports all clocks from the Golden and Revised designs that were added with the ADD
CLOCK command.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
-Both Displays all added clocks from both the Golden and Revised
-Golden Displays all added clocks from the Golden design.
-Revised Displays all added clocks from the Revised design.
Command Reference
RESOLVE
Command Reference
REPORT COMMAND PROFILE
REPort COmmand PRofile
[-Summary | -Detail]
(Setup / LEC Mode)
Displays a prole of all of the commands you executed after you used SET COMMAND
PROFILE with the -on option. (The default setting for SET COMMAND PROFILE is -off.)
The prole report includes the order in which commands were executed and the memory use.
The prole includes commands that were executed in the GUI mode.
Parameters
Related Commands
SET COMMAND PROFILE
SET LOG FILE
-SUMmary Lists a summary table of all of the commands in alphabetical
order. This is the default.
-Detail Lists all commands in order of execution.
Command Reference
REPORT COMPARE DATA
REPort COmpare Data
[-CLASS <EQuivalent | INVequivalent | NONEQuivalent
| ABort | NOTcompared | SYStem | USEr | FULL
| INSTance_eq | OUTput_eq | PIN_eq>]
[-Type <PO | DFF | DLAT | BBOX | CUT >]
[-Verbose | -SUMmary]
|<identifier> [-INSTance_eq <identifier>
|-OUTput_eq <identifier> | -PIN_eq <identifier>]
[-Golden |-REvised]
[-noreport_bbox_input | -report_bbox_input]
(LEC Mode)
Displays a list of all or specied compared points. If no options are specied, Conformal
identies all equivalent and nonequivalent compared points and displays a summary.
The compared points are listed in pairs of rows with three elds in each row. The rst row in
each pair represents the Golden design. The second row in each pair represents the Revised
design. The three elds in each row are:
I Firstthe gate identication number
I Secondthe gate type
I Thirdthe instance path or pin path
Parameters
-CLASS class_type
Displays the specied class of compared points:
EQuivalent
INVequivalent
Inverted-equivalent points
NONEQuivalent
Nonequivalent points
ABort Aborted points
NOTcompared All points not compared
SYStem Automatically mapped points
USEr User-mapped points
Command Reference
FULL Both automatically-mapped and
user-mapped points
INSTance_eq Equivalent instances
OUTput_eq Equivalent outputs
PIN_eq Equivalent pins
-TYPE compared_points_type
Displays the specied type of compared points:
PO Primary output
DFF D ip-op
DLAT D-latch
BBOX Blackbox
CUT Compared points with articial gates to
break combinational loops
-Verbose Displays all compared points. This is the default.
-SUMmary Lists a summary report of the compared points.
identifier Lists compared points for the specied gate ID or path.
-INSTance_eq <identifier>
Displays compare data for a pair of instances previously
identied with the ADD INSTANCE EQUIVALENCE command.
-OUTput_eq <identifier>
Displays compare data for a pair of outputs previously identied
with the ADD OUTPUT EQUIVALENCES command.
-PIN_eq <identifier>
Command Reference
Examples
Related Commands
COMPARE
DIAGNOSE
PROVE
REPORT STATISTICS
REPORT COMPARE TIME
Display compare data for a pair of pins previously identied with
the ADD PIN EQUIVALENCE command.
-Golden The specied identiers are from the Golden design. This is
the default.
-REvised The specied identiers are from the Revised design.
-noreport_bbox_input
Does not report the blackbox input pins in the compare report
results. This is the default.
-report_bbox_input Report the blackbox input pins in the compare report results
(Equivalent, Non-equivalent, Abort, and Not-compared).
Command Reference
REPORT COMPARE TIME
REPort COmpare TIME
[-SORT]
[-MAX n]
[-RTLINFO]
[-ABORT_ONLY]
[-GOLD g]
[-REVI r]
[-ENABLE]
[-DISABLE]
(LEC Mode)
Reports the CPU time consumed during a comparison.
You must enable this feature before starting a comparison; otherwise, Conformal does not
record any information.
For example:
compare
report compare time -enable
compare
report compare time
In this example, Conformal records the CPU time for the second comparison only.
Note: Conformal does not record compare time for trivial cones.
Parameters
-SORT Sorts the information based on the recorded CPU time.
-MAX n Species the maximum number, denoted by n, of key points to
report.
-RTLINFO Reports RTL information inside the cone.
-ABORT_ONLY Report only the abort points.
-GOLD g and -REVI r
Species particular key points to report. If you do not specify these
options, Conformal reports all key points.
-ENABLE Use this option to start recording CPU time. If you do not set this
option before your comparison, Conformal does not record CPU
time.
Command Reference
Examples
The following demonstrates how to use this command with other commands.
Note: Use these steps after you read in your library and design les.
1. Add your compare points.
LEC > add compared points -all
// 3113 compared points added to compare list
2. Enable the report compare time feature.
LEC> report compare time -enable
3. Start your comparison.
LEC> compare
================================================================================
Compared points PO DFF DLAT BBOX Total
--------------------------------------------------------------------------------
Equivalent 123 2983 2 5 3113
================================================================================
// Warning: 1 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison
4. Report the compare time. In this example, Conformal sorts the information based on
CPU time and only reports RTL information within the cone.
LEC>report compare time -sort -rtlinfo
CPU Time Used: 5.29, Result: Equivalent:
(G) + 536 DFF /cpu_core/CPU/cpu_dp/alu/v_alo_1l_reg[30]
(R) + 1284 DFF /cpu_core$CPU$cpu_dp$alu$v_alo_1l_reg_30_/U$1/U$1
RTL modules at Golden:
RTL modules at Revised:
CPU Time Used: 4.64, Result: Equivalent:
(G) + 533 DFF /cpu_core/CPU/cpu_dp/alu/o_alvo_1l_reg
(R) + 1364 DFF /cpu_core$CPU$cpu_dp$alu$o_alvo_1l_reg/U$1/U$1
RTL modules at Golden:
RTL modules at Revised:
.
.
.
Related Commands
ADD COMPARED POINTS
COMPARE
-DISABLE Disables the recording of CPU time.
Command Reference
REPORT COMPARE DATA
Command Reference
REPort COmpared Points
[-SUMmary | -PO | -DFf | -DLat | -Bbox | -Cut]
(LEC Mode)
Displays the compared points that were added with the ADD COMPARED POINTS command.
Refer to the sample report shown below. The rst row represents the Golden design; the
second row represents the Revised design. It also shows a tabulated summary of the
compared points for each design. This report includes the total number of compared points
for primary outputs, D ip-ops, D-latches, blackboxes, and cut gates.
If you do not specify any options, Conformal lists all added compared points, and a tabulated
summary appears at the end of the list. However, if you use the -summary option, Conformal
displays only the tabulated summary.
Parameters
Related Commands
ADD COMPARED POINTS
COMPARE
REPORT STATISTICS
-SUMmary Lists a summary table of all of the added compared points in
the Golden and Revised designs. (Refer to the sample report
given below.) This is the default.
-PO Lists all primary output compared points.
-DFf Lists all D ip-op compared points.
-DLat Lists all D-latch compared points.
-Bbox Lists all blackbox compared points.
-Cut Lists all compared points for articial gates that break
combinational loops.
Command Reference
REPORT CPF LOGIC
REPort CPf Logic
[-ISOlation]
[-Level_shifter]
[-RETention]
[-Verbose]
(Setup / LEC Mode)
Reports the low power cells that were inserted by the Conformal Low Power software.
Parameters
Note: By default, this command reports all inserted low power cell types.
Example
The following commands read the lib.cpf and design.cpf les, performs low power cell
insertion, and reports only the interted isolation and level-shifter cells:
read cpf lib.cpf design.cpf
commit cpf -insert
report cpf logic -isolation -level_shifter
Related Commands
COMMIT CPF
READ CPF
-ISOlation Reports the inserted isolation cells only .
-Level_shifter Reports the inserted level-shifter cells only .
-RETention Reports the inserted state retention cells only .
-VERbose Reports detailed information of each dened CPF cell, including
cell types and rules that triggered this cell to be inserted in the
design.
Command Reference
REPORT CUT POINT
REPort CUt Point
(Setup / LEC Mode)
Displays all cut points from the Golden and Revised designs that were added with the ADD
CUT POINT command.
Parameters
Related Commands
ADD CUT POINT
DELETE CUT POINT
REPORT PATH
-Both Lists all cut points in both the Golden and Revised designs.
-Golden Lists all cut points in the Golden design.
-Revised Lists all cut points in the Revised design.
Command Reference
REPort DAtapath Option
(Setup / LEC Mode)
Displays current data path option settings.
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
SET DATAPATH OPTION
SET FLATTEN MODEL
Command Reference
REPort DATapath REsource
[-Verbose]
[-Analyzed]
[-Type <MULT | ADD | SUB | MERGED>]
(LEC Mode)
Displays information about data path resources from the Golden and Revised designs.
Parameters
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
REPORT DESIGN DATA
-Verbose Provides additional information, such as lename and line
number.
-Analyzed Provides information only for resources analyzed by ANALYZE
DATAPATH command.
-Type Provides information only for resources of the specied type.
Choose one of the following:
I MULT multipliers
I ADD adders
I SUB subtractors
I MERGED merged operators
Command Reference
REPORT DESIGN DATA
REPort DEsign Data
[module_name]
[-NOKey_point | -Key_point]
[-Extra <INPut | Output | INOut>]
(Setup / LEC Mode)
Displays design data on the Golden and Revised designs. It displays the number of design
modules, library cells, inputs, outputs, primitives, and one-to-one mapped state points.
This report includes word-level information about the design in terms of the number of
arithmetic/keyword operations. This report includes data path elements such as WMUX,
WAND, WXOR and other word-level representations of Boolean logic. It displays simpler
representations of data path logic that may need to be separated out for the comparison
process.
Use Control-C to interrupt the key point listing if you nd that the report is too long.
Parameters
module_name Reports design data for the named module. By default, the
Conformal software reports design data on the top root design
module.
-Summary Summarizes the design data for the total number of the
following:
I Design modules
I Library cells
I Inputs
I Outputs
I Primitives
Command Reference
Report Design Data
Figure 2-1 is an example of the default design data report.
-Verbose Reports a detailed list of the designs total number of:
I Design modules
I Each different library cell
I Inputs
I Outputs
I Each different primitive
-NOKey_point Does not report the total one-to-one mapped state points. This
is the default.
-Key_point Reports the total one-to-one mapped state points.
Note: If you use the -verbose option in conjunction with this
option, Conformal reports all one-to-one mapped state points.
Otherwise, Conformal reports the total in summary.
-Extra Reports the extra input, output, or I/Opins for pair-able modules
between the Golden and Revised designs.
INPut Species input pins.
Output Species output pins.
INOut Species inout pins.
-Both Report design data on both the Golden and Revised designs.
-Golden Report design data on the Golden design.
-Revised Report design data on the Revised design.
Command Reference
Figure 2-1 Design Data Report
Related Commands
READ DESIGN
READ LIBRARY
Command Reference
REPORT DESIGN SIMILARITY
REPort DEsign SIMilarity
[-INStance <instance_name*>]
[-GOLDen | -REVised]
(LEC Mode)
Displays the similarity degree of a design with reference to the other netlist. The similarity is
measured by the number of corresponding points in the two designs. The value of similarity
ranges from0%to 100%. If the two designs are identical in structure, the similarity degree is
100%.
Parameters
Examples
I The following command displays the similarity of the Golden designs netlist. The
Revised designs netlist is used for reference.
report design similarity
I The following command displays the similarities of the instances whose name begins
with mult in the Golden designs netlist:
report design similarity -instance mult*
Related Topic
Reporting Design Similarities
-INStance <instance_name*>
Displays the similarity degree of the netlist inside the specied
instance. The similarity is evaluated with reference to the other
netlist.
If no instance is specied, the similarity is for the entire design.
-Golden Species that the similarity evaluation is performed on the
Golden design. The Revised netlist is used for reference. This
is the default.
-Revised Species that the similarity evaluation is performed on the
Revised design. The Golden netlist is used for reference.
Command Reference
REPort DYnamic Constraints
(LEC Mode)
Displays all of the dynamic constraints you added to the Golden and Revised designs with
the ADD DYNAMIC CONSTRAINTS command.
Parameters
Examples
Related Commands
COMPARE
PROVE
-Both Lists all dynamic constraints in both the Golden and Revised
-Golden Lists all dynamic constraints in the Golden design.
-Revised Lists all dynamic constraints in the Revised design.
Command Reference
REPORT ECO CELL
REPort ECo Cell
[-FReedcell]
[-SParecell]
(Setup Mode)
Reports the spare cells or freed cells available for the MAP ECO PATCH command.
Parameters
Related Commands
ADD ECO CELL
MAP ECO PATCH
-FReedcell Reports only the freed cells.
-SParecell Reports only the spare cells.
Command Reference
REPORT ECO CHANGES
REPort ECo Changes
[-MODule <module_name>]
[-SUMmary]
(Setup Mode)
Reports the ECO changes. To report the ECO change with this command, the ECOs must
have been applied with the APPLY PATCH or OPTIMIZE DESIGN command.
Parameters
Related Commands
WRITE ECO DESIGN
Species the module to report. By default, the command
reports all nets and instances that have been added and
deleted.
-SUMmary Shows a summary only.
Command Reference
REPORT ECO PATCH
REPort ECo PAtch
(Setup Mode)
Reports the ECO patch specied by the ADD ECO PATCH command.
Related Commands
ADD ECO PATCH
DELETE ECO PATCH
Command Reference
REPORT ENVIRONMENT
REPort ENvironment
[-Setup | -MOdeling | -MApping | -COMpare | -Diagnosis | -FUnctiondefault]
(Setup / LEC Mode)
Displays global settings for the Golden and Revised designs and system settings.
Parameters
Environment Report
Figure 2-2 is an example of the default environment report (no options were added).
-Setup Reports environment related to Setup. This is the default.
-MOdeling Reports environment related to Modeling.
-MApping Reports environment related to Mapping.
-COMpare Reports environment related to Compare.
-Diagnosis Reports environment related to Diagnosis.
-FUnctiondefault Reports environment related to the default return value.
Command Reference
Figure 2-2 Environment Report
Related Commands
SET CASE SENSITIVITY
SET COMPARE EFFORT
SET CPU LIMIT
SET FLATTEN MODEL
Command Reference
SET GATE REPORT
SET IMPLEMENTATION
SET LOG FILE
SET MAPPING METHOD
SET NAMING RULE
SET ROOT MODULE
SET SCREEN DISPLAY
SET SYSTEM MODE
SET UNDEFINED CELL
SET UNDRIVEN SIGNAL
SET WIRE RESOLUTION
SET X CONVERSION
Command Reference
REPORT FLOATING SIGNALS
REPort FLoating Signals
[-ROot | -Module <name> | -All]
[-UNDriven | -UNUsed] [ |-Net | -Pin]
(Setup / LEC Mode)
Displays all oating signals in the Golden and Revised designs or in specied modules of a
design. The reported oating signals are either nets or pins and are either undriven or
unused. Use the SET UNDRIVEN SIGNAL command to specify the global behavior of the
undriven oating signals in the Golden and Revised designs.
Parameters
-ROot Displays all of the oating signals in the root module. This is
the default.
-Module name Displays all the oating signals in the specied module
-All Displays all the oating signals in all design modules
-UNDriven Displays only undriven oating signals. This is the default.
-UNUsed Displays only unused oating signals.
-Net Displays only oating nets.
If you do not specify -net or -pin, Conformal displays
both oating nets and oating pins.
-Pin Displays only oating pins.
If you do not specify -net or -pin, Conformal displays
both oating nets and oating pins.
-Both Displays oating signals from both the Golden and Revised
-Golden Displays oating signals from the Golden design.
-Revised Displays oating signals from the Revised design.
Command Reference
Related Commands
ADD TIED SIGNALS
SET UNDRIVEN SIGNAL
Command Reference
REPORT GATE
REPort GAte
[<identifier>
[-SUPport]
[-FRONTIER]
[-FANIn <integer>]
[-FANOut <integer>]
[-UNReach]
[-SHORT_list | -NOSHORT_list]
[-SOURCE]
[-Collapse]
[-NODYNamic | -DYNamic]
[-INDent <integer>]]
[-Type <PI | 0 | 1 | E | Z | BBOX | DFF | DLAT | CUT | OUT | COMB | PO>]
[-RETention]
[-CORRespondence]
[-SUMmary]
(Setup / LEC Mode)
Displays attened gate information. By default, it reports the gate ID, type, name, and its
fanins and fan-outs at the primitive level. After you specify options for the initial report, use the
REPORT GATE command without options to generate a report on the same gates, or specify
new options as needed.
Important
ID numbers can differ fromone version of Conformal to another. Always use the full
path in doles and any time you rerun a design with a different Conformal version.
Parameters
identifier If you do not specify one of the following options, Conformal
-INStance Instance path
-Pin Pin path
-Net Net path
Command Reference
-ID Gate identication number
-Golden The identier is in the Golden design. This is the default.
-Revised The identier is in the Revised design.
-SUPport Reports the supported key points from the fanin cone.
-FRONTIER Reports the frontier key points from the fan-out cone.
-FANIn integer Reports this number of levels in the fanin cone. The default
value is 0.
-FANOut integer Reports this number of levels in the fan-out cone. The default
value is 0.
-UNReach Displays diagnosis information for unmapped points that were
classied as unreachable.
-SHORT_list Lists the rst and last 20 gates of a long display list. This is the
default.
-NOSHORT_list Displays the entire display list.
-SOURCE Reports the gate information and the following location
information:
I Module name
I Instance name
I Filename
I Source line
-Collapse Does not report inverters and buffers in the fanin cone. The
default is to report all inverters and buffers in the
fanin/fan-out cone.
-NODYNamic Use this option in conjunction with the -fanin option.
The fanin cone does not stop at a gate with dynamic
constraints. This is the default.
Command Reference
-DYNamic Use this option in conjunction with the -fanin option. The
fanin cone stops at the gate with dynamic constraints.
-INDent integer Displays this amount of whitespace when reporting the fanin
and fan-out cones. The default value is 2.
-Type gate_type Reports all gates with the specied gate type. The available
gate types are as follows:
PI Primary inputs
0 TIE-0 gates
1 TIE-1 gates
E TIE-E gates
Z TIE-Z gates
BBOX Blackboxes
DFF D ip-ops
DLAT D-latches
feedback loops
OUT Articial gates for the multiple outputs of
blackboxes
COMB Combinational gates
PO Primary Outputs
-RETention Note: This is a Conformal Low Power option.
If the gate is a sequential element (DFF or DLAT) and belongs
to the Golden Design, this option reports the tag-name (if any)
associated with the DFF or DLAT. If the gate is a sequential
element (DFF or DLAT) and belongs to the Revised Design, this
option reports the power gating cell attribute (if any) associated
with the DFF or DLAT. For non-sequential elements, nothing is
reported.
-CORRespondence Reports the correspondence gates in the other (Golden or
Revised design) netlist. The correspondence gate is potentially
equivalent with the gate specied in this command. Use the
PROVE command to formally prove the equivalence.
-SUMmary Reports gate type statistics. The default is not to report the
statistics.
Command Reference
Related Commands
BACKWARD
CHANGE GATE TYPE
FORWARD
REPORT PATH
SET GATE REPORT
Command Reference
REPORT HIER_COMPARE RESULT
REPort HIer_compare Result
[-Summary | -Equivalent | -NONEQuivalent | -Abort
| -UNcompared | -FLattened | -DYNamicflattened
| -EXTRA_po | -ALL]
[-USage]
(Setup / LEC Mode)
Displays the results of the hierarchical comparison. If the WRITE HIER_COMPARE DOFILE
command is used, this command is automatically placed at the end of the hierarchical dole
script. It lists the summary results and any modules that are nonequivalent, aborted, or
uncompared.
Parameters
-Summary Displays a summary table of the hierarchical comparison
results. This is the default.
-Equivalent Displays only the hierarchical modules that are equivalent.
-NONEQuivalent Displays only the hierarchical modules that are nonequivalent.
-Abort Displays only the hierarchical modules that had abort key
points.
-UNcompared Displays only the hierarchical modules that are not compared.
-FLattened Displays only the hierarchical modules that were found to be
nonequivalent and, as a result, were attened.
Use this option when you have used write hier_compare
dofile -conditional
-DYNamicflattened Displays only the hierarchical modules that were either found to
be non-equivalent, or were equivalent but caused
non-equivalence at the parent level, and were automatically
attened.
Use this option when performing hierarchical comparison with
the RUN HIER_COMPARE command.
-EXTRA_po Displays only the hierarchical modules that have extra
(not-mapped) primary outputs.
-ALL Displays the results of all of the modules.
-USage Displays the CPU use time for each module comparison.
Command Reference
Related Commands
RESET HIER_COMPARE RESULT
RUN HIER_COMPARE
SAVE HIER_COMPARE RESULT
Command Reference
REPort IGnored Inputs
[-Both | -Golden | -REvised]
(Setup / LEC Mode)
Displays the input pins, which were added as ignored inputs, in the Golden and Revised
designs. These pins were originally specied with the ADD IGNORED INPUTS command.
Parameters
Related Commands
ADD IGNORED INPUTS
-ROot Displays only the input pins in the root module. This is the
default.
-Module name Displays only the ignored input pins in the named module.
-All Displays all ignored input pins in all modules.
-Both Displays both the Golden and Revised added ignored
inputs. This is the default.
-Golden Displays the added ignored inputs from the Golden design.
-REvised Displays the Revised ignored inputs.
Command Reference
REPort IGnored Outputs
(Setup / LEC Mode)
Displays the output or I/O pins, which were added as ignored outputs, in the Golden and
Revised designs. These outputs were originally specied with the ADD IGNORED OUTPUTS
command.
Parameters
Related Commands
ADD IGNORED OUTPUTS
-ROot Displays only the input pins in the root module. This is the
default.
-Module name Displays only the ignored output or I/O pins in the specied
module.
-All Displays all ignored input pins in all modules.
-Both Displays both the Golden and Revised added ignored
outputs. This is the default.
-Golden Displays only the Golden added ignored outputs.
-REvised Displays only the Revised ignored outputs.
Command Reference
REPort INstance Attribute
(Setup Mode)
Displays the attributes placed on instances in the Golden and Revised designs. These
attributes were originally specied with the ADD INSTANCE ATTRIBUTE command.
Parameters
Related Commands
-ROot Displays only the added instance attributes in the root
module. This is the default.
-Module name Displays only the added instance attributes in the specied
module.
-All Displays all added instance attributes within the given
defaults.
-Summary Displays a summary message of the total number of added
instance attributes. This is the default.
-Verbose Displays all added instance attributes.
-Both Displays the added instance attributes in both the Golden
-Golden Displays the added instance attributes in the Golden design.
-REvised Displays the added instance attributes in the Revised
design.
Command Reference
REPort INstance Constraints
(Setup / LEC Mode)
Displays the constraints placed on instances in the Golden and Revised designs. These
constraints were originally specied with the ADD INSTANCE CONSTRAINTS command.
Parameters
Related Commands
-Both Displays the instance constraints in both the Golden and
-Golden Displays the instance constraints in the Golden design.
-Revised Displays the instance constraints in the Revised design.
Command Reference
REPort INstance Equivalences
(Setup / LEC Mode)
Displays the equivalences placed on instances in the Golden and Revised designs. These
equivalences were originally specied with the ADD INSTANCE EQUIVALENCES command.
Parameters
Related Commands
-Both Displays the instance equivalences in both the Golden and
-Golden Displays the instance equivalences in the Golden design.
-Revised Displays the instance equivalences in the Revised design.
Command Reference
REPORT KEY POINT
REPort KEy Point
[[-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO> ...
| -NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO> ...]
| -Mapped | -UNMapped | -UNReached]
[-PROPerty]
[-DC]
(Setup / LEC Mode)
Report key points in the design.
Parameters
-TYpe
-NOTYpe
Displays all key points with the specied type.
Displays all key points except the specied type.
The available types are as follows:
PI Primary inputs
E TIE-E gates
Z TIE-Z gates
DFf D ip-ops
DLat D-latches
CUt Articial gates for breaking combinational
feedback loops
BBox Blackboxes
PO Primary Outputs
-Mapped Displays all mapped key points in the design.
-UNMapped Displays all unmapped key points in the design.
-UNReached Displays diagnosis information for unmapped key points that
were classied as unreachable.
-PROPerty Displays support and fan-out key points for each key point
-DC Displays the number of DC gates in the compare cone
-Golden Species that the report applies only to the Golden design.
Command Reference
Related Commands
MAP KEY POINTS
-Revised Species that the report applies only to the Revised design.
Command Reference
REPORT LIBRARY DATA
REPort LIbrary Data
[-Source]
[-SORT <NAME | REFerence | INStance>]
[-SKIP_Unref]
(Setup / LEC Mode)
Displays the following columns:
I IDSpecies the cell ID.
I NameSpecies the cell name.
I CostSpecies the cost of each library cell, which is the product of the number of
instances of primitive gates within each library cell (Ins) and the number of times the
library cell is instantiated (Ref).
I InsDisplays the number of instances of primitive gates within each library cell.
I RefDisplays the number of times the library cell is referenced in the design.
I TOTDisplays the total number of gates per library cell.
This total is calculated by Ins times Ref. If Ins is 3 and Ref is 3, the total is 9. If Ins is 3
and Ref is 0, the total is 0.
I DFFSpecies whether the cell contains a D ip-op.
I DLATSpecies whether the cell contains a D-latch.
I BUFSpecies whether the cell contains a buffer.
I NOTSpecies whether the cell contains an inverter gate.
I BBOXSpecies whether the cell contains a blackbox.
I UDPSpecies whether the cell is a UDP.
By default, Conformal reports on the library for the Golden design if you do not specify
options.
Note: When you read in a library, you can specify whether it is for the Golden or Revised
design.
Command Reference
Parameters
Related Commands
READ LIBRARY
READ DESIGN
REPORT DESIGN DATA
-SOURCE Displays the source lename and line number for each cell.
-SORT Sorts report data as specied:
NAME Sorts report data alphabetically by library
cell name.
REFerence Sorts report data according to the Reference
column, in descending order.
INStance Sorts report data according to the Instance
column in descending order.
-SKIP_Unref Does not display unreferenced library modules.
-Golden Displays the library data for the Golden design. This is the
default.
-Revised Displays the library data for the Revised design.
Command Reference
REPort LOwpower Cells
[-Module | -Instance]
[-Summary]
(Setup / LEC Mode)
Reports the low power cells used in the design.
Parameters
Related Commands
ADD LOWPOWER CELLS
SET LOWPOWER OPTION
-Module Reports only the modules with low power cells. This is the default.
-Instance Reports only the instances with low power cells.
-Summary Displays a summary of low power cells.
Command Reference
REPort LOwpower Data
[-STatus <All | Pass | Fail | Notcheck>]
[-TYpe [All | Retention_cell_check [ -Rule <rulename>]
| Isolation_cell_check
| Level_shifter_cell_check
| POWER_domain_check]
]
[-SUMmary | -Verbose]
(LEC Mode)
Reports the low power data. These are the results of the low power check performed on low
power cells using the CHECK LOWPOWER CELLS command.
CELLS on page 143.
Parameters
-STatus Species the status reporting.
For retention-register cell types, the -STatus arguments are described
as follows:
-All Reports all the sequential pairs (LEC mapped points) that
passed or failed the default rule or user rule. This is the
default.
-Pass Reports all the sequential pairs that passed the default rule
or user rule.
-Fail Reports all the sequential pairs that failed the default rule or
user rule.
Notcheck
Reports the sequential pairs that were not checked for
retention-register consistency
For isolation and level-shifter cell types, the -STatus arguments are
described as follows:
-All Reports all the low power cut gates that passed or failed the
technology mapping check. This is the default.
Command Reference
-Pass Reports all the low power cut gates that passed the
technology mapping check.
-Fail Reports all the low power cut gates that failed the technology
mapping check.
Notcheck
Reports the low power cut gates that were not checked for
isolation and level-shifter consistency.
For the power domain consistency check, the -STatus arguments are
described as follows:
All Reports all the mapped sequential points that passed and
failed the power domain consistency check
Pass Reports the mapped sequential points that passed the power
domain consistency check.
Fail Reports the mapped sequential points that failed the power
domain consistency check.
Notcheck
Reports the mapped sequential points that were not checked
for power domain consistency
-TYpe Species the module type reporting.
-All Reports on all low power cells. This is the default.
-Retention [-Rule <rulename>]
Reports on only the low power state retention cells.
-Rule <rulename> reports all the sequential pairs that
passed or failed the specied rulename.
-Isolation_cells
Reports on only the low power isolation cells.
-Level_shifter_cells
Reports on only the low power level-shifter cells.
-POWER_domain_check
Reports the results of power domain consistency check for
the mapped sequential points.
Command Reference
Related Commands
ADD LOWPOWER CELLS
SET LOWPOWER OPTION
-SUMmary Displays the status summary of the check performed on low power cells.
-Verbose For state retention cells, this reports the sequential pairs (LEC mapped
points) that passed or failed the default rule or user rule. For each passed
or failed sequential pair, the corresponding rule it passed or failed on is
also reported. In addition, this reports any tag-name for the sequential
element in the Golden Design, and any power gating cell attribute for the
sequential element in the Revised Design.
For isolation cells and level-shifter cells, this reports the PASS or FAIL
status of low power cut gates that correspond to the isolation cells and
level-shifter cells.
Command Reference
REPort MApped Points
[< gate_id |instance_pathname* | pin_pathname*>
| [ -TYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>
| [ -NOTYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>]
[-INVert_mapped] | -SUMmary]
[-LOng]
[-CLass <Full | System | User>]
[-INput]
[-OUTput]
[-GRoup]
[-REName]
[-RETention]
[-METHOD]
[-RENAME]
[-UNReachable]
(LEC Mode)
Displays the mapped points that were automatically identied or added with the ADD MAPPED
POINTS command. Each mapped point from the Golden and Revised design is displayed
along with a summary of all Golden and Revised mapped points.
The summary includes the total number of primary inputs, primary outputs, D ip-ops,
D-latches, TIE-Es, TIE-Zs, blackboxes, and cut gates.
If no options are entered, the command default is to display both the User and System
classes of mapped points.
Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths
of mapped points.
Parameters
gate_id Reports the mapped points for the identied gate.
instance_pathname* Reports the mapped points for the named instance path(s).
Command Reference
pin_pathname* Reports the mapped points for the named pin path(s).
-Type mapped_point_type
Displays all mapped points with the specied type. The
PI Primary Inputs
E TIE-E mapped points
Z TIE-Z mapped points
DFF D ip-ops
DLAT D-latches
feedback loops
BBOX Blackboxes
PO Primary Outputs
-NOType mapped point_type
Does not display mapped points with the specied type. The
PI Primary Inputs
E TIE-E mapped points
Z TIE-Z mapped points
DFF D ip-ops
DLAT D-latches
feedback loops
BBOX Blackboxes
PO Primary Outputs
-INVert_mapped Displays all mapped points with inverted mapping.
-SUMmary Displays a table summary of the mapped points in the Golden
-LOng Displays pairs of mapped points on separate lines.
Command Reference
-INput Displays the input port mapping pairs of the specied DFF,
DLAT, or blackbox gate.
-Class Displays the following class of mapped points.
Full Mapped points from both the User and
System classes. This is the default.
System Mapped points from the original design.
User Mapped points added with the ADD MAPPED
POINTS command
-OUTput Displays the output port mapping pairs of the specied blackbox
gate.
-GRoup Displays the mapping pairs in which either the Golden or
Revised key point is a group of equivalent gates rather than a
single gate.
The group can be dened with the ADD INSTANCE
EQUIVALENCE command or the -seq_merge option of the
SET FLATTEN MODEL command.
A key point group is counted as one key point.
-REName Lists the keypoint with renaming rules applied to the names.
-Golden The mapped points are from the Golden design. This is the
default.
-REVised The mapped points are from the Revised design.
If the mapped point is a sequential pair (DFF or DLAT pair), this
option reports the status of the mapped point (Pass, Fail, or
Unknown) in accordance with the state retention mapping rules.
This also reports the tag-name (if any) associated with the
Golden DFF or DLAT and the power gating cell attribute (if any)
associated with the Revised DFF or DLAT. For non-sequential
elements, nothing is reported.
-METHOD Shows the method used in mapping the keypoints.
-RENAME Displays the keypoints with renaming rules applied to their
names.
-UNReachable Lists unreachable keypoints. Unreachable key points are those
that do not eventually affect the primary output of the design.
Command Reference
Related Commands
ADD MAPPED POINTS
MAP KEY POINTS
REPORT STATISTICS
SET MAPPING METHOD
SET NAMING RULE
Command Reference
REPORT MESSAGES
REPort MEssages
[-MOdeling | -MAPping | -Compare]
[-RUle <rule_name>]
[-NOSORT | -SORT]
(Setup / LEC Mode)
Displays either a summary or complete list of the warning messages that come from the
modeling, mapping, or comparison process. (The modeling process occurs when Conformal
exits the Setup mode.) A summary of the warning messages is always displayed when the
modeling, mapping, or comparison process is in progress; however, this command displays
each individual warning message for the Golden and Revised designs, according to your
specications.
See Modeling Messages in the Encounter Conformal Equivalence Checking User
Guide for information on the Modeling Messages and the commands/options that trigger
them.
Parameters
-MOdeling Displays only warning messages from the processing and
modeling of the Golden and Revised designs. This is the
default.
-MAPping Displays warning messages only from the automatic key
point mapping process.
-Compare Displays warning messages only from the comparison
process.
-RUle rule_name Displays only the named rule.
-Summary Displays only a summary message for common warning
messages. This is the default.
-Verbose Displays all warning messages.
-NOSORT Does not sort messages. This is the default.
-SORT Sorts messages alpha-numerically. (Use this option with the
-verbose option.)
-Both Displays warning messages that come fromboth the Golden
and Revised designs and libraries. This is the default.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
SET FLATTEN MODEL
-Golden Displays warning messages that come from the Golden
design and library.
-REvised Displays warning messages that come from the Revised
design and library.
Command Reference
REPort MOdule Attribute
[-ALL | -PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit]
(Setup Mode)
Displays the module attributes in the Golden and Revised designs. These attributes were
originally added with the ADD MODULE ATTRIBUTE command.
Parameters
Related Commands
READ DESIGN
READ LIBRARY
-ALL Displays all added module attributes within the given defaults.
-PIPELINE_Retime Displays only the modules added for pipeline-retiming.
-COMPARE_Effort Displays only the modules that have specied compare effort
levels.
-CPU_Limit Displays the modules with a specied CPU time limit.
-Both Displays the module attributes for both the Golden and Revised
-Golden Displays the module attributes for the Golden design.
-Revised Displays the module attributes for the Revised design.
Command Reference
REPORT MODULES
REPort MOdules
[-ROot | module_name [-Up | -Down] | -All | -Top]
[-Source]
[-INSTantiation]
[-USer]
[-VHDLname]
[-LEVEL <value>]
[-Library]
[-NOINTERLeave |-INTERLeave]
(Setup / LEC Mode)
Displays module information for the Golden and Revised designs. If you specify a module,
Conformal displays additional information on modules and library cells up or down the
hierarchy of the given module name.
Parameters
-ROot Displays the name of the root module.
module_name Reports module information on the specied module. An
additional option lets you report on modules and library cells
either up or down the hierarchy of the specied module name.
The default is to report modules and library cells up the
hierarchy of the specified module name.
-Up Reports on modules and library cells up the
hierarchy of the specied module name.
-Down Reports on modules and library cells down
the hierarchy of the specied module name.
-All Displays all the modules within the given defaults. The top root
module is denoted by (T).
-Top Displays the top modules.
-Source Displays the source-code information identifying where the
module is located.
-Instantiation Displays instances and modules.
Command Reference
Examples
This example shows the difference between running the REPORT MODULES command
without any options versus running the command with the -USer option.
The following design le contains only one module named test. Module
VDW_mult_nbw_u8_u8_16 is internal module which is not dened in this le:
module test(aa, bb, oo);
input [7:0] aa, bb;
output oo;
assign oo = aa * bb;
endmodule
Running the following command:
report modules
the Conformal software reports the test and VDW_mult_nbw_u8_u8_16 modules.
However, when running the following command:
report modules -user
-USer Reports only the modules dened in the design les, and skips
the internal modules which are not dened in the design les.
Note: Some internal modules can be created by the Conformal
tools after reading the design les. These internal modules are
not dened in the design les.
-VHDLname Displays the full name, rather than just the entity name.
For example: libname.entityname(architecturename).
-LEVEL value Shows modules in a hierarchical order up to the specied level.
-Library Displays all of the library cells that are in the module hierarchy.
-NOINTERLeave Reports the Golden and Revised module hierarchies
separately, rst list Golden modules, and then list Revised
modules. This is the default.
-INTERLeave Reports the Golden and Revised module hierarchies together.
-Both Displays information for both the Golden and Revised designs.
-Golden Displays module information for the Golden design.
-Revised Displays module information for the Revised design.
Command Reference
the Conformal software reports only the test module.
Related Commands
REPORT PATH
Command Reference
REPort MOs Direction
[module_name]
[-BIdirection | -UNidirection ]
(Setup / LEC Mode)
Displays the unidirectional and bidirectional transistor-MOS instances with their source and
drain ports.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
module_name Reports on the named module.
-Summary Displays a summary message of the total number of
unidirectional and bidirectional transistor-MOS. This is the
default.
-Verbose Displays all of the unidirectional and bidirectional
transistor-MOS.
-BIdirection Displays only the bidirectional transistor-MOS instances. This
is the default.
-UNidirection Displays only the unidirectional transistor-MOS instances.
-Both Displays MOS direction from both the Golden and Revised
-Golden Displays MOS direction from the Golden design.
-Revised Displays MOS direction from the Revised design.
Command Reference
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
REPort MUltiplier Option
(Setup / LEC Mode)
Displays current multiplier option settings.
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
SET DATAPATH OPTION
SET FLATTEN MODEL
Command Reference
REPort NEt Attribute
[-ALL | -VDD | -GND | -CLOCK0 | -CLOCK1 | -DYNSTate]
[-Module <name>]
Displays attributes on transistor-MOS nets. The attributes were originally added with the ADD
NET ATTRIBUTE command.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
-ALL Displays all added net attributes within the given defaults.
-VDD Displays only the added VDD net attributes.
-GND Displays only the added GND net attributes.
-CLOCK0 Displays only the added Clock-0 net attributes.
-CLOCK1 Displays only the added Clock-1 net attributes.
-DYNSTate Displays only the added dynamic state net attributes.
-Module name Reports net attributes from the named module.
-Both Displays net attributes from both the Golden and Revised
-Golden Displays net attributes from the Golden design.
-Revised Displays net attributes from the Revised design.
Command Reference
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
REPort NEt Constraints
(Setup / LEC Mode)
Displays all net constraints in the Golden and Revised designs that were added with the ADD
NET CONSTRAINTS command.
Parameters
Related Commands
ADD NET CONSTRAINTS
-Both Displays added net constraints in both the Golden and Revised
-Golden Displays the added net constraints in the Golden design.
-Revised Displays the added net constraints in the Revised design.
Command Reference
REPORT NOBLACK BOX
REPort NOblack Box
(Setup / LEC Mode)
Displays all of the modules in the Golden and Revised designs that will not be included in the
hierarchical dole script generation. These modules were originally specied with the ADD
NOBLACK BOX command.
Parameters
Related Commands
ADD NOBLACK BOX
DELETE NOBLACK BOX
-Both Displays added noblackboxes in both the Golden and Revised
-Golden Displays the added noblackboxes in the Golden design.
-Revised Displays the added noblackboxes in the Revised design.
Command Reference
REPort NOtranslate Filepathnames
(Setup / LEC Mode)
Displays all of the library and design le pathnames originally added with the ADD
NOTRANSLATE FILEPATHNAMES command. The Conformal software will not compile these
modules dened in libraries and design les.
Parameters
Related Commands
-Library Displays only the added library le pathnames.
-Design Displays only the added design le pathnames.
-Both Displays added le pathnames in both the Golden and Revised
-Golden Displays the added le pathnames in the Golden design.
-Revised Displays the added le pathnames in the Revised design.
Command Reference
REPort NOtranslate Modules
(Setup / LEC Mode)
Displays all of the library and design modules originally added with the ADD NOTRANSLATE
MODULES command. Conformal will not compile these modules when reading in libraries and
designs.
Related Commands
READ DESIGN
READ LIBRARY
Command Reference
REPort OUtput Equivalences
[-ROot | -Module <name> | -All ]
(Setup / LEC Mode)
Displays the output pin equivalences in the Golden and Revised designs. These output pin
equivalences were originally added with the ADD OUTPUT EQUIVALENCES command.
Parameters
Related Commands
-ROot Displays all output pin equivalences from the root module.
-Module name Displays the output pin equivalences in the specied module.
-All Displays all output pin equivalences in all modules within the
given defaults.
-Both Displays the output pin equivalences in both the Golden and
-Golden Displays the output pin equivalences in the Revised design.
-Revised Displays the output pin equivalences in the Golden design.
Command Reference
REPort OUtput Stuck_at
[-ROot |-Module <name> | -All ]
(Setup / LEC Mode)
Displays the output stuck_at values and pin names in the Golden and Revised designs.
These output stuck_at values were originally added to pins with the ADD OUTPUT
STUCK_AT command.
Parameters
Related Commands
ADD OUTPUT STUCK_AT
-ROot Displays the output stuck_at values and pin names from the
root module. This is the default.
-Module name Displays the output stuck_at values and pin names from the
specied module.
-All Displays all output stuck_at values and pin names in all
modules within the given defaults.
-Both Displays the output stuck_at values and pin names in both
the Golden and Revised designs. This is the default.
-Golden Displays the output stuck_at values and pin names in the
Revised design.
-Revised Displays the output stuck_at values and pin names in the
Golden design.
Command Reference
REPort PArtition Key_point
(Setup / LEC Mode)
Displays the partition key points originally added with the ADD PARTITION KEY_POINT
command.
Related Commands
Command Reference
REPort Partition Points
[-Verbose | -Summary]
(LEC Mode)
Displays the partition points that were created with the ADD PARTITION POINTS command.
Parameters
Related Commands
-Both Lists the partition points in both the Golden and Revised
-Golden Lists the partition points in the Golden design.
-Revised Lists the partition points in the Revised design.
-Verbose Displays all added partition points. This is the default.
-Summary Displays a summary message of the total number of added
partition points.
Command Reference
REPORT PARTITION RESULT
REPort PArtition Result
(Setup Mode)
Displays the results after running partition dole.
Related Commands
Command Reference
REPORT PATH
REPort PAth
<<source> <destination> | -Feedback | -SELF | -SELF <gate>>
[-Source]
[-NET]
[-SEQ_ASYNC]
(Setup / LEC Mode)
Displays the paths between a source gate and a destination gate. The -feedback option
displays all feedback paths for all CUT gates. The source and destination gates can be:
I Gate ID numbers
I Instance paths
I Pin paths
To report the feedback path on one CUT gate, use the same CUT gate ID, instance path, or
pin path for both the source and the destination.
Parameters
source Species the gate ID number, instance path, or pin path of
the source gate.
Note: ID numbers can differ from one version of Conformal
to another. Always use the full path in doles and any time
you rerun a design with a different Conformal version.
destination Species the gate ID number, instance path, or pin path of
the destination gate.
Note: ID numbers can differ from one version of Conformal
to another. Always use the full path in doles and any time
you rerun a design with a different Conformal version.
-Feedback Reports the feedback path of all CUT gates.
-SELF [<gate>] Reports all loops to DFF and DLATs. If you specify a gate, it
reports only loops to that gate.
-Source Displays the le and line number location of the gate in the
path.
Command Reference
Related Commands
ADD CUT POINT
DELETE CUT POINT
REPORT CUT POINT
REPORT GATE
-NET Displays the corresponding net of the gate in the path.
-SEQ_ASYNC Reports DFF/DLAT to DFF/DLAT paths passing through the
asynchronous set or reset of a sequential element.
-Golden Reports the specied path in the Golden design. This is the
default.
-Revised Reports the specied path in the Revised design.
Command Reference
REPort PIn Constraints
(Setup / LEC Mode)
Displays the constraints placed on primary input pins in the Golden and Revised designs.
These constraints were originally specied with the ADD PIN CONSTRAINTS command.
Parameters
Related Commands
ADD PIN CONSTRAINTS
-ROot Displays the pin constraints from the root module. This is
the default.
-Module name Displays the pin constraints from the specied module.
-All Displays pin constraints in all modules.
-Both Displays the constrained primary input pins from both the
Golden and Revised designs. This is the default.
-Golden Displays the constrained primary input pins fromthe Golden
design.
-Revised Displays the constrained primary input pins from the
Revised design.
Command Reference
REPort PIn Direction
[-IO | -IN | -OUT]
[module_name]
(Setup / LEC Mode)
Displays the assigned pin directions for each module. The default is to display only a
summary message.
Note: Use the ASSIGN PIN DIRECTION command to assign pin direction to module I/O
pins.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
-IO Reports assigned module I/O pins. This is the default.
-IN Reports assigned module input pins.
-OUT Reports assigned module output pins.
module_name Reports pin direction for the specied module. The default
is to report pin direction for all modules.
-Summary Displays only a summary message of assigned pin
directions. This is the default.
-Verbose Displays all assigned pin directions.
-Both Reports the assigned pin directions in both the Golden and
-Golden Reports the assigned pin directions in the Golden design.
-Revised Reports the assigned pin directions in the Revised design.
Command Reference
DELETE CLOCK
READ PATTERN
REPORT CLOCK
RESOLVE
Command Reference
REPort PIn Equivalences
(Setup / LEC Mode)
Displays a list of added pin equivalences and inverted pin equivalences. These pin
equivalences were originally added with the ADD PIN EQUIVALENCE command. Inverted
pin equivalences are distinguished by a - next to the primary input pin name.
Parameters
Related Commands
-ROot Displays pin equivalences from the root module. This is the
default.
-Module name Displays pin equivalences from the specied module.
-All Displays pin equivalences in all modules.
-Both Displays pin equivalences from both the Golden and Revised
-Golden Displays pin equivalences from the Golden design.
-REvised Displays pin equivalences from the Revised design.
Command Reference
REPort PRimary Inputs
[-Class <Full | System | User>]
(Setup / LEC Mode)
Displays primary input pins from the Golden and Revised designs.
Parameters
Related Commands
ADD PRIMARY INPUT
-Class Displays the following class of primary inputs.
Full Primary inputs from both the User and
System classes
System Primary inputs from the original design
User Primary inputs added with the ADD
PRIMARY INPUT command
-Both Displays both the Golden and Revised primary inputs. This is
the default.
-Golden Displays the Golden design primary inputs.
-Revised Displays the Revised design primary inputs.
Command Reference
REPort PRimary Outputs
[-Class <Full | User| System>]
[-Both |-Golden |-Revised]
(Setup / LEC Mode)
Displays primary output pins from the Golden and Revised designs.
Parameters
Related Commands
ADD PRIMARY OUTPUT
-Class Displays the following class of primary outputs.
Full Primary outputs from both the User and
System classes
System Primary outputs from the original design
User Primary outputs added with the ADD
PRIMARY OUTPUT command
-Both Displays both the Golden and Revised primary outputs. This is
the default.
-Golden Displays Golden design primary outputs.
-Revised Displays Revised design primary outputs.
Command Reference
REPORT PULSE GENERATOR
REPort PUlse Generator
[-ALL | MODule <module_name>]
(Setup / LEC Mode)
Reports the instances that were transformed with the SET ABSTRACT MODEL
-transform_pulse_generator_on command.
Parameters
Related Commands
SET ABSTRACT MODEL
-ALL Displays all instances. This is the default.
-MODule Displays a specied module that was transformed.
-Both Applies to both the Golden and Revised designs. This is the
default.
-Golden Applies to the Golden design.
Command Reference
REPORT REMOVED INSTANCE
REPort REMoved Instance
(Setup / LEC Mode)
Report instances removed with the REMOVE command.
Parameters
Related Command
REMOVE
-Golden Reports instances removed from the Golden design. This is
the default.
-Revised Reports instances removed from the Revised design.
Command Reference
REPort REnaming Rule
[ |-MAp | -MOdule | -PIn]
(Setup / LEC Mode)
Displays the list of renaming rules for mapping, module, and pin renaming. These rules were
originally added with the ADD RENAMING RULE command. The list displays a rule number
along with a renaming rule. If you do not enter options, Conformal displays all renaming rules.
Parameters
Related Commands
ADD RENAMING RULE
READ DESIGN
READ LIBRARY
SET MAPPING METHOD
SET NAMING RULE
TEST RENAMING RULE
-MAp Displays only mapping renaming rules. If you do not specify
-map, -module, or -pin, Conformal reports all renaming
rules.
-MOdule Displays only module renaming rules.
-PIn Displays only pin renaming rules.
-Both Displays the renaming rules applied to both the Golden and
-Golden Displays the Golden design renaming rules.
-Revised Displays the Revised design renaming rules.
Command Reference
REPort REtention Mapping
(Setup / LEC Mode)
Reports the retention mapping rules. The set of rules reported include the user rules added
using the ADD RETENTION MAPPING command and the default rule added by the system.
CELLS on page 143.
Note: The default rule is always reported even if no user rule is added using the ADD
RETENTION MAPPING command.
Related Commands
Command Reference
REPORT RULE CHECK
REPort RUle Check
[-All | -MODIfied | rule_name* [-SETTING] ]
[-File <filename> [linenumber]]
[-MODUle <modname>]
[-HELP]
[ | -Design | -Library]
[-Ignore]
[-Note]
[-Warning]
[-Error]
(Setup / LEC Mode)
Displays the list of rule violations after the designs and libraries have been read in. Use the
-summary option to display all of the violated rules.
Use the SET RULE HANDLING command to change the handling of any of these reported
rule violations.
See the Encounter Conformal Equivalence Checking User Guide for rule denitions and
sample cases.
Rules with a severity of Ignore are not reported except with the rule_name or -ignore
options.
Parameters
-All Reports all rule violations encountered in the designs and
libraries.
-MODIfied Reports all the rule check violations that have a different
severity level than the original default.
rule_name Reports specied rule violations. Wildcards are supported.
-SETTING Displays the current severity level for the rule.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
SET RULE HANDLING
-File filename [linenumber]
Reports all rule check messages in a le. With the
linenumber option, you can report all rule check messages
for a specic line number.
-Module modname Reports the rule checks that are specic to the specied
module.
-Summary Display a summary of the rule violations. This is the default.
-Verbose Displays each instance of the rule violation.
-HELP Lists the names and numbers of all HDL rules.
-Design Reports the design rule violations.
If you do not specify -design or -library, the Conformal
software reports rule violations from both designs and libraries.
-Library Reports the library rule violations.
If you do not specify -design or -library, the Conformal
software reports rule violations from both designs and libraries.
-Ignore Reports violations that have a severity level of Ignore.
-Note Reports violations that have a severity level of Note.
-Warning Reports violations that have a severity level of Warning.
-Error Reports violations that have a severity level of Error.
Note: By default, rules with severity levels other than Ignore will be reported
-Both Reports the rule violations from Golden and Revised designs
and libraries. This is the default.
-Golden Reports the Golden design and library rule violations.
-Revised Reports the Revised design and library rules violations.
Command Reference
REPORT SEARCH PATH
REPort SEarch Path
[ | -Design | -Library]
(Setup / LEC Mode)
Displays the paths Conformal searches to locate lenames included in the READ DESIGN
and READ LIBRARY commands.
Parameters
Related Commands
ADD SEARCH PATH
DELETE SEARCH PATH
READ DESIGN
READ LIBRARY
-Design Reports the search path used by the READ DESIGN command.
If you do not specify -design or -library, Conformal
reports the search path used by both the READ DESIGN
command and the READ LIBRARY command.
-Library Reports the search path used by the READ LIBRARY
command.
reports the search path used by both the READ DESIGN
command and the READ LIBRARY command.
-Both Reports the search path used by both the Golden and Revised
-Golden Reports the search path used by the Golden design and library.
-Revised Reports the search path used by the Revised design and
library.
Command Reference
REPORT STATISTICS
REPort STatistics
(LEC Mode)
Summarizes the mapping and comparison statistics for the Golden and Revised designs in a
table.
Related Commands
REPORT COMPARE DATA
Command Reference
REPORT TESTCASE
REPort TEstcase
< [-NONEQ]
[-ABORT]
[-Golden <<gate_id> | <instance_pathname> ...> ]
[-Revised <<gate_id> | <instance_pathname> ...> ]
>
[-DIR_name <directory_name>]
[-NAME | -NONAME]
[-KEYPOINT_DEPTH <number>]
[-REPlace]
(LEC Mode)
Automatically extracts testcases for selected key points and generates a dole and a le
containing mapping information. Running the generated dole can reproduce the problem in
original design, such as non-equivalences and aborts.
Parameters
-NONEQ Species that all non-equivalent points will be selected for
the generated testcase.
-ABORT Species that all abort points will be selected for the
generated testcase.
-GOlden Applies the testcase extraction to the Golden design.
-Revised Applies the testcase extraction to the Revised design.
<gate_id> Species the gate ID of the testcase. You can specify
multiple gate IDs.
<instance_pathname> Species the instance pathname of the testcase. You can
specify multiple instance pathnames.
-DIR_name <directory_name>
Species the name of the testcase directory.
-NAME Includes the names of design objects (nets, instances,
ports) in the generated testcase. This is the default.
-NONAME Does not includes the names of design objects (nets,
instances, ports) in the generated testcase.
-KEYPOINT_DEPTH <number>
Command Reference
Examples
I The following command selects all non-equivalent points, all abort points, and key points
with gate id 10, with instance dlat in the Golden design netlist and the key point with
instance dff in the Revised design netlist, allowing the names of design objects to be
included in the generated testcase:
report testcase -noneq -abort -golden 10 dlat -revised dff
I The following command will select key point with gate id 10 in Revised design netlist for
testcase extraction. The names of design objects will use generic names (gate type and
a serial number)
report testcase -revised 10 -noname
I The following command will select all non-equivalent points for testcase extraction, using
keypoint depth:
report testcase -noneq -keypoint_depth 1
Species the depth of the key points to report. Starting from
the selected key point, the closest key point in its fanin or
fan-out cone is a depth of 1. The default is 3.
-REPlace Overwrites the existing testcase directory.
Command Reference
REPORT TEST VECTOR
REPort TEst Vector
< gate_id | instance_pathname | pin_pathname>
[<gate_id | instance_pathname | pin_pathname> [-Index <integer>]]
[-Golden |-Revised]
| [-NONEQ]
(LEC Mode)
Displays error patterns for a specic nonequivalent compared point.
I The rst argument is the nonequivalent compared point.
This point can be identied with a gate identication number, instance path, or a pin path.
I The second argument, which is optional, is the diagnosis input point. These points are
gates that connect directly to the input ports of the nonequivalent compared point where
the logic cones are different. The display shows the diagnosis input point to the
nonequivalent compared point; corresponding and non corresponding support key
points with their simulation values; and nal simulation result of the diagnosis input point
I The Index option is used to specify which error pattern is displayed after you use the
command. If you do not specify an index number, Conformal displays the rst error
pattern.
You can also use this command with the -noneq option to report error patterns for every
nonequivalent compared key point.
Parameters
gate_id | instance_pathname | pin_pathname
Species the gate identication number, instance path, or pin
path of the nonequivalent compared point.
gate_id |instance_pathname | pin_pathname
Command Reference
Related Command
DIAGNOSE
Species the gate identication number, instance path, or pin
path of the diagnosis input point to the nonequivalent compared
point.
Note: These options apply only to diagnosis points for DFF,
DLAT, and BBOX. If you enter a point that is not a diagnosis
point, Conformal will error out.
-Index integer Displays the specied error pattern. The default is to display
the first error pattern.
-Golden Species that the nonequivalent compared point is from the
-Revised Species that the nonequivalent compared point is from the
Revised design.
-NONEQ Displays the error pattern for every nonequivalent point.
Command Reference
REPORT TIED SIGNALS
REPort TIed Signals
[-ROot | -Module <name>]
[ | -TIE0 | -TIE1 | -TIEZ | -TIEX]
[ | -Net | -Pin]
[-Class <Full | System | User>]
(Setup / LEC Mode)
Displays tied signals from the Golden and Revised designs.
Parameters
-ROot Displays tied signals in the root module. This is the
default.
-Module name Displays tied signals in the specied module.
-TIE0 Displays signals tied to logic 0.
If you do not specify the logic, Conformal displays signals
tied to logic 0, 1, Z, and X.
-TIE1 Displays signals tied to logic 1.
-TIEZ Displays signals tied to logic Z.
-TIEX Displays signals tied to logic X.
-All Displays all net and instance names that have tied signals
assigned to them.
-Net Displays net names that have tied signals assigned to them.
-Pin Displays pin names that have tied signals assigned to them.
Command Reference
Related Commands
ADD TIED SIGNALS
DELETE TIED SIGNALS
-Class Displays this class of tied signals:
Full Tied signals from both the User and
System classes
System Tied signals from the original design.
User Tied signals added with the ADD TIED
SIGNALS command.
-Both Displays tied signals from both the Golden and Revised
-Golden Displays tied signals from the Golden design.
-REvised Displays tied signals from the Revised design.
Command Reference
REPort UNmapped Points
[-SUMmary| -Extra | -UNReachable | -NOTmapped
| [ -TYpe <PI | E | Z | DFf | DLat |CUt | BBox | PO>
|-NOTYpe <PI | E |Z | DFf | DLat |CUt |BBox | PO>]
]
[-GRoup]
[-LIBName | -NOLIBName]
[-RETention]
[-NODLAT_GATED_CLOCK]
[-GOlden | -Revised]
(LEC Mode)
This report lists unmapped points, along with a summary of all of the unmapped points in the
Note: If you do not specify options, Conformal identies all unmapped points and displays a
summary. Furthermore, if you do not specify either Golden or Revised, Conformal reports
unmapped points for both designs.
Parameters
-SUMmary Lists a summary report of all of the unmapped points in the
-Extra Lists extra points. These points are unmapped because they do
not map with a counterpart in the comparison design. Extra
points do not affect the circuit.
-UNReachable Lists unreachable unmapped points. Unreachable key points
are those that do not eventually affect the primary output of the
design.
-NOTmapped Lists Not-mapped unmapped key points.
Not-mapped key points are those that failed to be mapped.
-Type Lists unmapped points of the specied type. Available types are
as follows:
PI Primary input
E TIE-E
Z TIE-Z
DFf D ip-op
Command Reference
DLat D-latch
CUt All unmapped points for articial gates that
BBox Blackbox
PO Primary output
-NOType Does not list unmapped points of the specied type.
-GRoup Displays the unmapped groups in which either the Golden or
Revised key point is a group of equivalent gates rather than a
single gate.
The group can be dened with the ADD INSTANCE
EQUIVALENCE command or the -seq_merge option of the
SET FLATTEN MODEL command.
A key point group is counted as one key point.
-LIBName When displaying unmapped points, includes sufxes. This is
the default.
-NOLIBName When displaying unmapped points, does not include sufxes.
If the unmapped point is a sequential element (DFF or DLAT)
and belongs to the Golden Design, this option reports the
tag-name (if any) associated with the DFF or DLAT. If the
unmapped point is a sequential element (DFF or DLAT) and
belongs to the Revised Design, this option reports the power
gating cell attribute (if any) associated with the DFF or DLAT.
For non-sequential elements, nothing is reported.
The sequential unmapped points are not written out during the
CHECK RETENTION MAPPING command, but if present, they
are reported as Not-Checked in the summary section.
-NODLAT_GATED_CLOCK Does not report deglitching clock-gating DLATs under the
Unreachable category.
-GOlden Lists only the Golden unmapped points. This is the default.
-Revised Lists only the Revised unmapped points.
Command Reference
Related Commands
ADD MAPPED POINTS
MAP KEY POINTS
REPORT STATISTICS
SET MAPPING METHOD
SET NAMING RULE
Command Reference
REPORT VERIFICATION
REPort VErification
[-Verbose]
[-Summary]
(LEC Mode)
Reports a table of all violated checklist items for the following categories:
1. Non-standard modeling options used:
Tristated output: checked/not checked
Revised X signals set to E: yes|no
Floating signals tied to Z: yes|no
Command add clock for clock-gating used: yes|no
2. Incomplete verication:
All primary outputs are mapped: yes|no
All mapped points added as compare points: yes|no
All compare points compared: yes|no
User added black box: yes|no
Black box mapped with different module name: yes|no
Command add ignore outputs used: yes|no
3. Modication to design:
Change gate type: yes|no
Change wire: yes|no
Primary inputs added: yes|no
4. Conformal extended checks recommended:
FSM encoding: used|not used
RTL5.1 Overlapped case items in parallel case statement: used|not used
RTL5.4 Partial case items in full case statement: used|not used
Multiple clocks in the design: yes|no
Command Reference
5. Design ambiguity:
Duplicate module denition: yes|no
Black box due to undened cells: yes|no
6. Compare results: FAIL|ABORT|INCOMPLETE|<number> EQ|NOT_COMPARED
Number of EQ compare points: <number>
Number of NON-EQ compare points: <number>
Number of Aborted compare points: <number>
Number of Uncompared compare points: <number>
Parameters
Related Command
COMPARE
-Verbose Prints out each category and the count of violations.
-Summary Prints all items for each category and the violated items are
marked with an asterisk (*).
Command Reference
RESET
RESET
(Setup / LEC Mode)
Resets the system to the initial state. All existing designs and libraries are deleted, and all
previously issued commands are cancelled.
Related Commands
EXIT
Command Reference
REset ABSTract Model
[-ALL | -MODule <module_name>]
(Setup / LEC Mode)
Resets the abstraction conditions that you set using the SET ABSTRACT MODEL command.
Parameters
Related Commands
ABSTRACT LOGIC
SET ABSTRACT MODEL
-All Resets abstraction conditions for all modules.
-MODule module_name
Resets abstraction conditions for the specied modules.
-Both Resets abstraction conditions for both the Golden and Revised
-Golden Resets abstraction conditions for the Golden design.
-Revised Resets abstraction conditions for the Revised design.
Command Reference
RESet HIer_compare Result
(Setup / LEC Mode)
Resets the results of the hierarchical comparison. It is useful when you do multiple
hierarchical compare runs and you wish to display the results of each hierarchical compare
separately.
Related Commands
RUN HIER_COMPARE
RESET
Command Reference
RESOLVE
RESolve
<module_name>
[-All]
(Setup Mode)
Ungroups a module in the Golden or Revised design hierarchy. Resolving or ungrouping is
the process of eliminating a module and promoting its content up one level of the hierarchy.
Parameters
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD MOS DIRECTION
ADD NET ATTRIBUTE
DELETE CLOCK
READ PATTERN
REPORT CLOCK
module_name Resolves hierarchy for the specied module.
-All Resolves the specied module within all hierarchies of the
specied design.
-Golden Resolves hierarchy in the Golden design. This is the default.
-Revised Resolves hierarchy in the Revised design.
Command Reference
UNIQUIFY
Command Reference
RESTORE SESSION
REStore SEssion
<session_name>
(Setup / LEC Mode)
Restores a session you previously initiated and saved using the SAVE SESSION command.
Before entering this command, Conformal must be in its initial state. Therefore, you must
either use the RESET command, or exit Conformal and restart it.
Important
You must run this restarted session on the same platform and same Conformal
version.
Parameters
Related Commands
RESET
SAVE SESSION
session_name Restores the specied session.
Command Reference
RUN HIER_COMPARE
RUN HIer_compare
<dofile_name>
[-ROOT_module <golden_module> <revised_module>]
[-DYNamic_hierarchy | -NODYNamic_hierarchy]
[-NOREStart | -REStart]
[-ANALYZE_abort]
[-RETIMED_modules [-TOP | -NOTOP]]
[-BREAK_NONEQ]
[-BREAK_ABORT]
[-ANALYZE_BOUNDARY_conditions | -NOANALYZE_BOUNDARY_conditions]
[-VERBOSE]
(Setup Mode)
Runs dynamic hierarchical comparison. This command on completion produces one of the
following three statuses:
I Equivalentall the compared modules are equivalent.
I Non-Equivalentat least one of the compared module is non-equivalent.
I Inconclusiveindicates one of the following conditions:
at least one of the compared module has abort points
at least one module is not-compared (for example, due to running the add module
attribute -compare_effort none command)
at least one module has incomplete compare result (for example, due to extra
primary outputs)
Note: When the status is Inconclusive the number of abort modules, not-compared
modules, or modules that have incomplete compare result are reported.
For more information, see Dynamic Hierarchical Comparison in the Encounter Conformal
Equivalence Checking User Guide.
<dofile_name> Species the name of the hierarchical dole that was generated
with the WRITE HIER_COMPARE DOFILE command.
Note: Cadence does not recommend manually editing or
modifying this hierarchical dole prior to running the RUN
HIER_COMPARE command. This might lead to unexpected
results. If you want to edit or modify the hierarchical dole, use
the static hierarchical comparison (dofile hier.do).
Command Reference
-ROOT_module <golden_module> <revised_module>
Uses the specied modules as the root modules. This is similar
to the -Module option with the WRITE HIER_COMPARE
DOFILE command without having to the regenerate the dole.
-DYNamic_hierarchy
Auto-attens the submodules to propagate any design errors to
the top level. The attened modules are merged to the next
level in the hierarchy and compared at that level. This is the
default.
-NODYNamic_hierarchy
Runs static hierarchical comparison without auto-attening the
submodules.
Note: Do not use this option if the hierarchical dole is
generated using the WRITE HIER_COMPARE DOFILE
-run_hier_compare command.
-NOREStart Continues an interrupted session, preserving the previous
compare results. This is the default.
You can interrupt dynamic hierarchical comparison by pressing
Ctrl-c.
-REStart Deletes the previous comparison results.
-ANALYZE_abort Inserts the ANALYZE ABORT -compare command into each
uncompared and aborted modules compare script.
Command Reference
Examples
I The following command uses the hier.do dole for hierarchical comparison:
run hier_compare hier.do
If the previous comparison run of the hier.do dole resulted in three aborted modules,
you can run a second comparison using the following command:
-RETIMED_modules [-TOP | -NOTOP]
Compares and blackboxes the submodules with the
PIPELINE_Retime attribute. The PIPELINE_Retime
attribute can be attached to a module using the ADD MODULE
ATTRIBUTE command. For this option to work correctly,
modules with PIPELINE_Retime attribute should exist in the
hierarchical dole script.
-TOP runs the comparison of the top module such that
submodules without the PIPELINE_Retime attribute are fully
attened. This is the default for -RETIMED_module.
-NOTOP species that comparison stops after the modules with
the PIPELINE_Retime attribute have been compared and
blackboxed. The hierarchical result is reported as Inconclusive
because the entire design is not compared.
-BREAK_NONEQ The comparison stops when it encounters a non-equivalent
module. To continue comparing from the next module in the
hierarchy, use the RUN HIER_COMPARE command.
-BREAK_ABORT The comparison stops when it encounters an abort module. To
continue comparing from the next module in the hierarchy, run
the RUN HIER_COMPARE command.
-ANALYZE_BOUNDARY_conditions
Reduces the number of attened modules by resolving
boundary constraints. This is the default.
-NOANALYZE_BOUNDARY_conditions
Does not perform resolution on boundary constraints.
Note: Do not use this option if the hierarchical dole is
generated using the WRITE HIER_COMPARE DOFILE
-run_hier_compare command.
-VERBOSE Lists all the hierarchical constraints and additional information.
Command Reference
run hier_compare hier.do -analyze_abort
This command only operates on aborted modules from the previous run, and
automatically runs the ANALYZE ABORT -compare command after the default
COMPARE command.
I The following command uses m4 as the root module for both the Golden and Revised
designs, deleting the previous comparison results:
run hier_compare hrcmod.do -root_module m4 m4 -restart
I The following command runs hierarchical comparison on modules with the
PIPELINE_Retime attribute attached:
run hier_compare hier.do -retimed_modules
Related Commands
ANALYZE ABORT
COMPARE
Command Reference
RUN PArallel Compare
[-NONEQ_Stop <integer>]
[-ABORT_Stop <integer>]
[-NONEQ_Print]
[-ABORT_Print]
[-GATE_TO_GATE]
[-TEST]
[-SUBMIT_OPTIONs <string>]
[-DPL]
(LEC Mode)
Runs equivalency checking comparison between the Golden and Revised designs on the
added compared points using parallel processing. During the comparison, the Conformal
software displays following information:
I A progress percentile number that shows the completion rate
I A running count that shows the number of key points that have been compared along
with the total number of non-equivalent key points
Parameters
-NONEQ_Stop Stops the comparison after nding the specied number of
-ABORT_Stop Stops the comparison after nding the specied number of
abort points.
-NONEQ_Print Displays the non-equivalent points as they are found.
-ABORT_Print Displays the abort points as they are found.
-GATE_TO_GATE Enables an algorithm that might improve the run time of large
gate-to-gate netlist comparisons.
-TEST Launches qualication run to test if the environment is suitable
for parallel processing.
-SUBMIT_OPTIONs Species the options which will replace the keyword
<submit_options> in the submit command line (see the SET
PARALLEL OPTION -SUBMIT_COMMAND_LINE command).
Command Reference
Examples
The following commands run the rst parallel job in queue q1, and the second parallel run in
queue q2.
run parallel compare -submit_options "-q q1"
run parallel compare -submit_options "-q q2"
Related Commands
COMPARE
SET PARALLEL OPTION
-DPL Uses the Cadence Distributed Processing Library (DPL) to
interface to the Load Sharing Facility (LSF) daemon. Refer to
the Cadence DPL User Guide for more information.
Command Reference
RUN PARTITION_COMPARE
RUN PArtition_compare
[-Keypoint <identifier...>]
[-Number <number>]
[-VERBOSE]
(LEC Mode)
Runs comparisons with functional partitioning. You can specify partitioned key points in the
Golden design and the number of key points for a partition. If no key points are specied, this
command will automatically choose appropriate key points for the partition.
Note: You do not need to switch to Setup mode to atten the netlist in each partition iteration.
With the constants assigned on the selected key points, comparison can become easier in
each partition iteration.
For example, when abort points are encountered in comparison, you can run this command
to do functional partitioning for the abort points.
Related Commands
COMPARE
-Keypoint Species the partition key point in the Golden design. The key
point can be specied by gate instance pathname or gate ID. If
no key points are specied, this command will automatically
choose appropriate key points for the partition.
-Number Species the number of key points for a partition. The maximum
number of compare iterations is the base-2 exponent of the
partitioned key point number. The default partitioned key point
number is 8.
-VERBOSE Provides additional information in the functional partition.
Command Reference
SAVE DOFILE
SAVe DOfile
<filename>
[-Replace]
(Setup / LEC Mode)
Saves the commands entered during the current session to a le. Use the saved dole later
as a batch le to repeat the Conformal session.
When running a Conformal session from a dole, this command does not save individual
commands included in a separate dole (that is, Conformal saves the manually entered
commands, which can include a dofile <filename> command).
Note: If the lename you specify already exists, you must use either the -replace or
-append option.
Related Commands
DOFILE
SET COMMAND PROFILE
SET LOG FILE
filename Writes the dole to the specied le.
-Replace Replaces the contents of the specied preexisting le.
Command Reference
SAVe HIer_compare Result
(LEC Mode)
Saves the hierarchical comparison results of the module comparison. If the WRITE
HIER_COMPARE DOFILE command is used, this command is placed after every module
compared.
After the hierarchical comparison of all modules is complete, use the REPORT
HIER_COMPARE RESULT command to display the results of the hierarchical comparison.
Related Commands
RUN HIER_COMPARE
Command Reference
SAVE SESSION
SAVe SEssion
[-REPlace]
<session_name>
(Setup / LEC Mode)
Saves your session up to a current point and outputs the session le in gzip format. You can
then restore the session later using the RESTORE SESSION command. You can use this
command if priorities demand that another session preempt your session.
Important
When you use the RESTORE SESSION command, you must run the restarted
session on the same platform and same Conformal version.
Parameters
Related Command
RESTORE SESSION
-REPlace Replaces the existing session. If the session already exists, it
will be overwritten and no backup copy will be created.
By default, backup copies are created automatically.
This option is useful if you want to save disk space and only
need to save your session occasionally.
session_name Attaches this session name to the saved session.
Command Reference
SEARCH
SEArch
[-USage] <string1> [<string2>]
(Setup / LEC Mode)
Searches the database of commands and parameters, and displays those commands that
match all of the specied strings. Strings can be specied in any order; however, every
specied string must match.
Parameters
Related Command
HELP
-USage Displays the commands that have parameters that match the
search string. This outputs the entire command syntax for each
command.
string1 Displays commands that match the specied string.
string2 Displays commands that match additional specied strings.
Command Reference
SET ABSTRACT MODEL
SET ABSTract Model
[-ALL |-MODule <module_name>]
[-NOKEEPER2PUllup | -KEEPER2PUllup ]
[-NOWEAKPULLUP | -WEAKPULLUP ]
[-NOWEAKPULLDOWN | -WEAKPULLDOWN ]
[-NOKEEPERSTate | -KEEPERSTate ]
[-NODYNSTate | -DYNSTate ]
[-NOPRE_CHARGE_KEEP_Clock | -PRE_CHARGE_KEEP_Clock ]
[-NODOMINOLATch | -DOMINOLATch ]
[-Bulk | -NOBulk ]
[-NOMEM_BL_EQualizer | -MEM_BL_EQualizer]
[-NOBUF_AMP | -BUF_AMP]
[-NOMULTICLOCKPRECHARGE | -MULTICLOCKPRECHARGE]
[-REPHASE_BY_NAME_POSitive <name>] [-REPHASE_BY_NAME_NEGative <name>]
[-TRANSFORM_PULSE_GENERATOR_ON]
[-NOIGNORE_DLAT_CONTENTION | -IGNORE_DLAT_CONTENTION]
[-Both | -Golden | -Revised ]
(Setup Mode)
Specify certain conditions for abstracting transistor logic.
information about using this command in the Conformal Custom ow.
Parameters
-ALL Abstracts transistor logic from all modules within the given
defaults. This option is the default.
-MODule module_name
Abstracts transistor logic from the specied modules.
-NOKEEPER2PUllup Does not regard charge keepers as weak pull-up devices.
-KEEPER2PUllup Regards charge keepers as weak pull-up devices.
-NOWEAKPULLUP Does not regard devices that are tied to PMOS as weak
devices. This is the default.
-WEAKPULLUP Regards devices that are tied to PMOS as weak devices.
-NOWEAKPULLDOWN Does not regard devices that are tied to NMOS as weak
devices. This is the default.
Command Reference
-WEAKPULLDOWN Regards devices that are tied to NMOS as weak devices.
-NOKEEPERSTate Does not regard charge keepers as latches. This is the
default.
-KEEPERSTate Regards charge keepers as latches.
-NODYNSTate Does not regard tristate table nets as latches. This is the
default.
-DYNSTate Regards tri-statetable nets as latches.
-NOPRE_CHARGE_KEEP_Clock
In domino logic, does not regard pre-charge clocks as part of
the logic function. This is the default.
-PRE_CHARGE_KEEP_Clock
For domino logic, regards pre-charge clocks as part of the
logic function.
This option includes the dened pre-charge clock in the
abstracted logic function (the default behavior removes the
dened pre-charge clock from the abstracted logic). This is
indicated when you dene a precharge clock with one of the
following commands:
add net attribute CLOCK0 | CLOCK1
add clock 0 | 1
When you use -pre_charge_keep_clock, the resulting
logic is equivalent to RTL that explicitly models the pre-charge
condition, rather than RTL that models only the evaluate
function. In the latter, the output function is not dened during
pre-charging.
-NODOMINOLATch Does not abstract pre-charge logic functions as a latch. This
is the default.
-DOMINOLATch Abstracts pre-charge logic functions as a latch. This assumes
that data input is stable in active clocks.
-BULK Identies nets connected to PMOS bulk terminals as power
and nets connected to NMOS bulk terminals as ground. This
is the default.
Command Reference
-NOBULK By default, Conformal Custom identies nets connected to
PMOS bulk terminals as power and nets connected to NMOS
bulk terminals as ground. However, this option removes that
assumption and you will need to specify power and ground
pins/nets by using *.GLOBAL <name>:P for power nets and
*.GLOBAL <name>:G for ground nets or use Conformal
commands to add constraints, tied signals (pins), or net
attributes.
Important
You must use SET ABSTRACT MODEL -NOBulk
before reading in the SPICE le.
-NOMEM_BL_EQualizer
Does not handle bit-line pre-charge, and equalization. This is
the default.
-MEM_BL_EQualizer Handles circuits that include bit-line pre-charge, and
equalization.
-NOBUF_AMP Does not handle buffered-type sense ampliers, level shifters,
pre-charge, and equalization. This is the default.
-BUF_AMP Handles the following portions of a circuit: buffered-type sense
ampliers, level shifters, pre-charge, and equalization.
-NOMULTICLOCKPRECHARGE
Does not propagate clocks through logic gates which have
more than one clock input. This is the default.
-MULTICLOCKPRECHARGE
Propagates clocks through logic gates which have more than
one clock input.
Command Reference
-REPHASE_BY_NAME_POSitive <name>
Gives abstract logic a hint about the desired phase of
state elements, such as D-latches and DFFs. When
abstracting state elements, abstract logic will choose a
phase for each state element, where <name> species the net
which will be driven by the Q pin, if possible.
If this is not possible, then abstraction will try to choose a net
for the Qn pin which has a name specied by the
-REPHASE_BY_NAME_NEGative option.
Note: The set mapping method commands -phase option
will allow mapping and comparison of state elements with
different phases in the Golden and Revised designs. Consider
running set mapping method -phase before using this
option, as it requires less effort.
-REPHASE_BY_NAME_NEGative <name>
Species the net which will be driven by the Qn pin, if
possible.
-TRANSFORM_PULSE_GENERATOR_ON
Enables pulse transformation.
-NOIGNORE_DLAT_CONTENTION
Stops forming the D-Latch when contention on a net is
detected. This is the default.
-IGNORE_DLAT_CONTENTION
Continues to form the D-Latch, even if contention on a net is
detected.
By default, the SET ABSTRACT MODEL command stops the
execution of abstraction of latches and ip-ips (state
elements) when a power to ground through a stack of active
ON transistors is possible. Use this option to report the short
and continue to abstract the state element.
-Both Species abstraction conditions for both the Golden and
-Golden Species abstraction conditions for the Golden design.
-Revised Species abstraction conditions for the Revised design.
Command Reference
Examples
Sample Dole:
read design test.v -golden
set abstract model -keeper2pullup -weakpullup -golden
report abstract model -golden
abstract logic
Related Commands
ABSTRACT LOGIC
ADD CLOCK
ADD NET ATTRIBUTE
REPORT PULSE GENERATOR
Command Reference
SET ANALYZE OPTION
SET ANalyze Option
[-NOAUTO
| -AUTO [-ANALYZE_SETUP | -NOANALYZE_SETUP]
[-ANALYZE_ABORT | -NOANALYZE_ABORT]
]
(Setup Mode)
Automatically determines the best place to run the ANALYZE SETUP command. In addition,
the Conformal software automatically runs the ANALYZE ABORT command whenever the
comparison returns abort points but no non-equivalent points.
Parameters
Related Command
ANALYZE ABORT
ANALYZE SETUP
-NOAUTO Disables automatic analysis. This is the default.
-AUTO Enables automatic analysis.
-ANALYZE_SETUP Enables automatic setup analysis. This is the default when
running this command with the -AUTO option.
-NOANALYZE_SETUP Disables automatic setup analysis.
-ANALYZE_ABORT Enables automatic abort point analysis. This is the default.
-NOANALYZE_ABORT Disables automatic abort point analysis.
Command Reference
SET_ATTR INPUT_PRAGMA_KEYWORD
SET_ATtr INPUT_PRAGMA_Keyword
<string>
(Setup Mode)
Species a keyword that the Conformal software must consider as an input pragma when it
encounters it as the rst word in a Verilog or VHDL source comment.
A pragma is a comment in the Verilog or VHDL source and is set off fromordinary comments
by the pragma keyword. The pragma keyword is the rst word listed in a pragma, and it
noties the Conformal software that the remainder of the comment is a command and not a
comment. Changing this keyword allows you to set up compatibility with other tools.
Parameters
Examples
Sample Dole:
set_attr input_pragma_keyword rtl
set synthesis_off_command turn_off
set synthesis_on_command turn_on
After running these three commands, the Conformal and VHDL parsers will recognize the
pragmas in the VHDL and Verilog Source les.
In a VHDL le, the code between -- rtl turn_off and -- rtl turn_on will not be
synthesized.
In a Verilog le, the code between // rtl turn_off and // rtl turn_on will not be
synthesized.
Related Commands
SET SYNTHESIS_OFF_COMMAND
SET SYNTHESIS_ON_COMMAND
string Species the name of the keyword for a tool vendor.
Default: pragma, synthesis, synopsys, cadence, ambit,
verplex, conformal
Command Reference
SET CASE SENSITIVITY
SET CAse Sensitivity
<ON | OFf>
(Setup Mode)
Species whether names you enter are case sensitive. The system default is no case
sensitivity for both the Golden and Revised designs.
Execute this command before READ LIBRARY and READ DESIGN. Use the REPORT
ENVIRONMENT command to display the case sensitivity setting.
Parameters
Related Command
REPORT ENVIRONMENT
ON Names that are entered are case sensitive.
OFf Names that are entered are not case sensitive. This is the
system default.
Command Reference
SET COMMAND PROFILE
SET COmmand PRofile
[OFF | ON]
(Setup / LEC Mode)
Starts or stops recording a prole of commands executed in Conformal. This command
records the order of command execution and the memory use. The prole includes
commands used in the GUI mode.
Use the REPORT COMMAND PROFILE command to view the prole.
Parameters
Related Commands
SET LOG FILE
OFF Stops tracking executed commands. This is the default.
ON Starts tracking executed commands.
Command Reference
SET COMPARE EFFORT
SET COmpare Effort
<Low | Medium | High | Auto>
(Setup / LEC Mode)
Species the amount of effort equivalency checking applies to the key points comparison. If
you know your designs have many complex key points, increase the effort level. However,
when you raise the effort level, you also increase the amount of time involved in checking.
Hence, you increase the total CPU time.
Use the REPORT ENVIRONMENT command to display the compare effort setting. The
system default is set to low compare effort.
Parameters
Related Commands
COMPARE
REPORT ENVIRONMENT
Low Applies minimal effort to equivalency checking for each gate.
Medium Applies greater effort to equivalency checking for each gate.
High Applies the maximum effort to equivalency checking for each
gate.
Auto Starts with low effort and automatically increases the compare
effort when abort points are present in the design.
Command Reference
SET COMPARE OPTIONS
SET COmpare Options
[-GENLATCH | -NOGENLATCH]
[-NOALLGENLATCH | -ALLGENLATCH]
[-VERIFY_Disabled_ports]
(Setup / LEC Mode)
Turns on options to the comparison process.
Parameters
-GENLATCH Compares latches as generic latches by analyzing all logic
cones simultaneously. The software automatically determines
which latches are to be compared as generic latch, and the
reset are compared by individual logic cones. This is the
default.
With this option, you can compare latches that are truly
functionally equivalent, even though the logic cones of the
separate input pins are not.
-NOGENLATCH Species that no latch is compared as a generic latch. All
latches are compared by individual logic cones.
-NOALLGENLATCH Does not compare all latches as generic latches. This is the
default.
This option has no effect when using -NOGENLATCH.
Note: The input cones compared are set cones, reset cones,
clock cones, and data cones.
-ALLGENLATCH Compares all latches as generic latches.
This option has no effect when using -NOGENLATCH.
-VERIFY_Disabled_ports
Compares data cones even if their clocks are disabled. By
default, a data cone will not be compared if its corresponding
clock port is tied to a constant (for DFFs) or to zero (for latches).
Note: You should use this command option before running the
rst COMPARE command. If you use this after running COMPARE,
this option has no effect.
Command Reference
Related Command
COMPARE
Command Reference
SET CPU LIMIT
SET CPu Limit
<integer> <-Days | -Hours | -Minutes>
[-NOKill]
[-WALLTIME]
(Setup / LEC Mode)
Species the time limit for the compare effort. The systemdefault is 525,600 minutes. Set the
time limit for minutes, hours, or days.
Use the REPORT ENVIRONMENT command to display the setting for the CPU time limit.
Note: When the Conformal software reaches the specied CPU limit, it stops all processing
and exits.
Parameters
Example
The following commands show an example of using the SET CPU LIMIT command with and
without the -WALLTIME option.
The time is 11:00 amand you start two Conformal sessions on the same machine, executing
the same dole, that will run more than 20 minutes. You set the time limit for session 1 in real
clock time with the following command:
set cpu limit 10 -minutes -walltime
You set the time for session 2 at the same limit but without using the real clock time with the
following command:
set cpu limit 10 -minutes.
integer Species a positive integer for the CPU time limit.
-Days Species that the CPU time limit refers to days.
-Hours Species that the CPU time limit refers to hours.
-Minutes Species that the CPU time limit refers to minutes.
-NOKill Prevents the software from exiting. This returns the command
prompt.
-WALLTIME Species that the time limit is in real clock time.
Command Reference
At 11:10, session 1 will terminate because the real clock time has elapsed 10 minutes.
However, session 2 might not terminate because the real time it consumed during this 10
minutes is less than 10 minutes if some of the time is consumed by other processes running
on the machine.
Related Command
REPORT ENVIRONMENT
Command Reference
SET DATAPATH OPTION
SET DAtapath Option
[-MERGE |-NOMERGE]
[-NOAUTO |-AUTO [-MODULE [-RESOURCEFILE <filename>]]
]
[-NOSHARE | -SHARE]
[-NOADDERTREE | -ADDERTREE]
[-EFFort <MEDium | HIgh>]
[-Verbose]
(Setup / LEC Mode)
Species whether Conformal automatically analyzes data paths on switching from Setup to
LEC mode and whether to apply operator merging. The results of the analysis enable
Conformal Ultra to automatically resolve multipliers, operator merging, and resource sharing
problems.
Note: You cannot run datapath analysis without rst mapping the Revised design keypoints
to the Golden design keypoints.
Parameters
-MERGE Automatically applies the operator merging technique when
switching from Setup to LEC mode. This is the default.
-NOMERGE Does not automatically apply the operator merging technique
when switching from Setup to LEC mode.
-NOAUTO Does not automatically analyze data paths when switching from
Setup to LEC mode. This is the default.
-AUTO Automatically analyzes data paths when switching from Setup
to LEC mode. This also performs additional carry-save adder
(CSA) analysis.
-MODULE Automatically applies analysis on the datapath modules in the
Revised design netlist.
-RESOURCEFILE <filename>
Species the resource lename to analyze the datapath
modules.
-NOSHARE Does not apply the resource sharing technique. This is the
default.
-SHARE Analyzes the design for datapath resource sharing.
Command Reference
Examples
I The following command applies module-based datapath analysis followed by the
operator-level datapath analysis when switching from Setup to LEC mode:
set datapath option -auto -module -verbose
set system mode lec
I The following command applies operator-level datapath analysis when switching from
Setup to LEC mode:
set datapath option -auto
set system mode lec
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
SET FLATTEN MODEL
-NOADDERTREE Does not automatically add parentheses to the input operands
of adder trees when switching fromSetup to LEC mode. This is
the default.
-ADDERTREE Automatically adds parentheses to the input operands of adder
trees when switching from Setup to LEC mode.
-EFFort <MEDium | HIgh>
Species the effort level. Choose MEDium (the default), or HIgh
to help provide better analysis of some multipliers, but can
increase the analysis runtime.
Command Reference
SET DIRECTIVE
SET DIrective
<ON | OFf>
[[synthesis | vendor_name] directives]
[-file <file_name*>]
(Setup Mode)
Species whether to enable or disable the effects of the specied synthesis directives when
reading in a Verilog or VHDL le. If you enter this command and do not specify any directives,
this command enables (or disables) all of the directive effects. The system default enables
all directives. (Thus, if you want Conformal to enable all directives, no action is necessary
on your part.)
Execute this command before READ LIBRARY and READ DESIGN.
For each disabled directive used in the HDL source code, Conformal responds as follows:
I If the directive is supported but disabled, Conformal returns a message stating the
directive is disabled.
I If the directive is unsupported and disabled, Conformal returns a message stating that
the directive is unsupported.
Conformal Directives
The following information includes short descriptions and examples of four supported
Conformal directives.
I clock_hold <name>
This directive instructs Conformal to synthesize latch arrays so that the array address is
placed into the clock cone of the synthesized logic.
Example:
// conformal clock_hold memory_array
always @(clk or we or addr or din) begin
if (clk && we) memory_array[addr] = din;
end
Without this directive, the above always process results in a latch array with both clk
and we in the clock logic. And addr is used to mux between din and the old state.
Thus, with this directive, we move the addr into the clock logic of the array. This
directive is useful for register les and memory arrays.
Command Reference
I infer_latch
This directive instructs Conformal to use a D-latch instead of a DFF when there is an
always statement with an edge-triggered clock. The default is to use a DFF.
Example:
always @(posedge clk) begin // conformal infer_latch
qstate = din;
end
In this example, the infer_latch directive tells Conformal to synthesize a latch
enabled with a high clock (rather than a D ip-op with a positive edge triggered clock)
for the always process. It is similar to writing the following RTL:
always @(clk or din) begin
if (clk) qstate = din;
end
I multi_port
This directive instructs Conformal to synthesize a multi-port latch or register when
multiple, simultaneous denitions exist for the same state variable.
Example:
always @(clk1 or din1) if (clk1) qstate = din1;
always @(clk2 or din2) if (clk2) qstate = din2;
always @(clkn or dinn) if (clkn) qstate = dinn;

This sample case results in n number of latches, each with separate clocks and data
inputs and all outputs wired together. However, the implementation of a multiport cannot
be compared with an n port latch. Thus, you would use the // conformal
multiport qstate directive to synthesize an n port latch with one Q output.
Internally, a primitive UDP model represents the valid function. If a simultaneous write
occurs on multiple ports and the input data on those ports is not equal, the state
becomes an X. This directive is generally used for multi-port memory arrays and custom
designs.
I mem_rowselect
This directive supersedes the clock_hold directive. It guides memory array RTL
model synthesis so that it includes the same logic in the clock and data cones as in the
implementation. Thus, Conformal can complete equivalence checking.
Example:
// conformal mem_rowselect mem clk addr[7:5] addr[2:0]
Command Reference
always @(clk or we or addr or din) begin
if (clk && we) mem[addr] = din;
end
The synthesized result creates a row decoder with address bits 7, 6, 5, and 2, 1,
0, and used clk as an enable. The addr bits 3 and 4 are used to column multiplex
input data when we is active. However, when we is not active or a column is selected,
the array data input is in a high Z state, which is representative of memory
implementation.
I one_hot/one_cold/zero_one_hot/zero_one_cold "<name>..."
This directive instructs Conformal to adds one-hot constraints on specied net path. The
one_hot and zero_one_hot constraints let only zero or one net be at a 1-state and
the remaining nets be at a 0-state. The one_cold and zero_one_cold constraints let
only zero or one net be at a 0-state, and the remaining nets be at a 1-state.
In the following example, only zero or one of net aa and bb is constrainted to be
1-state, and the other one is constrainted to be at 0-state:
// pragma one_hot "aa, bb"
Note: The wildcard (*) represents any zero or more characters in lenames.
Parameters
ON Enables the specied directives. (The initial system default
enables all directives.)
OFf Disables the specied directives. If you do not specify
directives, all directives are disabled.
synthesis Enables (or disable) the specied Synplicity synthesis
directives.
Command Reference
vendor_name Enables (or disable) the specied synthesis directives when
they are used with the specied vendor_name prex.
Supported vendor_names are listed below:
I cadence
I synopsys
I ambit
I quickturn
I verplex
I conformal
Command Reference
directives Enables (or disables) the specied synthesis directives. If you
do not specify any directives, all directives are enabled (or
disabled), accordingly. Supported directives are listed below.
I assertion_library
I black_box
I built_in
I clock_hold
I compile_off
I compile_on
I dc_script_begin
I dc_script_end
I divider
I enum
I full_case
I infer_latch
I mem_rowselect
I multi_port
I multiplier
I operand
I parallel_case
I pragma
I state_vector
I synthesis_off
I synthesis_on
I template
I translate_off
I translate_on
-File file_name* Enables (or disables) a list of directives that are specied in a
RTL le. This option supports wildcards.
Command Reference
Examples
Enabling Directives
The Conformal, Synopsys, and Ambit directives are enabled by default. The Quickturn
directives are disabled by default. To recognize the Quickturn directives, you must rst turn
on all of the directives for Quickturn using the following command:
set directive on quickturn
Enabling One Directive
When you employ the SET DIRECTIVE command and you do not specify a directive, the
command applies to all directives. In the following example, the objective is to enable only the
parallel_case directive. To do so, rst disable all directives, then enable the specied
directive (parallel_case).
//disable all directives
set directive off
//enable parallel_case
set directive on parallel_case
Disabling All Directives for One Vendor
In the following example, the objective is to disable all Synopsys directives (synopsys
translate_off, synopsys translate_on, synopsys full_case).
//disable all synopsys directives
set directive off synopsys
Disabling Specied Directives for One Vendor
In the following example, the objective is to disable synopsys translate_off and
synopsys translate_on. This command has no effect on conformal
translate_off and conformal translate_on.
//disable synopsys translate_off and synopsys translate_on
set directive off synopsys translate_off translate_on
Enabling a List of Directives from an RTL File
In the following examples, we have 2 RTL les: test.v and test1.v.
I In the following command, the synthesis directive parallel_case is on (enabled) in le
test.v:
Command Reference
set directive on parallel_case -file test.v
I In the following command, the synthesis directive parallel_case is on (enabled) in le
test.v and test1.v:
set directive on parallel_case -file *.v
Related Commands
READ DESIGN
READ LIBRARY
Command Reference
SET DOFILE ABORT
SET DOfile Abort
<ON | OFf | Exit>
(Setup / LEC Mode)
Species how Conformal handles the dole when an error message occurs.
I If the dole abort handling is set to On, the dole terminates when an error message
occurs. This is the default.
I If the dole abort handling is set to Off, the dole continues even if an error message
occurs.
I If the dole abort handling is set to Exit, the session exits when an error message occurs.
Parameters
Related Commands
BREAK
CONTINUE
DOFILE
ON Terminates the dole if an error message occurs. This is the
default.
OFf Continues the dole even if an error message occurs.
Exit Exits the session if an error message occurs.
Command Reference
SET EXIT CODE
SET EXit Code
[-CLEAR]
[-VERBOSE]
[ | -INTERNAL_ERROR | -NOINTERNAL_ERROR]
[ | -COMMAND_ERROR | -NOCOMMAND_ERROR]
(Setup / LEC Mode)
Controls and displays the exit code for the Conformal session. This command is useful when
running a complex ow, such as hierarchical comparison and iterative comparison.
Parameters
Examples
I The following command displays current exit code:
set exit code
I If a failing comparison was followed by a passing comparison (after xing some
constraints), bit 4 in the exit code is still non-zero. However, the following command
clears the exit code and displays a table listing the status codes and decimal exit code:
set exit code -clear -verbose
I The following command set command error bit to 1:
set exit code -command_error
-CLEAR Clears the exit code to only reect most current running status.
-VERBOSE Displays a table listing the status codes.
-INTERNAL_ERROR Sets the internal error bit.
-NOINTERNAL_ERROR Clears the internal error bit.
-COMMAND_ERROR Sets the command error bit.
-NOCOMMAND_ERROR Clears the command error bit.
Command Reference
SET FLATTEN MODEL
SET FLatten Model
[-Map | -NOMap]
[-NOPin_keep | -PIN_keep]
[-NOLATCH_Fold | -LATCH_Fold]
[-NOLATCH_Transparent | -LATCH_Transparent]
[-NOLATCH_FOLD_Master | -LATCH_FOLD_Master]
[-NOLATCH_MERGE_PORT | -LATCH_MERGE_PORT]
[-NOALL_SEQ_Merge | -ALL_SEQ_Merge]
[-NOSEQ_Merge | -SEQ_Merge]
[-NOALL_INV_SEQ_Merge | -ALL_INV_SEQ_Merge]
[-NOSEQ_Redundant | -SEQ_Redundant]
[-NOLIB_SEQ_Redundant | -LIB_SEQ_Redundant]
[-NOSEQ_SIMPLIFY_Clock | -SEQ_SIMPLIFY_Clock]
[-NOSEQ_Constant | -SEQ_Constant]
[-NOGATED_Clock | -GATED_Clock]
[-DFF_TO_DLAT_ZERO | -NODFF_TO_DLAT_ZERO]
[-DFF_TO_DLAT_FEEDBACK | -NODFF_TO_DLAT_FEEDBACK]
[-NOLOOP_AS_DLAT | -LOOP_AS_DLAT]
[-SEQ_CONSTANT_FEEDBACK | -NOSEQ_CONSTANT_FEEDBACK]
[-SEQ_CONSTANT_X_TO < 0 | 1 >]
[-AUTO_MODELING | -NOAUTO_MODELING]
[-OUTPUT_Z | -NOOUTPUT_Z]
[-NOBBOX_MERGE | -BBOX_MERGE]
[-SHOW_MESSAGE_NAME]
[-NOKEEP_IGnored_PO | -KEEP_IGnored_PO]
[-CUT_REMOVE REDUNDANT]
[-NOECO | -ECO]
(Setup Mode)
Species certain conditions for the attened model. Refer to the arguments table for a
complete list of options and their effects.
Use the REPORT ENVIRONMENT command to display the settings for the attened model, or
you can run this command without any options (in either Setup or LEC mode) to report a
complete list of attened modeling options.
Parameters
-Map Does automatic key point mapping. This is the
default.
-NOMap Skips the automatic key point mapping when the
system mode is changed from Setup to LEC.
Command Reference
-NOPin_keep In an effort to reduce memory use, Conformal does not
keep certain gate pins. This is the default.
-PIN_keep Keeps all gate pin information for gate reporting. Use
this option when reporting gate information at the
design level. It will increase memory use.
-NOLatch_fold Does not fold a master-slave latch into a D ip-op.
-Latch_fold Folds a master-slave latch into a D ip-op.
-NOLATCH_Transparent Does not treat latches that are always enabled as
transparent. This is the default.
-LATCH_Transparent Converts D-Latches into buffers if the clock ports of the
D-latches are always enabled.
-NOLATCH_FOLD_Master Does not convert two latches in an LSSD format into a
DFF gate when the reset signal is connected only to
the master.
-LATCH_FOLD_Master Converts two latches in an LSSD format into a DFF
gate when the reset signal is connected only to the
master.
-NOLATCH_Merge_port Does not collapse multi-port latches into a single-port
latch. This is the default.
-LATCH_Merge_port Collapses multi-port latches into a single-port latch.
-NOALL_SEQ_Merge Does not merge state elements that are functionally
equivalent. This is the default.
-ALL_SEQ_Merge Merges state elements that are functionally equivalent.
-NOSEQ_Merge Does not merge sequential elements in the clock cone
of a DFF or D-latch. This is the default.
-SEQ_Merge Merges common groups of sequential elements into
one sequential element in the clock cone of a DFF or
D-latch.
-NOALL_INV_SEQ_Merge Does not merge state elements that are functionally
inverted. This is the default.
-ALL_INV_SEQ_Merge Merges state elements that are functionally inverted.
-NOSEQ_Redundant Does not remove redundant fan-out gates from DFFs
and DLATs. This is the default.
Command Reference
-SEQ_Redundant Removes redundant fan-out gates from DFFs and
D-Latches.
-NOLIB_SEQ_Redundant Retains redundant fan-out gates from DFFs and
DLATs in the Library. This is the default.
-LIB_SEQ_Redundant Removes redundant fan-out gates from DFFs and
DLATs in the Library.
-NOSEQ_SIMPLIFY_Clock Does not fold master and slave latches when there is a
redundant interaction between the clock and reset
signals. This is the default.
-SEQ_SIMPLIFY_Clock Folds master and slave latches when there is a
redundant interaction between the clock and reset
signals.
-NOSEQ_Constant Does not propagate constant data through latches and
registers. This is the default.
-SEQ_Constant Propagates constant data through latches and
registers.
-NOGATED_Clock Does not remodel gated-clock sequential instances.
-GATED_Clock Remodels the gated-clock logic of the clock port of a
DFF. If the clock pin cannot be automatically
determined, use the ADD CLOCK command to dene
the clock pin.
-DFF_TO_DLAT_ZERO Converts a DFF to a DLAT if the clock port is zero.
-NODFF_TO_DLAT_ZERO Does not convert a DFF to a DLAT if the clock port is
zero.
-DFF_TO_DLAT_FEEDBACK Converts a DFF to a DLAT if the Q output feeds back
to the D input. This is the default.
-NODFF_TO_DLAT_FEEDBACK Does not convert a DFF to a DLAT if the Q output has
feedbacks to the D input.
-NOLOOP_AS_DLAT Does not use a DLAT to model a combinational loop.
-LOOP_AS_DLAT Uses a DLAT to model a combinational loop.
Command Reference
-SEQ_CONSTANT_FEEDBACK Remodels registers that also have feedback to
constants. Use this option with -seq_constant. This
is the default.
-NOSEQ_CONSTANT_FEEDBACK Does not remodel registers that also have feedback to
constants. Use this option with -seq_constant.
-SEQ_CONSTANT_X_TO Optimizes a op to a constant value (either zero or
one) when the op is always in a dont care (X) state.
Use this with the -seq_constant switch.
0: Optimizes a op to a constant zero.
1: Optimizes a op to a constant one.
-AUTO_MODELING Enables selective modeling for designs that can be
mapped mostly by name. This option applies only to
sequential constants. This is the default.
-NOAUTO_MODELING Disables the auto modeling feature.
-OUTPUT_Z Checks for oating conditions at top-level output ports
and inputs to blackboxes. This is the default.
-NOOUTPUT_Z Does not check for oating conditions at top-level
output ports and inputs to blackboxes.
-NOBBOX_MERGE Does not performautomatic blackbox merging. This is
the default.
-BBOX_MERGE Performs automatic blackbox merging.
-SHOW_MESSAGE_NAME Prints message names to the log as they occur.
-NOKEEP_IGnored_PO Does not retain the ignored primary outputs (added
with the ADD IGNORED OUTPUTS command) in the
attened netlist. This is the default.
-KEEP_IGnored_PO Retains the ignored primary outputs (added with the
ADD IGNORED OUTPUTS command) in the attened
netlist. These ignored primary outputs appear as
unreachable unmapped points in the design.
-CUT_REMOVE_REDUNDANT Removes as many redundant cuts as possible. Use
this option if you suspect that the software inserted
more cuts than necessary.
Command Reference
Examples
set flatten model -latch_fold
set flatten model -pin
set flatten model -latch_transparent
set flatten model -nomap
set flatten model -nodff_to_dlat_zero
set flatten model -seq_constant -noseq_constant_feedback
set flatten model -gated_clock
set flatten model -seq_redundant
set flatten model -all_seq_merge
set flatten model -nodff_to_dlat_feedback
Related Commands
READ MAPPED POINTS
REMODEL
REPORT ENVIRONMENT
REPORT MESSAGES
SET GATE REPORT
-NOECO Does not preserve extra circuit information for model
attening. This is the default.
-ECO Preserves extra circuit information during model
attening for subsequent ANALYZE ECO command
runs in the Conformal ECO ow.
Command Reference
SET FPGA TECHNOLOGY
SET FPga Technology
[NONE | VIRTEX | VIRTEX2]
(Setup Mode)
Note: This command is an FPGA command.
Turns on FPGA-specic processing. It is included in the fpgaR2G.do dole.
Parameters
NONE Does not turn on any FPGA-specic processing. This is the
default.
VIRTEX Turns on the Xilinx Virtex processing.
VIRTEX2 Turns on Virtex2 processing.
Command Reference
SET GATE REPORT
SET GAte Report
[-PRImitive | -DESign]
[-DYNamic | -NODYNamic]
[-FUNction | -STRucture]
(Setup / LEC Mode)
Species the detail level of gate reports in the Conformal gate information display. Gate report
features include the following:
I Returns information at the design or primitive level
I Displays the dynamic constraints
I Displays the fanin cone of the zero/one gates
By default, this command reports gate information at the primitive level, displays the dynamic
constraints, and does not display the fanin cone of the zero or one gates.
Use the REPORT ENVIRONMENT command to display the gate report level settings.
Note: If the gate report is set to Design, you must use the SET FLATTEN MODEL command
with the -pin_keep option in the Setup system mode. The gate information is reported in
the LEC system mode.
Parameters
-PRImitive Displays the gate report information at the primitive level. This
is the default.
-DESign Displays the gate report information at the design level.
-DYNamic Displays the dynamic constraints in the gate report information.
-NODYNamic Does not display the dynamic constraints in the gate report
information.
-FUNction Does not display the fanin cone of the zero/one gates in the
gate report information. This is the default.
-STRucture Displays the fanin cone of the zero/one gates in the gate report
information.
Command Reference
Related Commands
REPORT ENVIRONMENT
REPORT GATE
SET FLATTEN MODEL
Command Reference
SET GUI
SET GUi
[ON | OFf]
(Setup / LEC Mode)
Switches Conformal to the GUI mode from the non-GUI mode or to the non-GUI mode from
the GUI mode.
Parameters
ON Switches to the GUI mode. This option is the initial system
default.
OFf Switches to the non-GUI mode.
Command Reference
SET HDL DIAGNOSIS
SET HDl Diagnosis
<OFf | ON>
(Setup Mode)
Enables the debugging features before reading design and libraries. By default, the source
code debugging features (such as tracing drivers and loads) are off. Execute this command
before READ LIBRARY and READ DESIGN.
Parameters
Related Commands
DIAGNOSE
REPORT TEST VECTOR
OFf Disables the Source Code Managers debugging features. This
option is the initial system default.
ON Enables the Source Code Managers debugging features.
Command Reference
SET HDL OPTION
SET HDl Option
[-VERILOG_OUTOFBOUNDWrite <Noeffect | X>]
[-VHDL_OUTOFBOUNDWrite <X | Noeffect>]
[-VERILOG_OUTOFBOUNDRead <PARTIAL_X | ALL_X>]
[-VHDL_OUTOFBOUNDRead <ALL_X | PARTIAL_X>]
[-VERILOG_TRIMINDex <OFF | ON>]
[-VHDL_TRIMINDex <OFF | ON>]
(Setup Mode)
Controls the interpretation of some RTL semantics.
Parameters
-VERILOG_OUTOFBOUNDWrite <Noeffect | X>
Controls the interpretation of Verilog bit (or part)-select of vector
typed variable/signal when index is out of the dened index
range.
Noeffect species that out-of-bound writing will have no
effect. This is the default.
X species that when there is out-of-bound writing, the related
part of the variable/signal is assigned value x.
-VHDL_OUTOFBOUNDWrite <X | Noeffect>
Controls the interpretation of VHDL bit (or part)-select of vector
range.
X species that when there is out-of-bound writing, the related
part of the variable/signal is assigned value x. This is the
default.
Noeffect species that out-of-bound writing will have no
effect.
Command Reference
-VERILOG_OUTOFBOUNDRead <PARTIAL_X | ALL_X>
Controls the interpretation of Verilog bit (or part)-select of vector
range.
PARTIAL_X species that out-of-bound reading will have
values from the valid index locations of the vector, and will have
x value from the invalid (i.e. out of bound) locations of the
vector. This is the default.
ALL_X species that when there is out-of-bound reading, the
selected portion of the vector will be treated as all x values.
-VHDL_OUTOFBOUNDRead <ALL_X | PARTIAL_X>
Controls the interpretation of VHDL bit (or part)-select of vector
range.
ALL_X species that when there is out-of-bound reading, the
selected portion of the vector will be treated as all x values.
PARTIAL_X species that out-of-bound reading will have
values from the valid index locations of the vector, and will have
x value from the invalid (i.e. out of bound) locations of the
vector.
-VERILOG_TRIMINDex <OFF | ON>
ON controls to trim the index to necessary bits for the Verilog
les. OFF is the command default.
Note: This option might be used to verify implementations in
which indexes are intentionally trimmed.
-VHDL_TRIMINDex <OFF | ON>
ON controls to trim the index to necessary bits for the VHDL
les. OFF is the command default.
Note: This option might be used to verify implementations in
which indexes are intentionally trimmed.
Command Reference
Examples
The following examples use the Verilog language to show how to control index out of bound
handling. You can use similar VHDL command options to control the interpretations for the
VHDL language designs.
In the following RTL-1 example, the index range of variable mem is 0 to 2.
RTL-1
wire a;
reg [2:0] index;
reg [2:0] mem;
always @(*) mem[index] = a;
If index is greater than 2, it is out of the index range. Some synthesis tools might intentionally
interpret the RTL the same as with the following RTL-2 example:
RTL-2
wire a;
reg[2:0] index;
reg[2:0] mem;
always @(*) mem[index[1:0]] = a;
But with simulation, RTL-1 and RTL-2 behave differently.
With the Conformal Equivalence Checking software, when running the command:
set hdl option -verilog_outofboundwrite x
then
I index=0 : mem[0] is assigned to the value of a
I index=3,4,5,6,7 : mem[0], mem[1], and mem[2]are assigned to the value of 1bx.
This interpretation assumes that out-of-bound writing will not happen, and consequently
ignores the behavior difference when index is greater than 2.
Command Reference
When running the command:
set hdl option -verilog_outofboundwrite noeffect
then
I index=3,4,5,6,7 : mem[0], mem[1], and mem[2]will not be affected with their
current value.
Based on this interpretation, RTL-1 and RTL-2 are considered functional non-equivalent, and
consequently the implementation from RTL-2 will be non-equivalent to RTL-1.
Using the same RTL-1 and RTL-2 examples, when running the command:
set hdl option -verilog_trimindex on
The Conformal Equivalence Checking software will interpret RTL-1 as RTL-2 by ignoring
index[2] in the expression mem[index] (RTL-1). With the -verilog_trimindex on
option, RTL-1 and RTL-2 are considered equivalent.
Related Commands
ELABORATE DESIGN
READ DESIGN
Command Reference
SET IMPLEMENTATION
SET IMPlementation
<MULtiplier [-AUTO | -CSA | -WALL | -RCA | -NBW | -BKA] |
DIVider [-RPL | -BLA]
[-CLA | -CLA2]
[-OVERFLOW_TRUNCATE | -OVERFLOW_SATURATE | -OVERFLOW_DONTCARE]
[-ALL_div | -RTL_div | -DW_div]>
(Setup Mode)
Species the multiplier and divider implementations in the Golden and Revised designs.
Execute this command before READ LIBRARY and READ DESIGN.
The types of multipliers supported are:
I Carry Save Adder (CSA)
I Ripple Carry Adder (RCA)
I Booth Encoded-Wallace tree (WALL)
I Non-Booth Encoded-Wallace tree (NBW)
I Brent-Kung Adder (BKA)
Default Multiplier Implementation Is Automatically Determined
By default, Conformal automatically determines the multiplier implementation as follows:
If a_width + b_width <42, Conformal chooses NBW.
If a_width + b_width >=42, Conformal chooses WALL.
The -auto default setting is best suited when you are using Synopsys Design Compiler with
DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to
specify -csa.
The types of dividers supported are:
I Ripple Borrow (RPL)
I Borrow Look-Ahead
I Carry Look-Ahead
I Carry Look-Ahead, 2-Way
Command Reference
Required Options
With this command, you must include either the multiplier or divider option;
however, Conformal permits both options, as shown below:
set implementation multiplier -csa divider -bla
Specifying Multiplier Implementations with Directives
Specify the multiplier implementation with a Synopsys or Conformal directive in the design.
(See the Set Implementation examples below and in the Examples section of this command.)
I Synopsys Directive:
// synopsys dc_script_begin
// set_implementation <csa | rca | wall | nbw | bka> [instance_name]
// synopsys dc_script_end
I Conformal Directive:
// conformal multiplier <csa | rca | wall | nbw | bka>
Note: Use either directive for multipliers specied with operational assignments. For
DesignWare instances, use only the Synopsys directive along with the instance name.
Parameters
MULtiplier By default, Conformal automatically determines the multiplier
implementation as follows:
If a_width + b_width < = 52, Conformal chooses NBW.
If a_width + b_width > 52, Conformal chooses WALL.
The multiplier type is one of the following:
-AUTO The -auto default setting is best suited
when you are using Synopsys Design
Compiler with DesignWare Foundation. If
you are not using DesignWare Foundation,
it is probably best to specify -csa. This is
the default.
-CSA Carry Save Adder
-WALL Booth Encoded, Wallace tree
-RCA Ripple Carry Adder
Command Reference
-NBW Non-Booth Encoded, Wallace tree
-BKA Brent-Kung Adder
DIVider The divider type is one of the following:
-RPL Ripple Borrow, which is the initial default
-BLA Borrow Look-Ahead
-CLA Carry Look-Ahead
-CLA2 Carry Look-Ahead, 2-Way
The following options specify how to treat over signed division
overflow, which is when a minimum negative value is divided by -1.
-OVERFLOW_TRUNCATE Truncates results as dened by
twos-complement arithmetic. This is the
default.
-OVERFLOW_SATURATE Saturates results to the largest positive
value.
-OVERFLOW_DONTCARE Treats overow results as dont cares.
DIVider can be inferred from either DW_div instantation or RTL
arithmetic operation (for example, / in Verilog). The following options
specify the divider class for the preceeding settings.
-ALL_div Species that dividers are inferred from
both RTL and DW. This is the default.
-RTL_div Species that dividers are only inferred from
RTL operation.
-DW_div Species that dividers are only inferred from
DW_div instantiation.
-Both Species the implementation type for both the Golden and Revised
-Golden Species the implementation type for the Golden design.
-Revised Species the implementation type for the Revised design.
Command Reference
Examples
Synopsys Directive
The following examples illustrate Conformal-supported use of the Synopsys directive:
// set_implementation wall
assign out = in1 * in2;
// set_implementation wall U1
DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1b0), .PRODUCT (out));
// set_implementation wall cla2 U1
DW_div #(A_width, B_width, TC_mode, REM_mode) U1 (...);
Conformal Directive
The following example illustrates the Conformal directive.
Note: The directive applies to only the statement on the following line. In this example, it does
not apply to assign out2:
// conformal multiplier wall
assign out1 = in1 * in2;
Related Command
READ DESIGN
Command Reference
SET LOG FILE
SET LOg File
[<filename>
[-Replace | -Append]
[-PROGRESS | -NOPROGRESS]
[-NOBACkup]]
(Setup / LEC Mode)
Writes the transcript to a specied le. The commands and any output information write to
this le. As you review the le, identify commands by the keyword:
//Command:
When you want the Conformal software to stop writing to the log le, enter the command
without any options.
Note: If the lename you specify already exists, you must use either the -replace or
-append option. If you do not include an option, the Conformal software generates an error
message that the le exists. If you receive this message, reenter the command with either a
new lename or the appropriate option. If the lename is not writable, the software writes it to
the /tmp directory.
If you are writing the transcript to a le, you might want to turn off the screen transcript display
with the SET SCREEN DISPLAY command. (If you do not specify otherwise, the transcript
prints to the screen.)
To store log les based on the software version, use the LEC_VERSION environment variable.
For example:
set log file lec.$LEC_VERSION.log -replace
To verify the current log le setting, use the REPORT ENVIRONMENT command.
Parameters
<filename> Writes the transcript run to this le.
-Replace If the specied lename already exists, overwrites the contents
of that le.
-Append Appends the transcript run to the end of the specied lename.
-PROGRESS Writes the percentage completion progress to the log le. This
is the default.
-NOPROGRESS Does not write the percentage completion progress to the log
le.
Command Reference
Related Commands
REPORT ENVIRONMENT
SET COMMAND PROFILE
SET SCREEN DISPLAY
-NOBACkup Does not create a backup le.
Note: If you do not specify this option, it will create a backup le
when you replace or append a le.
Command Reference
SET LOWPOWER OPTION
SET LOwpower Option
[-NOauto | -Auto |
[-Retention_cells_check]
[-Isolation_cells_check]
[-Level_shifter_cells_check]
[-POWER_domain_check
[-GOLDen_power_domain [CPF | PHYsical | HYbrid]]
[-REVised_power_domain [PHYsical | CPF | HYbrid]]
]
[-MERge]
(Setup Mode)
Enables the low power check for different types of low power cells. Low power checking
includes either the technology mapping check or the equivalence check (EC), or both,
depending on the low power cell type.
For retention-register cells, only the technology mapping check is performed. For isolation
cells and level-shifter cells, both technology mapping check and EC is performed. For more
information on these low power checks and cell types, see CHECK LOWPOWER CELLS.
Parameters
-NOauto Does not automatically enable the low power check. This is
the default.
-Auto Enables the low power check for the isolation cells, level-shifter
cells, and state retention cells.
-Retention_cells_check
Enables the low power check for state retention cells only.
-Isolation_cells_check
Enables the low power check for isolation cells only.
-Level_shifter_cells_check
Enables the low power check for level-shifter cells only.
-POWER_domain_check
Enables the power domain consistency check for the sequential
compare points.
Command Reference
Examples
The following commands perform low power checking that includes both the technology
mapping check and the equivalence check:
set lowpower option -auto
set lowpower option -retention -level_shifter
-GOLDen_power_domain [CPF | PHYsical | HYbrid]
Species the mechanism for obtaining the power domains in
the Golden design to do the power domain consistency check.
I CPFobtains the power domain from the CPF
specication. This is default for the Golden design.
I PHYsicalextracts the power domains by tracing the
power and the ground pins.
I HYbridextracts the power domains by tracing the power
and the ground pins. If the power domain cannot be
obtained by tracing the power and ground pins, the software
obtains the power domain from the CPF specication.
-REVised_power_domain [PHYsical | CPF | HYbrid]
Species the mechanism for obtaining the power domains in
the Revised design to do the power domain consistency check.
I PHYsicalextracts the power domains by tracing the
power and the ground pins. This is default for the Revised
design.
I CPFobtains the power domain from the CPF
specication.
I HYbridextracts the power domains by tracing the power
and the ground pins. If the power domain cannot be
obtained by tracing the power and ground pins, the software
obtains the power domain from the CPF specication.
-MERge Merges the equivalent outputs of the low power cells. This is
enabled only for isolation and level-shifter cells.
Command Reference
Related Commands
ADD LOWPOWER CELLS
Command Reference
SET MAPPING METHOD
SET MApping Method
< [-NAme < First | Guide | Only> |-NOName]
[-NOPhase | -Phase]
[-NOSensitive | -Sensitive]>
[-NOUNREACH | -UNREACH]
[-REPORT_UNREACH | -NOREPORT_UNREACH]
[-NAME_EFFORT <HI | LOW>]
[-NONETS | -NETS]
[-BBOX_NAme_match | -NOBBOX_NAme_match]
[-REPORT_SUMMARY_SHOW_ZERO_COUNT]
[-TIMEOUT_minutes <number>]
[-PHASEMAPMODEL]
(Setup / LEC Mode)
Species the mapping method, phase, case sensitivity, and handling for unreachable points
and blackboxes when Conformal maps the key points. With the -name option, paths of the
gates indicate some type of starting point to map key points. The system default is name
first. This default lets Conformal rst map key points with the same paths, then map the
remaining unresolved key points with a mapping algorithm. All remaining unresolved key
points become unmapped points.
Use the REPORT ENVIRONMENT command to display the setting of the mapping method and
phase.
Parameters
-NAme The mapping method operates under the modes described as
follows:
First Conformal maps the key points with the
paths of the gates rst. Then, Conformal
uses the mapping algorithm to map the rest
of the key points. This option is the
system default.
Guide Conformal maps key points with a mapping
algorithm rst.
Only Conformal only maps the key points based
on the paths of the gates
-NOName Does not map key points based on the paths of the gates. If the
mapping algorithm cannot map a key point, it remains
unmapped.
Command Reference
-NOPhase Does not map key points with an inverted phase. This is the
default.
These key points are represented with the symbol +.
Comparison results are either equivalent or nonequivalent.
-Phase Maps key points with an inverted phase.
These key points are represented with the symbol -.
Comparison results are either inverted-equivalent or
nonequivalent.
-NOSensitive Species that key point names are not case sensitive. This is
the default.
-Sensitive Species that key point names are case sensitive.
-NOUNREACH Does not map unreachable key points. Unreachable key points
are those that dont eventually affect the PO of the design. This
is the default.
-UNREACH Maps unreachable key points. Unreachable key points are
those that dont eventually affect the PO of the design.
-REPORT_UNREACH Reports unreachable key points. This is the default.
-NOREPORT_UNREACH Does not report unreachable key points.
-NAME_EFFORT Uses the specied amount of effort for key point mapping. This
option eliminates the need for simple renaming rules such as:
add renaming rule R1 reg\[%d\] reg(@1)
-golden, which maps the following Golden and Revised
design DFFs:
Golden: DFF A/B/C_reg[5]
Revised: DFF A/B/C_reg(5)
This option applies to only DFFs and DLATs.
HI This option is the system default level. It
eliminates the need for simple renaming
rules.
LOW Uses low effort for key point mapping
-NONETS Does not map according to net names. This is the default.
-NETS Maps key points according to net names.
Command Reference
Related Commands
ADD MAPPED POINTS
ADD RENAMING RULE
MAP KEY POINTS
REPORT ENVIRONMENT
-BBOX_NAme_match Maps blackboxes only if both the module names and instance
names match. This is the default.
-NOBBOX_NAme_match Maps blackboxes if instance names match.
-REPORT_SUMMARY_SHOW_ZERO_COUNT
Species that the summary will be reported with ZERO count if
there is an unmapped point of the same type either in Golden or
Revised design.
-TIMEOUT_minutes <number>
Species the number of minutes for the mapping process to
continue before it is interrupted. The default value is zero (0),
which disables this check.
-PHASEMAPMODEL Uses the phase information provided by the ADD MAPPING
MODEL command to determine the mapping phase. Use this
option when there is a phase mismatched between the
simulation model and the synthesis model.
Command Reference
SET MOS MODEL
SET MOs Model
<NMOS/PMOS>
[Spice_model_name]
(LEC Mode)
Species the MOS model names used in SPICE. You can then re-read the SPICE netlist.
When reading in SPICE netlists, the parser automatically identies transistor model names
as PMOSand NMOStypes. However, if you have models that were not dened using .MODEL
statements, the parser identies themas ERROR. Instead of altering your SPICE le, you can
use this command.
Note: You must run this command before reading in the SPICE netlist.
Parameters
NMOS Denes the model name as an N-Channel device.
PMOS Denes the model name as a P-Channel device.
Spice_model_name Species a single or list of names for which to dene models.
This is necessary only if you have a P-Channel model names
not starting with a p, and N-Channel model names not starting
with n.
Command Reference
SET MULTIPLIER IMPLEMENTATION
SET MUltiplier Implementation
<AUTO | CSA | RCA | WALL | NBW | BKA>
[-Verbose]
(Setup Mode)
Species the multiplier implementation in the Golden and Revised designs. Execute this
command before READ LIBRARY and READ DESIGN.
The types of multipliers you can specify are:
I Carry Save Adder (CSA)
I Ripple Carry Adder (RCA)
I Booth Encoded-Wallace tree (WALL)
I Non-Booth Encoded-Wallace tree (NBW) multipliers
I Brent-Kung Adder (BKA)
The CSA multiplier implementation is the default.
An alternate method for specifying the multiplier implementation is to use a Synopsys or
Conformal directive in the design. See the following set multiplier implementation examples
for using these directives and those shown in the Examples section below.
Synopsys Directive:
// set_implementation <csa | rca | wall | nbw | bka> [instance_name]
Conformal Directive:
// conformal multiplier <csa | rca | wall | nbw | bka>
Note: Use either directive for multipliers specied with operational assignments. However, for
DesignWare instances, use only the Synopsys directive along with the instance name.
Command Reference
Parameters
Examples
Synopsys Directive
The following two examples illustrate Conformal-supported use of the Synopsys directive:
// set_implementation wall
AUTO The system default for Conformal is that it automatically
determines the multiplier implementation as follows:
If a_width + b_width < = 52, Conformal chooses NBW.
If a_width + b_width > 52, Conformal chooses WALL.
The auto default setting is best suited when you are using
Synopsys Design Compiler with DesignWare Foundation. If you
are not using DesignWare Foundation, it is probably best to
specify csa.
CSA Species that the multiplier type is a Carry Save Adder (CSA)
multiplier.
RCA Species that the multiplier type is a Ripple Carry Adder (RCA)
multiplier.
WALL Species that the multiplier type is a Booth Encoded, Wallace
tree multiplier.
NBW Species that the multiplier type is a non-Booth Encoded,
Wallace tree multiplier.
BKA Species that the multiplier type is a Brent-Kung Adder (BKA).
-Both Species the multiplier implementation type for both the Golden
-Golden Species the multiplier implementation type for the Golden
design.
-Revised Species the multiplier implementation type for the Revised
design.
Command Reference
assign out = in1 * in2;
// set_implementation wall U1
DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1b0), .PRODUCT (out));
Conformal Directive
The following example illustrates the Conformal directive.
Note: The directive applies to only the statement on the following line. In this example, it does
not apply to assign out2:
// conformal multiplier wall
Related Command
READ DESIGN
Command Reference
SET MUltiplier Option
[-NOAUTO | -AUTO]
[-NOCDP_INFO | -CDP_INFO]
[-Verbose]
(Setup Mode)
Species whether Conformal will automatically analyze multipliers when switching from
Setup to LEC mode. Additionally, use the -cdp_info option if you want Conformal to let
you know when Conformal Ultra will be helpful.
Parameters
Related Commands
ANALYZE DATAPATH
ANALYZE MULTIPLIER
SET DATAPATH OPTION
SET FLATTEN MODEL
-NOAUTO Does not automatically analyze multipliers when switching from
-AUTO Automatically analyzes multipliers when switching from Setup
to LEC mode.
-NOCDP_INFO Does not display a message when Conformal Ultra can
enhance multiplier analysis. This is the default.
-CDP_INFO Displays a message when Conformal Ultra can enhance
multiplier analysis.
Command Reference
SET NAMING RULE
SET NAming Rule
<<<string> -Hierarchical_separator> |
<<string> -Tristate> |
<<string> -REGister> |
<<string> -Inverted_pin_extension> |
<<string> -Parameter> |
<<left_string> <right_string> -Array_delimiter> |
<<left_string> <right_string> -Field_delimiter> |
<<label_string> <forgen_string> <instance_string> -INStance> |
<<label_string> <forgen_string> <variable_string> -VARiable>>
(Setup Mode)
Species the naming rules for an RTL or hierarchical design. Execute this command before
READ LIBRARY and READ DESIGN.
Naming rules for RTL designs specify the following:
I Hierarchical separator
I Tristate and register names
I Array delimiter
Naming rules for hierarchical designs specify the hierarchical separator.
I Use the hierarchical separator string when matching key points between the Golden and
Revised designs. The hierarchical separator setting has no effect on the way key points
are reported (for example, when you use the REPORT GATE command).
I Use the register, tristate, and array delimiter strings to instruct the Verilog RTL compiler
how key point names (inferred ip-op/latch instance names) are constructed.
I Use the following example to understand the correct use of the inverted pin extension
string.
Golden design: pin a
Revised design: inverted pin a_BAR
Type the following command:
set naming rule _BAR -inverted_pin_extension -golden
I The parameter string denes the name of the new parameterized module name when
new parameters are passed. When an existing module has dened parameters and it is
being instantiated with new parameters, a duplicate module is created with the specied
parameter string.
Command Reference
I The instance strings dene the way instance names are generated. Different synthesis
tools use different schemes to generate instance names. To facilitate the compare
process, you can use this command to instruct Conformal to generate instance names
in the same way as the synthesis tool.
I The variable strings dene the way variable names are generated.
Each string for all of the settings must be enclosed in double quotes ( ). These double quotes
can be empty.
Use the REPORT ENVIRONMENT command to display the settings for the naming rules for the
Parameters
<string> -Hierarchical_separator
A character or string that species the hierarchical separator.
The default is /.
<string> -Tristate A string that species the tristate naming. The default is
%s_tri. The string must contain exactly one %s.
<string> -REGister A string that species the register naming. The default is
%s_reg. The string must contain exactly one %s.
<string> -Inverted_pin_extension
A string that species the inverted pin extension. This option
appends the string to the Golden or Revised pin name. Refer to
the example shown in Denition.
<string> -Parameter A string that species parameter naming. The default is
_%s.
<left_string> <right_string> -Array_delimiter
Two strings that specify the left and right array delimiter. The
default is [ and ] for the left and right string.
<left_string> <right_string> -Field_delimiter
Two strings that specify the left and right record eld delimiter
for VHDL designs. The default is [ and ] for the left and
right string.
label_string forgen_string instance_string -instance
Command Reference
forgen_string applies to for generate blocks that have a
name and index, label_string applies to all of the other
blocks.
label_string species how to include the block name in the
instance name, where:
I %L species the block name.
I %s species the current instance name.
The default setting for label_string is %s.
For example, instance ins1 is inside block b1, and b2 is inside
b1. If you specify a label_string of %L_%s, this command
generates the instance name b1_b2_ins1. If you specify a
label_string of %s[%L], this command generates the
instance name ins1[b1][b2].
forgen_string species how to use the generated block
name and loop index to form an instance name, where:
I %L species the block name.
I %s species the current instance name.
I %d species the block index.
The default setting for forgen_string is %s_%d.
For example, instance ins1 is inside block b2 with a forloop
index of 3, and b2 is inside block b1 with a forloop index of 0.
If you specify a forgen_string of %L[%d].%s, this
command generates the instance name b1[0].b2[3].ins1.
instance_string denotes how to specify the instance name,
where %s species the current instance name. For example,
your current instance name is ins1. If you specify an
instance_string of %s_INS, this command replaces the
instance name with ins1_INS. Note: The result of this option
replaces the %s in label_string and forgen_string.
The default setting for instance_string is %s.
label_string forgen_string variable_string -variable
Command Reference
Examples
set naming rule : -hierarchical_separator -golden
set naming rule register_%s -register -revised
set naming rule tristate_%s -tristate
set naming rule < > -array -golden
For instance name generation, consider the following sample Verilog code:
generate
begin: blkA
for (i=0;i<=0;i=i+1) begin: forblkB
or n1(a,b,c);
The variable naming scheme is similar to the instance naming
scheme.
forgen_string applies to generated blocks that have a name
and index, label_string applies to all of the other blocks.
label_string species how to include the block name in the
variable name (applies to all variables inside the for generate
block), where:
I %L species the generated block name.
I %s species the current variable name.
The default setting for label_string is %s.
forgen_string species how to use the generated block
name and loop index to form a variable name, where:
I %L species the generated block name.
I %s species the current variable name.
I %d species the generated block index.
The default setting for forgen_string is %s_%d.
variable_string denotes how to specify the variable name,
where %s species the current variable name. The default
setting for variable_string is %s.
-Both The naming rule applies to both the Golden and Revised
-Golden The naming rule applies to the Golden design alone.
-REvised The naming rule applies to the Revised design alone.
Command Reference
for (j=23;j<=23;j=j+1) begin: forblkC
and n2(d,e,f);
end
begin : blkD
nor n3 (g,h,i);
end
end
end
endgenerate
I set naming rule "%s" "%s_%d" "%s" -instance
This renames instances n1, n2 and n3 as n1_0, n2_0_23, and n3_0, respectively. This
is also the default setting.
I set naming rule "%s" "%L[%d].%s" "%s_INS" -instance
This renames instances n1, n2 and n3 as forblkB[0].n1_INS,
forblkB[0].forblkC[23].n2_INS, and forblkB[0].n3_INS, respectively.
I set naming rule "%L_%s" "%L[%d].%s" "%s" -instance
This renames instances n1, n2 and n3 as blkA_forblkB[0].n1,
blkA_forblkB[0].forblkC[23].n2, and blkA_forblkB[0].blkD_n3,
respectively.
Related Commands
ADD MAPPED POINTS
ADD RENAMING RULE
MAP KEY POINTS
READ DESIGN
REPORT ENVIRONMENT
TEST RENAMING RULE
Command Reference
Command Reference
SET PARALLEL OPTION
SET PARAllel Option
[-MAX_Remote <integer>]
[-SUBMIT_COMMAND_LINE <string>]
[-KILL_COMMAND_LINE <string>]
[-KEEP_DIR]
[-RESERVE_LICense <integer>]
(LEC / Setup Mode)
Sets the parameters for parallel processing. This command should be run immediately before
the RUN PARALLEL COMPARISON command.
Parameters
-MAX_Remote Species the maximum number of remotes used for performing
the tasks. The number of available CPUs is considered as that
number of remotes. However, this is just a recommendation.
The Conformal software will check the number of available
licenses and might launch remote jobs less than the number
specied.
-SUBMIT_COMMAND_LINE
Species the submit command interface.
The default value is:
bsub -o <logdir>/<jobnum>_LSF.log
<submit_options> <command>
The keywords <logdir>, <jobnum>, and <command> are
determined by the software.
You can specify <submit_options> with the RUN PARALLEL
COMPARE command.
-KILL_COMMAND_LINE Species the kill command interface. The default value is
bkill <jobid>. The keyword <jobid> is determined by the
software.
-KEEP_DIR Species that the directory created during parallel processing
will be saved.
-RESERVE_LICense Species the number of XL licenses to be reserved for other
use.
Command Reference
Related Commands
Command Reference
SET RETIMING OPTION
SET REtiming Option
[-NOAUTO | -AUTO]
[-NORETIMED_MODULE | -RETIMED_MODULE]
(Setup Mode)
Species whether the Conformal software automatically performs retiming analysis for
designs when switching from Setup to LEC mode. According to the structure of the designs,
the software automatically determines whether to use forward or backward pipeline retiming,
or general retiming. The results of analysis enable the software to automatically resolve
retiming designs.
Tip
Use the ADD MODULE ATTRIBUTE command to attach the PIPELINE_Retime
attribute to a module.
Parameters
Related Commands
ANALYZE RETIMING
-NOAUTO Does not automatically analyze retiming when switching from
-AUTO Automatically analyzes retiming when switching from Setup to
LEC mode.
-NORETIMED_MODULE Performs retiming analysis on all modules with or without the
PIPELINE_Retime attribute. This is the default.
-RETIMED_MODULE Performs retiming analysis only on modules with the
PIPELINE_Retime attribute.
Command Reference
SET ROOT MODULE
SET ROot Module
<module_name>
(Setup Mode)
Species the name of the root module for the Golden and Revised designs. The system
default species that when the design is read, Conformal automatically assigns the root
module. Thus, the SET ROOT MODULE command overrides the automatic assignment.
Use the REPORT ENVIRONMENT command to display the settings for the root module for the
Parameters
Related Commands
READ DESIGN
REPORT ENVIRONMENT
module_name This module is the root. This assignment overrides the
automatic root module assignment Conformal makes when you
use the READ DESIGN command.
-Golden Assigns the root module name for the Golden design. This is
the default.
-Revised Assigns the root module name for the Revised design.
-Both Assigns the root module name for both the Golden and Revised
designs.
Command Reference
SET RULE FILTER
SET RUle Filter
<-ROOT_HIER_only>
(Setup Mode)
Filters out rules that occur in modules outside the root hierarchy. It is a means to remove
unnecessary rule reporting and focus only on the root module's hierarchy.
Use the REPORT RULE CHECK command with the -summary option to display all of the rules
and their settings and occurrences.
Parameters
Related Commands
READ DESIGN
READ LIBRARY
REPORT RULE CHECK
-ROOT_HIER_only Filters out rules that occur in modules outside the root
hierarchy.
-Golden Applies the lter to the Golden design and library. This is the
default.
-Revised Applies the lter to the Revised design and library.
Command Reference
SET RULE HANDLING
SET RUle Handling
<[<rule_name*> [-Warning | -Error [-CONTinue] | -Ignore | -Note]]
[[-EXCLude | -INCLude] <-MODule | -DESIGN_FILE | -LIB_FILE> <name*>]>
[ |-Design | -Library]
(Setup Mode)
Species the rule handling when reading in the designs and libraries or exclude the specied
module, design le, library le, or rule from rule checking. Most rules are either warnings or
notes. Execute this command before READ LIBRARY and READ DESIGN.
Note: Multiple SET RULE HANDLING commands can be specied, and the effects are
cumulative.
Use the REPORT RULE CHECK command with the -summary option to display all of the rules
and their settings and occurrences.
See the Encounter Conformal Equivalence Checking User Guide for rule denitions and
sample cases.
Note: The wildcard (*) represents any zero or more characters in rule names.
Parameters
rule_name* Changes rule handling for the specied rules. This supports
wildcards.
-Warning The rule handling will be a warning
message. This is the default.
-Error [-CONTinue]
The rule handling will be an error message.
With the -CONTinue option, the program
will continue to run instead of erroring out.
-Ignore The rule handling will be ignore. See
REPORT RULE CHECK to see how this
severity level affects reporting.
-Note The rule handling will be a note.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
REPORT RULE CHECK
-EXCLude | -INCLude
Removes the unwanted rules. All rules will be checked by
default.
-EXCLude removes some rules in the specied list.
-INCLude removes all rules not in the specied list.
-MODule Excludes the specied module from the RTL
Rule check.
-DESign_file Excludes the specied design le from the
RTL Rule check.
-LIB_file Excludes the specied library le from the
RTL Rule check.
name* Species the name of the module, design
le, or library le.
-Design Applies the rule handling to only the designs.
applies the rule handling to both designs and libraries.
-Library Applies the rule handling to only the libraries.
applies the rule handling to both designs and libraries.
-Both Applies the rule handling to both the Golden and Revised
designs and libraries. This is the default.
-Golden Applies the rule handling to the Golden design and library.
-Revised Applies the rule handling to the Revised design and library.
Command Reference
SET SCREEN DISPLAY
SET SCreen Display
<ON | OFf>
(Setup / LEC Mode)
Species whether the transcript output is displayed on the terminal screen.
Tip
If the screen display is set to off, use the SET LOG FILE command to save the
transcript to a le.
Use the REPORT ENVIRONMENT command to display the setting for the screen display. By
default, screen display is on.
Parameters
Related Commands
REPORT ENVIRONMENT
SET LOG FILE
ON Displays the transcript on the terminal screen. This option is
the system default.
OFf Does not display the transcript on the terminal screen.
Command Reference
SET SPICE OPTION
SET SPIce OPTion
[-BUlk | -NOBUlk]
[-BBOX | -NOBBox]
[-NOADDGLOBALPINs | -ADDGLOBALPINs]
[-NOKEep_InstanceX | -KEep_InstanceX]
(Setup Mode)
Species options for reading the SPICE netlist design (when running the read design
-spice command).
Parameters
-BULK Identies nets connected to PMOS bulk terminals as power
and nets connected to NMOS bulk terminals as ground. This
is the default.
-NOBULK By default, Conformal Custom identies nets connected to
PMOS bulk terminals as power and nets connected to NMOS
bulk terminals as ground. However, this option removes that
assumption and you will need to specify power and ground
pins/nets by using *.GLOBAL <name>:P for power nets and
*.GLOBAL <name>:G for ground nets or use Conformal
commands to add constraints, tied signals (pins), or net
attributes.
-BBOX Species that SUBCKT contains no transistors and will be
treated as a blackbox. This is the default.
-NOBBox Species that SUBCKT contains no transistors and will be
removed along with all of its instantiations.
-NOADDGLOBALPINs Species that no extra ports for GLOBAL signals will be created
for SUBCKT. This is the default.
-ADDGLOBALPINs Species that extra ports for GLOBAL signals will be created for
SUBCKT.
-NOKEep_InstanceX Species that the rst character X of the name of instance will
not be retained. This is the default.
-KEep_InstanceX Species that the rst character X of the name of instance will
not be retained.
Command Reference
Examples
Sample Dole:
set spice option -nobulk -nobbox -addglobalpins -keep_instanceX
read design -spice library.spi -golden
abstract logic
Related Commands
ABSTRACT LOGIC
READ DESIGN
Command Reference
SET STATETABLE
SET STATEtable
<ON | OFf>
(Setup Mode)
Controls the global setting of the Synopsys Liberty state table support.
Note: This command must be used before READ DESIGN and READ LIBRARY.
Note: Using the READ DESIGN and READ LIBRARY commands -STATEtable option
supersedes these settings (it also supersedes the global setting).
Parameters
Related Commands
READ DESIGN -statetable
READ LIBRARY -statetable
ON Enables support for Synopsys Liberty state tables. This option
is the system default.
OFf Disables support for Synopsys Liberty state tables.
Command Reference
SET SYNTHESIS_OFF_Command
<string>
(Setup Mode)
Species the pragma that is used to indicate the beginning of non-synthesizable constructs
in the source code or in the generated generic netlist.
Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to running
this command, the default is translate_off.
Note: If this command is run multiple times, only the last value is used.
Parameters
Examples
Sample Dole:
synthesized.
synthesized.
Related Commands
string Species the action.
Default: translate_off synthesis_off
Command Reference
SET SYNTHESIS_ON_Command
<string>
(Setup Mode)
Species the pragma that is used to indicate the end of non synthesizeable constructs in the
source code or in the generated generic netlist.
Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to running
this command, the default is translate_on.
Note: If this command is run multiple times, only the last value is used.
Parameters
Examples
Sample Dole:
synthesized.
synthesized.
Related Commands
string Species the action.
Default: translate_on synthesis_on
Command Reference
SET SYSTEM MODE
SET SYstem Mode
<Setup | LEc [-Map | -Nomap] [-PRESERVE] | EXPlorer>
(Setup / LEC / Explorer Mode)
Switches system modes between the Setup mode and the LEC mode.
I Setup mode: While in this mode, you read in the design and set all of the necessary
constraints and environment variables.
I LEC mode: While in this mode, Conformal does the comparison and diagnosis.
I Explorer mode: While in this mode, you can cross-link from a timing report to an RTL
design or a gate-level design through a schematic viewer or source code browser.
Note: This mode requires the Conformal Explorer license.
When you exit the Setup mode, Conformal attempts to map all key points in the Golden and
Revised designs. A summary is given for the mapped points in the Golden and Revised
designs. An additional summary is given if Conformal identies any unmapped key points.
Use the REPORT ENVIRONMENT command to display the current system mode.
Parameters
Related Command
REPORT ENVIRONMENT
REPORT TESTCASE
Setup Switches the system mode to Setup.
LEc Switches the system mode to LEC.
-Map Maps key points when entering the LEC system mode. This is
the default.
-Nomap Does not map key points when entering the LEC system mode.
-PRESERVE Preserves the netlist modeling. You can use this option for
netlists created with the REPORT TESTCASE command only.
EXPlorer Switches the system mode to Conformal Explorer.
Command Reference
SET UDP PIN
SET UDp Pin
<udp_name> <pin_name <0 | 1> ...>
(Setup Mode)
Sets the pin inputs of the user-dened primitive (UDP) to constant values, which are
propagated into the UDP. Some inactive entries will be removed.
The constant set to inputs simplies the state table of the UDP, which will sometimes eliminate
some ambiguity in the UDP description.
Note: This must be used before running the READ DESIGN command.
Parameters
Example
In this example, pins in1 and in2 of the UDP named udp_1 are set to 0 and 1, respectively:
set udp pin udp_1 in1 0 in2 1
Related Commands
READ DESIGN
READ LIBRARY
udpname Species the name of the UDP.
pin_name <0 | 1> Species the name of the pin and its input value. Choose 0
or 1.
-Golden Sets the UDP inputs in the Golden design. This is the
default.
-Revised Sets the UDP inputs in the Revised design.
-Both Sets the UDP inputs in both the Golden and Revised
designs.
Command Reference
SET UNDEFINED CELL
SET UNDEfined Cell
<Error | Black_box | Generic_BBox>
[-AUTO_Assign | -NOAUTO_Assign]
[-ASCEND | -NOASCEND]>
(Setup Mode)
Species how Conformal handles undened cells it encounters when reading in the Golden
and Revised designs. The system default is to give an error message if there are any
undefined cells.
Use the REPORT ENVIRONMENT command to display the settings for the undened cells
handling for the Golden and Revised designs. Execute this command before READ LIBRARY
and READ DESIGN.
Parameters
Error When reading the designs, undened cells trigger an error
message. This is the default.
Black_box When reading the designs, regards undened cells as
blackboxes. This option takes Verilog parameter values to
construct the module name for the created blackbox module.
Generic_BBox When reading the designs, regards undened cells as
blackboxes. This option ignores Verilog parameter values and
uses the object bit widths to construct the module name for the
created blackbox module.
-AUTO_Assign Automatically determines and assign directions to all blackbox
pins. This is the default.
Note: If Conformal cannot determine the direction of a pin as
input or output, it assigns I/O direction.
-NOAUTO_Assign Assigns I/O direction to all blackbox pins.
Note: You must manually reassign all pin directions according
to the design.
-ASCEND Arranges bits of bus pins in ascending order; that is, in1 (0 to 7).
-NOASCEND Arranges bits of bus pins in descending order; that is, out1 (7
down to 0).
Command Reference
Related Commands
ADD BLACK BOX
READ DESIGN
READ LIBRARY
REPORT ENVIRONMENT
-Both The specied handling for undened cells applies in both the
-Golden The specied handling for undened cells applies in only the
Golden design.
-Revised The specied handling for undened cells applies in only the
Revised design.
Command Reference
SET UNDEFINED PORT
SET UNDEfined Port
<Error | Ignore>
(Setup Mode)
Species how Conformal handles undened ports it encounters when reading in the Golden
and Revised libraries and designs. The system default is to report an error message if
there are any undefined ports referenced by the module instance.
Use the REPORT ENVIRONMENT command to display the settings for the undened ports
handling for the Golden and Revised designs. Execute this command before READ LIBRARY
and READ DESIGN.
Parameters
Related Commands
READ DESIGN
READ LIBRARY
REPORT ENVIRONMENT
Error Displays an error message for undened ports.
Ignore Ignores undened ports.
-Both Applies the specied handling for undened ports in both the
-Golden Applies the specied handling for undened ports to the Golden
design.
-Revised Applies the specied handling for undened ports to the
Revised design.
Command Reference
SET UNDRIVEN SIGNAL
SET UNDRiven Signal
< Z | 0 | 1 | X >
(Setup Mode)
Species globally how Conformal treats undriven signals in the Golden and Revised designs.
The system default specifies that undriven signals are classified as high-impedance
(always driven by Z) in the Golden and Revised designs.
Use the REPORT ENVIRONMENT command to display the settings for the undriven signals for
both the Golden and Revised designs. Execute this command before READ LIBRARY and
READ DESIGN.
Parameters
Related Command
REPORT ENVIRONMENT
Z Species undriven signals as high impedance (always driven by
Z). This option is the system default.
0 Species undriven signals as Logic 0.
1 Species undriven signals as Logic 1.
X Species undriven signals as unknown (X).
-Both Applies the state of the undriven signal to both the Golden and
-Golden Applies the state of the undriven signal to the Golden design.
-Revised Applies the state of the undriven signal to the Revised design.
Command Reference
SET WIRE RESOLUTION
SET WIre Resolution
<And | Or | Wire>
(Setup Mode)
Species howConformal treats the output behavior of multi-driven nets. The system default
for both the Golden and Revised designs specifies that multi-driven nets are treated
as a wire-AND behavior.
When you use the wire option and Conformal encounters a multi-driven net (that is, bus
contention) in a design, Conformal models this multi-driven net as TIE-X.
Note: This TIE-X is a pseudo input, not a dont care.
Use the REPORT ENVIRONMENT command to display the settings of the wire resolution for
the Golden and Revised designs.
Parameters
Related Command
REPORT ENVIRONMENT
And Assigns a wire-AND behavior to multi-driven nets. This option
is the system default.
Or Assigns a wire-OR behavior to multi-driven nets.
Wire Assigns a TIEX behavior to multi-driven nets.
-Both Applies the specied behavior of multi-driven nets to both the
-Golden Applies the specied behavior of multi-driven nets to the
Golden design.
-Revised Applies the specied behavior of multi-driven nets to the
Revised design.
Command Reference
SET X CONVERSION
SET X COnversion
<DC | E | 0 | 1>
(Setup Mode)
Species how Conformal handles X assignments when modeling the design. It takes effect
when changing from the Setup mode to the LEC mode.
The systemdefaults specify that X assignments are treated as Dont Cares for the Golden
and Error (E) Gates for the Revised design. If the X assignment space of the Revised
design is within the X assignment space of the Golden design, then the E gate is marked as
an extra unmapped point (redundant gate) after comparison.
Tip
The Revised X Handling feature enhances RTL-to-RTL comparisons. It ensures that
the Revised Xs are in the Golden Don't Care space. To turn off this feature, use
set x conversion dc -revised. This feature has been available since version
4.3.
However, use this option only if you are certain that the X assignment space of the
Revised design is within the X assignment space of the Golden design; otherwise,
potential errors might be masked.
Use the REPORT ENVIRONMENT command to display the settings of the X assignment for the
Parameters
DC Assigns Dont Care handling to X.
E Assigns Error Gate handling to X. E is a pseudo input.
0 Assigns Zero logic handling to X: 1b0.
1 Assigns One logic handling to X: 1b1.
-Both Applies the specied behavior of X assignments to both the
-Golden Applies the specied behavior of X assignments to the Golden
design.
Command Reference
Related Command
REPORT ENVIRONMENT
-Revised Applies the specied behavior of X assignments to the Revised
design.
Command Reference
SET XC
SET XC
(Setup Mode)
Analyzes switch and primitive drive strength to achieve the most accurate logic function
result. This technique can be applied to complex custommacros such as RAMand ROMand
is essential to accurate verication of circuits with complex layer switch nets.
Command Reference
SETENV
SETENV
<variable> <value>
(Setup / LEC Mode)
Assigns a value to an environment variable name.
Parameters
Examples
setenv LM_LICENSE_FILE 5280@host
where host is the license server host name.
Related Command
PRINTENV
variable Adds the specied variable to the environment.
value Assigns the specied value to the variable.
Command Reference
SUBSTITUTE BLACKBOX MODELS
SUBStitute BLackbox Models
[-NO_RENAME_RULE]
(Setup Mode)
Replaces all blackboxed modules in the design space with modules in the library space.
Use this command after running the READ DESIGN and READ LIBRARY commands.
Parameters
Related Command
ADD BLACK BOX
-Golden Applies to all blackboxed modules in the Golden design. This is
the default.
-Revised Applies to all blackboxed modules in the Revised design.
-NO_RENAME_RULE Does not use renaming rules for matching pin and module
names.
Command Reference
SUBSTITUTE BLACKBOX WRAPPER
SUBStitute BLackbox Wrapper
<pattern_list>
(Setup Mode)
Searches for each blackbox instance in your design whose module name matches those in a
specied pattern list, and replaces them with new, fully-dened modules. Use this module in
conjunction with the WRITE BLACKBOX WRAPPER command.
Parameters
Example
The following is a set of sample commands that show this and related commands in context.
Sample module:
<<< gol.v>>>
module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst,
cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout;
DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs),
.wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );
1. Specify that Conformal treat undened cells as blackboxes.
> set undefined cell black_box
2. Read in the Golden design, which contains our sample module.
> read design gol.v
3. Write a wrapper le dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module
DW_ram_r_w_s_dff_5_8_0.
write blackbox wrapper DW* -directory dir
break
Note: This command also generates synthesis script template les dir/dc.tcl and
dir/rc.tcl.
pattern_list Searches for blackbox instances whose module name matches
the specied pattern(s).
This option accepts the * wildcard.
Command Reference
4. Use the dir/dc.tcl script with your own synthesis tool to generate
dir/_DW_ram_r_w_s_dff_5_8_0.g.v.
5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v le into the design.
> read design -append dir/*.g.v
6. Substitute the old module of blackbox instance ram with the new module
_DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w
_s_dff_5_8_0.g.v:229).
> substitute blackbox wrapper DW*
Related Command
WRITE BLACKBOX WRAPPER
Command Reference
SYSTEM
SYSTEM
<string_command>
(Setup / LEC Mode)
Enables any command your UNIX operating system recognizes.
Note: In GUI mode, the Conformal software prints the return in the transcript window.
You can substitute the exclamation mark (!) for the word System, as shown in the Example
section, below.
Parameters
Example
system ls
system pwd
!pwd
string_command Any valid UNIX command.
Command Reference
TCLMODE
TCLMODE
(Setup / LEC Mode)
Switches from native Conformal command entry mode (VPX mode) to Tcl command entry
mode. VPX mode is the default command mode.
There are two types of Tcl mode commands:
I Native Tcl commands
I Conformal Tcl commands
Note: When issuing commands in Tcl mode mode, you must type them in lowercase.
For more information about native Tcl commands, refer to the public Tcl manual, which is
widely available online. Conformal Tcl commands are discussed in detail in the Encounter
Conformal Equivalence Checking User Guide.
Tip
To start the Conformal software in Tcl mode without executing any initialization
script, run the following command at a UNIX system prompt:
UNIX% lec -tclmode
Tip
In the Tcl command entry mode, you can save report data to a le using the
redirection command. For example, the following command saves the gate report
data to a le named gate.out:
TCL_SETUP> report_gate -type dff > gate.out
Related Command
VPXMODE
Command Reference
TEST RENAMING RULE
TESt REnaming Rule
<-Design [-NOprint | -Print <Single | Pair | Group>]
|<string>
|-GATE_id <gate_id>>
[-All | -NEw_rule <string> <string>]
[-MAp [-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>
|-NOTYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>]
|-MOdule |-PIn [-BBox <module_name>]]
[-RULE_USAGE | -NORULE_USAGE]
[-SORTNAme]
[-File <filename> [-REPlace]]
[-VErbose]
(LEC Mode)
Displays the results of the key point matching based on the user-specied renaming rules.
Use this command to obtain a quick summary of how well the key points will be mapped
based on the specied renaming rules. Test new and existing rules.
Parameters
-Design Tests the renaming rules on the entire design. This argument
instructs Conformal to display a summary of the Golden and
Revised pairs and groups and Golden and Revised single
un-grouped key points for the entire design.
-NOprint Does not display the key point pairs, un-grouped single key
points, or grouped key points. This is the default.
-Print Displays key points as follows:
Single Un-grouped single key points
Pair Key point pairs
Group Grouped key points
string A string that the renaming rule uses as an example.
-GATE_id gate_id Tests renaming rules on the specied gate.
-All Tests all renaming rules. This is the default.
-NEw_rule string string
Command Reference
A new renaming rule:
The rst string is the pattern to be matched; the second string is
the substitution pattern.
-MAp Tests the renaming rules on key points that will be mapped.
-TYpe Tests renaming rules for all key points of the specied type.
The available types are as follows:
PI Primary Inputs
E TIE-E gates
Z TIE-Z gates
DFF D ip-ops
DLAT D-latches
feedback loops
BBOX Blackboxes
PO Primary Outputs
-NOTYpe Tests renaming rules for all key points except the specied
types. The available types are as follows:
PI Primary Inputs
E TIE-E gates
Z TIE-Z gates
DFF D ip-ops
DLAT D-latches
feedback loops
BBOX Blackboxes
PO Primary Outputs
-MOdule Tests the renaming rules on the modules in the design.
-PIn Tests the renaming rules on pin names of blackboxes.
Command Reference
Examples
I The following command displays the summary results of the renaming rules on the
designs:
test renaming rule -design -all
I The following command displays a list of all Golden/Revised un-grouped single key
points:
test renaming rule -design -print single
I The following command displays a list of all Golden/Revised grouped key points:
test renaming rule -design -print group
I The following command displays a list of all Golden/Revised pair key points:
test renaming rule -design -print pair
I The following command writes a list of all Golden/Revised grouped key points to a le:
test renaming rule -design -print group -file group_list
I The following command displays the summary results of the renaming rule on the
designs with a new rule:
test renaming rule -design -new_rule <string> <string>
-RULE_USAGE Displays the number of matches for the specied string. This
option is turned on by default.
-NORULE_USAGE Does not display the number of matches for the specied
renaming rule.
-BBox module_name Tests the pin renaming rule on the specied blackbox module.
The default is to test all blackboxes.
-Both Tests the renaming rules on both the Golden and Revised
-Golden Tests the renaming rules on the Golden design.
-Revised Tests the renaming rules on the Revised design.
-SORTNAme When this option is used with the -print option, the results
appear in alphabetical order by name.
-File filename Writes the results to the specied le.
-REPlace Replaces the above le, if it exists.
-VErbose Displays both the original key point name and the renamed key
point.
Command Reference
I The following command displays the summary results of the renaming rules applied to a
sample string:
test renaming rule <string> -all
I The following command displays the summary results of the new renaming rule applied
to a sample string:
test renaming rule <string> -new_rule <string> <string>
Related Commands
ADD RENAMING RULE
MAP KEY POINTS
SET NAMING RULE
Command Reference
UNIQUIFY
UNIQuify
<module_name | -ALL [-Library | -NOLibrary]>
[-Force]
[-USE_RENaming_rules]
(Setup Mode)
Makes the specied module, which has multiple instances, unique. This command lets you
remedy the incompatible instantiations warnings during hierarchical script generation. If
Conformal does not make the modules unique, they are not included in the hierarchical dole.
When using hierarchical compare for abort resolution, this command allows you to include
more modules in the hierarchical dole, therfore reducing the compare complexity of helping
resolve aborts.
For more information, see Hierarchical Comparison for Abort Resolution in the Encounter
Conformal Equivalence Checking User Guide.
Parameters
module_name Makes the specied module(s) unique.
-ALL Makes all modules in the specied design unique.
-Library Makes all modules in designs and libraries unique. This is the
default.
-NOLibrary Makes all modules in designs unique.
-Force Forcibly makes specied modules in the Golden or Revised
design unique, even if those modules have not been made
unique in the complementing design. (For example, forcibly
make Golden modules unique when the Revised modules have
not been made unique.)
-USE_RENaming_rules Considers renaming rules for instances.
When adding renaming rules, the software renames the Golden
design instances to be same as in the Revised design, so
running a subsequent UNIQUIFY command with this option will
make the Golden modules that have matching instance names
in the Revised design unique.
Command Reference
Example
The following command example creates a hierarchical dole script named hier.do
containing the compare script for the sub-modules and the root module, then runs
hierarchical compare. This is can help in resolving aborts.
...
uniquify -all
write hier_compare dofile hier.do
run hier_compare hier do
Related Commands
RESOLVE
RUN HIER_COMPARE
-Summary Summarizes the outcome of making modules unique. This is
the default.
-Verbose Provides expanded information about the modules that were
made unique.
-Golden The specied modules are in the Golden design. This is the
default.
-Revised The specied modules are in the Revised design.
Command Reference
USAGE
USAge
[-Elapse | -Delta ]
(Setup / LEC Mode)
Displays the total CPU run time and peak memory use since you started Conformal.
Parameters
Related Command
COMPARE
-Elapse Displays the elapsed time of a process.
-Delta Displays the difference, in seconds, between the current CPU
run time and CPU run time when you last issued the usage
command.
Command Reference
VALIDATE CIRCUIT
VALidate CIrcuit
[-Revised | -Golden]
[-BBOXSCRipt <filename>]
[-MODule <module name>]
[-DOfile <filename>]
[-POWERPINs <name 0> <name 1> <name N>]
[-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs]
[-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput]
[-ASM | -NOASM]
(Setup Mode)
Checks circuit libraries and custom blocks (when applicable), and enables equivalence
checking on the full integrated circuit design. Use this command at the integrated-circuit level
for RTL or Gate to nal circuit. This application is for checking the consistency of pre-dened
libraries during design verication.
Important
Do not use this command for validating the library itself. To validate library itself, use
the VALIDATE LIBRARY command instead.
For both the Golden and Revised designs, refer to the same library so that any
inconsistencies at the library cell level will not affect the equivalence checking on design level.
After which, all the library cells under this checking will be replaced by their counterpart
reference cells.
Note: Conformal Ultra users can use this to check a veried circuit. However, you need a
Conformal Custom license to diagnose logic abstraction and errors that relate to library
comparisons.
Parameters
-Revised Validates the Revised database. This is the default.
-Golden Validates the Golden database.
-BBOXSCRipt <filename>
Creates a dole with the specied name that blackboxes all
validated cells for structural verication, which is more
accurate than logical verication.
Command Reference
-MODule <module name>
Validates the specied module.
By default, Conformal Ultra validates the root module. Use
this option to validate a module other than the root module.
Note: Conformal Ultra validates only the topmost library and
custom cells (that exist in the reference side) that are used by
the specied module.
-DOfile <filename>
Species the name of the dole that was used to verify all
custom blocks so that they can be re-checked.
If a custom module has not been veried yet, blackbox it
before running the VALIDATE CIRCUIT command.
VALIDATE CIRCUIT can check for consistency in custom
blocks, but it cannot verify custom blocks. Use Conformal
Custom to verify custom blocks.
-POWERPINs <name 0> <name 1> ... <name N>
Denes names for the pin(s) that are used as extraneous
power pins, which are ignored during cell verication. For
multiple power pins, each pin name must be separated by a
space.
Cadence recommends that you use the ADD PIN
CONSTRAINT command to tie power pins to 1 and ground
pins to 0.
-PRESERVE_MODEL_OPTIONs
Command Reference
Preserves any user-dened settings made prior to this
command. This is the default.
This option disables any attening options that VALIDATE
CIRCUIT sets by default.
By default, the following atten model options are set when
VALIDATE CIRCUIT compares two modules:
-seq_redundant
-latch_fold
-all_inv_seq_merge
-all_seq_merge
-seq_const
See the SET FLATTEN MODEL command for an explanation
of these options.
With -PRESERVE_MODEL_OPTIONs, the comparison is done
without changing any atten model options. Any options that
were set prior to running validate circuit are used instead.
-NO_PRESERVE_MODEL_OPTIONs
Does not disable any attening options that VALIDATE
CIRCUIT sets by default.
-POWERPIN_TO_INput
Species that if there are power pins that are input/output
pins, they will be changed to input pins before validation. This
is the default.
-NO_POWERPIN_TO_INput
Species that power pins that are input/output pins will NOT
be changed to input pins before validation.
algorithm. This helps to analyze loop structure to produce
better modeling of state elements, such as D-Latch, DFF, and
bus-keeping I/O logic. This is the default.
Command Reference
Related Commands
READ DESIGN
READ LIBRARY
SET FLATTEN MODEL
algorithm.
Tip
Command Reference
VALIDATE LIBRARY
VALidate LIbrary
[-Revised | -Golden]
[-NOSPIce | -SPIce]
[-NOGOLPINDir | -GOLPINDir]
[-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs]
[-POWERPINs <name 0> <name 1> <name N>]
[-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput]
[-ASM | -NOASM]
(Setup Mode)
Note: This is a Conformal Ultra and Conformal Custom command.
Compares all top-level cells with matching names. Conformal abstracts the modules on the
SPICE side before comparison. This application is for library verication during library design.
Important
To abstract SPICE modules, you must have a Conformal Custom license.
Parameters
-Revised Validates the Revised database. This is the default.
-Golden Validates the Golden database.
-NOSPIce Abstracts and validates the modules that are not SPICE. This
is the default.
Note: This option requires a Custom license.
-SPIce Abstracts and validates the SPICE modules.
Note: This option requires a Custom license.
-NOGOLPINDir Does not copy the pin directions from the Golden design to the
Revised design. This is the default.
-GOLPINDir Copies the pin directions fromthe Golden design to the Revised
design. This is for all pins within the library cells being validated.
Command Reference
-PRESERVE_MODEL_OPTIONs
Preserves any user-dened settings made prior to this
command. This is the default.
This option disables any attening options that VALIDATE
LIBRARY sets by default.
-NO_PRESERVE_MODEL_OPTIONs
Does not disable any attening options that VALIDATE
LIBRARY sets by default.
-POWERPINs <name 0> <name 1> ... <name N>
Denes names for the pin(s) that are used as extraneous power
pins, which are ignored during cell verication. For multiple
power pins, each pin name must be separated by a space.
Cadence recommends that you use the ADD PIN
CONSTRAINT command to tie power pins to 1 and ground pins
to 0.
-POWERPIN_TO_INput Species that if there are power pins that are input/output pins,
they will be changed to input pins before validation. This is the
default.
-NO_POWERPIN_TO_INput
Species that power pins that are input/output pins will NOT be
changed to input pins before validation.
algorithm. This helps to analyze loop structure to produce better
modeling of state elements, such as D-Latch, DFF, and
bus-keeping I/O logic. This is the default.
algorithm.
Tip
Command Reference
Related Command
VALIDATE CIRCUIT
Command Reference
VERSION
VERsion
(Setup / LEC Mode)
Displays the current version release number of Conformal. You can use this command after
the SET LOG FILE command so the version becomes a part of the transcript log. In this way,
you record the Conformal version that created your results. This command is also helpful
when you use the SAVE SESSION and RESTORE SESSION commands, because you must
use the same Conformal version when you restore a session.
Related Commands
RESTORE SESSION
SAVE SESSION
SET LOG FILE
Command Reference
VPXMODE
VPXMODE
(Setup / LEC Mode)
Switches from Tcl mode to native Conformal command entry mode (VPX mode). VPX is the
default command mode.
Important
When issuing this command in the Tcl command interpreter, you must type this in
lowercase. For example:
TCL_LEC> vpxmode
Tip
In VPX mode, you can save report data to a le using the redirection command. For
example, the following command saves the gate report data to a le named
gate.out:
SETUP> report gate -type dff > gate.out
Related Command
TCLMODE
Command Reference
WRITE BLACKBOX WRAPPER
WRIte BLackbox Wrapper
-DIRectory <dirname> <pattern_list>
(Setup Mode)
Creates a wrapper for each blackbox instance in your design whose module name matches
those in a specied pattern list. Use this command to help complete equivalency checking for
designs that contain DesignWare or ChipWare blackboxed modules.
This command produces a module instantiation wrapper le for each blackboxed module
wrapper, and synthesis script templates that you can use with your own synthesis tool to
synthesize the modules that Conformal blackboxed.
Synthesize the wrapper modules using the outputted scripts. Then, read in the
newly-synthesized les using the READ DESIGN -append command. Finally, use the
SUBSTITUTE BLACKBOX WRAPPER command to substitute the old blackboxed modules with
the newly synthesized modules.
Note: When specifying the cells that Conformal will treat as blackboxes, use the set
undefined cell black_box command instead of the add notranslate modules
command.
Parameters
Examples
The following is a set of sample commands that show this and related commands in context.
Sample module:
<<< gol.v>>>
module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst,
cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout;
DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs),
.wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );
-DIRectory <dirname> Writes out the module instantiation wrapper le and the
scripts to this directory.
pattern_list Writes out module wrappers for blackbox instances
whose module name matches the specied pattern(s).
This option accepts the * wildcard.
Command Reference
1. Specify that Conformal treat undened cells as blackboxes.
> set undefined cell black_box
2. Read in the Golden design, which contains our sample module.
> read design gol.v
3. Write a wrapper le dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module
DW_ram_r_w_s_dff_5_8_0.
write blackbox wrapper DW* -directory dir
break
Note: This command also generates synthesis script template les dir/dc.tcl and
dir/rc.tcl.
4. Use the dir/dc.tcl script with your own synthesis tool to generate
dir/_DW_ram_r_w_s_dff_5_8_0.g.v.
5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v le into the design.
> read design -append dir/*.g.v
6. Substitute the old module of blackbox instance ram with the new module
_DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w
_s_dff_5_8_0.g.v:229).
> substitute blackbox wrapper DW*
Related Command
SUBSTITUTE BLACKBOX WRAPPER
Command Reference
WRITE COMPARED POINTS
WRIte COmpared Points
[-CLass <All | Eq | INVequivalent | NONeq | ABort | NOTcompared>]
[-TYpe <All | PO | DFf | DLat | Bbox | Cut>]
[-File <filename>]
[-Replace]
(LEC Mode)
Writes compared points information to a le. You can use this le to add a specic class and
type of compared points to a compare list.
Parameters
-CLass Writes out the class of compared points. By default, the
command writes out all classes.
All Writes all compared point classes. This is
the default if you do not specify the -CLass
option.
Eq Writes compared points that are equivalent.
INVequivalent
Writes the compared points that are inverted
equivalent.
NONeq Writes the compared points that are
non-equivalent.
ABort Writes the aborted compared points.
NOTcompared Writes the compared points that are not
compared.
-TYpe Writes out the type of compared points. By default, the
command writes out all types.
All Writes all compared point types. This is the
default if you do not specify the -TYpe
option.
PO Writes the compared points of the primary
outputs.
DFf Writes the compared points of the D
ip-ops.
Command Reference
Related Commands
ADD COMPARED POINTS
DLat Writes the compared points of the D-latches.
Bbox Writes the compared points of the
blackboxes.
Cut Writes the compared points for articial
gates that break combinational loops.
-File <filename> Species the lename.
-Replace Replaces the existing le.
Command Reference
WRITE DESIGN
WRIte DEsign
<filename>
[ | -ALL | -BBOX]
[-Used]
[-Library]
[-REPlace]
[-RTL]
[-TEST_VIEW]
(Setup / LEC Mode)
Writes out the Golden or Revised design in Verilog format to examine how Conformal
abstracts RTL descriptions into gate-level descriptions.
Parameters
filename Writes the design to this le.
-ALL Writes out all modules that are stored in the design space.
-BBOX Writes out all of the empty module descriptions of blackboxes in
the design.
By default, the command writes out the design tree of the root
module, excluding modules in the library space.
-Used Writes out the specied modules and all the referenced
modules, including modules in the design space.
-Library Writes out the library information.
-RTL Outputs word-level operator expressions such as *, +, and -.
By default, the command writes out the design without using the
word-level operators. Without this option, the command writes
out the design in Verilog primitive gates.
Command Reference
Related Command
READ DESIGN
-TEST_VIEW Writes out the abstraction result of ABSTRACT LOGIC
-test_view.
The result might include Encounter Test primitives. To read the
netlist back, use the READ DESIGN commands -define
option for ET_EC_MODEL. For example:
read design <netlist> -define ET_EC_MODEL
-Golden Writes out the Golden design only. This is the default.
-REVised Writes out the Revised design only.
Command Reference
WRITE ECO DESIGN
WRIte ECo Design
[-OVERWrite | -NEWFILE [filename_fmt] | -REVIEWonly]
[-BACKup [filename_fmt]]
[-REPORT [filename]]
[-REPlace]
(Setup Mode)
Writes out the ECOnetlist and attempts to reduce the number of text differences between the
original netlist le and the ECOnetlist le. This will reduce the number of differences reported
by the UNIX diff command between the two les.
Limitations
I Does not work with VHDL netlists.
I Does not work if you atten the design during the ECO process.
Parameters
-OVERWrite Overwrites the original les. This is the default.
-NEWFILE [filename_fmt]
Writes the design into new les. The default format for the new
les is %s.eco, where %s is the original lename.
-REVIEWonly Reviews the changes only and does not write out the design
-BACKup [filename_fmt]
Creates a back up original les if using the -OVERWrite
option. The default format for the backup les is %s.bak,
where %s is the original le name.
-REPORT [filename]
Generates a report showing the differences between the
original design and the ECO design. If the lename is not
provided, the report will print to the screen.
-REPlace Replaces the le if it already exists when using the -NEWFILE
and -REPORT options.
Command Reference
Example
The following is a sample script that writes out the a.v.eco and b.v.eco les after running
the Conformal ECO commands:
read design a.v b.v -golden
// ECO process
analyze eco ...
optimize patch ...
write eco design -newfile -replace
Related Commands
REPORT ECO CHANGES
Command Reference
WRIte HIer_compare Dofile
<filename>
[-MODULE <golden_module> <revised_module>
[-HIERarchical | -FLATten]]
[-Black_box | -NOBlack_box]
[-CONDitional]
[-Exact_pin_match | -NOExact_pin_match]
[-NOConstraint
| -Constraint [-EXTRACT_Clock] [-INPUT_OUTPUT_Pin_equivalence]
[-RUN_HIER_compare]
]
[-PREPEND_String <string>]
[-APPEND_String <string>]
[-COMPARE_String <string>]
[-CONDitional]
[-Threshold <integer>]
[-LEVEL <integer>]
[-All]
[-Usage]
[-Replace]
[-RETIMED_modules]
[-IGNORE_MISMATCH_ports]
[-VERBOSE]
(Setup Mode)
Writes out a hierarchical dole script that veries the two hierarchical designs starting from
the lower-level modules and progressing to the top root module. Use options to specify one
of the following actions:
I Blackbox modules after comparison
I Write modules with different numbers of pins to the dole script
I Propagate the constraints to lower-level modules and apply them to the dole script
I Change the minimum number of module primitives considered for hierarchical
comparison
This command also generates a dole script to compare two libraries, such as a Liberty and
Verilog library. Use the -all option to write all library models to the dole script for
comparison.
Note: Hierarchical comparison is also useful in resolving aborts. See the UNIQUIFY
command for more information.
Command Reference
Parameters
<filename> Species the name of the dole script that veries design
hierarchy.
-MODULE <golden_module> <revised_module>
Writes the specied Golden module and Revised module to the
-HIERarchical Includes all of the submodules of the specied module in the
hierarchical dole script. This is the default.
-FLATten Flattens all of the submodules of the specied module.
-Black_box Blackboxes each module after comparison. This is the
default.
-NOBlack_box Does not blackbox each module after comparison.
-CONDitional Automatically merges the module to the next level in the
hierarchy if the comparison at the current level was
unsuccessful.
-Exact_pin_match Writes only those modules with matching pin names to the
hierarchical dole script. This is the default.
-NOExact_pin_match Writes all modules to the hierarchical dole script.
-NOConstraint Does not apply the root module constraints and equivalences to
the hierarchical dole script. This is the default.
-Constraint Propagates root module constraints and equivalences and
applies them to the hierarchical dole script.
-EXTRACT_Clock Extracts the clock pins in the Golden and Revised designs, and
automatically adds the renaming rules to hierarchical dole
script to map the clock ports in the two designs. This can be
used when the design has undergone Clock-Tree-Synthesis
(CTS).
-INPUT_OUTPUT_Pin_equivalence
Extracts input-output pin equivalences within a module and
applies them to hierarchical dole script. This can be used
when the design has feedthroughs or feedback buffers.
Command Reference
-RUN_HIER_compare Writes out more modules in the hierarchical dole script by
performing less stringent constraint checking.
The resulting dole must only be processed by the RUN
HIER_COMPARE command and its default options.
-PREPEND_String <string>
Appends any string of commands to the hierarchical dole
script before key point comparison for each module.
Use ; to separate commands.
Use double quotes to surround each prepended command (see
Examples).
-APPEND_String <string>
Appends any string of commands to the hierarchical dole
script after key point comparison for each module.
Use the semi-colon character (;) to separate commands. Use
double quotes to surround each appended command (see
Examples).
-COMPARE_String <string>
Replaces the default compare command with a string of
compare commands in the hierarchical dole script generation
for each module.
Use the semi-colon character (;) to separate commands. Use
double quotes to surround each compare command (see
Examples).
-CONDitional Skips blackboxing for nonequivalent submodules during the
hierarchical comparison. (The end result is that Conformal
attens these submodules.)
To report the attened modules, use the report
hier_compare result -flattened command.
-Threshold integer This threshold is the minimum number of primitives within a
module that will be written to the hierarchical dole script. The
minimum default number is 50 primitives.
-LEVEL integer Writes all modules to the hierarchical dole script up to the
specied hierarchical level.
Command Reference
Examples
write hier_compare dofile hier.do -replace
write hier_compare dofile lec.do -replace
write hier_compare dofile hier.do -append_string usage -prepend_string report
unmapped points -notmapped -replace
I The following is a sample dole that reads in the two hierarchical designs, writes out the
hierarchical dole script, and compares design hierarchies:
read library golden.lib -verilog -golden
read design golden.v -verilog -golden
read library revised.lib -verilog -revised
read design revised.v -verilog -revised
write hier_compare dofile hier.do -replace
set log file hier.log -replace
dofile hier.do
exit -force
I The following is a sample dole that reads in a synthesis library and simulation library,
writes out all of the library models, and compares library hierarchies:
read design syn.lib -liberty -golden
read design simulation.v -verilog -revised
write hier_compare dofile lib_ver.do -replace -all
-All Writes all library modules to the hierarchical dole script.
All applies within the given defaults. Use this option for library
verication.
-Usage Executes the USAGE command after each comparison and at
the end of the hierarchical comparison.
-RETIMED_modules Writes out only those modules which have the
PIPELINE_RETIME attribute attached to them.
Use the ADD MODULE ATTRIBUTE command to attach the
PIPELINE_RETIME attribute to a module.
-IGNORE_MISMATCH_ports
Forces all modules with mismatched ports to be written out in a
hierarchical dole.
-VERBOSE Provides additional information when writing out the
Command Reference
set log file lib_ver.log -replace
dofile lib_ver.do
exit -force
I In the following command, the default compare command is replaced with two
commands during each module comparison, set compare effort low and
compare -abort_stop 1 -noneq_stop 1:
write hier_compare dofile -compare_string \
set compare effort low; compare -abort_stop 1 -noneq_stop 1
I The following command example creates a hierarchical dole script named hier.do
containing the compare script for the sub-modules and the root module, then runs
hierarchical compare. This is can help in resolving aborts.
...
uniquify -all
write hier_compare dofile hier.do
run hier_compare hier do
Related Commands
ADD NOBLACK BOX
DELETE NOBLACK BOX
READ DESIGN
READ LIBRARY
REPORT NOBLACK BOX
RUN HIER_COMPARE
SET NAMING RULE
UNIQUIFY
Command Reference
WRITE LIBRARY
WRIte LIbrary
<filename>
[-Verilog]
[-REPlace]
(Setup / LEC Mode)
Writes out the Golden or Revised library to a Verilog le. The default is to write out the
library as functional Verilog model descriptions.
Use this command to examine how Conformal abstracts complex UDP library models.
Parameters
Related Command
READ LIBRARY
filename Species the library lename.
-Verilog Writes out the library in Verilog format. This is the default.
-Golden Writes out only the Golden library. This is the default.
-REVised Writes out only the Revised library.
Command Reference
WRITE MAPPED POINTS
WRIte MApped Points
<filename>
[-CLass < Full | System | User>
[-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>]
[-NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>]
[-REPlace]
(LEC Mode)
Writes the mapped point information to a le. If the comparison needs to be done at a later
time, you can use this command to accelerate the mapping process.
Use the READ MAPPED POINTS command to read the le.
Use the tilde character (~) to shorten the les path.
Parameters
filename Species the lename.
-CLass Writes out the System, User, or Full classes of mapped points.
Full Both the User and System class. This is
the default.
System Key points that are mapped automatically.
User User class: key points that are manually
mapped with the ADD MAPPED POINTS
command.
-TYpe mapped_keypoint_type
Writes only the mapped key points of the specied type.
Available types are as follows:
PI Primary input
E TIE-E
Z TIE-Z
DFf D ip-op
DLat D-latch
Command Reference
Related Commands
READ MAPPED POINTS
BBox Blackbox
PO Primary output
-NOTYpe mapped_keypoint_type
Does not write the mapped key points of the specied type.
Available types are as follows:
PI Primary input
E TIE-E
Z TIE-Z
DFf D ip-op
DLat D-latch
BBox Blackbox
PO Primary output
Command Reference
WRITE MEMORY PRIMITIVE
WRIte MEmory Primitive
<filename>
[-Module <name*> | -All]
[-REPlace]
[-OPTionsdef <filename1>]
[-COMmondef <filename2>]
(LEC Mode)
Writes memory primitives to a le. Use this command to retrieve information for simulation.
For additional information about memory primitives, refer to the Memory Primitive Data
Sheet located at <install_dir>/doc/MEM_datasheet.pdf.
Note: The wildcard (*) represents any zero or more characters in module names.
Parameters
filename Species the lename.
-Module name* Writes only the memory primitives for the specied module.
-All Writes out memory primitives for all modules.
-OPTionsdef <filename1>
Writes parameter option denitions to a separate le. This will
write the define statements, which are options to available
parameters, from the memory primitives to a separate le.
-COMmondef <filename2>
Writes the common module called Vpx_wireOrlatOrff_data
to a separate le. This module is common to all memory
primitives.
You can write common memory primitive denitions to a separate
le during each call to WRITE MEMORY PRIMITIVE, or you can
use an existing le using the -rep option.
Command Reference
Related Command
READ DESIGN
Command Reference
WRIte PArtition Dofile
<filename>
[-Map filename]
[-Usage]
[-Replace]
[-PREPEND_String <string>]
[-APPEND_String <string>]
[-COMPARE_String <string>]
(Setup / LEC Mode)
Writes out a partition dole script based on the key point names specied with the ADD
PARTITION KEY_POINT command. The number of compare iterations is based on whether
the key point names have all-pattern, one-hot, or one-cold constraints.
Parameters
filename The partition dole is written to this le.
-Map filename Uses the specied le for key point mapping. (You must use the
WRITE MAPPED POINTS command before using this option.)
-Usage Executes the USAGE command after each comparison and at
the end of the partition dole.
-PREPEND_String <string>
Appends any string of commands to the partition dole script
before key point comparison for each module.
Use double quotes to surround each prepended command (see
Examples below).
-APPEND_String <string>
Appends any string of commands to the partition dole script
after key point comparison for each module.
Use double quotes to surround each appended command (see
Examples below).
Command Reference
Example
write partition dofile partition.do -replace
write partition dofile ptn.do -append_string usage -prepend_string report
unmapped points -notmapped -replace
In the following command, the default compare command is replaced with two commands
during each module comparison, set compare effort low and compare
-abort_stop 1 -noneq_stop 1:
write partition dofile -compare_string set compare effort low; compare -abort_stop
1 -noneq_stop 1
Related Commands
WRITE MAPPED POINTS
-COMPARE_String string
Replaces the default compare command with a string of
compare commands in the partition dole script generation for
each module.
Use double quotes to surround each compare command (see
Examples).
Command Reference
WRITE RULE CHECK
WRIte RUle Check
<filename>
[-DEsign | -LIbrary]
[-Golden | -REVIsed]
[-Replace]
(Setup Mode)
Writes the rule violations into a rule le. Use this command the rst time you run a session.
For later runs, exclude the violations already agged with the read rule check -exclude
<filename> command.
Parameters
Examples
In the following example, the second report rule check will not report any rules.
read design g.v -golden
read design r.v -revised
write rule check rule.g -golden -replace
write rule check rule.r -revised -replace
read design g.v -golden -replace
read design r.v -revised -replace
filename Writes rule check violations to the specied le.
-DEsign Writes only design rule check violations. If you do not specify
-design or -library, Conformal writes rule check violations
-LIbrary Writes only library rule check violations. If you do not specify
-design or -library, Conformal writes rule check violations
-Golden Writes rule check violations from the Golden design. This is
the default.
-Revised Writes rule check violations from the Revised design.
-REPlace Replaces the previously saved le.
Command Reference
read rule check rule.g -exclude -golden
read rule check rule.r -exclude -revised
Related Command
READ RULE CHECK
3
HDL Rule Check Messages
This chapter is organized into sections by HDL rule categories. Each section lists all of the
rules and messages for the specied category. Each rule message is dened and followed by
a sample case that can cause the message. The examples include a brief explanation that
direct you to the pertinent lines of code, which appear in bold type.
The rule categories included in this chapter are listed below. Register Transfer Level
messages are a super-set of rules that apply to both Verilog and VHDL. However, rules
included in the Verilog category apply to Verilog, only.
I Directive on page 522
I File on page 549
I Hierarchy on page 551
I Ignored on page 584
I Register Transfer Level on page 603
I SPICE Netlist Format on page 720
I System Verilog on page 733
I User-Dened Primitive on page 752
I Verilog on page 764
Within each category, rules are grouped in sets according to their relationship to each other.
For example, DIR1.1 and DIR1.2 both relate to pragmas. Likewise, IGN3.1 and IGN3.2 are
grouped because they both address how the checker handles duplications.
Directive
This category of rules applies to designs that include directives or pragmas. The following
table lists the Directive (DIR) rule check numbers and messages.
Rule Number Message
DIR1.1 built_in pragma applied to function
DIR1.2 map_to_operator pragma applied to function
DIR1.3 return_port_name pragma applied to function
DIR2.1 full_case directive is detected
DIR2.2 parallel_case directive is detected
DIR3.1 synthesis/translate/compile on/off directive is detected
DIR3.2 dc_script_begin and dc_script_end directives is detected
DIR4.1 HDL directive/pragma is unsupported
DIR4.2 HDL directive/pragma is supported
DIR4.3 HDL directive/pragma is disabled
DIR4.4 HDL directive/pragma is ignored
DIR5.1 Conformal multi_port directive is detected
DIR5.2 Conformal multi_port directive is detected
DIR5.3 Conformal mem_rowselect directive is detected
DIR5.4 Conformal conformal cutpoint directive is supported
DIR6.1 Ignored compiler directive is detected
DIR6.2 Supported compiler directive is detected
DIR7.1 Unsupported synthesis attribute is detected
DIR7.2 Supported synthesis attribute is detected
DIR8.1 protected/endprotected pragma is used
DIR9.1 Verilog celldene is for timing simulation. Use the LIBERTY
library instead
DIR9.2 Illegal to redene a Verilog compiler directive as a macro
DIR9.3 Verilog compiler directive is redened as a macro
DIR1.1
Message
built_in pragma applied to function
Default Severity
Warning
Description
The design applies the built_in pragma to a function. If the checker supports the specied
pragma, it also displays the rule DIR4.2 message.
Example
In the following example, pragma built_in is inserted in function my_or. See line 4 (in
bold).
ARCHITECTURE arch OF test IS
FUNCTION my_or ( l, r : bit )
RETURN bit IS
-- pragma built_in SYN_OR
BEGIN
RETURN '0';
END my_or;
BEGIN
proc2 : PROCESS
BEGIN
out0 <= my_or (in1,in2);
END PROCESS;
END arch;
DIR1.2
Message
map_to_operator pragma applied to function
Default Severity
Warning
Description
The design applies the map_to_operator pragma to a function. If the checker supports the
specied pragma, it also displays the rule DIR4.2 message.
Example
In the following example, the map_to_operator pragma is inserted in function my_leq.
See line 5 (in bold).
FUNCTION my_leq ( l, r : bit_vector
(3 downto 0) )
RETURN boolean IS
-- pragma map_to_operator LEQ_TC_OP
BEGIN
RETURN false;
END my_leq;
BEGIN
proc2 : PROCESS
BEGIN
out0 <= my_leq (in1,in2);
END PROCESS;
END arch;
DIR1.3
Message
return_port_name pragma applied to function
Default Severity
Warning
Description
The design applies the return_port_name pragma to a function that contains this pragma.
If the checker supports the specied pragma, it also displays the rule DIR4.2 message.
Example
In the following example, the return_port_name pragma on line 8 (in bold) is inserted in
function DWF_div_uns.
module test;
parameter a_width = 16;
parameter b_width = 16;
function [a_width-1 : 0] DWF_div_uns;
// Function to compute the unsigned quotient
// pragma map_to_operator DIV_UNS_OP
// pragma return_port_name QUOTIENT
input [a_width-1 : 0] A;
input [b_width-1 : 0] B;
begin
// pragma translate_off
return 0;
// pragma translate_on
end
endfunction
endmodule
DIR2.1
Message
full_case directive is detected
Default Severity
Warning
Description
The design includes a full_case directive in a case statement. If the checker supports the
specied directive, it also displays the rule DIR4.2 message.
Example
The following example uses the synopsys full_case directive in line 7 (in bold).
module test ( a, e, sel, out0);
input a, e;
input sel;
output out0;
reg out0;
always @(sel or a or e) begin
case(sel) // synopsys full_case
1'b1 : out0 = a;
default: out0 = e;
endcase
end
endmodule
DIR2.2
Message
parallel_case directive is detected
Default Severity
Warning
Description
The design includes a parallel_case directive used in a case statement. If the checker
supports the specied directive, it also displays the rule DIR4.2 message.
Example
The following example includes the synopsys parallel_case directive on line 7 (in bold).
input a, e;
input sel;
output out0;
reg out0;
case(sel) // synopsys parallel_case
1'b1 : out0 = a;
default: out0 = e;
endcase
end
endmodule
DIR3.1
Message
synthesis/translate/compile on/off directive is detected
Default Severity
Warning
Description
The design includes a directive belonging to one of the following classes:
I
synthesis on/off
I
translate on/off
I
compile on/off
If the checker supports this directive, it also displays the rule DIR4.2 message.
In the Conformal Equivalency Checker, you can also dene your own directive to turn
synthesis on and off with the following commands:
I SET_ATTR INPUT_PRAGMA_KEYWORD <string>
I SET SYNTHESIS_OFF_COMMAND <string>
I SET SYNTHESIS_ON_COMMAND <string>
Example
The following example includes the synopsys translate_off and synopsys
translate_on directives. See lines 5 and 7 (in bold).
module test ( clk, din, dout );
input clk, din;
output dout;
reg dout;
// synopsys translate_off
reg [0:0] mem [1:0];
// synopsys translate_on
always @(posedge clk)
dout <= din;
endmodule
DIR3.2
Message
dc_script_begin and dc_script_end directives is detected
Default Severity
Warning
Description
The design includes the dc_script_begin and dc_script_end directives. If the checker
supports the specied directives, it also displays the rule DIR4.2 message..
Example
In the following example, the design includes the dc_script_begin and dc_script_end
directives. See lines 5 and 7 (in bold).
input clk, din;
output dout;
reg dout;
// set_implementation wall MPYDW
dout <= din;
endmodule
DIR4.1
Message
HDL directive/pragma is unsupported
Default Severity
Warning
Description
The design includes one or more HDL directives or pragmas that the checker does not
support.
Example
In the following example, the checker does not support the synopsys
not_defined_or_not_supported directive. See line 6 (in bold).
module test ( clk, in0, out0 );
input clk, in0;
output out0;
reg out0;
always @( posedge clk )
// synopsys not_defined_or_not_supported
out0 <= in0;
endmodule
DIR4.2
Message
HDL directive/pragma is supported
Default Severity
Warning
Description
The design includes one or more HDL directives or pragmas that the checker supports.
Example
In the following example, the checker supports the synopsys full_case directive. See line
7 (in bold).
input a, e;
input sel;
output out0;
reg out0;
case(sel) // synopsys full_case
1'b1 :
out0 = a;
default:
out0 = e;
endcase
end
endmodule
DIR4.3
Message
HDL directive/pragma is disabled
Default Severity
Warning
Description
The design includes one or more HDL directives or pragmas that were disabled by the user.
The command used to disable a directive or pragma is:
set directive off <directive_name>
Example
In the following example, the design includes the conformal assertion_library
directive on line 5 (in bold). However, we disabled it with the SET DIRECTIVE OFF
command. (Shown below the test case.)
module test (a, b, q);
input [3:0] a, b;
output [3:0] q;
reg [3:0] q;
// conformal assertion_library
always @ (a or b ) begin
q = a & b;
end
endmodule
Input:
SETUP>set directive off assertion_library
SETUP>read design test.v -verilog
DIR4.4
Message
HDL directive/pragma is ignored
Default Severity
Warning
Description
The specied HDL directive or pragma is not supported and will be ignored.
Example
In the following example, if the dole contains the following line:
set directive off translate_on translate_off unknown_pragma
The unknown_pragma is not a supported directive or pragma and will be ignored.
DIR5.1
Message
Conformal multi_port directive is detected
Default Severity
Warning
Description
The checker generates this message when the design includes the Conformal multi_port
directive. This directive species that the checker will model the specied register with
multiple clock ports, multiple data ports, and a single output port.
Note:
If you do not include the multi_port directive, by default, the checker creates
multiple registers with outputs wired together.
Example
In the following example, the design includes the conformal multi_port directive in line
5 (in bold).
module test ( clk1, clk2, in0, out0 );
input clk1, clk2, in0;
output out0;
reg out0;
// conformal multi_port out0
always @( posedge clk1 )
out0 <= 1'b0;
always @( posedge clk2 )
out0 <= in0;
endmodule
DIR5.2
Message
Conformal multi_port directive is detected
Default Severity
Warning
Description
The checker generates this message when the design includes the Conformal clock_hold
directive. This directive species that the checker will model the selected registers as
gated-clock registers.
Example
In the following example, the design includes the conformal clock_hold directive on line
5 (in bold).
module test ( clk, din, adr, out0 );
input clk, din, adr;
output out0;
reg [0:0] mem [1:0];
// conformal clock_hold mem
begin
mem[adr] <= din;
end
assign out0 = mem[adr];
endmodule
DIR5.3
Message
Conformal mem_rowselect directive is detected
Default Severity
Warning
Description
The checker generates this message when the design includes the Conformal
mem_rowselect directive. This directive species that the checker will model the following
type of RTL into a structure that lets you dene the signals that are synthesized as part of the
decoded word line of the ram_array, while all other signals on the sensitivity list are
synthesized into the logic cone of the input bit line.
always @(clk or we or din or addr)
begin
if (clk && we) ram_array(addr) = din;
end
Example
In the following example, the design includes the conformal mem_rowselect directive on
line 7 (in bold).
module test(clk, en, addr, din, dout);
input clk, en;
input [1:0] addr;
input [0:0] din;
output [0:0] dout;
reg [0:0] ram [3:0];
// conformal mem_rowselect ram clk en addr[1]
always @(clk or en or addr or din) begin
if (clk && en) ram[addr[1:0]] = din;
end
assign dout = ram[addr[1:0]];
endmodule
DIR5.4
Message
Conformal conformal cutpoint directive is supported
Default Severity
Warning
Description
The variable dened by the pragma is the cut point in the design.
Example
In the following example, ram is dened as the cutpoint.
module test(clk, en, addr, din, dout);
input clk, en;
input [1:0] addr;
input [0:0] din;
output [0:0] dout;
reg [0:0] ram [3:0];
// pragma cutpoint "ram
always @(clk or en or addr or din) begin
if (clk && en & ram[0] ) ram[addr[1:0]] = din;
end
endmodule
DIR6.1
Message
Ignored compiler directive is detected
Default Severity
Warning
Description
The checker detected the use of an ignored compiler directive. Below is a full list of ignored
compiler directives:
1.
accelerate
2.
autoexpand_vectornets
3.
default_decay_time
4.
default_strength
5.
delay_mode
6.
delay_mode_distributed
7.
delay_mode_unit
8.
delay_mode_zero
9.
end_pre_16a_paths
10.
expand_vectornets
11.
line
12.
noaccelerate
13.
noexpand_vectornets
14.
noremove_gatenames
15.
nounconnected_drive
16.
pre_16a_paths
17.
remove_gatenames
18.
remove_names
19.
switch
20.
timescale
21.
unconnected_drive
22.
unprotected
23.
uselib
Example
In the following example, the Verilog RTL accepts compiler directives celldefine and
endcelldefine on lines 1 and 8. All modules declared after celldene and before
endcelldene are marked as ASIC library cells. Currently only Conformal Constraint
Designer uses this marking for nding timing paths.
celldefine
module cell1 (a, b);
input a;
output b;
buf (b, a);
endmodule
endcelldefine
DIR6.2
Message
Supported compiler directive is detected
Default Severity
Warning
Description
The checker detected a supported compiler directive. Belowis a full list of supported compiler
directives:
1.
celldefine and endcelldefine
2.
define
3.
ifdef, ifndef, elsif, endif
4.
undef
5.
include <filename>
6.
protect and endprotect
7.
protected and endprotected
8.
default_nettype net_type
9.
resetall
Example
In the following example, the checker supports compiler directive default_nettype wire
on line 1 (in bold).
default_nettype wire
module test (din, dout);
input din;
output dout;
assign dout = din;
endmodule
DIR7.1
Message
Unsupported synthesis attribute is detected
Default Severity
Warning
Description
The checker detected a synthesis attribute that it does not support.
Example
In the following example, the checker ignores the attribute MAX_DELAY, rendering it ineffective
(see lines 9 and 10).
entity TEST is
port(
IN1 : in integer;
OUT1 : out bit
);
end test;
architecture RTL of TEST is
attribute MAX_DELAY : string;
attribute MAX_DELAY of TEST: entity is 1431;
begin
OUT1 <= 1 when IN1 > 329 else 0;
end RTL;
DIR7.2
Message
Supported synthesis attribute is detected
Default Severity
Warning
Description
The design includes a synthesis attribute that the checker supports.
Example
The following example denes the attribute ENUM_ENCODING to specify the encoding of the
enumeration type (see lines 10 and 11).
entity TEST is
port(
SEL : in bit_vector(2 downto 0);
OUT1 : out bit
);
end test;
architecture RTL of TEST is
type ET is (ET1, ET2, ET3);
attribute ENUM_ENCODING : string;
attribute ENUM_ENCODING of ET : type is 00 01 11";
signal SIG1 : ET;
begin
process (SEL)
begin
if (SEL = "000") then
SIG1 <= ET1;
elsif (SEL = "111") then
SIG1 <= ET2;
else
SIG1 <= ET3;
end if;
end process;
OUT1 <= 1 when (SIG1 = ET3) else 0;
end RTL;
DIR8.1
Message
protected/endprotected pragma is used
Default Severity
Warning
Description
The content after the pragma is protected.
Example
In the following example, line 3 is protected because it is between the protected and
endprotected directives:
Pragma `protected/èndprotected used
primitive FOO_P `protected
SOME98098jlkajdGOO
èndprotected endprimitive
DIR9.1
Message
Verilog celldefine is for timing simulation. Use the LIBERTY library instead
Default Severity
Ignore
Description
A Verilog module enclosed between celldefine and endcelldefine is recognized as
a technology library cell. Conformal Constraint Designer prefers using technology cells in the
LIBERTY format, and reports a rule check violation. The default severity for this rule check is
ERROR. You can override the severity with the SET RULE HANDLING command.
Example
If the following module is read using READ DESIGN or READ LIBRARY command, the
Conformal software reports this rule check error by default.
celldefine
module TECH_CELL_BUF (Y, A);
output Y;
input A;
buf I0(Y, A);
specify
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0;
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule // TECH_CELL_BUF
endcelldefine
DIR9.2
Message
Illegal to redefine a Verilog compiler directive as a macro
Default Severity
Warning
Description
You have attempted to redene a Verilog compiler directives that is one of the following:
celldefine
default_nettype
define
else
endcelldefine
endif
ifdef
ifndef
include
nounconnected_drive
resetall
timescale
unconnected_drive
undef
Example
The following define statement (see line 1) causes a DIR9.2 rule violation:
define timescale 1b0
module test (in,out);
input in;
output out;
assign out = in;
endmodule
DIR9.3
Message
Verilog compiler directive is redefined as a macro
Default Severity
Warning
Description
You have attempted to redene other Verilog compiler directives that are not as follows:
celldefine
default_nettype
define
else
endcelldefine
endif
ifdef
ifndef
include
nounconnected_drive
resetall
timescale
unconnected_drive
undef
Example
The following define statement (see line 1) causes a DIR9.3 rule violation:
define switch 1b1
module test (in,out);
input in;
output out;
assign out = in;
endmodule
The above statement causes the switch directive to be deleted and replaced by a user-
dened macro.
File
This category of rules applies to designs that include le issues. The following table lists the
File issue (FIL) rule numbers and their messages.
Rule Number Message
FIL1.1 Input le recursion detected
FIL1.1
Message
Input file recursion detected
Default Severity
Error
Description
This detects that input les are included recursively.
Example
The two les in the following example are recursively included:
In file file1.v, has include "file2.v".
In file file2.v, has include "file1.v".
Hierarchy
This category of rules applies to designs that are comprised of hierarchical modules. The
following table lists the Hierarchy (HRC) rule check numbers and messages.
Rule Number Message
HRC1.1 Module/entity is not loaded due to unsupported construct (blackboxed)
HRC1.2 Module/entity is not translated (blackboxed)
HRC1.3 Module/entity is undened and created (blackboxed)
HRC1.4 Module/entity is empty (blackboxed)
HRC1.5 Module/entity is referenced recursively (blackboxed)
HRC2.1 Module/entity instantiated from un-imported library
HRC2.2 Module/entity exists in library and design
HRC2.3 Module/entity is renamed
HRC2.4 Ambiguous component is instantiated
HRC2.6 Multiple component is declared
HRC3.1 Module instance has different number of arguments
HRC3.2 Component is instantiated without specifying any port connection
HRC3.2a Module/entity has no I/O ports
HRC3.3 Undened named port connection
HRC3.4 Duplicate port connection is detected
HRC3.4a Actual net is connected to more than one port
HRC3.5a Open input/inout port connection is detected
HRC3.5b Open output port connection is detected
HRC3.5c Expression to null port connection is detected
HRC3.6 Port connection width mis-matches. Undriven signals are oating
HRC3.7 Boundary port direction might not be correct
HRC3.8 Port positional association occurred in instantiation
HRC3.9 Constraint contains oating net
HRC3.10 Input port connects to instance output pin. This might cause multiple
drivers to the net
HRC3.11 Too many actuals connect to formals
HRC3.12 Port declaration error
HRC3.13 Usage of const ref port is treated as input port
HRC4 Multiple root modules/entities are found
HRC5 DesignWare is referenced but not dened
HRC6.1 Mapping empty edif cell to parameterized module is not supported
HRC7 Modules specied by the add notranslate modules command cannot
be found
Rule Number Message
HRC1.1
Message
Module/entity is not loaded due to unsupported construct (blackboxed)
Default Severity
Warning
Description
The design includes one or more modules or entities that contain unsupported constructs.
The checker will blackbox all modules and entities that contain unsupported constructs.
Example
In the following example, real value 50.2 is an unsupported construct (see lines 7 and 8)(in
bold).
module test (clk,in1,out0);
input clk,in1;
output out0;
reg out0;
real r1;
always @ ( posedge clk )
begin if (r1 > 50.2) begin
out0 <= in1;
end
end
endmodule
HRC1.2
Message
Module/entity is not translated (blackboxed)
Default Severity
Note
Description
The design includes one or more modules or entities that were blackboxed with the
command:
add notranslate module <module_name>
Example
Input:
SETUP> add notranslate module SUB
SETUP> read design SUB.v -verilog
// Note: (HRC1.2) Module/entity not translated (black boxed) (occurrence:1)
HRC1.3
Message
Module/entity is undefined and created (blackboxed)
Default Severity
Note
Description
Indicates that blackboxing was specied for design modules that are referenced but not
dened. This message can be generated by the following commands:
I
SET UNDEFINED CELL <blackbox>
I
The ADD NOTRANSLATE MODULES command causes undened modules to be blackboxed.
Example
In the following example, the design references module SUB on line 9, but it is not dened.
module TEST (in0,in1,in2,out0);
input in0,in1,in2;
output out0;
reg out0;
always @ ( in0 or in1 )
begin
out0 = in0 | in1;
end
SUB inst1 (.in2(in2));
endmodule
HRC1.4
Message
Module/entity is empty (blackboxed)
Default Severity
Warning
Description
The design includes one or more empty modules or entities. The checker blackboxes all
empty modules.
Example
In the following example, the checker blackboxes the empty SUB module.
module SUB (in2, out3);
input in2;
output out3;
endmodule
HRC1.5
Message
Module/entity is referenced recursively (blackboxed)
Default Severity
Warning
Description
The design includes one or more modules that are referenced recursively. The checker
blackboxes all recursively referenced modules.
Example
In the following example, module abc is referenced recursively and will be blackboxed (see
line 4).
module abc (a,b);
input a;
output b;
abc gen1_x1 (a,b);
endmodule
HRC2.1
Message
Module/entity instantiated from un-imported library
Default Severity
Warning
Description
The design includes one or more components that are instantiated, but the checker did not
nd an imported library containing the components.
Example
In the following example, component SUB is instantiated but the checker did not nd an
imported library (see line 8)(in bold).
BEGIN
proc2 : PROCESS (in0, in1, sig2)
BEGIN
out0 <= in0 or in1 or sig2;
END PROCESS;
sig1 <= in2;
inst1 : SUB PORT MAP (in0=>sig1, out0=>sig2);
END arch;
HRC2.2
Message
Module/entity exists in library and design
Default Severity
Warning
Description
One or more modules or entities exist in both design and library spaces. The checker selects
modules and entities from the design space.
Example
In the following example, we read in module test for both the library and design spaces.
Input:
SETUP> read library test.v
SETUP> read design test.v
HRC2.3
Message
Module/entity is renamed
Default Severity
Warning
Description
The library space includes one or more modules or entities with the same name. The checker
will rename these library modules or entities.
Example
In the following example, the design includes the entity name e1 in two libraries (lib1 and
lib2). Therefore, the checker renames the el entities as follows:
I
From library lib1:
ENTITY e1 IS
PORT (min1: IN bit;
mout1: OUT bit);
END;
ARCHITECTURE rtl OF e1 IS
BEGIN
mout1 <= not min1;
END;
Library 1: el is renamed lib1_e1
I
From library lib2:
ENTITY e1 IS
PORT (min1: IN bit;
mout1: OUT bit);
END;
ARCHITECTURE rtl OF e1 IS
BEGIN
mout1 <= not min1;
END;
Library 2: el is renamed lib2_e2
HRC2.4
Message
Ambiguous component is instantiated
Default Severity
Warning
Description
A library component is instantiated, but more than one library contains the component.
Example
In the following example, component e1 is instantiated, but both library liba and libb
contain the e1 component (see line 15)(in bold).
LIBRARY liba;
LIBRARY libb;
USE liba.pkg.ALL;
USE libb.pkg.ALL;
ENTITY top IS
PORT (in1: IN bit;
out1: OUT bit);
END;
ARCHITECTURE rtl OF top IS
COMPONENT e1
PORT(min1: IN bit; mout1: OUT bit);
END COMPONENT;
BEGIN
inst1: e1 PORT MAP (min1=>in1, mout1=>out1);
END;
HRC2.6
Message
Multiple component is declared
Default Severity
Warning
Description
A component is declared in more than one library.
Example
In the following example, In line 13, component c1 is declared in both lib1, package pp1
and lib2, package pp2:
library lib1, lib2;
use lib1.pp1.all;
use lib2.pp2.all;
ENTITY top IS
PORT (
ccc : IN bit;
bbb : IN bit;
ooo : OUT bit
);
END top;
ARCHITECTURE rtl OF top IS
BEGIN
u0: c1 port map (ccc=>ccc, bbb=>bbb, ooo=>ooo);
END rtl;
HRC3.1
Message
Module instance has different number of arguments
Default Severity
Warning
Description
The design includes one or more module instances with arguments that differ from the
module denition.
Example
In the following examples, instance inst1 has 3 connections, but module sub has only 2
ports:
module sub (in2,out3);
input in2;
output out3;
assign out3 = in2;
endmodule
module test (in2,out0);
input in2;
output out0;
sub inst1 (in2,in2,out0);
endmodule
HRC3.2
Message
Component is instantiated without specifying any port connection
Default Severity
Warning
Description
The design includes one or more components that are instantiated but do not have a port
connection.
Example
In the following example, module SUB is instantiated, but has no connected ports (see line
4)(in bold).
module TEST (in2,out0);
input in2;
output out0;
SUB inst1 ();
endmodule
HRC3.2a
Message
Module/entity has no I/O ports
Default Severity
Warning
Description
The module has no I/O ports.
Example
In the following example, module ABC does not have any I/O ports.
module ABC;
endmodule
HRC3.3
Message
Undefined named port connection
Default Severity
Error
Description
The design includes one or more module instances that refer to undened ports.
Example
In the following example, module sub references port in4, but does not dene it (see line
4)(in bold).
module test(a, b, c, d, e);
input a, b, c, d;
output e;
sub inst0 (.in1(a),.in2(b),.in3(c),.in4(d), .out1(e));
endmodule
module sub (in1, in2, in3, out1);
input in1, in2, in3;
output out1;
wire out1;
assign out1 = in1 ^ in2;
endmodule
HRC3.4
Message
Duplicate port connection is detected
Default Severity
Warning
Description
The design includes duplicate ports that the checker has ignored.
Example
In the following example, the checker will ignore the duplicate port .c included on line 4.
input [3:0] a, b;
output [3:0] q;
sub sub1 (.c(a), .c(b), .q1(q));
endmodule
module sub (c, d, q1);
input [3:0] c, d;
output [3:0] q1;
assign q1 = c | d;
endmodule
HRC3.4a
Message
Actual net is connected to more than one port
Default Severity
Warning
Description
Actual net is connected to more than one port in module declaration.
Example
In the following example, din is connected to both .in1 port and .in2 port (see line 1).
module sub(.in1(din), .in2(din), .out(dout));
input din;
output dout;
assign dout = din;
endmodule
module top(din, dout);
input din;
output dout;
sub sub1(.in1(din), .in2(din),.out(dout));
endmodule
HRC3.5a
Message
Open input/inout port connection is detected
Default Severity
Warning
Description
The design includes one or more input or inout ports with open connections.
Example
In the following example, the connection for port .d is open (see line 4).
input [3:0] a, b;
output [3:0] q;
sub sub1 (.c(a), .d(), .q1(q));
endmodule
input [3:0] c, d;
output [3:0] q1;
assign q1 = c | d;
endmodule
HRC3.5b
Message
Open output port connection is detected
Default Severity
Note
Description
The design includes one or more output ports with open connections.
Example
In the following example, the connection for port .q1 is open (see line 4).
input [3:0] a, b;
output [3:0] q;
sub sub1 (.c(a), .d(b), .q1());
endmodule
input [3:0] c, d;
output [3:0] q1;
assign q1 = c | d;
endmodule
HRC3.5c
Message
Expression to null port connection is detected
Default Severity
Warning
Description
The design includes one or more null ports with open connections.
Example
In the following example, the connection between module port c and d is open (see line 4).
input [3:0] a, b;
output [3:0] q;
sub sub1 (a, x, b, q);
endmodule
module sub (c,, d, q1);
input [3:0] c, d;
output [3:0] q1;
assign q1 = c | d;
endmodule
HRC3.6
Message
Port connection width mis-matches. Undriven signals are floating
Default Severity
Warning
Description
The design includes at least one port that has port connection width mis-matches.
Example
In the following example, port_name out1, which is two-bit, is greater in size than
port_expr e, which is one-bit. See line 4 (in bold).
module test(a, b, e);
input a, b;
output e;
sub inst0 (.in1(a),.in2(b),.out1(e));
endmodule
module sub (in1, in2, out1);
input in1, in2 ;
output [1:0] out1;
wire [1:0] out1;
assign out1 = {in1,in2};
endmodule
HRC3.7
Message
Boundary port direction might not be correct
Default Severity
Warning
Description
The design includes one or more module boundary ports that might be declared incorrectly
because of their irregular use.
Example
In the following example, both input in1 and input in2, drive output out0. Thus, the checker
interprets this situation to mean that input in2 is incorrectly declared (see lines 4 and 5).
module test(in1, in2, out0);
input in1, in2;
output out0;
not U1 (out0, in1);
assign out0=in2;
endmodule
Note: For multi-driven nets, the checker applies wire-AND resolution by default.
HRC3.8
Message
Port positional association occurred in instantiation
Default Severity
Warning
Description
The design includes one or more module instances that use port positional association. In a
positional association, the port_exprs connect to the ports of the module in the specied
order.
Port positional association syntax:
module_name instance_name( port_expr1,
port_expr2, );
Example
In the following example, port_expr a connects to port o0 and port_expr b connects to port
o1 of module sub. See line 9 (in bold).
module sub (o0, o1);
output o0, o1;
assign o0 = 1'b0;
assign o1 = 1'b1;
endmodule
module test(a, b);
output a, b;
sub s1(a, b);
endmodule
HRC3.9
Message
Constraint contains floating net
Default Severity
Warning
Description
The constraint has oating nets.
Example
In the following example, val is a oating net (see line 8):
module test(in, out);
input in;
output out;
wire val;
assign out = in;
endmodule
append_to module test;
$constraint( val == 1'b1);
endmodule
HRC3.10
Message
Input port connects to instance output pin. This might cause multiple drivers to
the net
Default Severity
Warning
Description
There is an input port connected to an instance output pin. This could cause multiple drivers
to the net.
Example
In the following example, the input pin b is connected to the instance sub output pin o1. In
module ABC it is an input pin, and in sub s1 is is an output pin.
module sub (o0, o1);
output o0, o1;
assign o0 = 1'b0;
assign o1 = 1'b1;
endmodule
module ABC(a, b);
output a;
input b;
sub s1(a, b);
endmodule
HRC3.11
Message
Too many actuals connect to formals
Default Severity
Error
Description
The number of actuals in the port map is more than the number of formals.
Example
In the following example, there are three actuals but only two formals (see line 20):
entity sub is
port (
o0, o1 : out bit
);
end sub;
architecture arch of sub is
begin
o0 <= '0';
o1 <= '1';
end arch;
entity test is
port (
a : out bit;
b : out bit;
c : in bit
);
end test;
architecture arch of test is
begin
u1 : sub port map (o0 => a, o1=> b, o1 =>c);
end arch;
HRC3.12
Message
Port declaration error
Default Severity
Error
Description
The external port name specied by .name should not conict with other internal port names,
or other external port names.
Example
In the following example, you cannot redeclare a1 input a1:
module hrc3_12 (.a1(a1));
endmodule;
HRC3.13
Message
Usage of const ref port is treated as input port
Default Severity
Warning
Description
The const ref port is treated as input port. You will get this message when running the READ
DESIGN -systemverilog command to read in the design and there is a violation on this
rule.
Example
In the following example, in line 5, port din of function func is declared as const ref, it will be
treated as input port.
input in;
output reg out;
function func;
const ref din;
begin
func = din;
end
endfunction
always @(in)
out = func(in);
endmodule
HRC4
Message
Multiple root modules/entities are found
Default Severity
Warning
Description
The design includes multiple modules or entities at the top level of hierarchy; thus, any one
of them can be designated as the root module. By default, the checker selects the module
with the greatest gate count.
Example
In the following example, the le test.v contains two possible root modules, TEST0 and
TEST1.
test.v file:
module TEST0 (in0,in1,in2,out0);
input in0,in1,in2;
output out0;
assign out0 = in0 | in1;
endmodule
module TEST1 (in0,in1,in2,out0);
input in0,in1,in2;
output out0;
assign out0 = in0 & in1;
endmodule
HRC5
Message
DesignWare is referenced but not defined
Default Severity
Warning
Description
The design includes one or more DesignWare multiplier/divider instances, but does not dene
them. The checker supplies the missing denition, using a Conformal multiplier denition.
Example
In the following example, DesignWare multiplier DW02_mult is instantiated (see line 9), but
the design does not dene it. The checker will supply the missing DW02_mult denition with
a Conformal multiplier denition.
module test(A,B,TC,PRODUCT);
parameter A_width = 8;
parameter B_width = 8;
input [A_width-1:0] A;
input [B_width-1:0] B;
input TC;
output [A_width+B_width-1:0] PRODUCT;
DW02_mult mult_1 (A,B,TC,PRODUCT);
endmodule
HRC6.1
Message
Mapping empty edif cell to parameterized module is not supported
Default Severity
Warning
Description
The EDIF design includes an empty cell that is an instance of a parameterizable Verilog
module, which is not supported.
Example
In the following example, top.edf is an EDIF le that contains a cell called CTLBLK, which
is dened in a Verilog module.
CTLBLK module:
module CTLBLK( A, SUM );
parameter INIT = 16'h0000;
endmodule
Input:
> read design top.edf -golden -edif
// Warning: (HRC6.1) Mapping empty edif cell to parameterized module is not
supported (occurrence:1)
HRC7
Message
Modules specified by the add notranslate modules command cannot be found
Default Severity
Warning
Description
A module cannot be found in the design that was specied with the ADD NOTRANSLATE
MODULES command.
Example
In the following example mod1 is the name of module that does not exist in the design.
Input:
> add notranslate modules mod1
// Warning: (HRC7) Modules specified by the add notranslate modules command
cannot be found (occurrence:2)
Ignored
This category of rules applies to designs that include constructs or statements that are either
redundant or unsupported, and thus ignored by the checker. The following table lists the
Ignored (IGN) rule numbers and messages. The severity level for all IGN rule check
messages is warning.
Rule Number Message
IGN1.1 initial assignment is ignored
IGN1.2 nal construct is ignored
IGN2.1 Delay value(s) are ignored
IGN2.2 Illegal defparam statement(s) are ignored
IGN2.3 Unsupported defparam statement is ignored
IGN3.1 Duplicated pin/port names are detected and ignored
IGN3.2 Duplicate modules/entities are detected. Subsequent modules/
entities are ignored
IGN3.3 Multiple declarations of same packages are detected. Earlier
declarations are ignored
IGN3.4 Duplicate modules/entities are detected. Previous modules/
entities are ignored
IGN3.5 Duplicate modules/entities are detected. Local module/entity is
used
IGN3.6 Blackbox is replaced with the current module/entity
IGN4 Attribute instance(s) are ignored
IGN5.1 Liberty state table is ignored with the -nostatetable option
IGN5.2 Liberty attribute is ignored
IGN5.3 Liberty state table contains lowercase value(s) and is ignored
IGN6.1 timeunit statement is ignored
IGN6.2 timeprecision statement is ignored
IGN7.1 trireg net is treated as regular wire net
IGN1.1
Message
initial assignment is ignored
Default Severity
Warning
Description
The initial statement is a SystemVerilog construct for simulation that the checker does
not support. Thus, when the checker detects this construct in the syntax, it ignores the entire
initial construct. Similarly, the checker reports rule IGN1.2 for the final statement.
Example
In the following example, the checker ignores the keyword initial. See line 5 (in bold).
input clk, din;
output dout;
wire dout;
initial dout = !din;
assign dout = din;
endmodule
IGN1.2
Message
final construct is ignored
Default Severity
Warning
Description
The final statement is a SystemVerilog construct for simulation that the checker does not
support. Thus, when the checker detects this statement in the syntax, it ignores the entire
final statement. Similarly, the checker reports rule IGN1.1 for the initial statement.
Example
In the following example, the checker ignores the entire final statement. See lines 7, 8, and
9 (in bold).
module test(aa, bb, o1, o2);
input aa, bb;
output o1, o2;
assign o1 = aa == bb;
assign o2 = aa != bb;
final begin
$display(done);
end
endmodule
IGN2.1
Message
Delay value(s) are ignored
Default Severity
Warning
Description
The checker has ignored one or more delay values.
Example
In the following example, the checker ignores delay value #(10). See line 5 (in bold).
input clk, din;
output dout;
wire dout;
not #(10) (dout, din);
endmodule
IGN2.2
Message
Illegal defparam statement(s) are ignored
Default Severity
Warning
Description
The design uses one or more defparam keywords illegally. The checker ignores illegally
used defparam keywords.
Example
In the following example, P8P is undened. The checker will ignore the statement. See line 4
(in bold).
input clk, din;
output dout;
defparam P8P.INI=8'h88;
assign dout = din;
endmodule
IGN2.3
Message
Unsupported defparam statement is ignored
Default Severity
Warning
Description
The defparam directive is unsupported and ignored.
Example
In the following example, defparam is ignored (see line 16):
module sub1(aa, oo);
parameter NN = 1'b0;
input aa;
output oo;
assign oo = aa & NN;
endmodule
input aa;
output oo;
sub1 u0 [2:0] (aa, oo);
endmodule
input aa;
output oo;
sub2 u0(aa, oo);
defparam u0.u0[0].NN = 1'b1;
endmodule
IGN3.1
Message
Duplicated pin/port names are detected and ignored
Default Severity
Warning
Description
The design includes duplicate pins or ports.
Example
In the following example, the checker ignores the duplicated port dout (see the rst line)
module test ( dout, clk, din, dout );
input clk, din;
output dout;
reg dout;
dout <= din;
endmodule
IGN3.2
Message
Duplicate modules/entities are detected. Subsequent modules/entities are ignored
Default Severity
Warning
Description
The design includes duplicate modules or entities. The checker ignores duplications.
Example
In the following example, the design duplicates module test. The checker ignores the
second module test.
Note:
Ellipses ( ) denote characters that are present in the le, but not shown in this
example.
endmodule
endmodule
IGN3.3
Message
Multiple declarations of same packages are detected. Earlier declarations are
ignored
Default Severity
Warning
Description
There are multiple declarations of the same package. The checker ignores earlier
declarations.
Note:
example.
Example
In the following example, the rst declaration for pkg is ignored.
package pkg is
CONSTANT val1 : bit := 1;
end pkg;
package pkg is
CONSTANT val1 : bit := 0;
end pkg;
IGN3.4
Message
Duplicate modules/entities are detected. Previous modules/entities are ignored
Default Severity
Warning
Description
There are multiple denitions for a module or entity. The checker takes the last denition and
ignores previous ones. This usually occurs when you use the -lastmod option with the READ
DESIGN command.
Example
In the following example, the checker ignores the rst denition for test when you use the
read design -lastmod test.v -replace command.
input clk, din;
output dout;
reg dout;
dout <- din;
endmodule
module test (clk, din, dout );
input clk, din;
output dout;
reg dout;
dout <= din;
endmodule
IGN3.5
Message
Duplicate modules/entities are detected. Local module/entity is used
Default Severity
Warning
Description
Duplicate modules are found and the Conformal software uses the local module. If you want
to use the local module, you must use the read design -localref command.
Example
In the following example, you can use read design -localref to use local module sub1
(see lines 9 for each of the following les). For each le, the instantiation of sub1 in lines 9
will use the sub1 dened in lines 1 (module sub1(aa, oo)).
File mod1.v
input aa;
output oo;
assign oo = aa;
endmodule
module mod1(aa, oo);
input aa;
output oo;
sub1 u0 (aa, oo);
endmodule
File mod2.v
input aa;
output oo;
assign oo = !aa;
endmodule
module mod2(aa, oo);
input aa;
output oo;
sub1 u0 (aa, oo);
endmodule
IGN3.6
Message
Blackbox is replaced with the current module/entity
Default Severity
Warning
Description
The blackbox module is replaced by a non-blackbox module.
Example
In the following example, same module, but the rst one is a blackbox, so this will replace the
module sub1 in mod2.v will replace the modue sub1 in mod1.v. Use read design
-bboxsolver to replace sub1 with a non-blackbox model
File mod1.v:
input aa;
output oo;
// this is a bbox
endmodule
File mod2.v:
input aa;
output oo;
assign oo = !aa;
endmodule
IGN4
Message
Attribute instance(s) are ignored
Default Severity
Warning
Description
The checker has ignored one or more attribute instances.
Example
In the following example, the checker ignores the attribute instance (* a = b *). See line 4.
module test(a, b);
input a;
output b;
(* a = b *) assign b = a;
endmodule
IGN5.1
Message
Liberty state table is ignored with the -nostatetable option
Default Severity
Note
Description
A Liberty le contains a state table and is ignored due to the -nostatetable option
specied in the READ DESIGN or READ LIBRARY command. The checker does not support
state tables.
Example
In the following example, while reading the Liberty library lsi_10k.lib, the checker
encountered 17 occurrences of the unsupported state table. Refer to the state table example
below.
Input:
SETUP>read lib -lib lsi_10k.lib
// Parsing file lsi_10k.lib
// Warning: (IGN5.1) Liberty State Table is not supported and is ignored
(occurrence:17)
State Table Example:
statetable ( " D CP ", " Q QN") {
table : " - ~R : - - : N N, \
H/L R : - - : H/L L/H";
}
IGN5.2
Message
Liberty attribute is ignored
Default Severity
Ignore
Description
The Liberty attribute is ignored.
Example
Some unsupported attributes are:
poly_template
hyperbolic_noise_above_high
hyperbolic_noise_low
hyperbolic_noise_high
steady_state_current_high
steady_state_current_low
steady_state_current_tristate
IGN5.3
Message
Liberty state table contains lowercase value(s) and is ignored
Default Severity
Warning
Description
The parser found lowercase value(s) in the truth table of the statetable. These must be
changed to uppercase.
Example
In the following example, lines 2 and 3 shows that the edge value(s) ~r and r are written
in lowercase, which should be changed to uppercase:
statetable( " D CP" , " Q QN" ) {
table : " - ~r : - - : N N,\
H/L r : - - : H/L L/H" ;
}
IGN6.1
Message
timeunit statement is ignored
Default Severity
Warning
Description
The timeunit statement is a SystemVerilog construct for simulation that the checker does
not support. When the checker detects this statement in the syntax, it ignores the entire
timeunit statement. Similarly, the checker reports rule IGN6.2 for the timeprecision
statement.
Example
In the following example, the checker ignores the timeunit statement on line 2:
timeunit 1ps;
input aa, bb;
output o1, o2;
endmodule
IGN6.2
Message
timeprecision statement is ignored
Default Severity
Warning
Description
The timeprecision statement is a SystemVerilog construct for simulation that the checker
does not support. When the checker detects this statement in the syntax, it ignores the entire
timeprecision statement. Similarly, the checker reports rule IGN5.3 for the timeunit
statement.
Example
In the following example, the checker ignores the timeprecision statement on line 2:
timeprecision 0.1ps;
input aa, bb;
output o1, o2;
endmodule
IGN7.1
Message
trireg net is treated as regular wire net
Default Severity
Warning
Description
A trireg net can model a charge storage node whose charge decays over time. The
Conformal software does not support charge storage and charge decays. As a result, the
software treats a trireg net as regular wire net.
Example
In the following example, the checker ignores the trireg statement on line 3 (in bold).
module test (clk, in1, out1);
input clk;
input trireg in1;
output reg out1;
always @(clk)
out1 = in1;
endmodule
Register Transfer Level
This category of rules applies to designs that are written in the register transfer level of
abstraction. The following table lists the Register Transfer Level (RTL) rule numbers and
messages.
Rule Number Message
RTL1.1 Variable/signal is assigned by more than one concurrent statement
RTL1.2 Variable/signal is assigned by multiple non-blocking assignments
RTL1.2a Variable/signal on instance INOUT port might have multiple drivers
RTL1.3 Variable/signal is assigned by both blocking and non-blocking
assignments
RTL1.4 Assignment with LHS bit width is greater than RHS bit width
RTL1.5a Assignment with RHS bit width is greater than LHS bit width
RTL1.5b Potential loss of RHS msb or carry-out bit
RTL1.6 Blocking assignment is in sequential always block
RTL1.7 Non-blocking assignment is in combinational always block
RTL1.8 Latch is assigned by blocking assignments
RTL1.9 Parameter bit width does not match RHS bit width
RTL1.11 Variable is assigned by both continuous and procedural statements
RTL1.12 variable(SV:logic/bit) is assigned by multiple continuous statements
RTL1.13 Mismatched enumeration types are in the assignment
RTL1.14 Mismatched enumeration types are in the expression
RTL2.1 Variable is referenced before the assignment
RTL2.1a Variable is referenced before assignment in subprogram. Possible
simulation mismatch
RTL2.2 Variable is referenced but never assigned
RTL2.3 Externally dened signal reference is not supported
RTL2.4 Externally dened signal reference is supported
RTL2.5 Undriven net is detected
RTL2.6 Shared variables are not supported
RTL2.7 Dynamic slice is not supported
RTL2.8 BUS and REGISTER signal type are not supported for synthesis
RTL2.9 Guarded assignment requires GUARD signal
RTL2.10 GUARD is not declared
RTL2.11 Implicitly declared GUARD signal cannot be updated
RTL2.12 Illegal redeclaration of GUARD signal
RTL2.13 Undriven pin is detected
RTL3.1 Variable/signal is unassigned in asynchronous set/reset
RTL3.2 Assignment of X is in asynchronous set/reset branch
RTL3.3 Non-constant value assignment is in asynchronous set/reset value
RTL3.4 DFF/DLAT is with both asynchronous set and reset connections
RTL3.5 Variable/signal is assigned without using asynchronous set/reset
RTL4.1 Enum encoding is applied to enum type
RTL4.2 Multiple wait statements. FSM encoding might be different
RTL4.3 Enum value size is different than the declared data type
RTL4.4 Encoding format has too many values
RTL5.1 Overlapped case items are in parallel case statement
RTL5.2 Non-binary case items are in case statement
RTL5.3 Case expressions/items are resized
RTL5.4 Partial case items are in full case statement
RTL6.1 X created due to the assignment of value X
RTL6.2 Integer value range constraint is added
RTL6.3 X created when divisor equals to zero
RTL6.4 Enum value constraint is added
RTL6.5 priority if and unique if statements are incomplete
RTL6.6 unique if statements have redundant or overlapping conditions
RTL7.1 Design includes comparison that uses X or Z values
Rule Number Message
RTL7.2 Gate or transistor primitive is using weak attributes
RTL7.3 Array index in RHS might be out of range
RTL7.4 Array index in LHS might be out of range
RTL7.5 Input signal is assigned by logic values
RTL7.6 Value X or Z is treated as 0 in unary/binary expressions
RTL7.7 Real number rounded to integer value
RTL7.8 Overowed integer is truncated
RTL7.9 Sign overowed integer is truncated
RTL7.10 Comparison with signed and unsigned operands
RTL7.11 Implicit signed expression is converted to unsigned
RTL7.12 Unsized integer number is truncated to 32 bits
RTL7.13 Logical operator is applied to multiple-bit operand
RTL7.14 Loop exceeds maximum iterations
RTL7.15 Null slice is not supported
RTL7.16 Variable index is out of the dened range
RTL7.17 Exponentiation operator is unsupported
RTL7.18 Argument size to integer type conversion is too large
RTL7.19 Added constraint on integer overow for arithmetic operation ADD/SUB
RTL7.20 Size value in size(expr) casting is too large
RTL7.21 Real variables are not supported
RTL8.1 Multiple multipliers/dividers are in module/entity
RTL8.2 Latch(es) are inferred due to an incomplete conditional statement
RTL8.3 Unreachable DFF/DLAT is removed
RTL8.4 Unreachable DFF/DLAT is kept
RTL8.5 Implicit signed multiplier is detected in module/entity
RTL9.1 Instance inout/output port has dynamic indexing. Treated as oating
RTL9.2 Design has irregularly used inout/output expression
Rule Number Message
RTL9.3 Supply0/supply1 is converted into a wire
RTL9.4 Supply0/supply1 net is not a module port
RTL9.5 Power pin is converted to an input pin
RTL9.7 Cannot read value from OUT port
RTL9.8 Set Liberty pin direction to output because it has an output function
RTL9.9 Extra ; is detected in port list
RTL9.10 Liberty cell does not use any input pin
RTL9.11 Liberty Master-Slave DFF cell clock phase does not match the timing
table
RTL9.12 Liberty cell with internal_node does not have correct statetable
RTL9.13 Set liberty cell to blackbox because some of its output pins have no
function
RTL9.14 Liberty cell has duplicate signal (pin/member)
RTL10 Both posedge and negedge are used in different always/process
RTL11 Incomplete condition is in a function/procedure/task block
RTL12 Referenced variable(s)/signal(s) are not in sensitivity list
RTL12.1 Constant object is in sensitivity list
RTL13 For loop condition is always false
RTL13.1 The FOR-LOOP index should not be assigned within the loop itself
RTL13.2 The evaluation of for-loop condition is not constant
RTL14 Signal with fanin drive and no fanout load is detected
RTL14.1 Fanout load of the signal is removed
RTL15 Clock and asynchronous set/reset expression must be one bit wide
RTL15.1 Else branch of event controlled if statement is not supported
RTL15.2 Sensitivity/clock style is unsupported
RTL16.1 Non-local variable is read in a function body
RTL16.2 Non-local variable is assigned in a function body
RTL17 Variable size exceeds the maximum limit
Rule Number Message
RTL17.1 Expression size exceeds the maximum limit
RTL18.1 Package is not an IEEE standard
RTL18.2 Function denition has empty body
RTL18.3 Function call does not refer to a function denition
RTL18.4 Ignoring resolution function. This might cause mismatches between
simulation and synthesis
RTL19.1 Identier is a reserved keyword and might conict in designs with mixed
languages
RTL20.1 Pre-dened attribute is not supported
RTL20.2 Function is not supported
RTL20.3 Could not nd conguration
Rule Number Message
RTL1.1
Message
Variable/signal is assigned by more than one concurrent statement
Default Severity
Warning
Description
The design includes one or more cases where a variable or signal is assigned by two or more
concurrent statements.
Example
In the following example, the design concurrently assigns output out0. See lines 4 and 5 (in
bold).
module SEN (clk,rst,in0,in1,out0);
input clk,rst,in0,in1;
output out0;
endmodule
RTL1.2
Message
Variable/signal is assigned by multiple non-blocking assignments
Default Severity
Warning
Description
The design includes one or more cases where a variable or signal is assigned by two or more
non-blocking assignments.
Example
In the following example, variable out0 is assigned by a non-blocking assignment. See lines
7 and 8 (in bold).
module VLGT (clk,rst,in0,in1,out0);
output out0;
reg out0;
begin
out0 <= in0 & in1;
out0 <= in1 & in0;
end
endmodule
RTL1.2a
Message
Variable/signal on instance INOUT port might have multiple drivers
Default Severity
Warning
Description
The variable or signal on the INOUT instance port might have multiple drivers.
Example
In the following example, in line 4 , ports VSSA and VSSG are dened as INOUT ports in the
library le:
module mod1_G(Y,A,VDDA,VSSA,VDDG,VSSG);
input A, VDDA, VSSA, VDDG, VSSG;
output Y;
KAQ2 I0(.Y(I0_Y), .A(A), .VDD_A(VDDA), .VSS_A(VSSA), .VDD_G(VDDG), \
.VSS_G(VSSG));
KAQ2 I2(.Y(Y), .A(I0_Y), .VDD_G(VDDG), .VSS_G(VSSG), .VDD_A(VDDA), \
.VSS_A(VSSA));
end
endmodule;
RTL1.3
Message
Variable/signal is assigned by both blocking and non-blocking assignments
Default Severity
Warning
Description
The design includes one or more cases where a variable or signal is assigned by both
blocking and non-blocking assignments.
Example
On line 7 of the following example, variable out0 is assigned by a blocking assignment, and
on line 9, variable out0 is assigned by a non-blocking assignment.
module VGT (rst,in0,in1,out0);
input rst,in0,in1;
output out0;
reg out0;
always @(rst or in1 or in0) begin
if (rst)
out0 = in1 & in0;
else
out0 <= in0 & in1;
end
endmodule
RTL1.4
Message
Assignment with LHS bit width is greater than RHS bit width
Default Severity
Warning
Description
The design includes one or more assignments with a left-hand-side (LHS) bit width greater
than the right-hand-side (RHS) bit width.
Example
In the following example, the assignment of in0 to out0 has mismatched bit widths. See line
6 (in bold).
module VT (clk,in0,out0);
input clk,in0;
output [3:0] out0;
reg [3:0] out0;
always @(posedge clk) begin
out0 <= in0;
end
endmodule
RTL1.5a
Message
Assignment with RHS bit width is greater than LHS bit width
Default Severity
Warning
Description
The design includes one or more assignments with a right-hand-side (RHS) bit width greater
than the left-hand-side (LHS) bit width.
Example
1.
In the following example, the design assigns a two-bit vector logic 2'b01 to a one-bit
output out0 (see line 3).
module test(out0);
output out0;
assign out0 = 2'b01;
endmodule
2. In the following Verilog example, the self-determined bit width for the RHS expression is
5, while the LHS is only 4.
x[3:0] = a[4:0] + b [4:0];
RTL1.5b
Message
Potential loss of RHS msb or carry-out bit
Default Severity
Warning
Description
The design includes one or more assignments where there is potential for the right-hand-side
(RHS) to lose its most-signicant-bit (MSB) or carry-out bit.
Example
1. In the following example, the self-determined bit width of the RHS is 4 and the LHS is
also 4; however, x[3:0] does not take the potential carry-out from the RHS.
x[3:0] = a[3:0] + b[3:0];
2. In the following Verilog example, the self-determined bit width for the RHS is 4 and the
LHS is also 4; however, arithmetically, the product is 8 bits and x[3:0] only takes the
lower 4 bits of the total 8 bits.
x[3:0] = a[3:0] * b[3:0];
RTL1.6
Message
Blocking assignment is in sequential always block
Default Severity
Warning
Description
The design includes one or more blocking assignments in a sequential always block.
Example
On lines 7 and 9 of the following example, the design uses blocking assignments:
module VLGT (clk,rst,in0,in1,out0);
output out0;
reg out0;
if (rst)
out0 = in1 & in0;
else
out0 = in0 & in1;
end
endmodule
RTL1.7
Message
Non-blocking assignment is in combinational always block
Default Severity
Warning
Description
The design includes one or more non-blocking assignments in a combinational always block.
Example
On lines 7 and 9 of the following example, the design uses non-blocking assignments:
module VT (sel,in0,in1,out0);
input sel,in0,in1;
output out0;
reg out0;
always @(sel or in1 or in0) begin
if (sel)
out0 <= in1 & in0;
else
out0 <= in0 & in1;
end
endmodule
RTL1.8
Message
Latch is assigned by blocking assignments
Default Severity
Warning
Description
The design includes one or more latches that are coded using a blocking assignment. We
recommend that sequential elements be coded using a non-blocking assignment rather than
a blocking assignment.
Example
In the following example, latch Q is coded using a blocking assignment (see line 7):
module Dlat(data, en, Q);
input data, en;
output Q;
reg Q;
always @( en or data)
if (en) Q = data;
endmodule
RTL1.9
Message
Parameter bit width does not match RHS bit width
Default Severity
Warning
Description
The design includes one or more parameter bit widths that do not match with right-hand-side
(RHS) bit widths.
Example
In the following example, parameter my_values is declared as a 3-bit vector, but was
assigned a 4-bit vector (see line 3):
module test (Z);
output [3:0]Z;
parameter signed [2:0] my_values = 4b1010;
assign Z = my_values;
endmodule
RTL1.11
Message
Variable is assigned by both continuous and procedural statements
Default Severity
Error
Description
A variable is assigned by both continuous and procedural statements.
Example
In the following example, variable t1 is assigned in lines 5 and 8.
module test (a, b,t1);
input a,b ;
output t1 ;
logic t1 ;
assign t1 = a & b;
always @(a or b )
begin
task1 (t1);
end
task task1 (output c);
begin
c = a | b;
end
endtask
endmodule
RTL1.12
Message
variable(SV:logic/bit) is assigned by multiple continuous statements
Default Severity
Error
Description
A variable is assigned by multiple continuous statements.
Example
In the following example, variable t1 is assigned in lines 5 and 6.
module test (a, b,t1);
input a,b ;
output t1 ;
logic t1 ;
assign t1 = a & b;
assign t1 = a | b;
endmodule
RTL1.13
Message
Mismatched enumeration types are in the assignment
Default Severity
Error
Description
There are mismatched enumeration types in the assignment.
Example
In the following example, In line 5, read and din have mismatched enumeration type.
typedef enum {write , add, sub, mult} instr_t;
typedef enum {WAIT, LOAD, STORE} state_t;
module test(output state_t read, input instr_t din);
always_comb
read = din;
endmodule
RTL1.14
Message
Mismatched enumeration types are in the expression
Default Severity
Error
Description
There are mismatched enumeration types in the expression.
Example
In the following example, In line 6, enumeration types are mismatched.
module test (output integer out1) ;
enum {IDLE=2b00, S1, S2} state;
assign state = S1;
always @*
begin
out1 = (state == 4)? 2b00:state;
end
endmodule
RTL2.1
Message
Variable is referenced before the assignment
Default Severity
Warning
Description
The design includes one or more variables that are referenced before they are assigned.
Example
On line 8 of the following example, the design references variable sig1, but does not assign
it until line 9:
module TPS (clk,in1,in2,out0);
input clk,in1,in2;
output out0;
reg out0;
always @ (in1 or in2)
begin
reg sig1;
out0 = sig1;
sig1 = in1 | in2;
end
endmodule
RTL2.1a
Message
Variable is referenced before assignment in subprogram. Possible simulation
mismatch
Default Severity
Warning
Description
For initialized variable in subprogram, simulation mismatch might occure when the variable is
referenced before the assignment. For the Conformal Equivalence Checking software and
synthesis tools, the variable will default to 0. However, for simulation, the variable assumes
previously assigned value.
Example
In the following example, in line 16, variable nxt_svl is referenced before assignment. This
can cause a simulation or synthesis mismatch.
function [11:0] foo;
...
reg nxt_svl;
begin
if (reset)
begin
...
nxt_svl = 1b0;
...
end
else
begin
...
case (state)
state0:
if (nxt_svl)
...
state5:
nxt_svl = 1b1;
...
endfunction
RTL2.2
Message
Variable is referenced but never assigned
Default Severity
Warning
Description
The design includes one or more variables that are referenced but never assigned in the
design.
Example
In the following example, the design references variable da0, but never assigns it:
module SEN (clk,rst,out0);
input clk,rst;
output out0;
reg out0;
reg da0;
always @ ( posedge rst or posedge clk )
begin
if (rst) begin
out0 <= 1'b0;
end
else begin
out0 <= da0;
end
end
endmodule
RTL2.3
Message
Externally defined signal reference is not supported
Default Severity
Warning
Description
The checker did not support one or more externally dened signal references when they were
used in multiple entities. The checker only supports one entity that uses the externally dened
signal.
Example
In the following example, the design references the externally dened signal glob1 in
multiple entities, which causes the checker to error out.
Note:
example.
PACKAGE pack IS
SIGNAL glob1 : boolean;
END PACK;
USE work. pack.all;
ENTITY test IS
END test;
glob1 <= in0 or in1;

END arch;
ENTITY test2 IS
END test2;
ARCHITECTURE arch OF test2 IS

END arch;
RTL2.4
Message
Externally defined signal reference is supported
Default Severity
Note
Description
The checker supports one or more externally dened signal references. The checker only
supports the rst entity that uses the externally dened signal.
Example
In the following example, the design uses signal glob1 although it is dened outside entity
TEST (see line 13).
package pack is
signal glob1 : boolean;
end pack;
use work. pack.all;
entity TEST is
port (
in0, in1, in2 : in boolean;
out0 : out boolean
);
end test;
architecture arch of test is
begin
out0 <= glob1 and in2;
end arch;
RTL2.5
Message
Undriven net is detected
Default Severity
Warning
Description
The specied wire is not assigned. It is connected to an object indicating that the wire has
been read at least once. Such usage leads to redundant code, undened states, and errors.
To avoid this, assign wires properly. If unassigned wires are not used, remove them. This rule
honors the synthesis off or on pragmas. This implies that a wire is considered unassigned
when assignment is made inside synthesis off or on pragma and its declaration is outside the
pragma.
Example
In the following example, g1 (line 5) is an undriven net:
module unassigned_wire (in1, out1);
input in1;
output out1;
wire g1;
assign out1 = in1 & g1;
endmodule
RTL2.6
Message
Shared variables are not supported
Default Severity
Warning
Description
Shared variables are not supported. To avoid this error, remodel the design.
Example
In the following example, shared variable counter (line 8) is not supported:
library IEEE;
use IEEE.std_logic_1164.all;
entity shared_variables is
port (DataIn : in integer);
end entity shared_variables;
architecture shared_variables_arch of shared_variables is
subtype ShortRange is integer range 0 to 1;
shared variable counter : ShortRange := 0;
begin
PROC1:process
begin
counter := counter + 1;
wait;
end process PROC1;
PROC2:process
begin
counter := counter - 1;
wait;
end process PROC2;
end architecture shared_variables_arch;
RTL2.7
Message
Dynamic slice is not supported
Default Severity
Warning
Description
The left and right bounds of the part range cannot be evaluated to constant values. Such
expressions are not supported by synthesis tools and are ignored.
Example
In the following example, the dynamic slice in line 14 is not supported:
Library IEEE;
Entity TEST is
Port (
Sdq_data : out std_logic_vector (7 downto 0));
End TEST;
Architecture ARCH_TEST of TEST is
Type vect_array is array (7 downto 0) of std_logic_vector (7 downto 0);
Signal data : vect_array;
Begin
Process
Variable I : integer;
Begin
Sdq_data (I+7 downto I) <= data (I) (7 downto 0);
End process;
End ARCH_TEST;
RTL2.8
Message
BUS and REGISTER signal type are not supported for synthesis
Default Severity
Warning
Description
The BUS and REGISTER signal type are not supported by the synthesis tools and are ignored.
Example
In the following example, the bus signal type in line 5 is not supported:
entity EG1 is
port (a: in BIT; z: out bit);
end;
architecture RTL of EG1 is
signal sig1: bit bus;
begin
process
begin
if a = 1 then z <= 1;
else z<= 0;
end if;
end process;
end;
RTL2.9
Message
Guarded assignment requires GUARD signal
Default Severity
Error
Description
The GUARD signal is not declared for guarded assignment.
Example
In the following example, the guarded signal is not declared for line 9s guarded assignment:
entity EG1 is
port (a,b: in bit; z: out bit);
end;
signal val: bit;
begin
guarded_block: block
begin
val <= guarded a and b;
end block;
z <= val;
end;
RTL2.10
Message
GUARD is not declared
Default Severity
Error
Description
The GUARD signal is not declared.
Example
In the following example, the guard signal in line 8 is not declared:
entity EG1 is
end;
begin
guarded_block: block --(a = 1)
begin
z <= 1 when guard else 0;
end block;
end;
RTL2.11
Message
Implicitly declared GUARD signal cannot be updated
Default Severity
Error
Description
The implicitly declared GUARD signal cannot be updated. The implicit guard signal will be
declared for a guarded block. This is illegal to update the implicitly declared GUARD signal.
Example
In the following example, the guard signal in in line 8 is illegal:
entity EG1 is
end;
begin
guarded_block: block (a = 1)
begin
guard <= (b= 1);
end block;
end;
RTL2.12
Message
Illegal redeclaration of GUARD signal
Default Severity
Error
Description
The redeclaration of GUARD signal is illegal. The implicit GUARD signal will be declared for a
guarded block. It is illegal to redeclare GUARD signal.
Example
In the following example, the guard signal in in line 7 is illegal:
entity EG1 is
end;
begin
guarded_block: block (a = 1)
signal guard : boolean;
begin
end block;
end;
RTL2.13
Message
Undriven pin is detected
Default Severity
Warning
Description
Undriven pin(s) are detected in the design.
Example
In the following example, pin in1 of instance test is undriven (see line 4):
module top (din1, dout1);
output dout1;
input din1;
test t1(.in2(din1),.out1(dout1));
endmodule
module test(in1,in2, out1);
input in1, in2;
output out1;
endmodule
RTL3.1
Message
Variable/signal is unassigned in asynchronous set/reset
Default Severity
Warning
Description
The design includes one or more variables or signals that are unassigned in one of the
conditional branches in asynchronous set/reset branches.
Example
In the following example, the design assigns output out0 in the else branch, but not in the
if branch of the asynchronous set/reset. See line 11 (in bold).
module SEN (clk,rst,in0,out0,out1);
input clk,rst,in0;
output out0,out1;
reg out0,out1;
begin
if (rst) begin
out1 <= 1'b0;
end
else begin
out0 <= in0;
out1 <= !in0;
end
end
endmodule
RTL3.2
Message
Assignment of X is in asynchronous set/reset branch
Default Severity
Warning
Description
The design includes one or more X value assignments in asynchronous set/reset branches.
Example
In the following example, the design assigns X value to out0. See line 8 (in bold).
module OPW (clk,rst,in0,out0);
input clk,rst,in0;
output out0;
reg out0;
begin
if (rst) begin
out0 <= 1'bx;
end
else begin
out0 <= in0;
end
end
endmodule
RTL3.3
Message
Non-constant value assignment is in asynchronous set/reset value
Default Severity
Warning
Description
The design includes one or more non-constant value assignments in asynchronous set/reset
branches.
Example
In the following example, the design assigns a non-constant value to out0. See line 8 (in
bold).
module OPW (clk,rst,in0,in1,out0);
output out0;
reg out0;
begin
if (rst) begin
out0 <= in1;
end
else begin
out0 <= in0;
end
end
endmodule
RTL3.4
Message
DFF/DLAT is with both asynchronous set and reset connections
Default Severity
Warning
Description
The design includes one or more DFFs or DLATs that have both asynchronous set and reset
connections.
Example
On line 8 of the following example, the design uses rst for an asynchronous reset. The
design then uses set for an asynchronous set on line 10.
module test (clk,set,rst,in0,in1,out0);
input clk,set,rst,in0,in1;
output out0;
reg out0;
always @ ( posedge rst or posedge set or
posedge clk )
begin
if (rst)
out0 <= 1'b0;
else if (set)
out0 <= 1'b1;
else
out0 <= in0;
end
endmodule
RTL3.5
Message
Variable/signal is assigned without using asynchronous set/reset
Default Severity
Ignore
Description
Design style check to report if the RTL codes infer to a DFF gate that does not use any
asynchronous set or reset signal.
Example
On line 6 of the following example, the design assigns output out0 without any asynchronous
set or reset signal:
module SEN (clk,rst,in0,out0);
input clk,rst,in0;
output out0;
reg out0;
out0 <= in0;
...
endmodule
RTL4.1
Message
Enum encoding is applied to enum type
Default Severity
Note
Description
The design includes one or more ENUM_ENCODING attributes to declare enumtype in VHDL.
For Verilog, use the synopsys enum directive to declare enum type.
Example
On line 14 of the following example, the design includes an ENUM_ENCODING attribute to
declare enum type:
PACKAGE small_1164 IS
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
attribute ENUM_ENCODING of std_ulogic : type is U D 0 1 Z D 0 1 D;
end package;
RTL4.2
Message
Multiple wait statements. FSM encoding might be different
Default Severity
Warning
Description
The design includes one or more always/process blocks containing multiple wait statements.
The checker creates a Finite State Machine (FSM) when it encounters multiple wait
statements. We recommend that you verify that the FSM encoding is what you expected.
Example
On lines 8 and 12 of the following example, the design uses the wait statement:
Module Medge (Clock, Cond, In1, In2, In3, Out1);
input Clock, Cond, In1, In2, In3;
output Out1;
reg Out1;
always
begin
@ (posedge Clock);
Out1 = In1;
if (Cond)
begin
@ (posedge Clock);
Out1 = In2;
end
else
begin
@ (posedge Clock);
Out1 = In3;
end
end
endmodule
RTL4.3
Message
Enum value size is different than the declared data type
Default Severity
Warning
Description
The enum value size is different than the declared data type.
Example
The declared type light size is 2, but the enum value GREEN size is 3:
module enum10(input clk,output reg out1);
typedef enum reg signed [1:0] { RED = 2'sb10,YELLOW,GREEN = 3'b000} light;
light mylight;
always @(clk)
begin
mylight=RED;
out1 = mylight;
end
endmodule
RTL4.4
Message
Encoding format has too many values
Default Severity
Warning
Description
There are more encoding values than necessary.
Example
In line 3, there are more encoding values than are needed:
type fifo_valid_state_type is (full1, full2, full3, empty);
attribute ENUM_ENCODING of fifo_valid_state_type : type is "0001 0011 0010 0000
0100 0101 0111 0110 1110";
RTL5.1
Message
Overlapped case items are in parallel case statement
Default Severity
Warning
Description
The design includes multiple case_items that potentially match the case_expressions in
parallel case statements.
A parallel case statement syntax:
case (case_expression) //synopsys Parallel_case case_item1 :
//case_item_statement1;
case_item2 : case_item_statement2;
default : case_item_statement3;
endcase
Example
On lines 8 and 9 of the following example, case_items 2'b1? and 2'b?1 match the
case_expression sel when sel is equal to 2'b11.
module test ( a, b, sel, out0);
input a, b;
input [1:0] sel;
output out0;
reg out0;
always @(sel or a or b) begin
casez (sel) //synopsys parallel_case
2'b1? : out0 = a;
2'b?1 : out0 = b;
default: out0 = 1'bx;
endcase
end
endmodule
RTL5.2
Message
Non-binary case items are in case statement
Default Severity
Warning
Description
The design includes one or more case_items with non-binary values in case statements.
A case statement syntax:
case (case_expression)
endcase
Example
In the following example, the design includes a Z value for a case_item. See line 9 (in bold).
module test ( a, b, c, sel, out0);
input a, b, c;
input sel;
output out0;
reg out0;
always @(sel or a or b or c) begin
case(sel)
1'b1 : out0 = a;
1'bz : out0 = b;
default: out0 = c;
endcase
end
endmodule
RTL5.3
Message
Case expressions/items are resized
Default Severity
Warning
Description
The design includes one or more case itemsizes that do not match the case expression sizes.
Example
On lines 8 and 10 of the following example, the case items have a single bit, while the case
expression (line 3) is a 2-bit vector.
input a, b, c;
input [1:0] sel;
output out0;
reg out0;
case(sel)
1b1 :
out0 = a;
1b0 :
out0 = b;
default:
out0 = c;
endcase
end
endmodule
RTL5.4
Message
Partial case items are in full case statement
Default Severity
Note
Description
The design includes a partial case enumeration in a full case statement.
Example
The following example contains a potential partial case enumeration. The 4b00 and 411
case items are not enumerated in the full_case statement(in bold).
module test (out, a, b, select);
output out;
input a, b;
input [1:0] select;
reg out;
always @(select or a or b) begin
casez (select) /* full_case */
4b01: out = a;
4b10: out = b;
endcase
end
endmodule
RTL6.1
Message
X created due to the assignment of value X
Default Severity
Warning
Description
One or more assignments use value X. The checker generates a dont care for any value X
assignment.
Example
In the following example, the design assigns a 1'bx value to output o. See line 6 (in bold).
module test(o,i);
output o;
reg o;
input i;
always
o = 1'bx;
endmodule
RTL6.2
Message
Integer value range constraint is added
Default Severity
Warning
Description
When you read in the design, you specied a constraint on integers for a specic range. The
switch of the command that you used to apply the constraint is -rangeconstraint.
Example
In the following example, integer int1 has a value range from -1024 to 1024 (see line 4).
ENTITY test IS
PORT (
clk : IN std_ulogic ;
int1 : IN integer range -1024 to 1024 ;
bufferA : BUFFER std_ulogic
);
END test;
ARCHITECTURE arc OF test IS
BEGIN
PROCESS
BEGIN
IF clk = '1' AND clk'event THEN
IF int1 = 4095 THEN
bufferA <= '0' ;
ELSE
bufferA <= '1' ;
END IF ;
END IF ;
END PROCESS;
END;
Input:
SETUP>read design test.vhdl -vhdl -rangeconstraint
RTL6.3
Message
X created when divisor equals to zero
Default Severity
Warning
Description
The design contains one or more divisors that are signals or variables, and not constants.
Thus, there is a chance that they will equal zero. In these cases, the checker creates X.
Example
In the following example, the divisor B is an input signal, thus the checker creates X (see line
4).
module test(A, B, QUOTIENT);
input [7:0] A, B;
output [7:0] QUOTIENT;
assign QUOTIENT = A / B;
endmodule
RTL6.4
Message
Enum value constraint is added
Default Severity
Warning
Description
The checker recognized the synopsys enum fsm_state directive, thus it added a
constraint to Enum value.
Example
In the following example, on lines 3 through 9 (in bold), the checker constrains enum states
ra_state and next_state to a one-hot condition.
module test (masterclk, reset_n, mem_write);
parameter [4:0] // synopsys enum fsm_states

iddle = 5b00001,
step01 = 5b00010,
step02 = 5b00100,
step03 = 5b01000,
step04 = 5b10000,
reg [4:0] /* synopsys enum fsm_states */ ra_state, next_state;
always @(ra_state or mem_write) begin
case (ra_state)
iddle: begin
tmp = mem_write;
next_state = step01;
end
step01: begin
tmp = 1b0;
next_state = step02;
end
default: begin
tmp = mem_write;
next_state = iddle;
end
endcase
end
endmodule
RTL6.5
Message
priority if and unique if statements are incomplete
Default Severity
Warning
Description
There are incomplete priority if and unique if SystemVerilog statements. The
priority if and unique if SystemVerilog statements ensure that all conditions are
complete; they ensure that default else statements exist and
if/else if conditions cover all
conditions.
Example
In the following example, the incomplete priority if statement in line 4 triggers this rule
check, while the complete priority if statement in lines 11-12 do not trigger this rule
check.
module test1(input aa, output oo);
reg oo;
always @* begin
priority if (aa) oo = !aa; // incomplete condition
end
endmodule
reg oo;
always @* begin
priority if (aa) oo = !aa;
else oo = aa; // complete condition
end
endmodule
RTL6.6
Message
unique if statements have redundant or overlapping conditions
Default Severity
Note
Description
There are possible redundant or overlapping conditions in unique if statements. Structural
checks generate this message; a more detailed analysis is done during compare.
Example
In the following example, there are overlapping conditions in the unique if statement that
will cause a rule check report. See line 5.
module test3(input aa, bb, output oo);
reg oo;
always @* begin
unique if (aa && bb) oo = !aa;
else if (aa || bb) oo = aa;
else oo = 1b0;
end
endmodule
RTL7.1
Message
Design includes comparison that uses X or Z values
Default Severity
Warning
Description
The design includes one or more comparisons that use X or Z values as comparators.
Example
In the following example, the design compares reset rst with an X value. See line 7 (in bold).
module test (clk,rst,in0,out0);
input clk,rst,in0;
output out0;
reg out0;
begin
if (rst == 1'bx)
out0 <= 1'b0;
else
out0 <= in0;
end
endmodule
RTL7.2
Message
Gate or transistor primitive is using weak attributes
Default Severity
Warning
Description
One or more gates or transistor primitives are using weak attributes.
Note: Not all weak attributes will be used. In the case of a multiple-driven net, the gate with
the strong attribute will drive the output.
Example
In the following example, the design uses a weak attribute for a buffer primitive. See line 5 (in
bold).
input clk,rst,in0;
output out0;
wire out0;
buf (weak0, weak1) (out0, in0);
endmodule
RTL7.3
Message
Array index in RHS might be out of range
Default Severity
Warning
Description
The design includes an index where its right hand side might be out of range.
Example
In the following example, it uses an index where its right hand side might be out of range. See
line 10
(in bold)
.
module test (clk, idx, in0, out0);
input clk;
input [3:0] idx;
input [3:0] in0;
output out0;
reg out0;
always @ ( posedge clk)
begin
out0 <= in0[idx];
end
endmodule
RTL7.4
Message
Array index in LHS might be out of range
Default Severity
Warning
Description
The design includes an index where its left hand side might be out of range.
Example
In the following example, it uses an index where its left hand side might be out of range. See
line 10
(in bold)
.
module test (clk, idx, in0, out0);
input clk;
input [3:0] idx;
input in0;
output [3:0] out0;
reg [3:0] out0;
always @ ( posedge clk)
begin
out0[idx] <= in0;
end
endmodule
RTL7.5
Message
Input signal is assigned by logic values
Default Severity
Warning
Description
The design includes one or more primary input signals that are assigned by logic values.
Example
In the following example, the design assigns logic value 1 to primary input a. See line 4 (in
bold).
module test(a, b);
input a;
output b;
assign a = 1'b1;
assign b = 1'b1;
endmodule
RTL7.6
Message
Value X or Z is treated as 0 in unary/binary expressions
Default Severity
Warning
Description
The checker treats the 1bx or 1bz in unary/binary expression as 1b0.
Example
In the following example, on line 7 (in bold), the 1bx value in the conditional expression is
treated as 1b0. Thus, input in2 will be assigned directly to output out.
module test(in1, in2, out);
input in1, in2;
output out;
reg out;
always begin
out = 1bx ? in1 : in2;
end
endmodule
RTL7.7
Message
Real number rounded to integer value
Default Severity
Warning
Description
The checker rounds real numbers to integer values.
Example
In the following example, on line 2 (in bold), input din has a real value of 2.2. However, the
checker truncates this value at .2.
input [2.2:0] din;
output [2:0] dout;
assign dout = din;
endmodule
RTL7.8
Message
Overflowed integer is truncated
Default Severity
Warning
Description
The design contains one or more integers that overow. Thus, the checker truncates them.
Example
In the following example, the checker truncates integer b;. See line 3.
module test (b);
output b;
integer b;
always
b = 5147483648;
endmodule
RTL7.9
Message
Sign overflowed integer is truncated
Default Severity
Warning
Description
The design contains one or more integers that overow at the sign bit. Thus, the checker
truncates them.
Example
In the following example, the checker truncates integer b;. See line 3 (in bold).
module test (b);
output b;
integer b;
always
b = 2147483648;
endmodule
RTL7.10
Message
Comparison with signed and unsigned operands
Default Severity
Warning
Description
The design includes both signed and unsigned operands used in a relational expression.
Example
In the following example, the checker compares the signed operand in1 (on line 4) to the
unsigned operand in2 (on line 5). The checker converts in1 to an unsigned operand rst,
and then compares it with in2. An unsigned comparison results.
module test (out0, in1, in2);
output out0;
input signed [31:0] in1;
input unsigned [31:0] in2;
assign out0 = in1 > in2;
endmodule
RTL7.11
Message
Implicit signed expression is converted to unsigned
Default Severity
Warning
Description
The design includes a signed expression that the checker has converted to an unsigned
expression implicitly.
Example
In the following example, the checker converts the signed operand in1 to unsigned in the
conditional expression. See line 7 (in bold).
module test (out0, cond1, in1);
output unsigned [32:0] out0;
input cond1;
input signed [31:0] in1;
assign out0 = cond1 ? out0 : in1;
endmodule
RTL7.12
Message
Unsized integer number is truncated to 32 bits
Default Severity
Warning
Description
The checker truncated an unsized integer literal to 32-bit.
Example
In the following example, the checker truncates hf00000000 to h00000000. See line 2.
assign oo = (hf00000000 > 32h0)?aa:!aa;
RTL7.13
Message
Logical operator is applied to multiple-bit operand
Default Severity
Warning
Description
The logical operator is applied to multiple-bit operand when the operand is not a single-bit
expression.
Example
In the following example, the logical operator && is applied to multiple-bit operand tmp (see
line 5):
input in;
output out;
wire [2:0] tmp;
assign out = in && tmp;
endmodule
RTL7.14
Message
Loop exceeds maximum iterations
Default Severity
Warning
Description
An index variable should be sufciently large enough to hold both the initial and the nal
values that the loop index could take. If the index variable is small, the loop will be executed
fewer number of times. This can lead to unpredictable behavior.
.Example
In the following example, I can only take values from 0 to 3 as its size 2 bits. Line 8 of the
code shows that the index of the for loop ranges from 0 to 5. Since the loop index variable I
is not large enough to hold the nal value of the loop index, the loop may never terminate.
module neg_BITUSD_loop_idx_bitsel(a, b, c);
input [3:0] a, b;
output [3:0] c;
reg [3:0] c;
always @(a or b)
begin: P
reg [1:0] I;
for (I = 2; I <= 5; I = I + 1)
begin: loop2
c[I] = a[I] | b[I];
end
end
endmodule
RTL7.15
Message
Null slice is not supported
Default Severity
Warning
Description
The specied datatype or node is dened with a null range, and it cannot hold any value. In
VHDL, a range is considered to be a null range, if the subset of values specied by the range
is empty (a decreasing range with a to direction, or an increasing range with a downto
direction). Examples of null range are (3 to 0) and (1 downto 8). The synthesis tools do not
support null range.
Example
In the following example, the null slice in line 9 is not supported:
entity TEST1 is
port (
in1: in integer ;
out2: buffer bit;
out3: out bit
) ;
end TEST1 ;
architecture ARCH_TEST1 of TEST1 is
type myvector is array(0 downto 7) of BIT;
begin
process (in1)
variable vec: myvector;
variable index: integer;
variable temp: bit;
begin
vec:= (1, 1, 1, 1, 1, 1, 1, 1) ;
temp:= vec(in1);
end process;
end ARCH_TEST1 ;
RTL7.16
Message
Variable index is out of the defined range
Default Severity
Warning
Description
A bit or part select reference in an expression is found to have an index specication outside
of the dened range of the variable. This can lead to unexpected simulation or synthesis
results. Cadence recommends that you change the reference so that the index or subrange
falls within the valid range.
Example
In the following example, index [4] is out of as range (see line 7):
module test1 (a, b, out1);
input [3:0] a;
input [3:0] b;
output out1;
reg out1;
always @(a or b)
out1 = a[4] & b[3];
endmodule
RTL7.17
Message
Exponentiation operator is unsupported
Default Severity
Warning
Description
Some synthesis tools do not support the exponentiation operator. Cadence recommends that
you remodel your HDL source code.
Example
In the following example, a ** 5 (line 14) is not supported:
Library IEEE;
use IEEE.std_logic_arith.all;
entity TEST1 is
port (
a : in INTEGER;
out1 : out INTEGER
) ;
end TEST1 ;
architecture ARCH_TEST1 of TEST1 is
begin
process (a)
begin
out1 <= a ** 5;
end process;
end ARCH_TEST1 ;
RTL7.18
Message
Argument size to integer type conversion is too large
Default Severity
Warning
Description
The argument width is too large for conversion CONV_INTEGER. The maximum argument
width is 32 for a signed argument or 31 for an unsigned argument.
The Logical Equivalency Checker does truncations for the following:
I unsigned (31 bits) conversion to integer
I signed (32 bits) conversion to integer
Example
In the following example, on line 10, the argument for conv_integer is 32 bit width
unsigned, is too large (maximum if 31 for an unsigned argument).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity IntCtrl is
port( IRQ : out integer;
IntCtrlReg_th : in std_logic_vector(31 downto 0));
end IntCtrl;
architecture rtl of IntCtrl is
begin
IRQ <= conv_integer(unsigned(IntCtrlReg_th));
end rtl;
RTL7.19
Message
Added constraint on integer overflow for arithmetic operation ADD/SUB
Default Severity
Warning
Description
A constraint is added on the integer overow for the ADD or SUB arithmetic operation.
Example
In the following example, in line 11, if (CONV_INTEGER(a) + b) > 2**31-1 (overow),
the software can derive a constraint on this overow, and then compare can ignore the
different interpretation synthesis tool made when (CONV_INTEGER(a) + b) > 2**31-1
occurs.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY test IS
PORT ( a, b : IN natural;
z : OUT integer );
END test;
ARCHITECTURE rtl OF test IS
BEGIN
z <= CONV_INTEGER(a) + b ;
END rtl;
RTL7.20
Message
Size value in size(expr) casting is too large
Default Severity
Error
Description
The size value in size(expr) casting is too large. Use a positive integer value as the size
value.
Example
In the following example, the size hffffffff in line 4 is too large:
input in;
output out;
assign out = hffffffff(in);
endmodule;
RTL7.21
Message
Real variables are not supported
Default Severity
Warning
Description
Real variables are not supported in synthesis models. They are converted to 32-bit integers
when encountered in the static verication tool ows.
Example
In the following example, r1 (line 5) is not supported:
module real_in_cmp (b, out1);
input [1:0] b;
output out1;
reg out1;
real r1;
always @(b)
r1 = b;
endmodule
RTL8.1
Message
Multiple multipliers/dividers are in module/entity
Default Severity
Note
Description
One or more modules or entities have multiple multipliers or dividers.
Example
In the following example, the design uses two multipliers in module test. See line 4 (in
bold).
module test (a, b, c, q);
input [3:0] a, b, c;
output [11:0] q;
assign q = a * b * c;
endmodule
RTL8.2
Message
Latch(es) are inferred due to an incomplete conditional statement
Default Severity
Note
Description
The checker has inferred one or more latches. The checker infers a latch when it nds an
incomplete conditional statement.
Example
In the following example, the checker infers latch out0 so that output out0 will retain its
previous value when the clk = 1'b0, the missing condition. See line 8 (in bold).
input clk,rst,in0;
output out0;
reg out0;
always @ ( clk or in0 )
begin
if (clk)
out0 = in0;
end
endmodule
RTL8.3
Message
Unreachable DFF/DLAT is removed
Default Severity
Warning
Description
The design includes one or more DFFs or DLATs that are unreachable. Unreachable registers
are those registers that do not propagate to any observable point (for example, spare ops).
By default, the checker removes all unreachable DFFs and DLATs that are local to a module.
If you want to keep the unreachable DFFs and DLATs, use the READ DESIGN commands
-keep_unreach option. For example:
read design test.vhdl -vhdl -keep_unreach
Example
In the following example, the output of register out1[1] does not propagate to any
observable point. See line 9 (in bold).
module TEST (clk,in1,in2,out0);
input clk,in1,in2;
output out0;
reg out0;
reg[1:0] out1;
begin
out0 <= in1;
out1[1] <= in2;
end
endmodule
RTL8.4
Message
Unreachable DFF/DLAT is kept
Default Severity
Warning
Description
The design includes one or more DFFs or DLATs that are unreachable. Unreachable registers
are those registers that do not propagate to any observable point (for example, spare ops).
By default, the checker removes all unreachable DFFs and DLATs that are local to a module.
You will receive this message if you use the READ DESIGN commands -keep_unreach
option. For example:
read design test.vhdl -vhdl -keep_unreach
Example
In the following example, on line 9, DFF out1[1] is unreachable:
module TEST (clk,in1,in2,out0);
input clk,in1,in2;
output out0;
reg out0;
reg[1:0] out1;
begin
out0 <= in1;
out1[1] <= in2;
end
endmodule
RTL8.5
Message
Implicit signed multiplier is detected in module/entity
Default Severity
Note
Description
The checker detected (and recognized) the Verilog signed multiplier coding style that uses
either sign-extension or subtraction.
Example
In the following example, on lines 5, a signed multiplier is created using sign-extension coding
style:
module test( in1, in2, out);//using sign-extension
input [21:0] in1;
input [13:0] in2;
output [34:0] out;
assign out= {{21{in2[13]}}, in2[13:0]} * {{13{in1[21]}}, in1[21:0]};
endmodule
RTL9.1
Message
Instance inout/output port has dynamic indexing. Treated as floating
Default Severity
Warning
Description
The design includes one or more instance inout/output ports with dynamic indexing. Dynamic
indexing is a non-synthesizable coding style. As a result, the checker creates oating signals
for all inout/outputs.
Example
In the following example, only one of the two-bit outputs out0 is dynamically selected by input
in2. See line 12 (in bold).
module SUB (in2, out3);
input in2;
output out3;
assign out3 = in2;
endmodule
input [1:0] in0;
input in1,in2;
output [1:0] out0;
reg [1:0] out0;
SUB inst1 (.in2(in0[in1]),.out3(out0[in2]));
endmodule
RTL9.2
Message
Design has irregularly used inout/output expression
Default Severity
Warning
Description
The design includes one or more irregularly used inout/output expressions.
Example
In the following example, inout port inout3 is tied to 0 logic value. See line 13 (in bold).
module SUB (in2, inout3);
input in2;
inout inout3;
wire inout3;
assign inout3 = in2;
endmodule
input [1:0] in0;
input in1,in2;
output [1:0] out0;
reg [1:0] out0;
SUB inst1 (.in2(in0[in1]),.inout3(1'b0));
endmodule
RTL9.3
Message
Supply0/supply1 is converted into a wire
Default Severity
Warning
Description
The supply0 or supply1 net is converted into a wire.
Example
In the following example, supply0 net in2 is converted to a wire.
module test (in, out);
input in;
output out;
supply0 in2;
assign out = in & in2;
endmodule
RTL9.4
Message
Supply0/supply1 net is not a module port
Default Severity
Warning
Description
The supply0 or supply1 net is not a module port.
Example
In the following example, supply0 net in2 is not a module port (see line 4):
module test (in, out);
input in;
output out;
supply0 in2;
assign out = in & in2;
endmodule
RTL9.5
Message
Power pin is converted to an input pin
Default Severity
Warning
Description
A power pin is converted to an input pin.
Example
In the following example, when running the following Conformal commands:
set power pin -input vss vdd
read des test.v -fix_power_pin
the vss and vdd pins are changed from inout to input pins.
input in;
output out;
inout vss, vdd; // changed to input pins
supply0 vss;
supply1 vdd;
assign out = !in;
endmodule
RTL9.7
Message
Cannot read value from OUT port
Default Severity
Error
Description
A feedback loop has been detected through the asynchronous set or resets of ip-op(s) and
the listed signals, wires, or expressions.
Example
In the following example, dout (line 5) is the outport. Attempting to read fromdout will cause
an error:
library ieee;
Entity dff is
port (clk: in std_logic;
reset: in std_logic;
din: in std_logic;
dout: out std_logic);
end dff;
Architecture behave of dff is
signal reset_cond: std_logic;
begin
reset_cond <= dout or reset; <b>
process (clk,din,reset_cond)
begin
if reset_cond = 1 then
dout <= 0;
elsif clkevent and clk = 1 then
dout <= din;
end if
end process;
end behave;
RTL9.8
Message
Set Liberty pin direction to output because it has an output function
Default Severity
Warning
Description
This rule check sets the pin direction from the Liberty library to an output because it has an
output function.
Example
In the following example, in line 9, the direction of pin Y is set to an output because it has an
output function:
library(test) {
cell (AND2X2) {
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(Y) {
function : "(A B)";
}
}
}
RTL9.9
Message
Extra ; is detected in port list
Default Severity
Warning
Description
This rule check indicates that there is an extra semi-colon (;) after the last port in the port list.
Example
In the following example, in line 3, there is an extra semi-colon (;) after bit:
entity e is
port(q : out bit;
d : in bit;);
end;
architecture a of e is+
begin
q <= d;
end;
RTL9.10
Message
Liberty cell does not use any input pin
Default Severity
Warning
Description
Indicates that the Liberty cell does not use any input pin.
Example
In the following example, in line 11, no input pin is used in the output function.
library(test) {
cell (AND2X2) {
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(Y) {
direction : output;
function: "(1)";
}
}
}
RTL9.11
Message
Liberty Master-Slave DFF cell clock phase does not match the timing table
Default Severity
Warning
Description
Indicates that the liberty cell is a master-slave ip op, but its clock phase does not match with
the timing table.
Example
In the following example, the master-slave ip-op is triggered by clocked_on_also :
!phi, but a timing_type of rising edge is used in pin q. This causes a phase mismatch.
cell (DFFDDRX8) {
...
pin (resetb) {
direction : input;
capacitance : 0.00563;
min_pulse_width_low : 0.33680;
}
pin (q) {
function : "IQ" ;
direction : output;
max_fanout : 7.8535;
timing() {
related_pin : "phi";
timing_type : rising_edge ;
...
}
}
ff (IQ,IQN) {
clocked_on : phi ;
clocked_on_also : !phi ;
clear : !resetb ;
next_state : "(!phi * dp) + (phi * dn)" ;
}
}
RTL9.12
Message
Liberty cell with internal_node does not have correct statetable
Default Severity
Warning
Description
Indicates that there is an internal_node in the liberty cell, but the corresponding statetable
is missing or a corresponding pin of the internal_node name is not found in the cell.
Example
In the correct liberty le, if the internal_node attribute exists, there should be a
corresponding statetable group as following:
statetable("in1", "ires"){
...
}
but there is no statetable in the cell in the following example:
cell(test){
pin (in1) {
direction: input;
}
pin (ires) {
direction: internal;
internal_node: "ires"
}
pin (out1) {
direction: output;
function: "in1 in2";
}
}
RTL9.13
Message
Set liberty cell to blackbox because some of its output pins have no function
Default Severity
Warning
Description
Indicates that some of the liberty cells output pin has no function attribute in it, but some
timing table exist in the output pin. Then the liberty cell is set to be a blackbox.
Example
In the following example, if line 3 is removed, the cell would be marked as a blackbox.
pin (out2) {
direction: output;
function: "!in1";
timing(){
...
}
}
RTL9.14
Message
Liberty cell has duplicate signal (pin/member)
Default Severity
Error
Description
Indicates that there are duplicated signals in a bundle declaration of the Liberty cell.
Example
In the following example, the bundle (z) has duplicated members z01:
cell(zhdp_mpt2) {
bundle(r) {
members(r0, r1);
direction : input;
fanout_load : 0.188;
min_pulse_width_high : 0.056;
}
bundle(z) {
members(z01, z01); /* ERROR: z01 is duplicated *
direction : inout;
}
} /* cell(zhdp_mpt2) */
RTL10
Message
Both posedge and negedge are used in different always/process
Default Severity
Warning
Description
Both the posedge and negedge of a clock are used in different always/process blocks.
Example
On line 5 of the following example, the design uses the posedge clock in an always block.
And on line 9, the design uses the negedge clock in another always block.
module SEN (clk,rst,in0,out0,out1);
input clk,rst,in0;
output out0,out1;
reg out0,out1;
begin
out0 <= in0;
end
always @ ( negedge clk )
begin
out1 <= !in0;
end
endmodule
RTL11
Message
Incomplete condition is in a function/procedure/task block
Default Severity
Warning
Description
The design includes one or more incomplete conditional statements within functions,
procedures, or task blocks.
Examples
I
In the following example, the if statement is missing its else branch. See line 8 (in
bold).
module TER (clk,rst,in0,out0);
input clk,rst,in0;
output out0;
wire out0;
assign out0 = func1 (in0,rst);
function func1;
input in0, rst;
if (rst)
func1 = in0;
endfunction
endmodule
I
Incomplete conditional statements might lead to false positive result under certain
circumstance and should be carefully examined.
In the following example, the variable parameter type output in the subprogrammight get
an ambiguous value because of the incomplete conditional statements. In this testcase,
nxt_state is associated with a variable parameter of mode OUT in procedure
next_state. Inside the procedure, when x = 3, there is no assignment to z. In this case,
nxt_state does not hold its original value of 3 after calling procedure next_state.
Instead, it gets a value 0 (in bold).
library ieee;
entity test is
procedure next_state(x: in integer range 0 to 3;
z: out integer range 0 to 3) is
begin
case x is
when 1 => z := 1;
when 2 => z := 2;
when others => NULL;
end case;
end next_state;
end test;
architecture rtl of test is
begin
process
variable cur_state: integer range 0 to 3;
variable nxt_state : integer range 0 to 3;
begin
cur_state := 3;
nxt_state := 3;
next_state(cur_state, nxt_state);
end process;
end rtl;
RTL12
Message
Referenced variable(s)/signal(s) are not in sensitivity list
Default Severity
Warning
Description
The design includes one or more variables or signals that are referenced but not included in
sensitivity lists.
Example
On line 7 of the following example, the design references variable in2, which is not included
in the sensitivity list on line 5.
module SEN (in0,in1,in2,out0);
input in0,in1,in2;
output out0;
reg out0;
always @ ( in0 or in1 )
begin
out0 = in0 | in1 | in2;
end
endmodule
RTL12.1
Message
Constant object is in sensitivity list
Default Severity
Warning
Description
There is a constant object in the sensitivity list.
Example
In the following example, val is a constant (see line 6):
module SEN (in0,out0);
input in0;
output out0;
parameter val = 1;
reg out0;
always @ ( in0 or val )
begin
out0 = in0 ;
end
endmodule
RTL13
Message
For loop condition is always false
Default Severity
Warning
Description
The design includes one or more for loops that will never hold true.
Example
On line 7 of the following example, the variable i is initialized with a value of 2 (i=2). Thus,
this for loop will never hold true, since i will never be less than a value of 1 (i<1).
module test(out,in);
output [3:0] out;
reg [3:0] out;
input [3:0] in;
integer i;
always begin
for (i=2; i<1; i=i+1) begin
out = i;
end
out = in;
end
endmodule
RTL13.1
Message
The FOR-LOOP index should not be assigned within the loop itself
Default Severity
Warning
Description
The FOR-LOOP index cannot be assigned within the loop.
Example
In the following example, i is the FOR-LOOP index and it is assigned within the loop (see line
8):
module top(input [1:0] in, output [4:0] out);
sum sum1(in,out);
endmodule
module sum(input [1:0] a, output [4:0]result);
integer i;
always begin
for (i=0; i<3; i=i+1) begin
i = a;
end
end
endmodule
RTL13.2
Message
The evaluation of for-loop condition is not constant
Default Severity
Warning
Description
The Conformal software detected a non-static loop. As per synthesis semantics, a loop in an
HDL design must be statically unrollablethat is, the number of loop iterations should be
statically known.
Example
In the following example, N is not a constant (see line 9):
module neg_NSLOOP (a, b, c);
input [1000:0] a, b;
output [1000:0] c;
reg [1000:0] c;
integer N;
always @(a or b)
begin: P
integer I;
for (I = 0; I < N; I = I + 1)
c[I] = a[I] & b[I];
end
endmodule
RTL14
Message
Signal with fanin drive and no fanout load is detected
Default Severity
Warning
Description
The checker has removed one or more oating signals. This situation occurs when the output
of a logic cone has no fan-out loads. In other words, the signal is driven by a gate or input port
(has drives), but its output does not drive any gate or output port (has no loads).
Example
On line 5 of the following example, flt does not have any fan-out loads, so the checker
issues the RTL14 warning.
input aa, bb;
output o1, o2;
wire flt;
assign flt = aa != bb;
endmodule
RTL14.1
Message
Fanout load of the signal is removed
Default Severity
Warning
Description
Indicates that the fanout load of a signal is removed, and therefore the signal becomes a
oating signal, which is also removed.
Example
In the following example, bb (on line 5) has fanout load at line 4, but this fanout is removed
because aa has RTL14 violation. The RTL14.1 rule checker reports that the fanout load of bb
is removed, and therefore bb becomes a oating signal, which is also removed.
module test(oo);
output oo;
wire aa, bb, cc;
assign aa = !bb; // RTL14 rule violation
assign bb = !cc;
// RTL14.1 rule violation
endmodule
RTL15
Message
Clock and asynchronous set/reset expression must be one bit wide
Default Severity
Error
Description
A clock variable or an asynchronous set/reset variable in the sensitivity list is more than one-
bit wide.
Example
On line 1 of the following example, myReset is declared as a two-bit wide. On line 2, an
RTL15 error is reported because myReSet is not a single-bit and it is used as an
asynchrounous set/reset variable on the sensitivity list.
reg [1:0] myReset; // myReset is two-bit wide
always @(posedge clk or posedge myReset) begin
...
end
RTL15.1
Message
Else branch of event controlled if statement is not supported
Default Severity
Warning
Description
For modeling a ip-op with asynchronous forces, the clock edge should be the fullling
condition of the last conditional block. In addition, there should be assignment to output under
only one clock edge. Both edges of clock signal are used in a sequential process.
Example
In the following example, both HIGH and LOW edges of the signal clk are used in a sequential
process (see lines 19 and 21, respectively):
library ieee;
use ieee.numeric_std.all;
entity ClockEdge is
port (sort : out unsigned (3 downto 0);
clk : in std_logic;
rst : in std_logic;
ena1 : in unsigned (3 downto 0));
end ClockEdge;
architecture rtl_clkedge of ClockEdge is
constant ZERO : unsigned(3 downto 0) := "0000";
constant HIGH : std_logic := 1;
constant LOW : std_logic := 0;
begin
p0_OK:process (clk,rst)
begin
if (rst =HIGH) then
sort <= ZERO;
elsif ( clkevent and clk=HIGH) then
sort <= ena1;
elsif ( clkevent and clk=LOW) then
sort <= ena1 + ena1;
end if;
end process p0_OK;
end rtl_clkedge;
RTL15.2
Message
Sensitivity/clock style is unsupported
Default Severity
Warning
Description
The always block is sensitive to both the edges and levels of some signals. Synthesis tools
do not support both level and edge sensitive nodes in the sensitivity list.
Example
In the following example, line 5 has both level and edge sensitivity nodes:
module mult_clks_in_always2 (clk, q, d, rst1, rst2);
input clk, d, rst1, rst2;
output q;
reg q;
always @(clk or posedge rst1)
begin
if (rst2)
q <= d;
end
endmodule
RTL16.1
Message
Non-local variable is read in a function body
Default Severity
Warning
Description
A non-local variable is read in a function body.
Example
On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7,
an RTL16.1 warning is reported because glob_1 is read inside the function body. RTL16.1
warns potential mismatch between synthesis and simulation semantics.
reg glob_1; // glob_1 is declared outside of function f1
...
function f1 ...
reg local_1;
begin
...
local_1 = glob_1; // RTL16.1: glob_1 is read inside the function body
...
end
RTL16.2
Message
Non-local variable is assigned in a function body
Default Severity
Warning
Description
A non-local variable is assigned in a function body.
Example
On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7,
an RTL16.2 warning is reported because glob_1 is assigned inside the function body.
RTL16.2 warns about the function body contains a side effect due to this external variable
assignment.
reg glob_1; // glob_1 is declared outside of function f1
...
function f1 ...
reg local_1;
...
begin
...
glob_1 = local_1; // RTL16.2: glob_1 is assigned inside the function body
...
end
RTL17
Message
Variable size exceeds the maximum limit
Default Severity
Error
Description
The variable size exceeds the maximum limit.
Example
In the following example, the variable tmp size exceeds the limit of 8192*8192 (see line 3)
module test (out);
output [31:0] out;
wire [8192*8192:0] tmp;
assign out = tmp[31:0];
endmodule
RTL17.1
Message
Expression size exceeds the maximum limit
Default Severity
Error
Description
The expression size exceeds the maximum limit.
Example
The following example triggers the RTL17.1 message because the expression size exceeds
limit 67108864. The objects maximum bit size of 67108864 is predened by all Conformal
tools.
module test(output r1);
wire [67108864:0] r1; // ERROR: RTL17.1 violation
assign r1 = 0;
endmodule
RTL18.1
Message
Package is not an IEEE standard
Default Severity
Ignore
Description
The IEEE package is not a standard package.
Example
In the following example, std_logic_arith is not a standard IEEE package (see line 2):
library ieee;
use ieee.std_logic_arith.all;
entity test is
port (out1 : out signed (1 downto 0);
in1 : in signed (1 downto 0);
in2 : in signed (1 downto 0));
end test;
architecture rtl of test is
begin
p1:process( in1,in2)
begin
out1 <= in1 + conv_integer(in2);
end process p1;
end rtl;
RTL18.2
Message
Function definition has empty body
Default Severity
Warning
Description
The function denition has empty body.
Example
In the following example, the function byte_reversal in line 10 is an empty function:
library ieee;
entity func is
port(
data:in std_logic_vector(8 downto 0);
rev_data:out std_logic_vector(8 downto 0)
);
end func;
architecture func of func is
function byte_reversal (arg:std_logic_vector)
return std_logic_vector is
begin
end byte_reversal;
begin
process
begin
rev_data <= byte_reversal(data);
end process;
end func;
RTL18.3
Message
Function call does not refer to a function definition
Default Severity
Error
Description
The function call does not refer to a function denition.
Example
In the following example, the function func in line 6 is not dened:
module test(in,out);
input in;
output out;
reg out;
always @(in)
out = func(in);
endmodule
RTL18.4
Message
Ignoring resolution function. This might cause mismatches between simulation and
synthesis
Default Severity
Warning
Description
The resolved function dened in package IEEE STD_LOGIC_1164 is the only supported
resolution function. Other resolution functions are ignored.
Example
In the following example, resolution function RESOLVE_VOLTAGE is ignored:
...
function RESOLVE_VOLTAGE ( V: UVOLTAGE_VECTOR ) return UVOLTAGE;
subtype VOLTAGE is RESOLVE_VOLTAGE UVOLTAGE;
RTL19.1
Message
Identifier is a reserved keyword and might conflict in designs with mixed languages
Default Severity
Warning
Description
The identier is a reserved keyword for Verilog or VHDL.
Example
In the following example, logic is a System Verilog keyword (see line 2):
module test (input din, output logic);
assign logic = din;
endmodule ;
RTL20.1
Message
Pre-defined attribute is not supported
Default Severity
Warning
Description
The specied pre-dened attribute in the design is not supported. Remodel the design to
avoid this error.
Example
In the following example, the last_attribute in line 21 is not supported:
library IEEE;
entity lat is
port ( din: in bit;
clk :in bit;
din1 : in bit_vector(1 downto 0);
dout : out bit_vector(2 downto 0);
dout1 : out bit_vector(1 downto 0));
end lat;
architecture behave of lat is
signal clk1 : bit;
component lat_bit is
port ( d: in bit;
clk :in bit;
q : out bit);
end component;
begin
dout(0) <= din;
process(clk1,din)
begin
if clk1last_value = 0 and clk1 = 1 then
dout(2 downto 1) <= din1;
end if;
end process;
I1 : lat_bit port map(din, clk, dout1(1));
I0 : lat_bit port map(din, clk, dout1(0));
end behave;
RTL20.2
Message
Function is not supported
Default Severity
Warning
Description
The referenced function is not supported (1bx will be returned).
Example
In the following example, the sqrt function (line 10) is not supported:
library ieee;
use ieee.math_real.all;
ENTITY test_constant_reals IS
PORT (
sample_out : OUT integer );
END test_constant_reals;
ARCHITECTURE rtl OF test_constant_reals IS
BEGIN
sample_out <= integer(sqrt(1.375));
END rtl;
RTL20.3
Message
Could not find configuration
Default Severity
Warning
Description
The refered conguration could not be found.
Example
In the following example, if the conguration bug2_cfg is not dened before conguration
bug_cfg, this message will be issued.
...
configuration bug_cfg of bug is
...
use configuration work.bug2_cfg
...
SPICE Netlist Format
This category of rules applies to SPICE netlists used for Conformal Custom. The following
table lists the SPICE (SPI) rule numbers and their messages.
Rule Number Message
SPI1.1 Diode instance is ignored
SPI1.2 Incorrect diode instance is ignored
SPI1.3 SPICE element/card is ignored
SPI1.4 Subckt name duplicated and previous ones are ignored
SPI3.2 Model redened. Using last denition and ignoring earlier ones
SPI4.1 .GLOBAL statement for pin is redened. Previous denition is
ignored
SPI4.2 .GLOBAL statement for pin with type C is not supported and is
ignored
SPI5.1 Implicit bulk VDD Net reset to GND due to .GLOBAL declaration
SPI5.2 Implicit bulk GND Net reset to VDD due to .GLOBAL declaration
SPI7.1 Duplicated pin in subckt. Creating new pin
SPI7.2 Duplicate pin of subckt with different pin connections in instance
SPI8.1 Undened Pin in *.PININFO is ignored
SPI1.1
Message
Diode instance is ignored
Default Severity
Warning
Description
The checker is ignoring one or more diode instances in the SPICE netlist.
Example
The checker reports the following:
SPI1.1: Ignoring diode instance
Type: Golden design Severity: Warning Occurrence: 1
1: ant/D1
on line 3 in file 'test.sp'
That is, the checker ignores a diode instance called D1 in the SPICE netlist.
.SUBCKT ant y
D1 y vss
.ENDS
SPI1.2
Message
Incorrect diode instance is ignored
Default Severity
Warning
Description
The checker is ignoring one or more incorrectly instantiated diode instances in the SPICE
netlist.
The checker ignores diodes in all cases. See SPI1.1 on page 721.
Example
In the following example, the checker generates the SPI1.2 message for line 3 (in bold)
because D should be followed by some alphanumeric characters. (Also, since the checker
ignores all diodes, line 2 triggers the SPI1.1 message.)
.subckt foo a b
D1 a b
D a b
.ends
SPI1.3
Message
SPICE element/card is ignored
Default Severity
Warning
Description
The SPICE element or card is ignored.
SPI1.4
Message
Subckt name duplicated and previous ones are ignored
Description
The checker encountered a subcircuit name that was already used in the SPICEnetlist. When
this duplication happens, the checker retains the last denition encountered and ignores
earlier ones.
SPI3.2
Message
Model redefined. Using last definition and ignoring earlier ones
Default Severity
Warning
Description
The checker encountered a redened model in the SPICE netlist. When this redenition
occurs, the checker uses the last denition encountered and ignores earlier ones.
Example
In the following SPICE netlist example, P1 is dened as PMOS and redened as NMOS. In this
case, the checker recognizes NMOS as the denition for P1.
.model P1 PMOS
.model P1 NMOS
SPI4.1
Message
.GLOBAL statement for pin is redefined. Previous definition is ignored
Default Severity
Warning
Description
The checker encountered a redened .GLOBAL statement in the SPICE netlist. When this
redenition occurs, the checker uses the last denition encountered and ignores earlier ones.
Example
In the following SPICE netlist example, pin pr is dened as power and redened as ground.
In this case, the checker recognizes ground as the denition for pin pr.
.global pr:P
.global pr:G
SPI4.2
Message
.GLOBAL statement for pin with type C is not supported and is ignored
Default Severity
Warning
Description
The checker encountered a .GLOBAL statement with pin type C in the SPICE netlist. When
this occurs, the checker ignores that pin type.
Example
In the following SPICE netlist example, pin type C of the global net a will be ignored:
.global vdd:P a:C;
SPI5.1
Message
Implicit bulk VDD Net reset to GND due to .GLOBAL declaration
Default Severity
Warning
Description
The SPICE netlist includes a .global declaration that overrides an implicit VDD assignment.
By default, the checker assumes that the bulk node of PMOS is VDD. The net connected to the
bulk node is thus implicitly assigned as VDD. However, if there is a .global declaration for a
PMOS net, the global declaration takes precedence over the implicit assignment.
Example
In the following example, net a retains its denition as assigned by the .global statement
on line 1 (in bold). The checker ignores the implicit meaning of this net based on the bulk
connection (see line 5). Also refer to SPI5.2
on page 729
.
.global a:G
.global b:P
.subckt inv aa bb out
M1 aa bb VDD a PMOS
M2 aa bb VSS b NMOS
.ends
SPI5.2
Message
Implicit bulk GND Net reset to VDD due to .GLOBAL declaration
Default Severity
Warning
Description
The SPICE netlist includes a .global declaration that overrides an implicit GND assignment.
By default, the checker assumes that the bulk node of NMOS is GND. The net connected to the
bulk node is thus implicitly assigned as GND. However, if there is a .global declaration for
an NMOS net, the global declaration takes precedence over the implicit assignment.
Example
In the following example, net b retains its denition as assigned by the .global statement
on line 2 (in bold). The checker ignores the implicit meaning of this net based on the bulk
connection (see line 6). Also refer to SPI5.1
on page 728
.
.global a:G
.global b:P
.subckt inv aa bb out
M1 aa bb VDD a PMOS
M2 aa bb VSS b NMOS
.ends
SPI7.1
Message
Duplicated pin in subckt. Creating new pin
Default Severity
Warning
Description
The checker encountered a duplicate pin name in the subckt denition while reading a SPICE
netlist. When this duplication occurs, the checker creates a new name for the second pin with
the following format: <duplicate_pin_name>_vplx_redundant_<number>.
Example
In the following SPICE netlist example, pin a is dened on line 2 (in bold) and repeated in the
subckt denition on line 3 (in bold). The checker creates a new pin for the second a it
encountered. The new pin is named a_vplx_redundant_0.
.subckt inv a b a out
M1 a b VDD VDD PMOS
M2 a b VSS VSS NMOS
.ends
SPI7.2
Message
Duplicate pin of subckt with different pin connections in instance
Default Severity
Warning
Description
The checker is detecting an instance with duplicated pins in the SPICE netlist:
Example
In the following SPICE netlist example, the second pin of instance x1 of subckt inv is
redundant and will be ignored:
.global vdd gnd;
.subckt inv in in;
m1 vdd in out vdd p;
m2 out in gnd gnd n;
.ends inv;
.subckt top o i;
x1 o i inv;
.ends top;
SPI8.1
Message
Undefined Pin in *.PININFO is ignored
Default Severity
Warning
Description
A SPICE *.PININFO statement includes an undened pin. *.PININFO can be used to
dene pins as input (I), output (O) or bidirectional (B). If I, O or B is missing for the pin dened
in a PININFO statement, the checker ignores the undened pin and issues a warning.
Example
In the following PININFO example, pin a is dened as I. However, on line 2 (in bold) the
denition for pin b is missing. When the checker encounters line 2, it generates the SPI8.1
message.
*.pininfo a:I
*.pininfo b:
System Verilog
This category of rules applies to SystemVerilog designs. The following table lists the System
Verilog (SV) rule numbers and messages.
Rule Number Message
SV1.1 covergroup usage is unsupported and ignored
SV1.2 assert property is unsupported and ignored
SV1.3 assume property is unsupported and ignored
SV1.4 cover property is unsupported and ignored
SV1.5 void type is not allowed in object declaration
SV1.6 Missing argument list for function call
SV1.7 Unbounded range parameter $ is not supported
SV1.8 Procedural assertion is unsupported and ignored
SV1.9 distribution weight is unsupported and ignored
SV1.10 Sequence operation is unsupported and ignored
SV1.11 Sequence concatenation is unsupported and ignored
SV1.12 number_of_ticks is not a constant value
SV1.13 number_of_ticks must be 1 or greater
SV1.14 Sequence method is unsupported and ignored
SV1.15 Recursive properties are unsupported and ignored
SV2.1 Packed type cannot contain real/shortreal/unpacked type
SV2.2 All elements must have same size in a packed union type
SV3.1 Modules can neither be declared nor instantiated in interfaces
SV1.1
Message
covergroup usage is unsupported and ignored
Default Severity
Warning
Description
The covergroup usage is not supported and is ignored.
Example
In the following example, g2 (line 2) is unsupported:
module test( input logic [7:0] in1, reg clk, output logic [7:0] out1);
covergroup g2 @(posedge clk);
endgroup
always@( posedge clk)
begin
out1 = in1;
end
endmodule
SV1.2
Message
assert property is unsupported and ignored
Default Severity
Warning
Description
The assert property is not supported and is ignored.
Example
In the following example, assert property p1 (line 3) is ignored
module prop1 (input clk,output logic [7:0] count1);
logic [7:0] counter1 = 0;
assert property (p1) count1 = counter1;
endmodule
SV1.3
Message
assume property is unsupported and ignored
Default Severity
Warning
Description
The assume property is not supported and is ignored.
Example
In the following example, assume property p1 is ignored:
assume property (p1) count1 = counter1;
endmodule
SV1.4
Message
cover property is unsupported and ignored
Default Severity
Warning
Description
The cover property is not supported and is ignored.
Example
In the following example, cover property p1 is ignored:
cover property (p1) count1 = counter1; <b>
endmodule
SV1.5
Message
void type is not allowed in object declaration
Default Severity
Error
Description
The void type is not allowed in the object declaration.
Example
In the following example, it is illegal to declare a void type variable for var1:
void var1;
SV1.6
Message
Missing argument list for function call
Default Severity
Error
Description
Indicates that the function call does not have an argument list.
Example
In the following example, in line 11, the argument list is missing:
input in;
output out;
function func;
input din;
begin
func = din;
end
endfunction
always @(in)
out = func;
endmodule
SV1.7
Message
Unbounded range parameter $ is not supported
Default Severity
Error
Description
Indicates that the unbounded range parameter
$
is not supported. This is for SystemVerilog
only.
Example
In the following example, in line 6, $ is used as parameter.
module test #(parameter p1 = 1)(input int i, output int out);
always @(i)
out = i+p1;
endmodule
module top(input int in, output int dout);
test #($) sub(in,dout);
endmodule
SV1.8
Message
Procedural assertion is unsupported and ignored
Default Severity
Warning
Description
Indicates that the procedural assertion is unsupported and is ignored. This is for System
Verilog only.
Example
In the following example, the procedural assertion in line 3 is unsupported and ignored.
module test (input logic clk,input logic in);
if (in == 1) assert (req1 || req2);
else begin
$error("assert failed" );
end
endmodule
SV1.9
Message
distribution weight is unsupported and ignored
Default Severity
Warning
Description
The usage of distribution weight is described in SystemVerilog LRM 13.4.4 Distribution.
The usage of distribution weight is unsupported and is ignored by all Conformal software
tools.
Example
In the following example, x is equal to 100, 200, or 300 with weighted ratio of 1-2-5. The
usage of the distribution weight will trigger this warning.
x dist {100 := 1, 200 := 2, 300 := 5}
SV1.10
Message
Sequence operation is unsupported and ignored
Default Severity
Warning
Description
The usage of sequence is described in SystemVerilog LRM 17.5 Sequences.
The usage of sequence is unsupported and is ignored by all Conformal software tools.
Example
In the following example, the usage of sequence operation (first_match in line 5) will
trigger this warning.
sequence t1;
te1 ## [2:5] te2;
endsequence
sequence ts1;
first_match(te1 ## [2:5] te2);
endsequence
SV1.11
Message
Sequence concatenation is unsupported and ignored
Default Severity
Warning
Description
The usage of sequence is described in SystemVerilog LRM 17.5 Sequences.
The usage of sequence is unsupported and is ignored by all Conformal software tools.
Example
In the following example, using cycle delay ##1 will trigger this warning.
@(posedge clk0) sig0 ##1 @(posedge clk1) sig1
SV1.12
Message
number_of_ticks is not a constant value
Default Severity
Error
Description
The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is:
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])
where the number_of_ticks must be 1 or greater. If number_of_ticks is not specied,
it defaults to 1. The SV1.12 error is reported if number_of_ticks is not evaluated to be a
constant value.
Example
The following example will trigger this error if input_port_N is not a constant expression:
$past( bet1, input_port_N)
SV1.13
Message
number_of_ticks must be 1 or greater
Default Severity
Error
Description
The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is:
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])
where number_of_ticks must be 1 or greater. If number_of_ticks is not specied, then it
defaults to 1. The SV1.13 error is reported if number_of_ticks is not evaluated to be 1 or
greater.
Example
The following example will trigger this error because -1 is not 1 or greater than 1:
$past( bet1, -1)
SV1.14
Message
Sequence method is unsupported and ignored
Default Severity
Warning
Description
The sequence usage is described in SystemVerilog LRM 17.5 Sequences.
The sequence methods are described in SystemVerilog LRM 17.12.6.
The SV1.14 warning is reported if sequence methods are used.
Example
The following example will trigger this warning because an ended method is used (line 5):
sequence e1;
@(posedge sysclk) $rose(ready) ##1 proc1 ##1 proc2 ;
endsequence
sequence rule;
@(posedge sysclk) reset ##1 inst ##1 e1.ended ##1 branch_back;
endsequence
SV1.15
Message
Recursive properties are unsupported and ignored
Default Severity
Warning
Description
The sequence usage is described in SystemVerilog LRM 17.11.4 Recursive property.
The SV1.15 warning is reported if recursive properties are used.
Example
I The following example shows a simple recursive property case, where a property
instantiation prop_always is inside the prop_always property declaration. This
causes a recursive property problem.
property prop_always(p);
p and (1b1 |=> prop_always(p));
endproperty
I The following example shows a mutually recursive case, where in property declaration
check_phase1, there is an instantiation check_phase2, and in property declaration
check_phase2, there is an instantiation check_phase1. This causes a mutually
recursive property problem.
property check_phase1;
s1 |-> (phase1_prop and (1b1 |=> check_phase2));
endproperty
property check_phase2;
s2 |-> (phase2_prop and (1b1 |=> check_phase1));
endproperty
SV2.1
Message
Packed type cannot contain real/shortreal/unpacked type
Default Severity
Error
Description
Noninteger data types, such as real and shortreal, are not allowed in packed structures or
unions. Neither are unpacked arrays.
Example
In the following packed struct type example, the errors are shown by comments:
typedef struct packed {
bit [3:0] GFC;
+real VPI; // real type is not allowed in a packed structure
bit PT [3:0] ; // unpacked type is not allowed a packed structure
bit [7:0] HEC;
} myPackedType;
SV2.2
Message
All elements must have same size in a packed union type
Default Severity
Error
Description
A packed union shall contain members that must be packed structures, or packed arrays or
integer data types all of the same size (in contrast to an unpacked union, where the members
can be different sizes). This ensures that a union member that was written as another
member can be read back.
Example
In the following packed union type example, the errors are shown by comments:
typedef union packed {
bit [7:0] v1;
bit [3:0][1:0] v2;
bit [8:0] v3; // ERROR: v3 has 9 bits, but both v1 and v2 have 8 bits
} badPkUnionType;
SV3.1
Message
Modules can neither be declared nor instantiated in interfaces
Default Severity
Error
Description
Interfaces can be declared and instantiated in modules (either at or hierarchical), but
modules can neither be declared nor instantiated in interfaces.
Example
In the following example, the module instantiation is not allowed in the interface declaration:
module mod1 (input aa, bb; output zz);
assign zz = aa && bb;
endmodule
interface simple_bus; // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
mod1 u0(req, gnt, rdy); // ERROR: SV3.1 violation.
endinterface: simple_bus
User-Dened Primitive
This category of rules applies to designs that include user-dened primitives. The following
table lists the User-Dened Primitive (UDP) rule numbers and their messages.
Rule Number Message
UDP1.1 Swapped set and reset of DFF/DLAT
UDP1.2 Removed set-domination logic of DFF/DLAT
UDP1.3 Unknown set and reset domination. Implemented as reset
domination
UDP2.1 Inverter on data input of DFF/DLAT is moved to output
UDP2.2 Inverter on data input of DFF/DLAT is not moved to output
UDP3 Merged redundant user-dened DFF/DLAT primitive(s)
UDP3.1 Conicting entries are detected in the outputs
UDP3.2 Primitive has unspecied term(s)
UDP4.1 Primitive contains illegal symbol z
UDP4.2 Primitive contains an x output without an x input
UDP1.1
Message
Swapped set and reset of DFF/DLAT
Default Severity
Note
Description
The checker swapped a set and reset for a user-dened DFF or DLAT primitive. Automatic
swapping of DFF and DLAT set and reset occurs only when there is a need to accommodate
a conversion (for example, merging DFFs).
Example
Two warnings occurred for the following example:
1.
On lines 5 through 8 (in bold), instance U1 is merged into instance U2 because they have
the same connection (except q and qb for outputs).
2.
The checker swaps set and reset of instance U2 to accommodate merging instance U1.
module RSLTA (Q,QB,S,R,notifier);
input S,R;
output Q,QB;
input notifier;
rsltaq U1(.q(Q),.s(S),.r(R),
.notify(notifier));
rsltaqb U2(.qb(QB),.s(S),.r(R),
.notify(notifier));
endmodule
UDP1.2
Message
Removed set-domination logic of DFF/DLAT
Default Severity
Note
Description
One or more user-dened DFF or DLAT primitives have multiple sets of set-dominant logic.
The checker removed the redundant set of set-dominant logic.
Example
On line 11 of the following example, the design includes an ORlogic to ensure a set-dominant
DFF, but the DESFQ primitive was already dened in line 1 as a set-dominant DFF. Thus, the
design includes two set-dominant logics (shown in lines 1 and 11).
primitive DESFQ = a set-dominant DFF
module test ( N01, H01, H02, H03, H04);
input H01;
input H02;
input H03;
input H04;
output N01;
not ( _G005, H03 );
not ( _G002, H04 );
or ( N01, _G008, H04 );
DESFQ ( .Q(_G008), .D(H01), .CP(H02),
.RB(_G005), .SB(_G002), .notifier(notifier) );
endmodule
UDP1.3
Message
Unknown set and reset domination. Implemented as reset domination
Default Severity
Warning
Description
A UDP is interpreted as a sequential DLAT or DFF logic, and:
I
DLAT or DFF has both asynchronous set and reset logic
I
set and reset logic might result in 1 at the same time
I
no domination on set or reset
Example
primitive srq0 ( Q, S, RX );
output Q; reg Q;
input S;
input RX;
table
S RX : Q- : Q+
1 1 : ? : 1 ;
0 0 : ? : 0 ;
? 1 : 1 : 1 ;
0 ? : 0 : 0 ;
0 1 : ? : - ;
endtable
endprimitive
The Conformal software will generate a DLAT circuit with asynchronous set and reset:
I set = S
I reset = RX
I d = 0
I clock = 0
The UDP does not specify the behavior when S = 1 and RX = 0. The Conformal software
implements the circuit as a reset dominated logic, which implies that when S = 1 and RX = 0,
Q = 0. This is usually caused by UDP table incompletion.
UDP2.1
Message
Inverter on data input of DFF/DLAT is moved to output
Default Severity
Warning
Description
One or more user-dened DFF or DLAT primitives (UDP) include an inverter on the data port.
By default, the checker relocates inverters from data port to output port.
Example
In the following example, primitive dff_simple has an inverter at the data port of the DFF,
but the checker moves it to the output port of the DFF.
primitive dff_simple(Q, S, R, CK, D);
output Q;
input S, R, CK, D;
reg Q;
table
1 0 ? ? : ? : 1;
? 1 ? ? : ? : 0;
0 0 r 0 : ? : 1;
0 0 r 1 : ? : 0;
0 0 (?0) ? : ? : -;
endtable
endprimitive
UDP2.2
Message
Inverter on data input of DFF/DLAT is not moved to output
Default Severity
Warning
Description
One or more user-dened DFF or DLAT primitives (UDP) include an inverter on the data port.
By default, the checker relocates inverters fromdata port to output port. However, in this case,
you specied that the checker will not move the DFF or DLAT when you used the following
command:
add udp model dff_simple -nomove_inverter
Example
In this example, primitive dff_simple has an inverter at the data port of the DFF, but the
checker did not move it since the user applied the -nomove_inverter option.
primitive dff_simple(Q, S, R, CK, D);
output Q;
input S, R, CK, D;
reg Q;
table
1 0 ? ? : ? : 1;
? 1 ? ? : ? : 0;
0 0 r 0 : ? : 1;
0 0 r 1 : ? : 0;
0 0 (?0) ? : ? : -;
endtable
endprimitive
Input:
SETUP>add udp model dff_simple -nomove_inverter
SETUP>read design test.v -verilog
UDP3
Message
Merged redundant user-defined DFF/DLAT primitive(s)
Default Severity
Note
Description
The design includes one or more redundant user-dened DFF or DLAT primitives. The
checker merges all redundant user-dened DFF and DLAT primitives.
Example
In the following example, DFF UDP_A is redundant and merged into DFF UDP_B. See lines 7
through 10 (in bold).
module test ( N01, N02, H01, H02, notifier );
input H01;
input H02;
input notifier;
output N01;
output N02;
DESFQ UDP_A(.Q(N01), .D(H01), .CP(H02), .RB(1'b1),
.SB(1'b1), .notifier(notifier));
DESFQ UDP_B(.Q(N02), .D(H01), .CP(H02),
.RB(1'b1), .SB(1'b1), .notifier(notifier));
endmodule
UDP3.1
Message
Conflicting entries are detected in the outputs
Default Severity
Warning
Description
There are conict entries in the user-dened primitive outputs.
Example
In the following example, the two lines have the same input values but different output values:
// D CK RB SB FLAG : Qt : Qt+1
? ? 0 0 ? : ? : 1;//
? ? 0 0 ? : ? : 0;//
UDP3.2
Message
Primitive has unspecified term(s)
Default Severity
Warning
Description
There are unspecied term(s) in the UDP table.
Example
In the following example, term 010 and 011 is unspecied:
primitive udp_inv_clr0 (qn, clr, pre, inp);
output qn;
input clr, pre, inp;
table
// clr pre inp : qn
0 0 ? : 0;
1 ? 0 : 1;
1 ? 1 : 0;
// ? 1 0 : 1;
// ? 1 1 : 0;
x x 1 : 0;
x x 0 : 1;
endtable
endprimitive
UDP4.1
Message
Primitive contains illegal symbol z
Default Severity
Warning
Description
The UDP contains an entry that has illegal symbol z.
Example
In the following example, because the entry in line 11 has symbol z, mydff will be
blackboxed:
primitive mydff (qq, clk, dd, ss, rr);
output qq; reg qq;
input clk, dd, ss, rr;
table
// clk dd ss rr : qq : qq+
r 0 0 0 : ? : 0 ;
r 1 0 0 : ? : 1 ;
f ? 0 0 : ? : - ;
? ? 1 0 : ? : 1 ;
? ? 0 1 : ? : 0 ;
? ? 1 1 : ? : z ;
endtable
endprimitive
UDP4.2
Message
Primitive contains an x output without an x input
Default Severity
Warning
Description
The UDP contains an entry that has an x value output without an x value input.
Example
In the following example, the last line of the table has x as an output, and its input does not
contain x:
primitive mydff (qq, clk, dd, ss, rr);
output qq; reg qq;
input clk, dd, ss, rr;
table
// clk dd ss rr : qq : qq+
r 0 0 0 : ? : 0 ;
r 1 0 0 : ? : 1 ;
f ? 0 0 : ? : - ;
? ? 1 0 : ? : 1 ;
? ? 0 1 : ? : 0 ;
? ? 1 1 : ? : x ;
endtable
endprimitive
Verilog
This category of rules applies to designs that are written in Verilog language. RTL rules apply
to Verilog designs and VHDL designs (see Register Transfer Level
on page 603
).
The following table lists the Verilog (VLG) rule numbers and their messages.
Rule Number Message
VLG1.1 Case inequality operators are treated as logical inequality
operators
VLG1.2 Case equality operators are treated as logical equality operators
VLG1.3 Wild inequality is treated as inequality
VLG1.4 Wild equality is treated as equality
VLG2.1 Non-constant case-item is used in casex/casez statement
VLG2.2 Non-binary case-item is used in casex/casez statement
VLG2.3 default keyword is not the last item in case statement(s)
VLG3.1 Unsized constant(s) with leading X/Z value is extended beyond
32 bits
VLG3.2 Verilog event expression in always block(s) are complex
VLG3.3 Replication is not a constant or it contains X or Z values
VLG3.4 Zero replication is treated as NULL in concatenation
VLG3.5 Null expression is not allowed (caused by zero replication)
VLG3.6 Negative replication is not allowed
VLG3.7 Unsized constant value is set to 32-bit in concatenation
VLG4.1 Wire type wand is used
VLG4.2 Wire type wor is used
VLG4.3 Implicit declared net is generated
VLG4.4 Cutpoint not found
VLG5.1 Primitive output port has multiple bits. Ignored all but LSB bit
VLG5.2 Primitive input port has multiple bits. Ignored all but LSB bit
VLG5.3 Wire and port size declaration(s) do not match
VLG5.4 Port size of array instance does not match
VLG5.5 Named port association ignored for primitive gate
VLG5.6 Named port association is ignored for primitive gate
VLG6.1 Globally referenced variable is unresolved
VLG6.2 Globally referenced variable resolved
VLG6.3 Unsupported system function call (converted to 1'b1)
VLG6.3a Unsupported system task call
VLG6.4 Supported system datapath function call
VLG6.5 Time literal is unsupported
VLG6.6 Event object is unsupported
VLG6.7 Hierarchical function call is not supported (blackboxed)
VLG6.8 Specify block is ignored
VLG6.10 Intra-assignment event specication is not supported
VLG6.12 fork-join constructs are not supported
VLG6.13 force-release constructs are not supported
VLG6.14 Global reference on the left side of the assignment is not
supported
VLG6.15 disable construct is not supported
VLG6.16 wait construct is not supported
VLG7 Nets renamed after removing backslash
VLG8 Buffer inserted
VLG9 Names conict with previous declarations
VLG9.1 Text macro is redened
VLG9.2 dene macro is used
VLG9.4 Instance name conicts with previous declarations
VLG10 Non-blocking assignment is in disabled block
VLG10.1 Non-blocking assignment encountered in function
Rule Number Message
VLG10.2 deassign statements cannot be synthesized and are not
supported
VLG10.3 Sequential assign statement is not supported
VLG11.1 Combinational logic is inferred in an always_latch block
VLG11.2 Latches are inferred in an always_comb block
VLG12.1 Null statement ; is not allowed inside a begin-end block and is
ignored
VLG13.1 Unpacked dimension is not allowed
VLG13.2 Unsized dimension is not allowed
VLG13.3 Associative dimension is not allowed
VLG14.1 Missing module instance name
VLG15.1 Block name is previously declared
VLG16.1 Syntax error in Verilog instantiation
Rule Number Message
VLG1.1
Message
Case inequality operators are treated as logical inequality operators
Default Severity
Warning
Description
The design includes one or more case inequality operators that the checker treats as logical
inequality operators.
Inequality operators syntax:
!== is a case inequality operator.
!= is a logical inequality operator.
Example
In the following example, the checker treats the case inequality operator as a logical inequality
operator. See line 7 (in bold).
module VLGT (clk,cond,in0,in1,out0);
input clk,in0,in1;
input [1:0] cond;
output out0;
reg out0;
if (cond[0] !== cond[1])
out0 <= in0;
else
out0 <= in1;
end
endmodule
VLG1.2
Message
Case equality operators are treated as logical equality operators
Default Severity
Warning
Description
The design includes one or more case equality operators that the checker treats as logical
equality operators.
Equality operators syntax:
=== is a case equality operator.
== is a logical equality operator.
Example
In the following example, the checker treats the case equality operator as a logical equality
operator. See line 7 (in bold).
module VLGT (clk,cond,in0,in1,out0);
input clk,in0,in1;
input [1:0] cond;
output out0;
reg out0;
if (cond[0] === cond[1])
out0 <= in0;
else
out0 <= in1;
end
endmodule
VLG1.3
Message
Wild inequality is treated as inequality
Default Severity
Warning
Description
The checker does not support the !?= SystemVerilog operator with the exact semantics
supported in simulation. The checker treats !?= as !=.
Example
In the following example, the checker encounters !?= on line 4 (in bold) and treats it as !=.
Similarly, on line 5, the checker treats !== (case inequality) as !=. (Refer to VLG1.1
on
page 767
.)
input aa, bb;
output o1, o2;
assign o1 = aa !?= bb;
assign o2 = aa !== bb;
endmodule
VLG1.4
Message
Wild equality is treated as equality
Default Severity
Warning
Description
The checker does not support the =?= SystemVerilog operator with the exact semantics
supported in simulation. The checker treats =?= as ==.
Example
In the following example, the checker encounters =?= on line 4 (in bold) and treats it as ==.
Similarly, on line 5, the checker treats === (case equality) as ==. (Refer to VLG1.2
on
page 768
.)
input aa, bb;
output o1, o2;
assign o1 = aa =?= bb;
assign o2 = aa === bb;
endmodule
VLG2.1
Message
Non-constant case-item is used in casex/casez statement
Default Severity
Note
Description
The design includes one or more case_items that use a non-constant value in a casex or
casez statement.
Sample casex statement syntax:
casex (case_expression)
endcase
Example
In the following example, the design uses primary input a for the second case_item (see line
9).
input a, b, c;
input sel;
output out0;
reg out0;
casex(sel)
1'b1 : out0 = a;
a : out0 = b;
default: out0 = c;
endcase
end
endmodule
VLG2.2
Message
Non-binary case-item is used in casex/casez statement
Default Severity
Note
Description
The design includes one or more case_items that use a non-binary value in a casex or casez
statement.
Example casex statement syntax:
endcase
Example
In the following example, the design uses an X value for the second case_item. See line 9 (in
bold).
input a, b, c;
input sel;
output out0;
reg out0;
casex(sel)
1'b1 : out0 = a;
1'bx : out0 = b;
default: out0 = c;
endcase
end
endmodule
VLG2.3
Message
default keyword is not the last item in case statement(s)
Default Severity
Warning
Description
The default keyword is not the last case_item in one or more case statements.
Sample case statement syntax:
endcase
Example
In the following example, the keyword default is not the last case_item. See line 9 (in bold).
input a, b, c;
input sel;
output out0;
reg out0;
casex(sel)
1'b1 : out0 = a;
default: out0 = c;
1'b0 : out0 = b;
endcase
end
endmodule
VLG3.1
Message
Unsized constant(s) with leading X/Z value is extended beyond 32 bits
Default Severity
Warning
Description
One or more unsized constants with a leading X/Z value are extend beyond 32 bits.
Example
In the following example, the design assigns an unsized constant with leading X value 'bx to
a 34-bit output out0 (see line 5).
module test(out0,y,in);
output [33:0] out0;
output y;
input in;
assign out0 = 'bx;
assign y = in;
endmodule
VLG3.2
Message
Verilog event expression in always block(s) are complex
Default Severity
Warning
Description
The Verilog event expressions used in one or more always blocks are complex.
Example
In the following example, event expression a|b is considered complex (see line 5).
input [3:0] a, b;
output [3:0] q;
reg [3:0] q;
always @ (a | b ) begin
q = a & b;
end
endmodule
VLG3.3
Message
Replication is not a constant or it contains X or Z values
Default Severity
Warning
Description
A replication multiplier is not a constant or it contains X or Z values.
Note: This check has a warning default severity level, but the module is blackboxed.
Example
In the following example, replication 2bx is illegal value (see line 6).
module test (a, q);
input [3:0] a;
output [4:0] q;
reg [4:0] q;
always @ (a ) begin
q = {{2b1x{1b1}}, 1b0};
end
endmodule
VLG3.4
Message
Zero replication is treated as NULL in concatenation
Default Severity
Warning
Description
A replication multiplier is a constant 0 but the entire concatenation remains valid. The
replicated concatenation portion is treated as NULL as if the portion is removed from the
entire concatenation.
Example
In the following example, replication 2b0 is illegal value (see line 6).
module test (a, q);
input [3:0] a;
output [4:0] q;
reg [4:0] q;
always @ (a ) begin
q = {{2b0{2b1}}, 1b0};
end
endmodule
VLG3.5
Message
Null expression is not allowed (caused by zero replication)
Default Severity
Warning
Description
A replication multiplier is a constant 0 and the entire concatenation becomes NULL. The
replicated concatenation portion is treated as NULL as if the portion is removed from the
entire concatenation.
Example
In the following example, on line 6 the replication multiplier is a constant 0 and the entire
concatenation becomes NULL, which is not allowed.
module test (a, q);
input [3:0] a;
output [4:0] q;
reg [4:0] q;
always @ (a ) begin
q = {2b0{2b1}};
end
endmodule
VLG3.6
Message
Negative replication is not allowed
Default Severity
Warning
Description
A replication multiplier is a negative integer constant.
Example
In the following example, replication -1 is not allowed (see line 6).
module test (a, q);
input [3:0] a;
output [4:0] q;
reg [4:0] q;
always @ (a ) begin
q = {{-1{2b1}}, 4b1};
end
endmodule
VLG3.7
Message
Unsized constant value is set to 32-bit in concatenation
Default Severity
Warning
Description
The unsized constant value is set to 32-bit in concatenation.
Example
In the following example, 1 is an unsized constant value, will be set to 32-bit in concatenation
(see line 6).
module test (a, q);
input [3:0] a;
output [4:0] q;
reg [4:0] q;
always @ (a ) begin
q = {1, 4b1};
end
endmodule
VLG4.1
Message
Wire type wand is used
Default Severity
Warning
Description
The design includes a user-specied wire-AND resolution for one or more multi-driven nets.
Example
In the following example, the design declares wire wand, which is used for multi-driven output
q. See line 4 (in bold).
module test (a,b,q);
input a, b;
output q;
wand q;
assign q = a
assign q = b;
endmodule
VLG4.2
Message
Wire type wor is used
Default Severity
Warning
Description
The design includes a user-specied wire-OR resolution for one or more multi-driven nets.
Example
In the following example, the design declares wire wor, which is used for multi-driven out0.
See line 5 (in bold).
input a, b, c;
input sel;
output out0;
wor out0;
assign out0 = a;
assign out0 = b;
endmodule
VLG4.3
Message
Implicit declared net is generated
Default Severity
Warning
Description
An implicit declared net is generated.
Example
In the following example, in_top is an implicit declared net (see line 13):
`default_nettype none
module test(out,in);
input in;
output out;
reg out;
always @(in)
begin
if (in ) out = in; else out = ~in;
end
endmodule
module top (out_top);
output out_top;
test s1(out_top,in_top);
endmodule
VLG4.4
Message
Cutpoint not found
Default Severity
Warning
Description
Cannot nd the specied cutpoint.
Example
In the following example, the pragma cutpoint ram2 cannot be found in the design (see line 7):
module test(clk, addr, din, dout);
input clk;
input [1:0] addr;
input [0:0] din;
output [0:0] dout;
reg [0:0] ram [3:0];
// pragma cutpoint "ram2"
always @(clk or addr or din) begin
if (clk && ram[0] ) ram[addr[1:0]] = din;
end
endmodule
VLG5.1
Message
Primitive output port has multiple bits. Ignored all but LSB bit
Default Severity
Warning
Description
The design includes one or more primitive output ports with multiple bits. The checker ignores
all but the least signicant bit (LSB) of the primary vector output.
Example
In the following example, output o has three bits. The checker only keeps the LSB. See line
4 (in bold).
module test(o,a,b);
output [2:0] o;
input a,b;
and(o,a,b);
endmodule
VLG5.2
Message
Primitive input port has multiple bits. Ignored all but LSB bit
Default Severity
Warning
Description
One or more primitive input ports have multiple bits. The checker changes all primitive vector
input ports to scalar input ports by applying OR logic reduction.
Example
In the following example, the checker reduces the two-bit input a to a single-bit input a by
OR-ing a[0] and a[1] together. See line 5 (in bold).
module test ( a, out0);
input[1:0] a;
output out0;
wire out0;
not (out0,a);
endmodule
VLG5.3
Message
Wire and port size declaration(s) do not match
Default Severity
Warning
Description
In one or more cases, the designs wire and port size declarations do not match.
Example
In the following example, the declared size of input ports a and b is [3:0], but the declared
size of wires a and b is [4:0]. See lines 2 and 4 (in bold).
input [3:0] a, b;
output [3:0] q;
wire [4:0] a, b;
assign q = a & b;
endmodule
VLG5.4
Message
Port size of array instance does not match
Default Severity
Warning
Description
In one or more cases, port sizes of an array instance do not match.
Example
In the following example, output o has a port size of [2:0], but inputs a and b have a port
size of [1:0] for instance array u1[1:0]. See lines 2 and 3.
module test(o,a,b);
output [2:0] o;
input [1:0] a,b;
and u1[1:0] (o,a,b);
endmodule
VLG5.5
Message
Named port association ignored for primitive gate
Default Severity
Warning
Description
The checker triggers this rule check when it encounters an internal primitive. This rule check
helps identify module instances that you should treat as blackboxes.
Example
In the following example, you might want to treat AND as a blackbox. See line 2.
AND u0(oo, aa, bb);
endmodule
VLG5.6
Message
Named port association is ignored for primitive gate
Default Severity
Warning
Description
The checker ignores the named port association for the primitive gate.
Example
In the following example, line 2 uses the named port association:
module test(input aa, bb, output oo);
AND u0(.o(oo), .a(aa), .b(bb));
endmodule
VLG6.1
Message
Globally referenced variable is unresolved
Default Severity
Warning
Description
The checker cannot nd the globally referenced variable. Thus, the variable remains
unresolved.
Example
In the following example, on line 16 (in bold), the checker cannot nd variable x in module
sub. Thus, variable x remains as an undriven net.
module sub (a, b, c);
input [7:0] a, b;
output [7:0] c;
wire [7:0] wiretmp ;
assign wiretmp = a & b;
assign c = wiretmp ;
endmodule
module main (i1, i2, o1, o2);
input [7:0] i1, i2;
output [7:0] o1;
output o2;
sub inst1 (i1, i2, o1);
assign o2= inst1.x;
endmodule
VLG6.2
Message
Globally referenced variable resolved
Default Severity
Note
Description
The checker found the globally referenced variable.
Example
In the following example, on line 16 (in bold), the checker nds variable tmp in module sub.
module sub (a, b, c);
input [0:0] a, b;
output [0:0] c;
wire [0:0] tmp ;
assign tmp = a & b;
assign c = tmp ;
endmodule
module main (i1, i2, o0, o1, o2, o3);
input [0:0] i1, i2;
output o0;
output [0:0] o1, o2, o3;
sub inst1 (.a(i1), .b(i2), .c(o1));
assign o2 = inst1.tmp ;
endmodule
VLG6.3
Message
Unsupported system function call (converted to 1'b1)
Default Severity
Warning
Description
The checker does not support the $system/$user_pli function calls; instead, the checker
approximates the $system/$user_pli function call to 1'b1.
Example
In the following example, the checker approximates $random and $time to 1b1. See lines
4 and 5.
input aa, bb;
output o1, o2;
assign o1 = $random;
assign o2 = $time;
endmodule
VLG6.3a
Message
Unsupported system task call
Default Severity
Error
Description
$systemtask(...) is called as a concurrent statement in Verilog.
Note: This check has default error severity level, but you can set it to lower severity level to
skip the error checking.
Example
In the following example, concurrent systemtask $mytask is not supported
module m1(aa, bb, oo);
input aa, bb;
output oo;
$mytask(aa, bb, oo);
endmodule
VLG6.4
Message
Supported system datapath function call
Default Severity
Note
Description
The checker triggers this rule check when it encounters any supported datapath functions.
Conformal supports the following datapath functions.
$abs()
$blend()
$carrysave()
$compge()
$intround()
$inttrunc()
$lead0()
$lead1()
$log2()
$max()
$min()
$rotatel()
$rotater()
$round()
$sat()
$sgnmult()
VLG6.5
Message
Time literal is unsupported
Default Severity
Warning
Description
The checker does not support time literals, such as 1fs, 2ps, and 3ns, and that it converted
the time literals to 1b1.
Example
In the following example, Conformal converts (2ns > 1ns) to (1b1 > 1b1). See line 4.
reg oo;
always @* begin
if (2ns > 1ns) oo = !aa;
else if (aa || bb) oo = aa;
else oo = 1b0;
end
endmodule
VLG6.6
Message
Event object is unsupported
Default Severity
Warning
Description
The event object is not supported.
Example
In the following example, -> ev (see line 7) is not supported:
module top (input in, output out);
test test1(in, out);
endmodule
module test(input aa, output oo);
event ev;
always begin
-> ev;
oo = aa;
end
endmodule
VLG6.7
Message
Hierarchical function call is not supported (blackboxed)
Default Severity
Warning
Description
The hierachical function call is not supported and will be blackboxed.
Example
In the following example, line 16 shows the unsupported hierachical function call:
module mod1 (input in1, output out1);
reg out1;
function ftn1;
input in1;
begin
if (in1 == 0) ftn1 = in1;
else ftn1 = 1;
end
endfunction
always @(in1)
out1 = ftn1(in1);
endmodule
module mod2 (input in2, output out2);
reg out2;
always @(in2)
out2 = mod1.ftn1(in2);
endmodule
VLG6.8
Message
Specify block is ignored
Default Severity
Ignore
Description
The specify block is ignored. In a design, Verilog specify blocks contain path delay information
that is not used in static verication. As a result, the contents of a specify block are ignored.
Some library cells may have notier registers used in a specify block that can potentially affect
the logic. Specify blocks are non-synthesizable.
Example
In the following example, specify (line 5) is ignored:
module specify_blk ( o, i);
input i;
output o;
buf(o, i);
specify
specparam T1RISE$ = 2.7;
( i *> o ) =( 183:311:549 , 179:304:536 );
endspecify
endmodule
VLG6.10
Message
Intra-assignment event specification is not supported
Default Severity
Warning
Description
This construct is not supported because intra-assignment event specications are not
synthesizable. Cadence recommends that you remodel your HDL source code.
Example
In the following example, the intra-assignment in line 8 is not supported:
module intra_assign_evt (clk, cout);
input clk;
output [3:0] cout;
reg [3:0] cout;
begin
cout = 4b0;
cout = @(posedge clk) cout + 1;
end
endmodule
VLG6.12
Message
fork-join constructs are not supported
Default Severity
Warning
Description
The design includes fork-join constructs. The fork-join constructs cannot be synthesized, and
are not supported. To avoid this error, remodel the design.
Example
In the following example, the fork and join contructs (lines 7 and 10) are not supported:
module neg_fork_join (clk, cout);
input clk;
output cout;
reg cout;
begin
fork
cout = 1b0;
cout = 1b1;
join
end
endmodule
VLG6.13
Message
force-release constructs are not supported
Default Severity
Warning
Description
The design includes force-release constructs. The force-release constructs cannot be
synthesized. To avoid this error, remodel your design.
Example
In the following example, the force and release contructs (lines 7 and 10) are not supported:
module force_release (clk, cin, cout);
input clk;
input cin;
output cout;
reg cout;
always @ (posedge clk)
begin
force cout = 1b1; <b>
cout = cin;
release cout; <b>
end
endmodule
VLG6.14
Message
Global reference on the left side of the assignment is not supported
Default Severity
Warning
Description
A global reference on left side of the assignment is not supported.
Example
In the following example, botInst.memNd (line 5) is a global reference on left side of the
assignment and is not supported:
module test(d);
input [1:0] d;
bot botInst();
always @(d)
botInst.memNd[0] = d;
endmodule
module bot();
reg [1:0] memNd [7:0];
endmodule
VLG6.15
Message
disable construct is not supported
Default Severity
Warning
Description
The disable construct is supported only when applied to an enclosing named block. The
Conformal software cannot disable tasks and non-enclosing named blocks. Remodel the
design to avoid this error.
Example
In the following example, specify (line 5) is ignored: xxxxxxxxxxxxxxx
module test;
always
begin : break
end
endmodule
module top;
test t();
integer i;
always
begin
if (i==1)
begin:cont
disable top.t.break;
end
end
endmodule
VLG6.16
Message
wait construct is not supported
Default Severity
Warning
Description
The design includes a Verilog wait event control, which is not supported. You will need to
remodel the design.
Example
In the following example, the wait event control (line 7) is not supported:
module neg_wait (enable, a, b, c, d);
input enable, b, d;
output a, c;
reg a, c;
always @(enable or b or d)
begin
wait (!enable) #10 a = b;
#10 c = d;
end
endmodule
VLG7
Message
Nets renamed after removing backslash
Default Severity
Warning
Description
The checker has renamed one or more net names. The checker renames all net names that
include a backslash (\).
Example
In the following example, net name \out3[0] will be renamed out3[0]1. See line 4 (in
bold).
module test ( in1, in2, out3 );
output [1:0] out3;
input in1, in2;
wire \out3[0] ;
assign \out3[0] = in1 & in2;
assign out3[1] = \out3[0] ;
assign out3[0] = \out3[0] ;
endmodule
VLG8
Message
Buffer inserted
Default Severity
Note
Description
The checker has inserted one or more buffers because the design includes the $setuphold
or $recrem timing checks from the Verilog IEEE Std P1364-Y2K.
Example
In the following example, the design uses the $setuphold timing check. See line 11 (in
bold).
module test (CK,D,O);
output O;
reg O;
input CK,D;
wire D_del,CK_del;
buf (CK_del,CK);
buf (D_del,D);
always @(posedge CK_del)
O <= D;
specify
$setuphold (posedge CK,posedge D, tsu_d_h_ck,th_ck_d_l, notifier,,,CK_del,D_del
endspecify
endmodule
VLG9
Message
Names conflict with previous declarations
Default Severity
Warning
Description
The checker found a name conict among declarations.
Example
In the following example on line 12 (in bold), instance a has the same name as input a at line
9 (in bold).
input din;
output dout;
assign dout=din;
endmodule
module top (a , b);
input a;
output b;
test a (a,b);
endmodule
VLG9.1
Message
Text macro is redefined
Default Severity
Warning
Description
The text macro is redened.
Example
In the following example, val1 is redened (see line 2):
define val1 0
`define val1 1
input din;
output dout;
assign dout=din;
endmodule
VLG9.2
Message
define macro is used
Default Severity
Note
Description
The define macro is used in the Verilog les.
Example
In the following example, define macro is used (see line 1):
`define VAL
module test(in,out);
input in;
output out;
assign out = in;
endmodule
VLG9.4
Message
Instance name conflicts with previous declarations
Default Severity
Error
Description
The checker found a name conict among instance declarations.
Example
In the following example, u0 is redened (see line 6):
module GCLK (clko, clki, ena);
input clki, ena;
output clko;
not u0 (clki, clki);
DLAT l0 (q0, 1b0, 1b0, clki_, ena);
and u0 (clko, q0, clki);
endmodule
VLG10
Message
Non-blocking assignment is in disabled block
Default Severity
Warning
Description
There are non-blocking assignments in a disabled block. These kind of assignments might
have undened behavior.
Example
In the following example, the disabled blk1 block contains a non-blocking assignment on line
6 (in bold).
module test (clk, a,b);
input clk,a;
output b;
always @(posedge clk) begin:blk1
b <= a;
disable blk1;
end
endmodule
VLG10.1
Message
Non-blocking assignment encountered in function
Default Severity
Error
Description
Non-blocking assignment was detected inside the function. You should not use non-blocking
statements inside functions. Such usage can lead to compilation failures.
Example
In the following example, get_address (line 12) is a non-blocking assignment:
module top (clk, result);
input clk;
output [3:0] result;
reg [3:0] result;
reg [1:0] state_var;
function [3:0] get_address;
input [1:0] state_var;
begin
case (state_var)
2b00:
begin
get_address <= "0000";
end
endcase
end
endfunction
begin
result = get_address(2b0);
end
endmodule
VLG10.2
Message
deassign statements cannot be synthesized and are not supported
Default Severity
Warning
Description
The deassign statements cannot be synthesized.
Example
In the following example, the deassign statment in line 13 is not supported:
module DeassignMod(a,b);
input a;
output b;
reg b;
reg reset, clk;
always
begin
if(clk)
b = a;
else if(reset)
b = ~a;
else
deassign b;
end
endmodule
VLG10.3
Message
Sequential assign statement is not supported
Default Severity
Warning
Description
Sequential assign statement is not supported.
Example
In the following example, the sequential assign statment in line 13 is not supported:
module assignMod(a,b);
input a;
output b;
reg b;
reg reset, clk;
always
begin
if(clk)
b = a;
else if(reset)
b = ~a;
else
assign b = 0;
end
endmodule
VLG11.1
Message
Combinational logic is inferred in an always_latch block
Default Severity
Warning
Description
There is combinational logic inferred in an always_latch block. Latches are expected to
have inferred logic.
Example
In the following example, the always_latch block contains combinational logic on line 7.
module test(a,in1,in2,o);
input a;
input byte in1, in2;
output byte o;
always_latch begin
o = in1 & in2;
end
endmodule
VLG11.2
Message
Latches are inferred in an always_comb block
Default Severity
Warning
Description
This rule check tells that there are inferred latches in an always_comb block. Combinational
logic is expected to have inferred logic.
Example
In the following example, the always_comb block contains an inferred latch on line 7 (in
bold).
module test(a,in1,in2,o);
input a;
input byte in1, in2;
output byte o;
always_comb begin
if (a)
o = in1 & in2;
end
endmodule
VLG12.1
Message
Null statement ; is not allowed inside a begin-end block and is ignored
Default Severity
Warning
Description
The null statement : is not allowed inside a begin-end block and will be ignored.
Example
In the following example, the extra null statement (line 7) will be ignored.
module test(clk, out1, in1);
input clk, in1;
output out1;
reg out1;
begin
out1 <= in1;;
end
endmodule
VLG13.1
Message
Unpacked dimension is not allowed
Default Severity
Warning
Description
The unpacked dimension declaration is not allowed. It is only allowed for SystemVerilog.
Example
In the following example, in line 4, the unpacked dimension for the wire declaration is only
allowed in SystemVerilog.
module test (aa, bb, oo);
input aa, bb;
output oo;
wire tt[1:0];
assign tt[0] = aa;
assign tt[1] = bb;
assign oo = tt[0] && tt[1];
endmodule
VLG13.2
Message
Unsized dimension is not allowed
Default Severity
Warning
Description
The unsized dimension is not allowed. Using unsized dimension in an array declaration will
cause SystemVerilog module to be blackboxed.
Example
The following SystemVerilog examples are not allowed and will cause modules to be
blackboxed:
task foo( string arr[] ); // Dynamic array of strings
bit [3:0] nibble[]; // Dynamic array of 4-bit vectors
integer mem[]; // Dynamic array of integers
VLG13.3
Message
Associative dimension is not allowed
Default Severity
Warning
Description
The SystemVerilog associative dimension is not allowed. Using associative dimension will
cause SystemVerilog module to be blackboxed.
Example
The following SystemVerilog examples are not allowed and will cause module to be
blackboxed:
integer i_array[*]; // associative array of integer (unspecified index)
bit [20:0] array_b[string];
// associative array of 21-bit vector, indexed by string
event ev_array[myClass]; // associative array of event indexed by class myClass
VLG14.1
Message
Missing module instance name
Default Severity
Error
Description
The instance name is missing for the module.
Example
In the following example, in line 3, the instance name is missing for instantiation of module
sub:
module top();
wire m, n, k;
sub (.o(k), .a(m), .b(n));
endmodule
VLG15.1
Message
Block name is previously declared
Default Severity
Error
Description
Indicates that the block name is previously declared in the same scope.
Example
In the following example, in line 9, block name b1 in redeclared:
module test(clk,in, out);
input in,clk;
output reg out;
always @(clk)
begin
begin:b1
out = in;
end
begin: b1
out = ~in;
end
end
endmodule
VLG16.1
Message
Syntax error in Verilog instantiation
Default Severity
Error
Description
Indicates that a syntax error was found in the Verilog instantiation.
The correct syntax is <modname> <mod_instance_name>(...).
Example
In the following example, in line 4, the correct syntax is test sub(...).
module top(din, dout);
input din;
output dout;
test sub;
endmodule
4
Modeling Messages
This chapter lists and describes the modeling messages you encounter when the system
mode changes from Setup to LEC in the Encounter
Conformal
software.
Modeling Messages
F1
Message
Modeled multiple-driven net(s)
Description
A multi-driven net has been remodeled into Boolean logic based on how the SET WIRE
RESOLUTION command is set.
Example
Sample modeling message:
F1: Modeled multiple-driven net(s) (Occurrence: 1)
1: /n1 (and)
In this message:
I /n1 is a multi-driven net
I (and) indicates that SET WIRE RESOLUTION is set to AND
The following code illustrates a circuit with a net n1 that has multiple drivers u0 and u1:
not u0 (n1,a);
not u1 (n1,b);
not u2 (z,n1);
Associated Commands
SET WIRE RESOLUTION
Modeling Messages
F2
Message
Inserted user cut point(s)
Description
Conformal inserted a cut point to break a combinational loop. This operation is enabled when
you use the ADD CUT POINT command.
Example
F2: Inserted user cut point(s) (Occurrence: 1)
1: CUT /n1
In this message:
I CUT indicates the gate type
I /n1 indicates the net name
You get this message when you add a cut point at net n1 using the
following command:
add cut point n1 -golden
Circuit example:
mux u0 (n1,n1,d,ck);
xor u1 (q,n1);
Associated Commands
ADD CUT POINT
Modeling Messages
F3
Message
Inserted system cut point(s)
Description
A cut point has been inserted automatically to break a combinational loop.
Example
F3: Inserted system cut point(s) (Occurrence: 1)
1: MUX /u0
In this message:
I MUX is the gate type
I /u0 is the driver instance name
The following circuit example inserts CUT gate at the output of a MUX instance u0:
xor u1 (q,n1);
Modeling Messages
F5
Message
Folded DLAT(s) into DFF(s)
Description
D-latches (DLATs) were folded into D ip-ops (DFFs). This operation is enabled when you
use the SET FLATTEN MODEL -LATCH_FOLD command, which species that two latches
that are in a master-slave conguration should be converted into a single DFF gate. This
operation is also affected by the SET FLATTEN MODEL
-LATCH_FOLD_MASTER command.
Example
F5: Folded DLAT(s) into DFF(s) (Occurrence: 1)
1: /l1 /l0
In this message, /l1 and /l0 are the instance names of the folded DLATs.
You would get this modeling message if you use the following command to convert two
master-slave DLATs l0 and l1 into a DFF:
Circuit example:
not u0 (ck_,ck);
DLAT l0 (n1,,1b0,1b0,ck_,d);
DLAT l1 (q ,,1b0,1b0,ck,n1);
Associated Commands
SET FLATTEN MODEL -LATCH_FOLD
SET FLATTEN MODEL -LATCH_FOLD_MASTER
Modeling Messages
F6
Message
Created DLAT(s) due to trireg net(s) or combinational loop(s)
Description
A DLAT was created due to trireg net or a series of buffers/inverters that were
implemented as a bus-holder.
Example
F6: Created DLAT(s) due to trireg net(s) or combinational loop(s)
(Occurrence: 1)
1: DLAT /n1 due to trireg net
This message indicates that a DLAT was created on net n1 for trireg, which is illustrated
in the following circuit example:
trireg n1;
bufif0 u0 (n1,a,s0);
bufif0 u1 (n1,b,s1);
buf u2 (z,n1);
Modeling Messages
F7
Message
Set DLAT data port(s) as ZERO due to disabled clock port(s)
Description
DLAT data ports were set to zero because there were disabled clock ports. This operation is
enabled when you use the SET FLATTEN MODEL -LATCH_FOLD command.
Example
F7: Set DLAT data port(s) as ZERO due to disabled clock port(s)
(Occurrence: 1)
1: Set DLAT q_reg data port /d to ZERO due to disabled clock port
This message indicates that data port d of register q_reg is tied to logic ZERO because
clock port of register q_reg is always disabled (logic ZERO).
You would get this message if you issue the following command:
Circuit example:
and u0 (g,1b0,ck);
always @(d or g)
begin
if (g)
q <= d;
end
Modeling Messages
F8
Message
Converted DLAT(s) to BUF(s) due to transparency
Description
DLATs were converted into buffers because of transparency. This operation is enabled when
you use the SET FLATTEN MODEL -LATCH_TRANSPARENT command, which species that
DLATs should be converted into buffers if the DLAT clock ports are always enabled.
Example
F8: Converted DLAT(s) to BUF(s) due to transparency (Occurrence: 1)
1: DLAT /q_reg
This message indicates that a buffer was converted buf (q,d), because the clock of
register q_reg is always enabled (logic ONE).
set flatten model -latch_transparent
Circuit example:
or u0 (g,1b1,ck);
always @(d or g)
begin
if (g)
q <= d;
end
Associated Commands
SET FLATTEN MODEL -LATCH_TRANSPARENT
Modeling Messages
F10
Message
Removed redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s)
Description
Redundant AND/NAND/OR/NOR fan-in gates for DFFs and DLATs were removed. This
operation is enabled when you use the SET FLATTEN MODEL
-SEQ_REDUNDANT command.
Example
F10: Removed redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s)
(Occurrence: 1)
1: Removed connection from INV /u0 to AND /u1 for DFF /f0_reg
This message indicates that the fan-in AND u1 and INV u0 gates were optimized for DFF
f0_reg due to redundant logic.
You would get this command if you issue the following command:
Circuit example:
not u0 (rst_,rst);
and u1 (sr,set,rst_);
DFF f0_reg(q,,sr,rst,ck,d);
Associated Commands
SET FLATTEN MODEL -SEQ_REDUNDANT
Modeling Messages
F11
Message
Removed redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s)
Description
Redundant AND/NAND/OR/NOR fan-out gates for DFFs and DLATs were removed. This
operation is enabled when you use the SET FLATTEN MODEL -SEQ_REDUNDANT command.
Example
F11: Removed redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s)
(Occurrence: 1)
1: Remodeled AND /u0 for DFF /n1_reg
This message indicates that the fan-out AND gate u0 was optimized for DFF n1_reg due
to redundant logic.
You would get this command if you issue the following command:
Circuit example:
always @(posedge ck or negedge rst )
begin
if (!rst)
n1 <= 0;
else
n1 <= d;
end
and u0 (q,n1,rst);
Associated Commands
SET FLATTEN MODEL -SEQ_REDUNDANT
Modeling Messages
F12
Message
Converted DFF(s) to DLAT(s) due to disabled clock port(s)
Description
DFFs were converted into DLATs due to disabled clock ports. This operation is enabled when
you use the SET FLATTEN MODEL -DFF_TO_DLAT_ZERO, which converts a DFF to a
DLAT when the clock port is zero.
Example
F12: Converted DFF(s) to DLAT(s) due to disabled clock port(s)
(Occurrence: 1)
1: DLAT /q_reg
This message indicates DFF q_reg was converted to a DLAT because the clock of the
register is always disabled (logic ZERO).
You would get this message with the following command:
set flatten model -DFF_TO_DLAT_ZERO
Circuit example:
and u0 (ck1,1b0,ck);
always @(posedge ck1)
begin
q <= d;
end
Note: The -DFF_TO_DLAT_ZERO option is enabled by default.
Associated Commands
SET FLATTEN MODEL -DFF_TO_DLAT_ZERO
Modeling Messages
F13
Message
Converted DFF(s) to DLAT(s) due to direct feedback
Description
DFFs were converted to DLATs due to direct feedback. This operation is enabled when you
use the SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK command, which converts a
DFF to a DLAT if the DFFs output feeds back directly to the DFFs input.
Example
F13: Converted DFF(s) to DLAT(s) due to direct feedback
(Occurrence: 1)
1: DLAT /q_reg
This message indicates that DFF q_reg was converted to a DLAT because of direct
feedback from output q of the register to its input d.
set flatten model -DFF_TO_DLAT_FEEDBACK
Circuit example:
always @(posedge ck)
begin
q <= q;
end
Note: The -DFF_TO_DLAT_FEEDBACK option is enabled by default.
Associated Commands
SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK
Modeling Messages
F14
Message
Remodeled gated-clock DFF(s) or DLAT(s) to mux-feedback
Description
Gated-clock logic for DFFs or DLATs were remodeled to MUX-feedback. This operation is
enabled when you run the SET FLATTEN MODEL command with the -GATED_CLOCK option,
which remodels gated-clock logic of the clock port of a DFF.
Example
F14: Remodeled gated-clock DFF(s) or DLAT(s) to mux-feedback
(Occurrence: 1)
1: /q_reg (DFF)
This message indicates that the de-glitch gating clock DLAT l0 and enable logic u1 for
register DFF q_reg was converted to a mux-feedback DFF
You would get this message when issue the following command:
set flatten model -GATED_CLOCK
Circuit example:
not u0 (ck_,ck);
DLAT l0 (en,,1b0,1b0,ck_,ena);
and u1 (ck1,ck,en);
begin
q <= d;
end
Associated Commands
SET FLATTEN MODEL -GATED_CLOCK
Modeling Messages
F14.1
Message
Remodeled gated-clock DFF(s) or DLAT(s) without latch to mux-feedback
Description
Conformal remodeled gated-clock logic for DFFs or DLATs without deglitching to MUX-
feedback. This operation is enabled when you use the SET FLATTEN MODEL
-GATED_CLOCK, which remodels gated-clock logic of the clock port of a DFF. This operation
might need the ADD CLOCK command to dene the clock pin
Example
F14.1: Remodeled gated-clock DFF(s) or DLAT(s) without latch to mux-
feedback(Occurrence: 1)
1: /q_reg (DFF)
This message indicates that the gated-clocking enable logic u1 for register DFF q_reg
was converted to a mux-feedback DFF.
You get this message when you issue the following commands:
add clock 0 ck
set flatten model -GATED_CLOCK
Circuit example:
and u0 (ck1,ck,ena);
begin
q <= d;
end
Associated Commands
ADD CLOCK
Modeling Messages
SET FLATTEN MODEL -GATED_CLOCK
Modeling Messages
F16
Message
Converted DLAT(s) to MUX(s) due to clock inversion relation
Description
DLATs were converted into MUXes due to clock inversion relationships.
Example
F16: Converted DLAT(s) to MUX(s) due to clock inversion relation
(Occurrence: 1)
1: /l0
This message indicates that a dual-port DLAT l0 was converted to a MUX - mux l0
(q,d0,d1,ck) due to the clock inversion relationship on the dual-port DLAT clock ports.
Circuit example:
not u0 (ck_,ck);
DLAT l0 (q,,1b0,1b0,ck_,d0,ck,d1);
Modeling Messages
F17
Message
Converted DLAT(s) to BUF(s)/INV(s) due to set/reset inversion relation
Description
DLATs were converted to buffers/inverters due to set/reset inversion relationships.
Example
F17: Converted DLAT(s) to BUF(s) due to set/reset inversion relation
(Occurrence: 1)
1: /l0
This message indicates that a DLAT l0 was converted to a buffer, buf l0 (q,a),
because of set/reset inversion relationships on asynchronous set/reset of DLAT.
Circuit example:
not u0 (a_,a);
DLAT l0 (q,,a,a_,ck,1b0);
Modeling Messages
F18
Message
Converted DFF/DLAT(s) to ZERO/ONE
Description
Conformal converted a DFF or a DLATs to a ZERO or ONE gate. This operation is enabled
when you use the SET FLATTEN MODEL -SEQ_CONSTANT command, which converts a
DFF or DLAT to a ONE or ZERO gate if the data port is a one or zero. This operation is also
affected by the SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK command.
Example
F18: Converted DFF/DLAT(s) to ZERO/ONE (Occurrence: 1)
1: DFF /n1_reg (ZERO)
This message indicates that DFF n1_reg was converted to logic ZERO because data port
is tied to logic ZERO.
Circuit example:
always @ (posedge ck)
n1 <= 1b0;
assign q = a | n1;
Associated Commands
SET FLATTEN MODEL -SEQ_CONSTANT
SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK
Modeling Messages
F19
Message
Merged DFF(s) or DLAT(s) in clock cones
Description
Sequentially equivalent DFFs or DLATs in clock cones were merged. This operation is
enabled when you use the SET FLATTEN MODEL -SEQ_MERGE command.
Example
F19: Merged DFF(s) or DLAT(s) in clock cones (Occurrence: 1)
1: DFF /ck0_reg /ck1_reg
This message indicates that DFF ck0_reg and DFF ck_reg were merged into a single
DFF because the two DFFs were sequentially equivalent.
You would get this message when you issue the following command:
Circuit example:
begin
ck0 <= a;
ck1 <= a;
end
always @ (posedge ck0)
q0 <= d;
always @ (posedge ck1)
q1 <= d;
Associated Commands
SET FLATTEN MODEL -SEQ_MERGE
Modeling Messages
F20
Message
Merged DFF(s) or DLAT(s)
Description
Sequentially equivalent DFFs and DLATs were merged. This operation is enabled when you
use the SET FLATTEN MODEL -ALL_SEQ_MERGE command, which merges common
groups of sequential elements into one sequential element in a logic cone of a key point.
Example
F20: Merged DFF(s) or DLAT(s) (Occurrence: 1)
1: DFF /q0_reg /q1_reg
This message indicates that DFF q0_reg and DFF q_reg were merged into a single DFF
because the two DFFs are sequentially equivalent.
You would get this message if you use the following command:
set flatten model -all_seq_merge
Circuit example:
begin
q0 <= d;
q1 <= d;
end
Associated Commands
SET FLATTEN MODEL -ALL_SEQ_MERGE
Modeling Messages
F21
Message
Merged DFF(s) or DLAT(s) defined by user
Description
User-dened DFFs or DLATs were merged using the ADD INSTANCE EQUIVALENCES
command.
Example
F21: Merged DFF(s) or DLAT(s) defined by user (Occurrence: 1)
1: DFF /q0_reg /q1_reg
This message indicates that you merged two DFFs q0_reg and DFF q1_reg into a single
DFF using the following command:
add instance equivalences /q0_reg /q1_reg -golden
Circuit example:
begin
q0 <= d;
q1 <= d;
end
Associated Commands
Modeling Messages
F23
Message
Merged DFF(s) or DLAT(s) multiple ports into single port due to equivalence
Description
Multiple ports belonging to DFFs or DLATs into one single port due to equivalence were
merged.
Example
F23: Merged DFF(s) or DLAT(s) multiple ports into single port due to
equivalence (Occurrence: 1)
1: DFF /f0
This message indicates that a dual-port DFF f0_reg with equivalent data and clock port
was merged into a single port DFF - DFF f0_reg (q,,1b0,1b0,ck,d).
Circuit example:
buf n0 (d0,d);
buf n1 (d1,d);
DFF f0_reg (q,,1b0,1b0,ck,d0,ck,d1);
Associated Commands
None.
Modeling Messages
F25
Message
Pipeline-retimed DFF(s) to outputs
Description
DFFs to outputs were pipeline-retimed. This operation is enabled when you use the ADD
MODULE ATTRIBUTE -PIPELINE_RETIME, which checks specied modules for pipeline
retiming and remodels when necessary.
Example
Sample modeling messages:
Report modeling message for Revised
F25: Pipeline-retimed DFF(s) to outputs (Occurrence: 1)
1: Pipeline retimed DFF q_reg to output
Report modeling message for Revised
F25: Pipeline-retimed DFF(s) to outputs (Occurrence: 2)
1: Pipeline retimed DFF a1_reg to output
2: Pipeline retimed DFF b1_reg to output
These messages indicate that the DFF a1_reg and DFF b1_reg performed pipeline-
retiming to the outputs.
You would get these messages if you issue the following command:
add module attribute ckt -pipeline_retime
Circuit example:
Golden:
assign n1 = a & b;
q <= n1;
Revised:
begin
Modeling Messages
a1 <= a;
b1 <= b;
end
assign q = a1 & b1;
Associated Commands
ADD MODULE ATTRIBUTE -PIPELINE_RETIME
Modeling Messages
F26
Message
Merged dual-port DLAT(s) into single port DLAT(s)
Description
Dual-port DLATs were merged into single-port DLATs. This operation is enabled when you
use the SET FLATTEN MODEL -LATCH_MERGE_PORT command.
Example
F26: Merged dual-port DLAT(s) into single port DLAT(s)
(Occurrence: 1)
1: Merged multi-port DLAT /l0 into single port DLAT
This message indicates that dual-port DLAT l0 was merged into a single port DLAT using
the following command:
set flatten model -latch_merge_port
Circuit example:
DLAT l0 (q,,1b0,1b0,ck,d0,sck,d1);
Result :
and u0 (n1,d0,ck);
and u1 (n2,d1,sck);
or u2 (din,n1,n2);
or u3 (ck_or,ck,sck);
DLAT l0 (q,,1b0,1b0,ck_or,din);
Associated Commands
SET FLATTEN MODEL -LATCH_MERGE_PORT
Modeling Messages
F27
Message
Converted internal input port(s) to inout port(s)
Description
Internal input ports were converted into inout ports because the input port does not drive any
instances.
Example
F27: Converted internal input port(s) to inout port(s)
(Occurrence: 1)
1: port /u0/y in module AN2
This message indicates that port y of module AN2 does not drive any load.
Circuit example:
module AN2 (y,z,a,b);
input a,b,y;
output z;
and u0 (z,a,b);
buf u1 (y,a);
endmodule
module ckt (y,z,a,b);
input a,b;
output y,z;
AN2 u0 (y,z,a,b);
endmodule
Modeling Messages
F28
Message
Converted internal output port(s) to inout port(s)
Description
Internal output ports were converted to inout ports because the output port is not driven.
Example
F28: Converted internal output port(s) to inout port(s)
(Occurrence: 1)
1: port /u0/a in module AN3 due to high-impedance (Z) gates
This message indicates that port a of module AN3 is not driven by any driver.
Circuit example:
module AN3 (z,a,b,c);
input b,c;
output z,a;
and u0 (z,a,b,c);
endmodule
module ckt (z,a,b,c);
input a,b,c;
output z;
AN3 u0 (z,a,b,c);
endmodule
Modeling Messages
F30
Message
Ignored weak device(s) due to the existence of strong device(s)
Description
Any weak devices were ignored due to the existence of a stronger device in a multiple-driven
net.
Example
F30: Ignored weak device(s) due to the existence of strong device(s)
(Occurrence: 1)
1: n1
This message indicates that a weak device buffer u0 driving net n1 was ignored due to the
existence of stronger buffer device u1 driving the same net n1.
Circuit example:
buf (weak0,weak1)u0 (n1,a);
buf u1 (n1,b);
buf u2 (z,n1);
Modeling Messages
F32
Message
Created Z gate(s) for floating net(s) and floating pin(s)
Description
Z gates were created for oating nets and oating pins.
Example
F32: Created Z gate(s) for floating net(s) and floating pin(s)
(Occurrence: 1)
1: c
This message indicates that a net c of instance u0 is not driven.
Circuit example:
module ckt (z,a,b);
input a,b;
output z;
wire c;
and u0 (z,a,b,c);
endmodule
Modeling Messages
F34
Message
Convert X assignment(s) as dont care(s)
Description
X assignments were converted to dont cares. This operation is enabled when you use the
SET X CONVERSION command.
Example
F34: Convert X assignment(s) as dont care(s) (Occurrence: 1)
1: Converted X assignment at N$1 be dont care
This message indicates that assignment in RTL code default: z = 1bx is converted
to dont cares through the following command:
set x conversion DC -golden
Note: This option in the golden design is enabled by default.
Circuit example:
always @(a or b or sel)
begin
case (sel)
2b01 : z = a;
2b10 : z = b;
default : z = 1bx;
endcase
end
Associated Commands
SET X CONVERSION
Modeling Messages
F34.1
Message
Convert X assignment(s) as zero(s)
Description
X assignments were converted to zero. This operation is enabled when you use the SET X
CONVERSION command.
Example
F34.1: Convert X assignment(s) as zero(s) (Occurrence: 1)
1: Converted X assignment N$1 as 0
This message indicates that X assignment in RTL code default: z = 1bx was
converted to logic ZERO using the following command:
set x conversion 0
Circuit example:
begin
case (sel)
2b01 : z = a;
2b10 : z = b;
default : z = 1bx;
endcase
end
Associated Commands
SET X CONVERSION
Modeling Messages
F34.2
Message
Convert X assignment(s) as one(s)
Description
X assignments were converted to one. This operation is enabled when you use the SET X
CONVERSION command.
Example
F34.2: Convert X assignment(s) as one(s) (Occurrence: 1)
1: Converted X assignment N$1 as 1
This message indicates that an X assignment in the RTL code default: z = 1bx was
converted to logic ONE using the following command:
set x conversion 1
Circuit example:
begin
case (sel)
2b01 : z = a;
2b10 : z = b;
default : z = 1bx;
endcase
end
Associated Commands
SET X CONVERSION
Modeling Messages
F34.3
Message
Converted 1 X assignment(s) as E(s)
Description
An X assignment was converted to an error (E) gate . This operation is enabled when you use
the SET X CONVERSION command. If the X assignment space of the Revised design is within
the X assignment space of the Golden design, then the E gate is marked as an extra
unmapped point (redundant gate).
Example
F34.2: Convert 1 X assignment(s) as E (Occurrence: 1)
1: Converted X assignment N$1 as E
This message indicates that an X assignment in the RTL code default: z = 1bx was
converted to logic E using the following command:
set x conversion E
Circuit example:
begin
case (sel)
2b01 : z = a;
2b10 : z = b;
default : z = 1bx;
endcase
end
Associated Commands
SET X CONVERSION
Modeling Messages
F36
Message
Dont care(s) added due to $constraint(s)
Description
dont cares were added due to $constraints.
Example
F36: Dont care(s) added due to $constraint(s) (Occurrence: 1)
1: u0: DFF q_reg
This message indicates that constraint cstr_0 for register q_reg is added to dont cares.
Circuit example:
begin
case (sel)
2b01 : z = a;
2b10 : z = b;
default : z = 1bx;
endcase
end
$constraint cstr_0 ($one_hot (sel));
q <= z;
Modeling Messages
F39
Message
Added output Z gate(s)
Description
Output Z gates were added. This operation is enabled by SET FLATTEN MODEL
-OUTPUT_Z, which is enabled by default.
Example
F39: Added output Z gate(s) (Occurrence: 1)
1: /z
This message indicates that a Z gate was added at the output z using the following
command:
set flatten model -output_z
Circuit example:
module ckt (z,a,sel);
input a,sel;
output z;
bufif0 u0 (z,a,sel);
endmodule
Associated Commands
SET FLATTEN MODEL -OUTPUT_Z
Modeling Messages
F41
Message
Converted set/reset loop(s) to data-hold(s)
Description
The Conformal software converted a data-hold function that is modeled using an
asynchronous set and an asynchronous reset functions, to a mux data-hold function
Example
F41: Converted set/reset loop(s) to data-hold(s) (Occurrence: 1)
1: DFF Q_reg
Circuit example:
assign RN = !Q & EN;
assign SET = Q & EN;
always @(posedge CK or posedge RN or posedge SET)
begin
if (RN)
Q <= 1b0;
else if (SET)
Q <= 1b1;
else
Q <= D;
end
Modeling Messages
F42
Message
Unfolded DFF to latches
Description
A DFF was unfolded into two DLATs. This operation is enabled when you use the REMODEL
-UNFOLD_DFF command, which species that a DFF should be converted into two DLATs
that are in a master-slave conguration.
Example
F42: Unfolded DFF to latches (Occurrence: 1)
1: /q_reg
This message indicates you converted a single DFF into a master-slave DLATs using the
following command:
remodel -unfold_dff
Circuit example:
q <= d;
Associated Commands
REMODEL -UNFOLD_DFF
Modeling Messages
F43
Message
Added DLATs to cut loops
Description
DLATs were added to cut combination loops.This operation is enabled by the SET FLATTEN
MODEL command.
Example
F43: Added DLATs to cut loops (Occurrence: 1)
1: /u0
This message indicates that a DLAT was added at instance driver u0 to cut the
combinational loop using the following command:
set flatten model -loop_as_dlat
Circuit example:
xor u1 (q,n1);
Associated Commands
SET FLATTEN MODEL
5
Tcl Command Entry Mode Support
Tcl Design Access Commands
I nd on page 865
I get_compare_points on page 866
I get_compare_result on page 866
I get_exit_code on page 867
I get_current_module on page 868
I get_fanins on page 868
I get_fanouts on page 868
I get_gate_count on page 868
I get_gate_id on page 868
I get_gate_type on page 868
I get_handle_type on page 869
I get_instances on page 869
I get_keypoint on page 870
I get_map_points on page 871
I get_module_denition on page 871
I get_names on page 872
I get_nets on page 872
I get_parent on page 873
I get_pins on page 874
I get_ports on page 875
I get_primitive_type on page 876
I get_property on page 877
I get_root_module on page 878
I get_unmap_points on page 878
I set_current_module on page 879
Tcl Utility Commands
I echo_result on page 879
I get_license_mode on page 879
I get_version_info on page 879
I help on page 880
I objtype on page 880
I usage on page 880
nd
find <-Module | -Instance | -Port [-Input | -Output | -Bidir]
| -Pin [ -Input | -Output| -Bidir]
| -Net | -Gate | -Id>
[-Single] <object_name>
Returns a design database object handle or list of handles for a design object or list of objects.
-Module The specied object_name is a module name.
-Instance The specied object_name is an instance name.
-Port The specied object_name is a port name.
-Input species an input port.
-Output species an output port.
-Bidir species a bidirectional port.
-Pin The specied object_name is a pin name.
-Input species an input pin.
-Output species an output pin.
-Bidir species a bidirectional pin.
-Net The specied object_name is a net name.
-Gate Species a attened gate name.
-Id Species the ID of a attened gate.
Note: Conformal automatically assigns IDnumbers. They can
differ from one version to another. Always use ID numbers
assigned by the Conformal version you are currently running.
-Golden Applies to the Golden design only.
-Revised Applies to the Revised design only.
-Both Applies to the Golden and Revised designs.
-Single Returns none or the rst found object handle instead of a list.
<object_name> This is the name of a specied design object. It is a name in
module context or hierarchical context.
Note: Hierarchical objects start with /.
Example
The following example shows how the return value of the command can be saved to a
variable for later reference:
set abc1 [find -instance /u1/U2]
set abc2 [find -single -instance /u1/U2]
get_nets [lindex $abc1 0]

get_nets $abc2
get_compare_points
get_compare_points
[key_point_types] [result_types]
[sort_type] [-count]
Queries for multiple objects and returns a list of compare point object handles or a count of
the selected compare points. A compare point handle is a MAP_POINT object handle.
get_compare_result
get_compare_result <obj_handle>
Returns compare results for the specied compare point. The key point is an object handle
of the COMPARE_POINT type. The returned result is POS_EQ, NEG_EQ, DIFF,
NOT_COMPARED, or ABORT.
key_point_types Species the key point type(s), which can be one or more of
-PO, -DFF, -DLAT, -BBOX, or -CUT.
result_types Species the result type(s), which can be one or more of
-POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.
sort_type Species the sort type, which can be either -Size or
-Support.
-count Returns a count of the selected compare points rather than a
list of compare point handles.
get_exit_code
get_exit_code
Returns the run status without exiting the Conformal software. The status codes are:
Note: For bits 0, and 2 through 5, once they are set to 1, they will remain at 1. For bit 1, once
it is set to 0, it will remain at 0.
Examples
I Case 1:
Start Conformal and then exit immediately
Status = 2 (00010 in binary). There are no equivalent points since there was no
comparison. Thus, bit 1 is set.
I Case 2:
Comparison produced a non-equivalent point, an abort point, and an equivalent point.
Status = 48 (110000 in binary). Bits 4 and 5 are set to ag the abort and non-equivalent
points.
I Case 3:
Comparison produced all non-equivalent points.
Status = 18 (010010 in binary). Bits 1 and 4 are set to show two conditions: During this
session, Conformal found no equivalent points and the comparison produced
Bit Condition
0 Internal Error
1 Status before comparison
2 Command error
3 Unmapped points or extra POs
4 Non-equivalent points during comparison
5 Abort or uncompared points exist during any comparisons.
6 Abort or uncompared points exist during the last comparision or hierarchical
comparison.
get_current_module
get_current_module
Returns the MODULE handle for the current module.
get_fanins
get_fanins <obj_handle>
Queries for multiple objects and returns a list of fan-in gate handles for the specied gate
object handle. The type of object handle is a FLAT_GATE.
get_fanouts
get_fanouts <obj_handle>
Queries for multiple objects and returns a list of fan-out gate handles for the specied gate
object handle. The type of object handle is a FLAT_GATE. The syntax is as follows:
get_gate_count
get_gate_count [-golden |-revised]
Returns the gate count for the specied design. The default design is Golden.
get_gate_id
get_gate_id <obj_handle>
Returns the gate id for the specied attened gate object handle.
Note: The Conformal software automatically assigns ID numbers. They can differ from one
version to another. Always use ID numbers assigned by the software version you are running.
get_gate_type
get_gate_type <obj_handle>
Returns the gate type of the specied obj_handle. The type of object handle is
FLAT_GATE.
get_handle_type
get_handle_type <obj_handle>
Returns the object type of the specied object handle. The returned result is one of the
following strings:
I MODULE
I MODULE_INSTANCE
I MODULE_PORT
I MODULE_INSTANCE_PIN
I MODULE_NET
I HIERARCHY_INSTANCE
I HIERARCHY_PORT
I HIERARCHY_INSTANCE_PIN
I HIERARCHY_NET
I FLAT_GATE
I MAP_POINT
get_instances
get_instances [-all_hierarchy] <obj_handle>
Queries for multiple objects and returns a list of instances associated with the specied object
handle.
-all_hierarchy Use this argument in combination with the HIERARCHY_NET
object handle type. It returns a list of hierarchical instance
object handles that are associated with the given hierarchical
net object.
get_keypoint
get_keypoint [-golden | -revised] <obj_handle>
Returns the key point (FLAT_GATE type) of a specied compare point. The object handle will
be a MAP_POINT type.
<obj_handle> The specied obj_handle as one of the following types:
I MODULE: lists the instances in the module
I MODULE_INSTANCE: lists the instance that identies itself
I MODULE_PORT: not applicable
I MODULE_INSTANCE_PIN: lists the instances whose pins
are listed in the specied object handle
I MODULE_NET: lists the instances that connect with the net
I HIERARCHY_INSTANCE: lists the hierarchical instance that
identies itself
I HIERARCHY_PORT: lists the hierarchical instance of which
pins include this pin
I HIERARCHY_INSTANCE_PIN: lists the hierarchical
instance of which pins include this pin
I HIERARCHY_NET: lists the hierarchical instances that
connect with the net in a hierarchical context
I FLAT_GATE: lists the hierarchical instance that represents
the attened gate
I MAP POINT: not applicable
get_map_points
get_map_points
Queries for multiple objects and returns a list of map point object handles or a count of the
selected map points. A map point handle is a MAP_POINT object handle.
get_module_denition
get_module_definition <obj_handle>
Returns a module denition for the specied object handle, where <obj_handle> is one of
the following types:
I MODULE: dene itself
I MODULE_INSTANCE: dene the module of the specied instance
I MODULE_PORT: not applicable
I MODULE_INSTANCE_PIN: not applicable
I MODULE_NET: not applicable
I HIERARCHY_INSTANCE: dene the module of the specied instance in a hierarchical
context.
I HIERARCHY_PORT: not applicable
I HIERARCHY_INSTANCE_PIN: not applicable
-PO, -DFF, -DLAT, -BBOX, or -CUT.
-POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.
-Support.
-count Returns a count of the selected map points rather than a list
of map point handles.
I HIERARCHY_NET: not applicable
I FLAT_GATE: dene the module of the specied attened gate
get_names
get_names <obj_handles>
Queries for multiple objects and returns a name or list of names for the specied object
handles.
get_nets
get_nets [-all_hierarchy] <obj_handle>
Queries for multiple objects and returns a list of nets for the specied object handle.
-all_hierarchy Use this argument in combination with the HIERARCHY object
handle type. It returns a list of hierarchical net object handles
that are associated with the given hierarchical design object (for
example, HIERARCHY_INSTANCE).
get_parent
get_parent <obj_handle>
Returns a handle to the parent of the specied object handle, where <obj_handle> is one
of the following types:
I MODULE: not applicable
I MODULE_INSTANCE: return the module that contains the specied instance
I MODULE_PORT: return the module that contains the specied port
I MODULE_INSTANCE_PIN: return the module that contains the specied pin
I MODULE_NET: return the module that contains the specied net
I MODULE: lists the nets of the specied module
I MODULE_INSTANCE: lists the nets that connect with the
specied instance
I MODULE_PORT: lists the nets that connect with the specied
port
I MODULE_INSTANCE_PIN: lists the nets that connect with
the specied pin
I MODULE_NET: lists the net that identies itself
I HIERARCHY_INSTANCE: lists the nets that connect with the
specied instance in a hierarchical context
I HIERARCHY_PORT: lists the nets that connect with the
specied port in a hierarchical context
I HIERARCHY_INSTANCE_PIN: lists the nets that connect
with the specied pin in a hierarchical context
I HIERARCHY_NET: lists the net that identies itself
I FLAT_GATE: lists the nets that connect with the specied
attened gate in a hierarchical context
I HIERARCHY_INSTANCE: return the module denition of the instance
I HIERARCHY_PORT: return the hierarchical instance that contains the specied port in a
hierarchical context
I HIERARCHY_INSTANCE_PIN: return the hierarchical instance that contains the
specied pin in a hierarchical context
I HIERARCHY_NET: return the hierarchical instance that contains the specied net in a
hierarchical context
I FLAT_GATE: return the hierarchical instance that contains the specied attened gate in
a hierarchical context
get_pins
get_pins [-all_hierarchy] <obj_handle>
Queries for multiple objects and returns a list of pins associated with the specied object
handle.
object handle type. It returns a list of hierarchical instance pin
object handles that are associated with the given hierarchical
net object.
get_ports
get_ports [-all_hierarchy] <obj_handle>
Queries for multiple objects and returns a list of ports associated with the specied object
handle.
I MODULE: lists the pins of the specied module
I MODULE_INSTANCE: lists the pins of the specied instance
I MODULE_PORT: lists the pins that connect with the net of the
specied port
I MODULE_INSTANCE_PIN: lists the pin that identies itself
I MODULE_NET: lists the pins that connect with the specied
net
I HIERARCHY_INSTANCE: lists the pins of the specied
instance in a hierarchical context
I HIERARCHY_PORT: lists the pins that connect with the net
of the specied port in a hierarchical context
I HIERARCHY_INSTANCE_PIN: lists the nets that connect
with the specied pin in a hierarchical context
I HIERARCHY_NET: lists the pin that identies itself
I FLAT_GATE: lists the pins of the specied attened gate in
a hierarchical context
object handle type. It returns a list of hierarchical port object
handles that are associated with the given hierarchical net
object.
get_primitive_type
get_primitive_type <obj_handle>
Returns the primitive type for the specied instance object handle, where <obj_handle> is
one of the following:
I MODULE_INSTANCE
I FLAT_GATE
I MODULE: lists the ports of the specied module
I MODULE_INSTANCE: lists the ports of the specied
instance
I MODULE_PORT: lists the port that identies itself
I MODULE_INSTANCE_PIN: returns the relative port of the
specied pin
I MODULE_NET: lists the ports that connect with the specied
net
I HIERARCHY_INSTANCE: lists the ports of the specied
instance in a hierarchical context
I HIERARCHY_PORT: lists the port that identies itself
I HIERARCHY_INSTANCE_PIN: returns the relative port of
the specied pin in a hierarchical context
I HIERARCHY_NET: lists the ports that connect with the
specied net in a hierarchical context
I FLAT_GATE: lists the ports of the specied attened gate
get_property
get_property <obj_handle> <property_type>
Returns the property of the specied object handle. The following lists the object handle one
of the following types, with their property types and return values.
I MODULE
Property Type: BlackBox; Return Value: YES, NO
Property Type: InLib; Return Value: YES, NO
Include the InLib property to test whether the module denition is dened in the library
space (YES) or design space (NO)that is, it tests whether the module denition is
imported by the READ LIBRARY or READ DESIGN command.
I MODULE_INSTANCE
Property Type: Primitive; Return Value: YES, NO
Property Type: CutPoint; Return Value: YES, NO
Include the CutPoint property to test whether the module denition is a cut pointthat is,
it tests whether you have run the ADD CUT POINT command on this module denition.
I MODULE_PORT
Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR
I MODULE_INSTANCE_PIN
I MODULE_NET
Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1,
TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE
Note: GLOBAL applies to those signals that cross multiple modules (for example,
assertions).
I HIERARCHY_PORT
I HIERARCHY_INSTANCE_PIN
I HIERARCHY_NET
Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1,
TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE
Note: GLOBAL applies to those signals that cross multiple modules (for example,
assertions).
I FLAT_GATE
Property Type: Golden; Return Value: YES, NO
Property Type: Revised; Return Value: YES, NO
Property Type: Result; Return Value: POS_EQ, NEG_EQ, DIFF, ABORT, UNKNOWN
get_root_module
get_root_module [-golden | -revised]
Returns the name of the root module for the specied design. The default design is Golden.
get_unmap_points
get_unmap_points
Queries for multiple objects and returns a list of unmap point object handles or a count of the
selected unmap points. An unmap point handle is a MAP_POINT object handle.
-PI, -PO, -DFF, -DLAT, -BBOX, or -CUT.
-Extra, -UNReachable, or -NOTmapped.
-Support.
set_current_module
set_current_module <[which_design] module_name | obj_handle>
Changes the current module. By default, the current module is the root module.
echo_result
echo_result [-on | -off]
Turns the command result printing on or off.
get_license_mode
get_license_mode
Returns the current license mode. For example, custom, ultra, asic, lp, rcv, verify,
and ccd.
get_version_info
get_version_info
Returns a TCL list of the version related info, including version_num, build_date, 32 or
64 bit, host name, and platform.
-count Returns a count of the selected unmap points rather than a
list of unmap point handles.
which_design Includes one or more of the following options.
Note: which_design is ignored if you use <obj_handle>.
-golden sets the current module for the Golden design. This
option is the default value.
-revised sets the current module for the Revised design.
<module_name> The specied name is a module name.
<obj_handle> This argument is a MODULE handle.
help
help [command_name]
Returns the command usage of the specied command or a list of all Conformal Tcl
commands if you do not specify a command.
objtype
objtype <obj_handle>
Returns the type of an native TCL object, for example string and list, or Conformal design
object handle type (i.e. vpxhandle).
usage
usage [-CPU | -MEM]
Displays usage values in Tcl scripts for total CPU run time and peak memory use.
Index
Numerics
3-2-1 rule 26
A
-all option 30
B
-both option 31
C
case sensitivity
in command syntax 26
commands
shorthand for entry 26
conventions for syntax 30
D
directives
rule check numbers and messages 522
H
HELP command 27
hierarchical design, naming rules
report 300
M
MAN command 27
man directory 27
messages
generated by HDL (RTL) rule check, see
individual messages 526
O
online help
Tcl commands 27
R
reports, examples of
environment 300
S
shorthand, for command entry 26
SPICE
HDL rules 720
syntax
rules 26
System Verilog
HDL rules 733
U
UNIX commands, using in Conformal
with exclamation (!) point 30
with system command 30
usage, command syntax help (Tcl) 27

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Equivalence Checking Reference Manual

Equivalence Checking solutions:

commands. The commands are

analyze multiplier -cdp_info

(Library extensions) A list of library extensions you can

set flatten model -seq_merge

always @(clkn or dinn) if (clkn) qstate = dinn;

glob1 <= in0 or in1;

glob1 <= in0 or in1;

parameter [4:0] // synopsys enum fsm_states

get_nets [lindex $abc1 0]

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