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5 4 3 2 1 TERASIC CYCLONE II EP2C35 DAUGHTER BOARD SCHEMATIC CONTENT PAGE D
5
4
3
2
1
TERASIC CYCLONE II EP2C35 DAUGHTER BOARD
SCHEMATIC
CONTENT
PAGE
D
D
TOP
COVER PAGE , TOP
01
~ 03
AUDIO
WM8731
04
~ 04
DISPLAY
LCD , LED , 7SEGMENT
05
~ 06
EP2C35
EP2C35 BANK1
BANK8
, POWER , CONFIG
07
~ 11
ETHERNET
DM9000A
12
~ 12
INPUT
CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT
13
~ 17
MEMORY
SRAM , DRAM , FLASH , SD CARD
18
~ 19
POWER
POWER
20
~ 20
C
C
USB BLASTER
USB BLASTER
21
~ 21
USB DEVICE
USB DEVICE
22
~ 22
VIDEO
ADV7181 , ADV7123
23
~ 24
B
B
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
<Doc>
<Doc>
<Doc>
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
1
1
1
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 DC USB USB USB LINE LINE MIC TV VGA RJ45
5
4
3
2
1
DC
USB
USB
USB
LINE LINE MIC
TV
VGA
RJ45
PS2
RS232
9V
BLASTER
DEVICE
HOST
IN
OUT
IN
DECODER
OUTPUT
KEYBORAD
D
D
FT245
ISP1362
WM8731
ADV7181
ADV7123
DM9000A
M3128
LCD MODULE
C
C
EP2C35
SD CARD
EPCS16
IrDA
SDRAM
SRAM
FLASH
B
B
EXT CLK
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
PLACEMENT
PLACEMENT
PLACEMENT
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
2
2
2
of
of
of
24
24
24
5
4
3
2
1
SW17
LED17
SW16
LED16
SW15
LED15
SW14
LED14
HEX7
SW13
LED13
HEX6
SW12
LED12
SW11
LED11
HEX5
SW10
LED10
HEX4
SW9
LED9
SW8
LED8
LED18
SW7
LED7
SW6
LED6
HEX3
SW5
LED5
HEX2
SW4
LED4
HEX1
SW3
LED3
HEX0
SW2
LED2
SW1
LED1
SW0
LED0
LED26
LED25
LED24
KEY3
LED23
LED22
KEY2
LED21
LED20
KEY1
LED19
KEY0
GPIO_0
GPIO_1
5 4 3 2 1 AUDIO PAGE 4 EP2S35 PAGE 7-11 PWR PAGE 20 AUD_BCLK
5
4
3
2
1
AUDIO
PAGE 4
EP2S35
PAGE 7-11
PWR
PAGE 20
AUD_BCLK
AUD_ADCDAT
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACDAT
AUD_ADCDAT
NCONFIG
TDO
NCONFIG
TDO
AUD_DACLRCK
TDI
DATA0
I2C_SDAT
I2C_SCLK
AUD_DACLRCK
AUD_ADCLRCK
DATA0
TMS
I2C_SDAT
CONF_DONE
I2C_SCLK
TMS
TDI
LED[5 26]
LED[5 26]
FLASH_A[0 21]
AUD_XCK
NSTATUS
AUD_XCK
CONF_DONE
FLASH_A[0 21]
SD_CLK
NSTATUS
SD_CLK
TCK
SD_CMD
D
NCE
TCK
SD_CMD
D
SD_DAT3
NCE
SD_DAT3
ASDO
HEX6_D[0 6]
DISPLAY
PAGE 5-6
SW[10 17]
HEX0_D[0 6]
GPIO_B[0 71]
ASDO
SW[10 17]
HEX4_D[0 6]
HEX4_D[0 6]
HEX6_D[0 6]
USB BLASTER
PAGE 21
HEX0_D[0 6]
GPIO_B[0 71]
HEX7_D[0 6]
HEX7_D[0 6]
DATA0
NCSO
DATA0
NCSO
HEX1_D[0 6]
HEX5_D[0 6]
TDO
DCLK
HEX1_D[0 6]
HEX5_D[0 6]
HEX2_D[0 6]
FLASH_D[0 7]
LINK_D3
FLASH_D[0 7]
TDO
DCLK
FLASH_CE
ASDO
HEX2_D[0 6]
FLASH_CE
LINK_D3
ASDO
HEX3_D[0 6]
SD_DAT
FLASH_OE
TMS
HEX3_D[0 6]
HEX4_D[0 6]
KEY[0 3]
SD_DAT
FLASH_OE
TMS
FLASH_RESET
TDI
HEX4_D[0 6]
KEY[0 3]
FLASH_RESET
TDI
HEX5_D[0 6]
SW[6 9]
FLASH_WE
NCONFIG
HEX5_D[0 6]
FLASH_WE
NCONFIG
HEX6_D[0 6]
DCLK
HEX6_D[0 6]
SW[6 9]
VGA_B[0 9]
TCK
DCLK
VGA_B[0 9]
TCK
HEX7_D[0 6]
NCSO
VGA_CLOCK
CONF_DONE
HEX7_D[0 6]
NCSO
VGA_CLOCK
CONF_DONE
LCD_BLON
SRAM_D[0 15]
LCD_BLON
SRAM_D[0 15]
VGA_R[0 9]
TD_D[0 7]
VGA_R[0 9]
NCE
NCE
LCD_ON
VGA_G[0 9]
NSTATUS
LCD_ON
TD_D[0 7]
VGA_G[0 9]
NSTATUS
LCD_WR
ENET_D[0 15]
VGA_BLANK
LINK_D0
LCD_WR
ENET_D[0 15]
VGA_BLANK
LINK_D0
LCD_D[0 7]
VGA_SYNC
LINK_D1
LCD_D[0 7]
VGA_SYNC
LINK_D1
LCD_EN
TD_HS
VGA_VS
LINK_D2
LCD_EN
VGA_VS
LINK_D2
LCD_RS
TD_VS
VGA_HS
12MHZ
LCD_RS
TD_VS
TD_HS
VGA_HS
12MHZ
LED[0 26]
27MHZ
TD_RESET
LED[0 26]
27MHZ
TD_RESET
ENET_INT
ENET_RESET
ENET_INT
ENET_RESET
LINK_D0
25MHZ
LINK_D0
25MHZ
LINK_D1
ENET_CMD
ENET_CMD
ETHERNET
PAGE 12
LINK_D2
LINK_D1
ENET_IOR
USB DEVICE
PAGE 22
LINK_D2
ENET_IOR
ENET_IOW
OTG_WE
OTG_INT1
ENET_IOW
OTG_WE
OTG_INT1
ENET_RESET
AUD_ADCDAT
ENET_CS
OTG_OE
OTG_INT0
C
ENET_RESET
ENET_CS
OTG_OE
OTG_INT0
25MHZ
ENET_INT
I2C_SDAT
AUD_ADCDAT
C
OTG_RESET
OTG_DREQ1
25MHZ
ENET_INT
I2C_SDAT
OTG_RESET
OTG_DREQ1
ENET_CMD
UART_RXD
OTG_DACK0
OTG_DREQ0
ENET_CMD
ENET_IOR
PS2_DAT
ENET_IOR
UART_RXD
OTG_DACK0
OTG_DREQ0
OTG_DACK1
PS2_DAT
OTG_DACK1
ENET_IOW
SW[3 5]
LINK_D3
OTG_CS
ENET_IOW
SW[3 5]
LINK_D3
OTG_CS
ENET_CS
OTG_DREQ1
AUD_XCK
OTG_A1
ENET_CS
ENET_D[0 15]
OTG_DREQ0
ENET_D[0 15]
OTG_DREQ1
AUD_XCK
OTG_A1
AUD_BCLK
OTG_A0
OTG_DREQ0
AUD_BCLK
OTG_A0
OTG_INT1
AUD_DACDAT
OTG_D[0 15]
AUD_DACDAT
OTG_D[0 15]
OTG_INT0
OTG_INT1
AUD_DACLRCK
OTG_LSPEED
OTG_INT0
AUD_DACLRCK
OTG_LSPEED
AUD_ADCLRCK
OTG_FSPEED
AUD_ADCLRCK
OTG_FSPEED
UART_TXD
12MHZ
UART_TXD
12MHZ
OTG_D[0 15]
PS2_CLK
PS2_CLK
SW[0 2]
LCD_D[0 7]
INPUT
IN/OUT
DRAM_D[0 15]
GPIO_B[0 71]
SW[0 17]
50MHZ
SW[0 2]
OTG_D[0 15]
LCD_D[0 7]
LCD_WR
DRAM_D[0 15]
LCD_WR
LCD_EN
GPIO_B[0
71]
SW[0
17]
LCD_EN
PS2_CLK
UART_RXD
EXT_CLOCK
LCD_RS
VIDEO
PAGE 23-24
PS2_CLK
UART_RXD
PS2_DAT
KEY[0 3]
IRDA_RXD
PS2_DAT
KEY[0 3]
EXT_CLOCK
50MHZ
LCD_RS
LCD_BLON
VGA_BLANK
TD_D[0 7]
IRDA_RXD
LCD_BLON
VGA_BLANK
TD_D[0 7]
UART_TXD
50MHZ
LCD_ON
VGA_R[0 9]
TD_HS
UART_TXD
50MHZ
LCD_ON
VGA_R[0 9]
TD_HS
IRDA_TXD
EXT_CLOCK
OTG_LSPEED
VGA_G[0 9]
27MHZ
IRDA_TXD
EXT_CLOCK
OTG_LSPEED
VGA_G[0 9]
27MHZ
IRDA_RXD
OTG_FSPEED
VGA_B[0 9]
TD_VS
IRDA_RXD
OTG_FSPEED
VGA_B[0 9]
TD_VS
OTG_DACK1
VGA_SYNC
OTG_DACK1
VGA_SYNC
OTG_DACK0
VGA_CLOCK
OTG_DACK0
VGA_CLOCK
OTG_RESET
VGA_HS
OTG_RESET
VGA_HS
VGA_VS
HEX3_D[0 6]
VGA_VS
MEMORY
PAGE 18-19
TD_RESET
B
B
HEX2_D[0 6]
TD_RESET
FLASH_RESET
FLASH_D[0 7]
HEX2_D[0 6]
HEX3_D[0 6]
I2C_SDAT
FLASH_RESET
FLASH_D[0 7]
HEX1_D[0 6]
HEX1_D[0 6]
I2C_SDAT
FLASH_WE
HEX0_D[0 6]
I2C_SCLK
FLASH_WE
HEX0_D[0 6]
I2C_SCLK
FLASH_A[0 21]
OTG_CS
FLASH_A[0 21]
OTG_CS
FLASH_CE
OTG_OE
FLASH_CE
OTG_OE
FLASH_OE
OTG_WE
FLASH_OE
OTG_WE
DRAM_A[0 11]
OTG_A0
DRAM_A[0 11]
OTG_A0
DRAM_LDQM
OTG_A1
DRAM_LDQM
OTG_A1
DRAM_UDQM
DRAM_UDQM
LED[0 4]
LED[0 4]
DRAM_CLK
DRAM_CLK
DRAM_CKE
I2C_SCLK
DRAM_CKE
I2C_SCLK
DRAM_BA0
DRAM_A[0 11]
DRAM_BA0
DRAM_A[0 11]
DRAM_BA1
DRAM_WE
DRAM_BA1
DRAM_WE
DRAM_D[0 15]
DRAM_CLK
DRAM_D[0 15]
DRAM_CLK
DRAM_WE
DRAM_CAS
DRAM_WE
DRAM_CAS
DRAM_CAS
DRAM_CKE
DRAM_CAS
DRAM_CKE
DRAM_RAS
DRAM_RAS
DRAM_RAS
DRAM_RAS
DRAM_CS
DRAM_BA0
DRAM_CS
DRAM_BA0
SRAM_A[0 17]
DRAM_CS
SRAM_A[0 17]
DRAM_CS
SRAM_D[0 15]
DRAM_BA1
SRAM_D[0 15]
DRAM_BA1
SRAM_WE
DRAM_LDQM
SRAM_WE
DRAM_LDQM
SRAM_CE
DRAM_UDQM
SRAM_CE
DRAM_UDQM
SRAM_OE
SRAM_CE
SRAM_OE
SRAM_CE
SRAM_UB
SRAM_OE
SRAM_UB
SRAM_OE
A
SRAM_LB
SRAM_WE
A
SRAM_LB
SRAM_WE
SD_DAT
SRAM_UB
SD_DAT
SRAM_UB
SD_CMD
SRAM_LB
SD_CMD
SRAM_LB
SD_CLK
SRAM_A[0 17]
SD_CLK
SRAM_A[0 17]
SD_DAT3
IRDA_TXD
SD_DAT3
IRDA_TXD
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
TOP LEVEL
TOP LEVEL
TOP LEVEL
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
3
3
3
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 J2J2 LINEINLINEIN VCC33 VCC33 R2 R2 R3 R3 C1C1 1U1U
5
4
3
2
1
J2J2
LINEINLINEIN
VCC33
VCC33
R2
R2
R3
R3
C1C1
1U1U
R1R1
4.7K4.7K
D
2K
2K
2K
2K
D
C2C2
1U1U
R4R4
4.7K4.7K
I2C_SCLK
I2C_SDAT
R5
R5
R6
R6
4.7K
4.7K
4.7K
4.7K
I2C ADDRESS READ IS 0x34
I2C ADDRESS WRITE IS 0x35
AGND
GND
AGND
AGND
I2C_SDAT
J1J1
MICINMICIN
I2C_SCLK
R7R7
330330
U1
U1
C3
C3
1U
1U
R8R8
680680
C
C
1
21
C4
C4
MCLK
MBIAS
2
20
XTO
VMID
10U
10U
3
19
R9
R9
AGND
A_VCC33
DCVDD
AGND
AGND
4
18
C5
C5
47K
47K
GND
DGND
AVDD
A_VCC33
5
17
DBVDD
ROUT
1000P
1000P
6
16
J3J3
LINEOUTLINEOUT
CLKO
LOUT
7
15
BCLK
HPGND
AGND
AGND
AGND
WM8731
WM8731
QFN28-0.45
QFN28-0.45
B
B
AUD_XCK
TC1
TC1
100U/6.3V
100U/6.3V
A_VCC33
AUD_BCLK
C-1210+
C-1210+
AUD_DACDAT
AGND
AUD_DACLRCK
AUD_ADCDAT
A_VCC33
AUD_ADCLRCK
TC2
TC2
100U/6.3V
100U/6.3V
C-1210+
C-1210+
R10
R10
R11
R11
47K
47K
47K
47K
BC1
BC1
BC2
BC2
BC3
BC3
BC4
BC4
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
AGND
AGND
R12R12
00
GND
AGND
AGND
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
AUDIO
AUDIO
AUDIO
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
4
4
4
of
of
of
24
24
24
5
4
3
2
1
8
28
DACDAT
SCLK
9
27
DACLRCK
SDIN
10
26
ADCDAT
CSB
11
25
ADCLRCK
MODE
12
24
HPVDD
LLINEIN
13
23
LHPOUT
RLINEIN
14
22
RHPOUT
MICIN
5
5
5
NCL
NCL
NCL
2
2
2
R
R
R
4
4
4
NCR
NCR
NCR
1
1
1
L
L
L
3
3
3
GND
GND
GND
5 4 3 2 1 RN1 RN1 Q1Q1 80508050 Q2Q2 85508550 LED0 1 3 1
5
4
3
2
1
RN1
RN1
Q1Q1
80508050
Q2Q2
85508550
LED0
1
3
1
2
LED1
3
4
LED2
LEDR0LEDR0 LEDRLEDR
5
6
LED3
7
8
C6
C6
R13
R13
1U
1U
330
330
LEDR1LEDR1 LEDRLEDR
VCC5
680
680
VCC43
D
D
GND
LEDR2LEDR2 LEDRLEDR
3
LCD_ON
Q3
Q3
2
8050
8050
LEDR3LEDR3 LEDRLEDR
1
R14R14
680680
GND
RN2
RN2
RN3
RN3
VCC43
Q4Q4
85508550
LEDG0LEDGLEDG0LEDG
LED4
LED19
1
3
1
2
1
2
GND
LED5
LED20
3
4
3
4
LED6
LEDR4LEDR4 LEDRLEDR
LED21
LEDG1LEDGLEDG1LEDG
5
6
5
6
LCD_BLON
LED7
LED22
7
8
7
8
VCC43
R15R15
680680
R16
R16
330
330
LEDR5LEDR5 LEDRLEDR
330
330
LEDG2LEDGLEDG2LEDG
LCD_D[0 7]
680
680
LCD_RS
LCD_EN
R17
R17
LEDR6LEDR6 LEDRLEDR
LEDG3LEDGLEDG3LEDG
3
LCD_WR
1K
1K
GND
LED[0 26]
Q5
Q5
2
8050
8050
LEDR7LEDR7 LEDRLEDR
1
GND
RN4
RN4
RN5
RN5
LEDG4LEDGLEDG4LEDG
GND
GND
LED8
LED23
1
2
1
2
GND
R18
R18
LED9
LED24
3
4
3
4
47
47
LED18
LEDR8LEDR8 LEDRLEDR
LED25
LEDG5LEDGLEDG5LEDG
5
6
5
6
LED26
7
8
7
8
C
C
330
330
LEDR9LEDR9 LEDRLEDR
330
330
LEDG6LEDGLEDG6LEDG
GND
LEDG8LEDGLEDG8LEDG
LEDG7LEDGLEDG7LEDG
GND
GND
RN6
RN6
LED10
1
2
LED11
3
4
LED12
LEDR10LEDR10LEDRLEDR
5
6
2
2
X 16 DIGIT LCD
X 16 DIGIT LCD
LED13
7
8
330
330
LEDR11LEDR11LEDRLEDR
LEDR12LEDR12LEDRLEDR
LEDR13LEDR13LEDRLEDR
GND
RN7
RN7
U2
U2
LCD16
LCD16
B
B
LED14
1
2
LED15
3
4
LED16
5
6
LEDR14LEDR14LEDRLEDR
LED17
7
8
330
330
LEDR15LEDR15LEDRLEDR
LEDR16LEDR16LEDRLEDR
LEDR17LEDR17LEDRLEDR
GND
1
2
A
A
3
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
LCD AND LED
LCD AND LED
LCD AND LED
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
5
5
5
of
of
of
24
24
24
5
4
3
2
1
2
20
NC3
19
NC2
18
NC1
17
NC0
2
16
GND1
LCD_BL
15
BL
LCD_D7
14
D7
LCD_D6
13
D6
LCD_D5
12
D5
LCD_D4
11
D4
LCD_D3
10
D3
LCD_D2
9 8 7 6 5 4 3 2 1
D2
LCD_D1
D1
LCD_D0
D0
LCD_EN
EN
LCD_WR
WR
LCD_RS
RS
LCD_CONT
CONT
LCD_VCC
VCC
GND0
5 4 3 2 1 HEX7 HEX7 HEX6 HEX6 A A A A 10 10
5
4
3
2
1
HEX7
HEX7
HEX6
HEX6
A
A
A
A
10
10
RN8
RN8
RN9
RN9
HEX0_D[0 6]
HEX7_D0
A7
B
B
HEX6_D0
A6
B
B
1
2
9
1
2
9
HEX1_D[0 6]
HEX7_D1
B7
HEX6_D1
B6
3
4
3
4
HEX2_D[0 6]
HEX7_D2
C7
C
C
VCC33
HEX6_D2
C6
C
C
VCC33
5
6
8
5
6
8
D
D
HEX3_D[0 6]
HEX7_D3
D7
HEX6_D3
D6
7
8
7
8
HEX4_D[0 6]
D
D
D
D
5
5
HEX5_D[0 6]
330
330
330
330
1
1
HEX6_D[0 6]
E
E
E
E
4
4
RN10
RN10
RN11
RN11
HEX7_D[0 6]
6
6
HEX7_D4
E7
F
F
HEX6_D4
E6
F
F
1
2
2
1
2
2
HEX7_D5
F7
HEX6_D5
F6
3
4
3
4
HEX7_D6
G7
G
G
HEX6_D6
G6
G
G
5
6
3
5
6
3
7
8
7
8
DP
DP
DP
DP
7
7
330
330
330
330
7Segment Display
7Segment Display
7Segment Display
7Segment Display
HEX5
HEX5
HEX4
HEX4
A
A
A
A
10
10
RN12
RN12
RN13
RN13
HEX5_D0
A5
B
B
HEX4_D0
A4
B
B
1
2
9
1
2
9
HEX5_D1
B5
HEX4_D1
B4
3
4
3
4
HEX5_D2
C5
C
C
VCC33
HEX4_D2
C4
C
C
VCC33
5
6
8
5
6
8
HEX5_D3
D5
HEX4_D3
D4
7
8
7
8
D
D
D
D
5
5
330
330
330
330
1
1
E
E
E
E
4
4
RN14
RN14
RN15
RN15
6
6
C
C
HEX5_D4
E5
F
F
HEX4_D4
E4
F
F
1
2
2
1
2
2
HEX5_D5
F5
HEX4_D5
F4
3
4
3
4
HEX5_D6
G5
G
G
HEX4_D6
G4
G
G
5
6
3
5
6
3
7
8
7
8
DP
DP
DP
DP
7
7
330
330
330
330
7Segment Display
7Segment Display
7Segment Display
7Segment Display
HEX3
HEX3
HEX2
HEX2
A
A
A
A
10
10
RN16
RN16
RN17
RN17
HEX3_D0
A3
B
B
HEX2_D0
A2
B
B
1
2
9
1
2
9
HEX3_D1
B3
HEX2_D1
B2
3
4
3
4
HEX3_D2
C3
C
C
VCC33
HEX2_D2
C2
C
C
VCC33
5
6
8
5
6
8
HEX3_D3
D3
HEX2_D3
D2
7
8
7
8
D
D
D
D
5
5
330
330
1
330
330
1
E
E
E
E
4
4
RN18
RN18
RN19
RN19
6
6
HEX3_D4
E3
F
F
HEX2_D4
E2
F
F
1
2
2
1
2
2
HEX3_D5
F3
HEX2_D5
F2
3
4
3
4
HEX3_D6
G3
G
G
HEX2_D6
G2
G
G
5
6
3
5
6
3
7
8
7
8
DP
DP
DP
DP
B
7
7
B
330
330
330
330
7Segment Display
7Segment Display
7Segment Display
7Segment Display
HEX0
HEX0
A
A
10
RN21
RN21
HEX0_D0
A0
B
B
1
2
9
HEX0_D1
B0
3
4
HEX0_D2
C0
C
C
VCC33
5
6
8
HEX0_D3
D0
7
8
HEX1
HEX1
D
D
5
A
A
330
330
10
1
RN20
RN20
E
E
4
RN23
RN23
HEX1_D0
A1
B
B
1
2
9
6
HEX1_D1
B1
HEX0_D4
E0
F
F
3
4
1
2
2
HEX1_D2
C1
C
C
VCC33
HEX0_D5
F0
5
6
8
3
4
HEX1_D3
D1
HEX0_D6
G0
G
G
7
8
5
6
3
D
D
5
7
8
330
330
DP
DP
1
7
E
E
330
330
4
RN22
RN22
7Segment Display
7Segment Display
6
HEX1_D4
E1
F
F
1
2
2
HEX1_D5
F1
3
4
A
HEX1_D6
G1
G
G
5
6
3
A
7
8
DP
DP
7
330
330
7Segment Display
7Segment Display
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
7
7
7
SEGMENT
SEGMENT
SEGMENT
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
6
6
6
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 U11A U11A U11B U11B HEX7_D[0 6] HEX6_D[0 6] GND SW10
5
4
3
2
1
U11A
U11A
U11B
U11B
HEX7_D[0 6]
HEX6_D[0 6]
GND
SW10
Y6
N1
GND_PLL1
CLK1
HEX5_D[0 6]
VCC12
50MHZ
Y7
N2
VCCD_PLL1
CLK0
HEX4_D[0 6]
GND
HEX6_D3
W7
M2
GND_PLL1
B2_L27N
DRAM_CKE
HEX6_D4
AA6
M3
PLL1_OUTN
B2_L27P/DPCLK0
DRAM_CLK
HEX6_D5
AA7
M5
PLL1_OUTP
B2_L28N
DRAM_CS
HEX6_D6
AC3
M4
B1_IO_0
B2_L28P
D
D
DRAM_D[0 15]
DRAM_RAS
AB4
L10
B1_L0N
B2_IO_0
DRAM_A[0 11]
DRAM_CAS
HEX7_D0
AB3
L3
B1_L0P
B2_L29N
DRAM_UDQM
DRAM_BA1
HEX7_D1
AE3
L2
B1_L1N
B2_L29P
DRAM_LDQM
DRAM_BA0
HEX7_D2
AE2
L9
B1_L1P
B2_IO_1
DRAM_CLK
DRAM_WE
HEX7_D3
AD3
L6
B1_L2N
B2_L30N
DRAM_CKE
DRAM_LDQM
HEX7_D4
AD2
L7
B1_L2P
B2_L30P
DRAM_BA0
DRAM_UDQM
HEX7_D5
Y5
P9
B1_L3N
B2_L31N
DRAM_BA1
DRAM_D15
HEX7_D6
AA5
N9
B1_L3P
B2_L31P
DRAM_WE
DRAM_D14
LCD_ON
AC1
L4
B1_L4N
B2_VREFN1
DRAM_CAS
DRAM_D13
LCD_BLON
AC2
K2
B1_L4P
B2_L32N
DRAM_RAS
DRAM_D12
LCD_RS
AA3
K1
B1_L5N
B2_L32P
DRAM_CS
DRAM_D11
LCD_EN
AA4
K3
B1_L5P
B2_L33N
DRAM_D10
LCD_WR
AB1
K4
B1_L6N
B2_L33P
DRAM_D9
LCD_D0
AB2
J1
B1_L6P
B2_L34N
DRAM_D8
LCD_D1
W6
J2
B1_VREFN1
B2_L34P
DRAM_D7
LCD_D2
V7
H1
B1_IO_1
B2_L35N
DRAM_D6
LCD_D3
T8
H2
B1_L7N
B2_L35P
DRAM_D5
LCD_D4
R8
J4
B1_L7P
B2_L36N
DRAM_D4
LCD_D5
Y4
J3
B1_L8N
B2_L36P
LCD_ON
DRAM_D3
LCD_D6
Y3
H4
B1_L8P
B2_L37N
LCD_BLON
DRAM_D2
LCD_D7
AA1
H3
B1_L9N
B2_L37P
LCD_RS
DRAM_D1
OTG_OE
AA2
G2
B1_L9P
B2_L38N
LCD_EN
DRAM_D0
OTG_WE
V6
G1
B1_L10N
B2_L38P/CDPCLK0
LCD_WR
DRAM_A11
OTG_CS
V5
F1
C
B1_L10P
B2_L39N
C
LCD_D[0 7]
DRAM_A10
OTG_A1
Y1
F2
B1_IO_2
B2_L39P
DRAM_A9
OTG_A0
W3
K7
B1_L11N
DRAM_A8
BANK1
BANK1
B2_L40N
OTG_D15
W4
K8
B1_L11P/CDPCLK1
B2_L40P
SW[10 17]
DRAM_A7
OTG_D14
BANK2
BANK2
U5
J6
B1_IO_3
B2_IO_2
DRAM_A6
OTG_D13
U7
G3
B1_L12N
B2_L41N
DRAM_A5
OTG_D12
U6
G4
B1_L12P
B2_L41P
DRAM_A4
OTG_D11
W1
K5
B1_L13N
B2_L42N
DRAM_A3
OTG_D10
W2
K6
B1_L13P
B2_L42P
DRAM_A2
OTG_D9
V3
E1
B1_L14N
B2_L43N
OTG_INT1
DRAM_A1
OTG_D8
V4
E2
B1_L14P
B2_L43P
OTG_INT0
DRAM_A0
OTG_D7
T6
H6
B1_L15N
B2_IO_3
OTG_DREQ1
SW13
OTG_D6
T7
J7
B1_L15P
B2_L44N
OTG_DREQ0
SW17
OTG_D5
V2
J8
B1_L16N
B2_L44P
OTG_DACK1
SW16
OTG_D4
V1
J5
B1_L16P
B2_VREFN0
OTG_DACK0
SW15
OTG_D3
U4
F7
B1_L17N
B2_IO_4
OTG_RESET
SW14
OTG_D2
U3
D1
B1_L17P
B2_L45N
OTG_A1
OTG_D1
U10
D2
B1_L18N
B2_L45P
OTG_A0
HEX4_D0
OTG_D0
U9
F4
B1_L18P
B2_L46N
OTG_CS
HEX4_D1
OTG_FSPEED
U1
F3
B1_L19N
B2_L46P
OTG_WE
HEX4_D2
OTG_LSPEED
U2
G6
B1_L19P
B2_L47N
OTG_OE
HEX4_D3
OTG_RESET
T4
G5
B1_VREFN0
B2_L47P
OTG_LSPEED
HEX4_D4
OTG_INT1
R7
C3
B1_L20N
B2_L48N
OTG_FSPEED
HEX4_D5
OTG_DACK0
R6
C2
B1_L20P
B2_L48P
HEX4_D6
OTG_DREQ0
B
T3
F6
B
B1_L21N
PLL3_OUTN
OTG_D[0 15]
HEX5_D0
OTG_DREQ1
T2
E5
B1_L21P
PLL3_OUTP
50MHZ
HEX5_D1
OTG_INT0
P6
B3
B1_L22N
B2_L49N/CLKUSR
HEX5_D2
OTG_DACK1
P7
B2
B1_L22P
B2_L49P/CRCERR
HEX5_D3
GND
T9
G7
B1_L23N
GND_PLL3
VCC12
T10
H7
B1_L23P
VCCD_PLL3
HEX5_D4
GND
R5
E4
B1_L24N
GND_PLL3
HEX5_D5
R4
B1_L24P
HEX5_D6
R3
B1_L25N
HEX6_D0
R2
B1_L25P
HEX6_D1
P4
B1_L26N
HEX6_D2
P3
B1_L26P/DPCLK1
SW11
P1
CLK3
SW12
P2
CLK2
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
VCCINT
VCC12
A
A
BC5
BC5
BC6
BC6
0.1U
0.1U
0.1U
0.1U
GND
GND
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
EP2C35 BANK1 AND BANK 2
EP2C35 BANK1 AND BANK 2
EP2C35 BANK1 AND BANK 2
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
7
7
7
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 U11C U11C U11D U11D VCC12 SW9 G8 A13 VCCA_PLL3 CLK9
5
4
3
2
1
U11C
U11C
U11D
U11D
VCC12
SW9
G8
A13
VCCA_PLL3
CLK9
GND
SW8
F8
B13
GNDA_PLL3
CLK8
AUD_ADCLRCK
LINK_D0
C5
B14
B3_L50N/DEV_CLRN
B4_L74P/DPCLK9
AUD_DACLRCK
LINK_D1
C6
A14
B3_L50P
B4_L74N
AUD_DACDAT
LINK_D2
A4
D14
B3_L51P
B4_IO_0
D
D
AUD_BCLK
LINK_D3
B4
F14
B3_L51N
B4_L75P
AUD_XCK
A5
G14
B3_L52P
B4_L75N
AUD_ADCDAT
B5
F13
B3_L52N
SW[7 9]
I2C_SDAT
B6
G13
B4_L76P
B3_L53P/CDPCLK7
B4_L76N
I2C_SCLK
A6
C15
B3_L53N
B4_L77P
VGA_R[0 9]
TD_RESET
ENET_D7
C4
B15
B3_L54P
B4_L77N
VGA_G[0 9]
TD_HS
ENET_D6
D5
B16
B3_L54N
B4_L78P
VGA_B[0 9]
TD_VS
K9
C16
B3_L55P
B4_L78N
VGA_BLANK
TD_D0
J9
D15
B3_L55N
B4_L79P
VGA_SYNC
TD_D1
E8
E15
B3_VREFN1
B4_L79N
VGA_CLOCK
TD_D2
H8
D16
B3_IO_0
VGA_HS
TD_D3
H10
H15
B4_VREFN1
B3_L56P
B4_L80P
VGA_VS
TD_D4
G9
H16
B3_L56N
B4_L80N
TD_D5
ENET_D5
F9
A17
B3_IO_1
B4_L81P
TD_D6
ENET_D4
D7
B17
B3_L57P
B4_L81N
TD_D7
C7
G15
B3_L57N
B4_L82P
TD_D[0 7]
VGA_BLANK
D6
F15
B3_IO_2
B4_L82N
TD_RESET
VGA_SYNC
B7
F16
B3_L58P
VGA_HS
A7
G16
B4_L83P
B3_L58N
B4_L83N
TD_HS
VGA_VS
ENET_D3
D8
A18
B3_L59P
B4_L84P
TD_VS
VGA_R0
ENET_D2
C8
B18
B3_L59N
B4_L84N
27MHZ
VGA_R1
ENET_D1
F10
C17
B3_L60P
B4_L85P/DPCLK8
VGA_R2
ENET_D0
G10
D17
B3_L60N
B4_L85N
VGA_R3
D9
G17
C
B3_L61P
B4_L86P
C
VGA_R4
C9
F17
B3_L61N
B4_L86N
VGA_CLOCK
B8
H17
B3_L62P/DPCLK11
B4_L87P
VGA_R5
A8
J17
B3_L62N
B4_L87N
ENET_D[0 15]
VGA_R6
H11
B3_L63P
BANK3
BANK3
F18
VGA_R7
H12
G18
B4_L88P
BANK4
BANK4
B3_L63N
B4_L88N
ENET_IOW
VGA_R8
ENET_D15
F11
D18
B3_L64P
B4_L89P
ENET_IOR
VGA_R9
ENET_D14
E10
E18
B3_L64N
B4_L89N
ENET_CMD
VGA_G0
ENET_D13
B9
A19
B3_L65P
B4_L90P
ENET_CS
VGA_G1
ENET_D12
A9
B19
B3_L65N
B4_L90N
ENET_RESET
VGA_G2
ENET_D11
C10
D19
B3_L66P
B4_L91P
ENET_INT
VGA_G3
ENET_D10
D10
C19
B3_L66N
B4_L91N
VGA_G4
ENET_D9
B10
A20
B3_L67P
B4_L92P
VGA_G5
ENET_D8
A10
B20
B3_L67N
B4_L92N
VGA_G6
G11
E20
B3_IO_3
VGA_G7
D11
D20
B4_VREFN0
B3_VREFN0
B4_IO_1
AUD_XCK
VGA_G8
E12
K16
B3_L68P
B4_L93P
AUD_BCLK
VGA_G9
D12
J16
B3_L68N
B4_L93N
AUD_DACDAT
VGA_B0
J13
K17
B3_L69P
B4_L94P
AUD_DACLRCK
VGA_B1
J14
J18
B3_L69N
B4_L94N
AUD_ADCLRCK
VGA_B2
ENET_CMD
F12
A21
B3_L70P
B4_L95P
AUD_ADCDAT
VGA_B3
ENET_INT
G12
B21
B3_L70N
B4_L95N
VGA_B4
ENET_IOW
J10
B22
B3_L71P
B4_L96P/CDPCLK6
I2C_SDAT
VGA_B5
ENET_IOR
J11
A22
B3_L71N
B4_L96N
I2C_SCLK
VGA_B6
ENET_CS
B
C11
A23
B
B3_L72P
B4_L97P
VGA_B7
ENET_RESET
B11
B23
B3_L72N
B4_L97N
VGA_B8
C12
D21
B3_L73P/DPCLK10
B4_L98P
LINK_D0
VGA_B9
B12
C21
B3_L73N
B4_L98N
LINK_D1
27MHZ
D13
C22
CLK11
B4_L99P
LINK_D2
SW7
C13
C23
CLK10
B4_L99N
LINK_D3
GND
F19
GNDA_PLL2
VCC12
G19
VCCA_PLL2
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
VCCINT
A
VCC12
A
BC7
BC7
BC8
BC8
0.1U
0.1U
0.1U
0.1U
Title
Title
Title
GND
GND
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
EP2C35 BANK3 AND BANK 4
EP2C35 BANK3 AND BANK 4
EP2C35 BANK3 AND BANK 4
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
8
8
8
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 U11E U11E U11F U11F GND SW2 E21 P25 GND_PLL2 CLK6
5
4
3
2
1
U11E
U11E
U11F
U11F
GND
SW2
E21
P25
GND_PLL2
CLK6
VCC12
EXT_CLOCK
H20
P26
VCCD_PLL2
CLK7
GND
KEY2
G20
P23
GND_PLL2
B6_L127P/DPCLK6
GPIO_B47
F20
P24
PLL2_OUTN
B6_L127N
GPIO_B48
F21
R25
E22
PLL2_OUTP
B6_L128P
GPIO_B49
R24
B5_L100P
B6_L128N
D
D
GPIO_B50
D23
R20
G21
B5_L100N
B6_IO_0
GPIO_B51
T22
B5_L101P
B6_L129P
GPIO_B52
G22
T23
B5_L101N
B6_L129N
H21
R17
B5_IO_0
B6_L130P
E23
P17
B5_L102P
B6_L130N
UART_RXD
GPIO_B53
E24
T24
B5_L102N
B6_L131P
UART_TXD
25MHZ
B24
GPIO_B54
T25
B5_L103P
B6_L131N
PS2_DAT
UART_TXD
GPIO_B55
B25
T18
B5_L103N
B6_L132P
PS2_CLK
UART_RXD
C25
T17
B5_L104P
B6_L132N
PS2_DAT
GPIO_B56
C24
T21
B5_L104N
B6_VREFN0
SD_CMD
PS2_CLK
GPIO_B57
D26
T20
B5_L105P
B6_IO_1
SD_CLK
GPIO_B0
GPIO_B58
D25
U26
B5_L105N
B6_L133P
SD_DAT
GPIO_B1
GPIO_B59
J22
U25
B5_VREFN0
B6_L133N
25MHZ
GPIO_B2
GPIO_B60
E26
U23
B5_L106P
B6_L134P
GPIO_B3
GPIO_B61
E25
U24
B5_L106N
B6_L134N
GPIO_B4
GPIO_B62
F24
R19
B5_L107P
B6_L135P
GPIO_B[0 71]
GPIO_B5
GPIO_B63
F23
T19
B5_L107N
B6_L135N
GPIO_B6
GPIO_B64
J21
U20
B5_L108P
B6_L136P
HEX1_D[0 6]
GPIO_B7
GPIO_B65
J20
U21
B5_L108N
B6_L136N
HEX2_D[0 6]
GPIO_B8
GPIO_B66
F25
V26
B5_L109P
B6_L137P
HEX3_D[0 6]
GPIO_B9
GPIO_B67
F26
V25
B5_L109N
B6_L137N
GPIO_B10
GPIO_B68
N18
V24
B5_L110P
B6_L138P
GPIO_B11
GPIO_B69
P18
V23
B5_L110N
B6_L138N
KEY[0 3]
GPIO_B12
KEY3
G23
W26
C
B5_L111P
B6_L139P/CDPCLK4
C
SW[0 2]
GPIO_B13
GPIO_B70
G24
W25
B5_L111N
B6_L139N
GPIO_B14
GPIO_B71
K22
W23
B5_IO_1
B6_L140P
EXT_CLOCK
GPIO_B15
BANK5
BANK5
HEX3_D6
BANK6
BANK6
G25
W24
B5_L112P/CDPCLK5
B6_L140N
KEY0
HEX3_D5
G26
U22
B5_L112N
B6_IO_2
IRDA_RXD
GPIO_B16
HEX3_D4
H23
Y25
B5_L113P
B6_L141P
IRDA_TXD
GPIO_B17
HEX3_D3
H24
Y26
B5_L113N
B6_L141N
SD_DAT3
GPIO_B18
HEX3_D2
J23
AA26
B5_L114P
B6_L142P
GPIO_B19
HEX3_D1
J24
AA25
B5_L114N
B6_L142N
GPIO_B20
HEX3_D0
H25
Y23
B5_L115P
B6_L143P
GPIO_B21
HEX2_D6
H26
Y24
B5_L115N
B6_L143N
GPIO_B22
HEX2_D5
H19
AB25
B5_IO2
B6_L144P
GPIO_B23
HEX2_D4
K18
AB26
B5_L116P
B6_L144N
GPIO_B24
HEX2_D3
K19
AC26
B5_L116N
B6_L145P
GPIO_B25
HEX2_D2
K21
AC25
B5_IO_3
B6_L145N
GPIO_B26
HEX2_D1
K23
V22
B5_L117P
B6_VREFN1
GPIO_B27
HEX2_D0
K24
AB23
B5_L117N
B6_L146P
GPIO_B28
HEX1_D6
L21
AB24
B5_L118P
B6_L146N
GPIO_B29
HEX1_D5
L20
AA23
B5_L118N
B6_L147P
GPIO_B30
HEX1_D4
J25
AA24
B5_L119P
B6_L147N
GPIO_B31
HEX1_D3
J26
Y22
B5_L119N
B6_L148P
GPIO_B32
HEX1_D2
L23
W21
B5_VREFN1
B6_L148N
GPIO_B33
HEX1_D1
L24
V21
B5_L120P
PLL4_OUTP
GPIO_B34
HEX1_D0
L25
V20
B5_L120N
PLL4_OUTN
GPIO_B35
SD_CMD
B
L19
Y21
B
B5_IO_4
B6_IO_3
GPIO_B36
SD_DAT
K25
AD24
B5_L121P
B6_L149P
GPIO_B37
SD_CLK
K26
AD25
B5_L121N
B6_L149N
GPIO_B38
IRDA_TXD
M22
AE24
B5_L122P
B6_L150P/NCEO
GPIO_B39
IRDA_RXD
M23
AE25
B5_L122N
B6_L150N/INIT_DONE
GPIO_B40
SD_DAT3
M19
AC23
B5_L123P
B6_IO_4
GPIO_B41
GND
M20
W20
B5_L123N
GND_PLL4
GPIO_B42
VCC12
N20
Y20
B5_L124P
VCCD_PLL4
GPIO_B43
GND
M21
AA21
B5_L124N
GND_PLL4
GPIO_B44
M24
B5_L125P
GPIO_B45
M25
B5_L125N
KEY1
N23
B5_L126P/DPCLK7
GPIO_B46
N24
B5_L126N
SW0
N25
CLK4
SW1
N26
CLK5
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
CYCLONE II EP2C35
VCCINT
A
VCC12
A
BC9
BC9
BC10
BC10
0.1U
0.1U
0.1U
0.1U
Title
Title
Title
GND
GND
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
EP2C35 BANK5 AND BANK 6
EP2C35 BANK5 AND BANK 6
EP2C35 BANK5 AND BANK 6
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
9
9
9
of
of
of
24
24
24
5
4
3
2
1
 

5

 

4

 

3

2

   

1

 
 

U11G

U11G

U11H

U11H

 
 

VCC12

AA19

   

SW5

AD13

 

GND

Y19

VCCA_PLL4

GNDA_PLL4

 

SW6

AC13

CLK14

CLK15

 

LED0

AE23

LED14

AF13

D

LED1

LED2

AF23

AB21

B7_L151N

B7_L151P

LED15

LED16

AE13

AE12

B8_L177N

B8_L177P/DPCLK3

 

D

LED3

AC22

B7_L152N

B7_L152P

B7_L153N

B7_L153P

B7_L154N

B7_L154P/CDPCLK3

B7_L155N

B7_L155P

B7_L156N

B7_L156P

 

LED17

AD12

B8_L178N

B8_L178P

B8_L179N

B8_L179P

B8_L180N

B8_L180P

B8_L181N

B8_L181P

B8_L182N

B8_L182P

LED4

AD22

LED18

Y12

LED5

AD23

HEX0_D6

HEX0_D6

AA12

LED6

AD21

U12

LED7

AC21

   

V11LED7 AC21     LED7 AC21    

LED19

AE22

V13

LED20

AF22

 

HEX0_D5

V14

 
LED[0 26] SW[3 6]
LED[0 26]
SW[3 6]

LED21

W19

HEX0_D4

AE11

LED22

V18

HEX0_D3

AD11

LED23

U18

HEX0_D2

AC12

 
 

LED24

U17

B7_L157N

HEX0_D1

AB12

B8_VREFN0

 

LED25

AA20

B7_L157P

B7_IO_0

B7_VREFN0

B7_L158N

B7_L158P

B7_L159N

B7_L159P

B7_L160N

B7_L160P

B7_L161N

 

HEX0_D0

AF10

B8_IO_0

B8_L183N

B8_L183P

B8_L184N

B8_L184P

B8_L185N

B8_L185P

B8_L186N

B8_L186P

B8_L187N

LED26

Y18

SRAM_WE

AE10

FLASH_D7

AE21

SRAM_CE

AC11

FLASH_D6

AF21

SRAM_OE

AD10

 

SRAM_D[0 15]

FLASH_D5

AC20

SRAM_UB

AF9

SRAM_A[0 17] SRAM_WE SRAM_CE SRAM_OE SRAM_UB SRAM_LB FLASH_RESET FLASH_CE FLASH_OE FLASH_WE FLASH_A[0 21]
SRAM_A[0 17]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
FLASH_RESET
FLASH_CE
FLASH_OE
FLASH_WE
FLASH_A[0 21]
FLASH_D[0 7]
HEX0_D[0 6]

FLASH_D4

AB20

SRAM_LB

AE9

FLASH_D3

AE20

SRAM_D15

AC10

FLASH_D2

AF20

SRAM_D14

AC9

FLASH_D1

AC19

SRAM_D13

W12

FLASH_D0

AD19

SRAM_D12

W11

C

FLASH_RESET

FLASH_WE

FLASH_CE

AA18

AA17

V17

B7_L161P

B7_L162N

B7_L162P

SRAM_D11

SRAM_D10

SRAM_D9

AF8

AE8

AF7

B8_L187P

B8_L188N

B8_L188P/DPCLK2

C

FLASH_OE

W17

B7_L163N

B7_L163P

B7_L164N

B7_L164P

B7_L165N

B7_L165P/DPCLK5

B7_L166N

B7_L166P

B7_L167N

B7_L167P

B7_L168N

 

SRAM_D8

AE7

B8_L189N

B8_L189P

B8_L190N

B8_L190P

B8_L191N

B8_L191P

B8_IO_1

B8_L192N

B8_L192P

B8_L193N

B8_L193P

 

FLASH_A0

AC18

SRAM_D7

Y11

FLASH_A1

AB18

SRAM_D6

AA11

FLASH_A2

AE19

BANK7

BANK7

 

SRAM_D5

AB10

BANK8

BANK8

 

FLASH_A3

AF19

SRAM_D4

AA10

FLASH_A4

AE18

SRAM_D3

AA9

FLASH_A5

AF18

 

SRAM_D2

AF6

   
 

FLASH_A6

Y16

SRAM_D1

AE6

FLASH_A7 AA16 SRAM_D0 AD8  

FLASH_A7

AA16

SRAM_D0

AD8

 
FLASH_A7 AA16 SRAM_D0 AD8  

FLASH_A8

FLASH_A9

AD17

AC17

SRAM_A17

SRAM_A16

AC8

AB8

   

FLASH_A10

AE17

B7_L168P

B7_L169N

B7_L169P

B7_L170N

B7_L170P

B7_VREFN1

B7_L171N

B7_L171P

B7_L172N

B7_L172P

B7_L173N

B7_L173P

SRAM_A15

Y10

B8_IO_2

B8_L194N

B8_L194P

FLASH_A11

AF17

SRAM_A14

W10

FLASH_A12

W16

SRAM_A13

W8

FLASH_A13

W15

SRAM_A12

AC7

B8_IO_3

B8_VREFN1

FLASH_A14

AC16

SRAM_A11

V9

FLASH_A15

AD16

SRAM_A10

V10

B8_L195N

B8_L195P

B8_L196N

B8_L196P

B8_L197N

B8_L197P

B8_L198N

FLASH_A16

AE16

SRAM_A9

AD7

FLASH_A17

AC15

SRAM_A8

AD6

FLASH_A18

AB15

SRAM_A7

AF5

FLASH_A19

AA15

SRAM_A6

AE5

B

FLASH_A20

FLASH_A21

Y15

Y14

SRAM_A5

SRAM_A4

AD5

AD4

B

LED8

AA14

B7_L174N

B7_L174P

B7_L175N

B7_L175P

B7_IO_1

B7_L176N

B7_L176P

CLK12

SRAM_A3

AC6

B8_L198P

B8_L199N

B8_L199P

LED9

Y13

SRAM_A2

AC5

LED10

AA13

SRAM_A1

AF4

LED11

AC14

SRAM_A0

AE4

B8_L200P

B8_L200N/DEV_OE

GNDA_PLL1

VCCA_PLL1

LED12

AD15

GND

Y8

LED13

AE15

VCC12

AA8

SW3

AE14

 

SW4

AF14

 
 

CLK13

 

CYCLONE II EP2C35

CYCLONE II EP2C35

VCCINT

CYCLONE II EP2C35

CYCLONE II EP2C35

A

VCC12 BC11 BC11 0.1U 0.1U GND GND
VCC12
BC11
BC11
0.1U
0.1U
GND
GND

BC12

BC12

0.1U

0.1U

 

A

   

Title

Title

Title

ALTERA DE2

ALTERA DE2

ALTERA DE2

 
 

Size

Size

Size

B

B

B

Document Number

Document Number

Document Number

EP2C35 BANK7 AND BANK 8

EP2C35 BANK7 AND BANK 8

EP2C35 BANK7 AND BANK 8

 

Rev

Rev

Rev

1.2

1.2

1.2

Date:

Date:

Date:

Monday, December 12, 2005

Monday, December 12, 2005

Monday, December 12, 2005

Sheet

Sheet

Sheet

10

10

10

of

of

of

24

24

24

 

5

 

4

 

3

2

   

1

 
B A 5 4 3 2 1 B A D C VCCIO VCCIO VCCIO VCCIO

B

A

5

4

3

2

1

B A 5 4 3 2 1 B A D C VCCIO VCCIO VCCIO VCCIO U11I

B

A

D

C

VCCIO VCCIO VCCIO VCCIO U11I U11I VCCINT Y17 V16 GND VCCINT Y9 U16 GND VCCINT
VCCIO
VCCIO
VCCIO
VCCIO
U11I
U11I
VCCINT
Y17
V16
GND
VCCINT
Y9
U16
GND
VCCINT
W22
U15
GND
VCCINT
W14
U14
GND
VCCINT
W13
U13
GND
VCCINT
W5
U11
GND
VCCINT
U19
T16
GND
VCCINT
U8
T11
GND
VCCINT
AF25
R16
GND
VCCINT
AF15
R11
GND
VCCINT
AF12
R10
GND
VCCINT
AF2
P10
GND
EP2C35-672 PIN POWER
EP2C35-672 PIN POWER
VCCINT
AE26
N17
GND
VCCINT
AE1
N10
GND
VCCINT
AD18
M17
GND
VCCINT
AD14
M16
GND
VCCINT
AD9
M11
GND
VCCINT
AC4
M10
GND
VCCINT
AB19
L18
GND
VCCINT
AB16
L17
GND
VCCINT
AB11
L16
GND
VCCINT
AB7
L11
GND
VCCINT
K15
VCCINT
K14
VCCINT
K13
VCCINT
GND
K12
VCCINT
K11
VCCINT
K10
VCCINT
CYCLONE II EP2C35
CYCLONE II EP2C35
V8
VCCIO1
T5
T1
GND
VCCIO1
R26
R9
GND
VCCIO1
R21
P5
GND
VCCIO1
R1
AD1
GND
VCCIO1
P19
AB5
GND
VCCIO1
P8
GND
N19
N5
GND
VCCIO2
N8
M9
GND
VCCIO2
M26
L1
GND
VCCIO2
M1
F5
GND
VCCIO2
L22
C1
GND
VCCIO2
L5
GND
K20
J12
GND
VCCIO3
H22
H9
GND
VCCIO3
H14
E13
GND
VCCIO3
H13
E9
GND
VCCIO3
H5
E6
GND
VCCIO3
E19
A11
GND
VCCIO3
E16
A3
GND
VCCIO3
E11
GND
E7
J15
GND
VCCIO4
D24
H18
GND
VCCIO4
D4
E17
GND
VCCIO4
C18
E14
GND
VCCIO4
C14
D22
GND
VCCIO4
B26
C20
GND
VCCIO4
B1
A24
GND
VCCIO4
A25
A16
GND
VCCIO4
A15
GND
A12
N22
GND
VCCIO5
A2
M18
GND
VCCIO5
T15
L26
GND
VCCIO5
T14
J19
GND
VCCIO5
T13
F22
GND
VCCIO5
T12
C26
GND
VCCIO5
R15
GND
R14
V19
GND
VCCIO6
R13
T26
GND
VCCIO6
R12
R18
GND
VCCIO6
P16
P22
GND
VCCIO6
P15
AD26
GND
VCCIO6
P14
AA22
GND
VCCIO6
P13
GND
P12
W18
GND
VCCIO7
P11
V15
GND
VCCIO7
N16
AF24
GND
VCCIO7
N15
AF16
GND
VCCIO7
N14
AD20
GND
VCCIO7
N13
AB22
GND
VCCIO7
N12
AB17
GND
VCCIO7
N11
AB14
GND
VCCIO7
M15
GND
M14
W9
GND
VCCIO8
M13
V12
GND
VCCIO8
M12
AF11
GND
VCCIO8
L15
AF3
GND
VCCIO8
L14
AB13
GND
VCCIO8
L13
AB9
GND
VCCIO8
L12
AB6
GND
VCCIO8
CONF_DONE NSTATUS NCONFIG NCE TDI TMS TCK TDO ASDO DCLK NCSO DATA0
CONF_DONE
NSTATUS
NCONFIG
NCE
TDI
TMS
TCK
TDO
ASDO
DCLK
NCSO
DATA0

GND

U11J

U11J

M7

ASDO

NCSO

TDI

TCK

TMS

TDO

DCLK

DATA0

NCONFIG

NCE

EP2C35 CTRL

EP2C35 CTRL

AND CONFIG

AND CONFIG

NSTATUS

CONF_DONE

MSEL1

MSEL0

NC0

NC1

NC2

Y2

AND CONFIG NSTATUS CONF_DONE MSEL1 MSEL0 NC0 NC1 NC2 Y2 ASDO NSTATUS NCSO TDI TCK E3

ASDO

NSTATUS

NCSO

TDI

TCK

E3

D3

M8

M6

L8

N6

N3

N7

N4

R22

R23

P21

P20

CONF_DONE

GND

GND

TMS

TDO

N21

L8 N6 N3 N7 N4 R22 R23 P21 P20 CONF_DONE GND GND TMS TDO N21 AC24
L8 N6 N3 N7 N4 R22 R23 P21 P20 CONF_DONE GND GND TMS TDO N21 AC24

AC24

DCLK

DATA0

NCONFIG

NCE

CYCLONE II EP2C35

CYCLONE II EP2C35

VCCIO

BC13 BC13 BC14 BC14 BC15 BC15 BC16 BC16 BC17 BC17 0.1U 0.1U 0.1U 0.1U 0.1U
BC13
BC13
BC14
BC14
BC15
BC15
BC16
BC16
BC17
BC17
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
VCCIO
BC18
BC18
BC19
BC19
BC20
BC20
BC21
BC21
BC22
BC22
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
VCCIO
BC23
BC23
BC24
BC24
BC25
BC25
BC26
BC26
BC27
BC27
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
VCCIO
BC28
BC28
BC29
BC29
BC30
BC30
BC31
BC31
BC32
BC32
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
VCCINT
BC33
BC33
BC34
BC34
BC35
BC35
BC36
BC36
BC37
BC37
BC38
BC38
BC39
BC39
BC40
BC40
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U

GND

D

C

Title

Title

Title

ALTERA DE2

ALTERA DE2

ALTERA DE2

Size

Size

Size

B

B B

Document Number

Document Number

Document Number

EP2C35 POWER AND CONFIG

EP2C35 POWER AND CONFIG

EP2C35 POWER AND CONFIG

Rev

Rev

Rev

1.2

1.2 1.2

Date:

Date:

Date:

Monday, December 12, 2005

Monday, December 12, 2005

Monday, December 12, 2005

Sheet

Sheet

Sheet

11

11 11

of

of

of

24

24

24

5

4

3

2

1

5 4 3 2 1 ENET_D7 ENET_D6 ENET_D5 D D ENET_D4 ENET_D3 ENET_D2 ENET_D1 ENET_D0
5
4
3
2
1
ENET_D7
ENET_D6
ENET_D5
D
D
ENET_D4
ENET_D3
ENET_D2
ENET_D1
ENET_D0
ENET_D15
ENET_D14
N_VCC33
GND
U35
U35
NGND
C7
C7
0.1U
0.1U
DM9000A-8/16bit
DM9000A-8/16bit
CHSGND
ENET_D13
12
26 25 SD13
SD5
ENET_D12
R19
R19
R20
R20
11
27 SD12
SD6
N_VCC33
ENET_D11
49R9
49R9
49R9
49R9
10
C
28 SD11
SD7
C
ENET_D10
J4
J4
9
29 SD10
AVDD25
ENET_D9
TX-
8
11
SD9
TX-
D3
R27
R27
TX+
7
1
N_VCC33
31 30 VDD
TX+
TD+
4.7K
4.7K
ENET_D8
6
2
SD8
AGND
TD-
ENET_CMD
5
3
12
32 33 CMD
AGND
NGND
RD+
D4
N_VCC33
RX-
YELLOW
YELLOW
4
4
GND
34 GND
RX-
N_VCC25
CTT
ENET_INT
RX+
3
5
35 INT
RX+
CTR
ENET_IOR
2
6
10
36 IOR#
AVDD25
N_VCC25
RD-
D2
ENET_IOW
L1L1
BEADBEAD
1
7
IOW#
BGRES
NC
8
CHSG
R21
R21
R22
R22
9
D1
N_VCC33
49R9
49R9
49R9
49R9
GREEN
GREEN
RJ45INTLED
RJ45INTLED
N_VCC33
R34
R34
C8
C8
CHSGND
CHSGND
4.7K
4.7K
R30
R30
BC57
BC57
BC58
BC58
TC30
TC30
DM9000AE/LQFP48
DM9000AE/LQFP48
6.8K
6.8K
0.1U
0.1U
0.1U
0.1U
100U/6.3V
100U/6.3V
0.1U
0.1U
C-1210+
C-1210+
NGND
ENET_RESET
N_VCC33
ENET_CS
L7L7
BEADBEAD
B
B
ACT
SPEED
R28R28
120120
SPEED
NGND
GND
ACT
R29R29
120120
25MHZ
GND
NGND
NGND
BC51
BC51
BC52
BC52
0.1U
0.1U
0.1U
0.1U
ENET_D[0 15]
N_VCC33
N_VCC25
ENET_RESET
CHSGND
CHSGND
ENET_INT
ENET_IOR
ENET_IOW
ENET_CS
ENET_CMD
BC53
BC53
BC54
BC54
BC55
BC55
BC56
BC56
BC59
BC59
BC60
BC60
25MHZ
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
NGND
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
DM9000AE
DM9000AE
DM9000AE
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
12
12
12
of
of
of
24
24
24
5
4
3
2
1
37
24
CS#
SD14
38
23
LED2(IOWAIT / WAKEUP for eeprom)
VDD
39
22
LED1(IO16 for eeprom)
SD15
40
21
41
42
PWRST#
TEST
VDD
EEDCS
20
EEDCK
19
EEDIO
43
18
X2
SD0
44
17
X1
SD1
45
16
GND
SD2
46
15
SD
GND
47
14
AGND
SD3
48
13
BGGND
SD4
13
14
SMNT0
SMNT1
15
16
MNT1
MNT0
5 4 3 2 1 U14 U14 GND 1 2 GND IOVCC VCC33 D 3
5
4
3
2
1
U14
U14
GND
1 2 GND
IOVCC
VCC33
D
3 VCC
D
5 4 AGND
R23R23
120120
6 SD
IRDA_RXD
RXD
GND
IRDA_TXD
7 8 TXD
VCC33
9 VLED
R24R24
120120
SHIELD
R25R25
4747
IRDA
IRDA
C11
C11
C12
C12
1U
1U
1U
1U
J5
J5
1
GND
GND
EXT CLOCK
EXT CLOCK
VCC33
C
C
R35
R35
1K
1K
GND
BC41
BC41
BC42
BC42
BC43
BC43
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
GND
VCC33
GND
GND
GND
Y1
Y1
BC61
BC61
OSC_EN
4
1 EN
VCC
0.1U
0.1U
3
2 GND
OUT
GND
B
B
50MHZ
50MHZ
50MHZ
EXT_CLOCK
IRDA_RXD
IRDA_TXD
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
CLOCK
CLOCK
CLOCK
1.2
1.2
1.2
Date:
Date:
Date:
Monday, December 12, 2005
Monday, December 12, 2005
Monday, December 12, 2005
Sheet
Sheet
Sheet
13
13
13
of
of
of
24
24
24
5
4
3
2
1
5 4 3 2 1 UART_RXD 1 2 RXD D D 3 4 5 6
5
4
3
2
1
UART_RXD
1
2
RXD
D
D
3
4
5
6
RXDRXD
LEDRLEDR
7
8
J6
J6
RN24RN24
330330
U15
U15
13
12
1
VCC33
R1IN
R1OUT
8
9
6
11
R2IN
R2OUT
TXDTXD
LEDGLEDG
11
14
2
T1IN
T1OUT
10
7
7
T2IN
T2OUT
UART_TXD
3
C13
C13
1
8
C+
1U
1U
3
4
C1-
4
16
9
10
C2+
VCC
VCC33
5
15
5
C2-
GND
C14
C14
2
V+
1U
1U
6
V-
RS232
RS232
GND
MAX232
MAX232
GND
C
C
C15
C15
C16
C16
1U
1U
1U
1U
GND
GND
VCC5
VCC5
R36
R36
R37
R37
2K
2K
2K
2K
B
B
PS2_DAT
R38R38
120120
PS2_CLK
R39R39
120120
J7
J7
VCC5
TOP
TOP
1 2 NC0
D1
D1
D2
D2
3 DAT
BAT54S
BAT54S
BAT54S
BAT54S
VCC
5 5
6 6
GND
5 4 GND
NC1
3 3
4 4
7 6 CLK
BC62
BC62
GND
8 SHIELD0
0.1U
0.1U
GND
1 1
2
2
9 SHIELD1
GND
SHIELD2
GND
VCC33 GND
VCC33
GND
PS2
PS2
A
A
Title
Title
Title
ALTERA DE2
ALTERA DE2
ALTERA DE2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A