1

Report on
Special Assignment
"Implementation of 8-bit ALU on SPARTAN-3"


By:
DHRUV JOSHI (12MECE33)
JAY PATEL (12MECE36)



SEPT - 2012


M.Tech. EC (Embedded Systems)
Electrical Department
Institute Of Technology
Nirma University



2

ABSRACT



The aim of this paper is to design 8-bit ALU to perform seven arithmetic and five logical
operation using VHDL Xilinx Synthesis tool ISE 13.1 and implementing it on SPARTAN 3E
FPGA board to simulate and synthesize the design. The ALU consists of two input register to
hold two 8-bit inputs data during operation and one 8-bits output to hold the result of the
operation, 8-bit full-adder with B-input logic to perform 2s complement for subtractions and
logic gates to perform logical operation.


































3

INDEX

Page NO.
LIST OF FIGURES 4

LIST OF TABLES 4

CHAPTER -1 INTRODUCTION 5

1.1 OVERVIEW OF ALU
1.2 BLOCK DIAGRAM OF ALU
1.3 ARITHMATIC UNIT
1.4 LOGICAL UNIT
1.5 INPUT/OUTPUT OF ALU
1.6 FUNCTION TABLE OF ALU

CHAPTER -2 SIMULATION AND SYNTHESIS on Xilinx ISE 9


2.1 OVERVIER OF Xilinx ISE
2.2 OVERVIEW OF VHDL
2.3 SYNTHESIS RESULT
2.3.1 RTL View
2.3.2 Technology view
2.3.3 SYNTHESIS REPORT
2.4 SIMULATION

CHAPTER-3 IMPLEMENTATION on SPARTAN-3 Kit 15

3.1 PROCESSOR: XC3S400PQ208 Features

CONCLUSION 17


REFERENCE 18









4

LIST OF FIGURES AND TABLES


Figures Page
1.1 Symbol of ALU 5
1.2 Block Diagram of ALU 6
2.1 RTL Design 11
2.2 RTL Design inside Entity 11
2.3 Technology View 12
2.4 Simulation waveform of AND operation 13
2.5 Simulation waveform of SUB operation 14
3.1 Circuit diagram of ALU 16

Tables Page
1.1 B-Input Logic 7
1.2 Function Table of ALU 8
2.1 Summary of Device Utilization 13
















5

CHAPTER-1


INTRODUCTION



1.1 OVERVIEW OF ALU :


ALU is the integral part of the Central Processing Unit for which it performs
the arithmetic and logical operation. The ALU takes input as the data to be operated on
(called operands) and a code, from the control unit, indicating which operation to perform.
The main operation of any processor is mainly fetching, decoding and executing an
instructions. The fetching of instructions is perform by instruction fetch unit, the decoding of
instructions is perform by decode unit(or control unit) which generate appropriate control
signals for ALU to carry-out the operation of instruction. These control signals refer to as
selection lines for ALU to select particular operation.


Fig 1.1 : Symbol of ALU





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1.2 BLOCK DIAGRAM OF ALU:



Fig 1.2: Block Diagram of ALU


1.3 ARITHMATIC UNIT:

Arithmetic operations performed are 8-bit addition and subtraction. Logical
operations performed are AND, OR, XOR and NOT. ALU also calculates 1s and 2s
complement for the 8-bit input for subtraction.
Arithmetic unit contains two blocks: 1) B-input logic
2) 8-bit Full-adder.
B-input logic is used to obtain 2s complement of input B when the subtraction is going to
perform. The B-input logic reduces the complexity of the circuit.
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S1 S0 Y=s1B +s0B
0 0 0
0 1 B
1 0 B
1 1 1

TABLE 1.1 INPUT LOGIC

And Full-adder is used to get addition of two operand with input carry and 8-bit sum and 1-
bit carry.

1.4 LOGICAL UNIT :

Logical operations performed are AND, OR, XOR and NOT. 4 to1 MUX selects the
logic operations based on the select lines in the logic unit.

Both arithmetic and logical unit are performed the operation in parallel. Finally a 2
to1 MUX selects between arithmetic and logic unit. Zero flag is obtain by applying all the
lines of result to Nor gate. And Negative flag is obtain by taking the 7
th
bit of the result.

1.5 INPUT/OUTPUT OF ALU:

Inputs of ALU:
1. Two 8-bit Operands A &B
2. Operation Selection lines : S0, S1
: Cin (carry-in)
3. Result selection line: M = 1 : Arithmetic result
= 0 : Logical result
Outputs of ALU:
1. One 8-bit result operand,
2. Z (Zero), Cout (carry-out),N(negative flags).





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1.6 FUNCTION TABLE OF ALU:




OPCODE
M S1 S0 CIN Operati! "#!$ti!
1000 1 0 0 0 O#t =% &ra!s'er %
1001 1 0 0 1 O#t=%+1 I!$re(e!t %
1010 1 0 1 0 O#t =%+B %))iti!
1011 1 0 1 1 O#t=%+B+1 %)) *it+ Carr,
1100 1 1 0 0 O#t=%+B % p-#s 1s
$(p-e(e!t ' B
1101 1 1 0 1 O#t=%+B+1 S#.tra$ti!
1110 1 1 1 0 O#t=%/1 De$re(e!t %
1111 1 1 1 1 O#t=% &ra!s'er %
0000 0 0 0 0 O#t=% 1 B %ND
0010 0 0 1 0 O#t=% 2 B O3
0100 0 1 0 0 O#t=%4B 0O3
0110 0 1 1 0 O#t=% NO& %51sC(p-e(e!t6
0111 0 1 1 1 O#t=B NO& B51sC(p-e(e!t6

Table 1.2 Function Table of ALU.




















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CHAPTER-2

SIMULATION AND SYNTHESIS on Xilinx ISE





2.1 OVERVIEW OF Xilinx ISE:


Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of
HDL designs, which enables the developer to synthesize ("compile") their designs, perform
timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and
configure the target device with the programmer.

ISE Design Suite -The ISE Design Suite: Embedded Edition includes all the
tools and capabilities of the Logic Edition with the added capabilities of the Embedded
Development Kit (EDK). This edition provides an integrated development environment of
embedded processing tools, processor cores, IP, software libraries, and design generators,
including the following:

Xilinx Platform Studio (XPS) - provides an integrated environment for creating software and
hardware specification flows for embedded processor systems based on MicroBlaze and
PowerPC processors. It also provides an editor and a project management interface to create
and edit source code. XPS allows you to customize tool flow configuration options and
provides a graphical system editor for connection of processors, peripherals, and buses.


Hardware Platform Generation Tool (PlatGen) - customizes and generates the embedded
processor system through the use of hardware netlist. Hardware Description Language (HDL)
files. By default, PlatGen synthesizes each processor IP core instance found in your
embedded hardware design using Xilinx Synthesis Technology (XST). PlatGen also
generates the system-level HDL file that interconnects all the IP cores, which can then be
synthesized as part of the overall design flow.


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Simulation Model Generation Tool (SimGen) - generates simulation models of the embedded
hardware system, based either on your original, behavioral embedded hardware design or
your finished, timing-accurate device implementation. SimGen can also incorporate your
embedded software to run on the model.


2.2 OVERVIEW OF VHDL:


VHDL (VHSIC hardware description language) is a hardware description
language used in electronic design automation to describe digital and mixed-signal systems
such as field-programmable gate arrays and integrated circuits.

VHDL is commonly used to write text models that describe a logic circuit. Such
a model is processed by a synthesis program, only if it is part of the logic design. A
simulation program is used to test the logic design using simulation models to represent the
logic circuits that interface to the design. This collection of simulation models is commonly
called a test bench.
The key advantage of VHDL, when used for systems design, is that it allows the
behavior of the required system to be described (modeled) and verified (simulated) before
synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system.
VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C,
and assembly code, which all run sequentially, one instruction at a time.

VHDL project is multipurpose. Being created once, a calculation block can be
used in many other projects. However, many formational and functional block parameters can
be tuned (capacity parameters, memory size, element base, block composition and
interconnection structure).


In this paper, we have simulated and synthesized the various parameters of ALUs
by using VHDL on Xilinx ISE 13.1 and SPARTAN 3E FPGA board.



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2.3 SYNTHESIS RESULT:


2.3.1 RTL View









Fig 2.1: RTL Design (Entity) Fig 2.2 RTL Design inside Entity





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2.3.2Technology view:






Fig 2.3 Technology view









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2.3.3 SYNTHESIS REPORT:

Target Device: xc3s400-4pq208




Table 2.1 Summary of Device Utilization

Maximum combinational path delay: 9.345ns
Total memory usage is 187568 kilobytes.



2.4 SIMULATION:


5a6 "r a=101110118 .=01100110 perati! a!s= a %ND .9
%!s=00100010: 5(=08 se-=008 $i!=0 =; !e<=08 =er=08 $#t=06





Fig 2.4 Simulation waveform of AND operation


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5.6 "r a= 101110118 .=01100110 perati! a!s= a s#. .95a/.+16
%!s=01010101: 5(=18 se-=108 $i!=1 =; !e<=08 =er=08 $#t=16




Fig 2.5 Simulation waveform of SUB operation




























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CHAPTER-3

IMPLEMENTATION on SPARTAN-3 Kit



3.1 PROCESSOR: XC3S400PQ208:

Features:

- It has the advanced features needed to fit the most demanding, high volume
applications

- SPARTAN3 400k logic cell in PQ208 Plastic Quad Flat Package

- Three families: SPARTAN 3, SPARTAN 3L, SPARTAN XA

- Very low cost, high performance logic solution for high volume, consumer
oriented applications.

- Densities as high as 72,880 logic cells.

- Three power rails for core, I/Os and Auxiliary purposes.

- 326 MHz system clock rate

- 90 nm process technology

- USB Interface

- RS232 Interface

- Configuration support for JTAG

- Flash PROM


The VHDL coding of this paper design is compiled and simulated using Xilinx ISE
13.1 and has been downloaded in FPGA using Spartan XC3S400PQ208 kit as shown in
Figure 3.1. The function of FPGA is embedded on the kit along with PROM, LEDs and DIP
switches. A Joint Test Action Group (JTAG) interface connects the FPGA chip with PROM
and leads to PC through a serial interface.

Due to limited DIP Switches, we would like give the value of A and B in the program.
The provision of a select switch used in this hardware enables the user to perform the
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required operation on the FPGA processor. The status of the selection lines, result and flags
are indicated by a series of bit LEDs.







Fig 3.1 Circuit diagram of ALU











17

CONCLUSION


VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was
implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device.
ALU was designed to perform arithmetic operations such as addition and subtraction using 8-
bit adder, increment, logical operations such as AND, OR, XOR and NOT operations and 1s
complement operations.
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REFERENCES


[1] J. Bhaskar, VHDL Primer, Pearson Education
[2] Charles Roth, Jr., Digital Systems Design Using VHDL, PWS Publishing Company
[3] ARM sys on chip architecture by steve furber
[4] Paper on VHDL Implementation of 8-Bit ALU by Suchita Kamble, Prof .N. N. Mhala
[5] Paper on Implementation of ALU using FPGA by Shikha Khurana, Kanika Kaur