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Code No: C5704, C6804, C7704
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech I SEMESTER EXAMINATIONS, APRIL/MAY-2013
ALGORITHMS FOR VLSI DESIGN AUTOMATION
(COMMON TO VLSI SYSTEM DESIGN, VLSI AND EMBEDDED SYSTEMS,
EMBEDDED SYSTEMS AND VLSI DESIGN)
Time: 3hours Max.Marks:60
Answer any five questions
All questions carry equal marks
- - -

1.a) Explain bottom to top design methodology.
b) How sales man algorithm is related in VLSI design?

2.a) Explain different automation tools preferred in VLSI design flow.
b) Explain dynamic programming with example.

3. Explain ROBBOD manipulation and its principles.

4.a) Explain in detail about Tabu search with pseudo code.
b) Explain in detail about gate level modeling and simulation with examples.

5.a) Explain binary decision diagrams of logic synthesis.
b) Explain the Liao wong algorithm.

6. Explain about packing LUTs to CLBs in FPGAs.

7. Explain FPGA Routing with path finder algorithm.

8.a) Explain MCM physical design cycle.
b) Differentiate chip array based with other methods.






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R09
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