1

Address Mode

As

Ad

Registers

Syntax

Operation

Registers

00

0

R0-R2, R4-
R15

Rn

Register Contents.

0

00



R3

#0

0 Constant source / bit bucket destination

Symbolic

01

1

R0

ADDR

(PC+next word) points to operand. (X(PC))

Indexed

01

1

R1, R4-R15

X(Rn)

(Rn+X) points to operand. X is next code word.

Absolute

01

1

R2

&ADDR

Next code word is the absolute address. (X(SR))

+1

01



R3

#1

+1 Constant

Indirect

10



R0-R1,R4-
R15

@Rn

Rn points to operand.

+4

10



R2

#4

+4 Constant

+2

10



R3

#2

+2 Constant

Immediate

11



R0

#N

Next word is the constant N. (@PC+)

Indirect auto-inc

11



R1,R4-R15

@Rn+

Rn points to operand, Rn is incremented (1 or 2).

+8

11



R2

#8

+8 Constant

-1

11



R3

#-1

-1 Constant



2

Op-code Instruction Format
0000 (0) Undefined Single Operand
0001 (1) RCC, SWPB, RRA, SXT, PUSH, CALL, RETI
0010 (2) JNE, JEQ, JNC, JC Jumps
0011 (3) JN, JGE, JL, JMP
0100 (4) MOV Double Operand
0101 (5) ADD
0110 (6) ADDC
0111 (7) SUBC
1000 (8) SUB
1001 (9) CMP
1010 (10-A) DADD
1011 (11-B) BIT
1100 (12-C) BIC
1101 (13-D) BIS
1110 (14-E) XOR
1111 (15-F) AND

3


4

5

6

7

8

9

10

11

12

13


14

15

16