EC6302 DIGITAL ELECTRONICS

2 Marks with Answers

Unit 1
1 De!ine "inar# $%&i'(
Binary logic consists of binary variables and logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two
distinct values: 1 and . There are three basic logic operations: A!", #$, and !#T.
2 )hat are the "asi' *i&ita$ $%&i' &ates(
The three basic logic gates are
A!" gate
#$ gate
!#T gate
3 )hat is a L%&i' &ate(
%ogic gates are the basic ele&ents that &a'e up a digital syste&. The electronic gate is a
circuit that is able to operate on a nu&ber of binary inputs in order to perfor& a
particular logical function.
+ Gi,e the '$assi!i'ati%n %! $%&i' !a-i$ies
Bipolar (nipolar
)aturated !on )aturated *+#)
!+#)
C+#)
$T% )chott'y TT%
,C% "T%
- - %
TT%
. )hi'h &ates are 'a$$e* as the /ni,ersa$ &ates( )hat are its a*,anta&es(
The !A!" and !#$ gates are called as the universal gates. These gates are used to
perfor& any type of logic application.
6 C$assi!# the $%&i' !a-i$# "# %0erati%n(
The Bipolar logic fa&ily is classified into
)aturated logic
(nsaturated logic.
The $T%, "T%, TT%, -
.
%, /T% logic co&es under the saturated logic fa&ily.
The )chott'y TT%, and ,C% logic co&es under the unsaturated logic fa&ily.
1 State the '$assi!i'ati%ns %! 2ET *e,i'es 2ET is '$assi!ie* as
1. 0unction 1ield ,ffect Transistor 201,T3
.. +etal oxide se&iconductor fa&ily 2+#)3.
3 Menti%n the '$assi!i'ati%n %! sat/rate* "i0%$ar $%&i' !a-i$ies.
The bipolar logic fa&ily is classified as follows:
$T%4 $esistor Transistor %ogic
"T%4 "iode Transistor logic -.%4
-ntegrated -n5ection %ogic TT%4
Transistor Transistor %ogic ,C%4
,&itter Coupled %ogic
4 Menti%n the i-0%rtant 'hara'teristi's %! *i&ita$ IC5s(
1an out
*ower dissipation
*ropagation "elay
!oise +argin
1an -n
#perating te&perature
*ower supply re6uire&ents
10 De!ine 2an6%/t(
1an out specifies the nu&ber of standard loads that the output of the gate can drive with
out i&pair&ent of its nor&al operation.
11 De!ine 0%wer *issi0ati%n(
*ower dissipation is &easure of power consu&ed by the gate when fully driven by all its
inputs.
12 )hat is 0r%0a&ati%n *e$a#(
*ropagation delay is the average transition delay ti&e for the signal to propagate fro&
input to output when the signals change in value. -t is expressed in ns.
13 De!ine n%ise -ar&in(
-t is the &axi&u& noise voltage added to an input signal of a digital circuit that does not
cause an undesirable change in the circuit output. -t is expressed in volts.
1+ De!ine !an in(
1an in is the nu&ber of inputs connected to the gate without any degradation in the
voltage level.
1. )hat is O0eratin& te-0erat/re(
All the gates or se&iconductor devices are te&perature sensitive in nature. The
te&perature in which the perfor&ance of the -C is effective is called as operating te&perature.
#perating te&perature of the -C vary fro&

C to 7

c.
16)hat is 7i&h Thresh%$* L%&i'(
)o&e digital circuits operate in environ&ents, which produce very high noise signals.
1or operation in such surroundings there is available a type of "T% gate which possesses a high
threshold to noise i&&unity. This type of gate is called /T% logic or /igh Threshold %ogic.
11 )hat are the t#0es %! TTL $%&i'(
1. #pen collector output
.. Tote&4*ole #utput
8. Tri4state output.
13 )hat is *e0$eti%n -%*e %0erati%n MOS(
-f the channel is initially doped lightly with p4type i&purity a conducting channel exists
at zero gate voltage and the device is said to operate in depletion &ode.
14 )hat is enhan'e-ent -%*e %0erati%n %! MOS(
-f the region beneath the gate is left initially uncharged the gate field &ust induce a
channel before current can flow. Thus the gate voltage enhances the channel current and such a
device is said to operate in the enhance&ent &ode.
20 Menti%n the 'hara'teristi's %! MOS transist%r(
1. The n4 channel +#) conducts when its gate4 to4 source voltage is positive.
.. The p4 channel +#) conducts when its gate4 to4 source voltage is negative
8. ,ither type of device is turned of if its gate4 to4 source voltage is zero.
21 7%w s'h%ttk# transist%rs are !%r-e* an* state its /se(
A schott'y diode is for&ed by the co&bination of &etal and se&iconductor. The
presence of schott'y diode between the base and the collector prevents the transistor fro& going
into saturation. The resulting transistor is called as schott'y transistor.
The use of schott'y transistor in TT% decreases the propagation delay without a sacrifice
of power dissipation.
22 List the *i!!erent ,ersi%ns %! TTL
1.TT% 2)td.TT%3 ..%TT% 2%ow *ower TT%3
8./TT% 2/igh )peed TT%3 9.)TT% 2)chott'y TT%3
:.%)TT% 2%ow power )chott'y TT%3
23 )h# t%te- 0%$e %/t0/ts 'ann%t "e '%nne'te* t%&ether
Tote& pole outputs cannot be connected together because such a connection
&ight produce excessive current and &ay result in da&age to the devices.
2+ State a*,anta&es an* *isa*,anta&es %! TTL
Adv:
,asily co&patible with other -Cs
%ow output i&pedance
"isadv:
;ired output capability is possible only with tristate and open collector type
)pecial circuits in Circuit layout and syste& design are re6uired.
2. )hen *%es the n%ise -ar&in a$$%w *i&ita$ 'ir'/its t% !/n'ti%n 0r%0er$#
;hen noise voltages are within the li&its of <!A2/igh )tate !oise +argin3 and <!= for
a particular logic fa&ily.
26 )hat ha00ens t% %/t0/t when a tristate 'ir'/it is se$e'te* !%r hi&h i-0e*an'e
#utput is disconnected fro& rest of the circuits by internal circuitry.
21 )hat is 1+000 series
-t is the oldest and standard C+#) fa&ily. The devices are not pin co&patible or
electrically co&patible with any TT% )eries.
Unit II
1 De!ine '%-"inati%na$ $%&i'
;hen logic gates are connected together to produce a specified output for certain
specified co&binations of input variables, with no storage involved, the resulting circuit is
called co&binational logic.
2 E80$ain the *esi&n 0r%'e*/re !%r '%-"inati%na$ 'ir'/its
The proble& definition
"eter&ine the nu&ber of available input variables > re6uired #?* variables.
Assigning letter sy&bols to -?# variables
#btain si&plified Boolean expression for each #?*.
#btain the logic diagra&.
3 De!ine 7a$! a**er an* !/$$ a**er
The logic circuit that perfor&s the addition of two bits is a half adder. The circuit that
perfor&s the addition of three bits is a full adder.
+ De!ine De'%*er(
A decoder is a &ultiple 4 input &ultiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different.
. )hat is "inar# *e'%*er(
A decoder is a co&binational circuit that converts binary infor&ation fro& n input lines
to a &axi&u& of .
n
out puts lines.
6 De!ine En'%*er(
An encoder has .
n
input lines and n output lines. -n encoder the output lines generate the
binary code corresponding to the input value.
1 )hat is 0ri%rit# En'%*er(
A priority encoder is an encoder circuit that includes the priority function. -n priority
encoder, if . or &ore inputs are e6ual to 1 at the sa&e ti&e, the input having the highest priority
will ta'e precedence.
3 De!ine -/$ti0$e8er(
+ultiplexer is a digital switch. -f allows digital infor&ation fro& several sources to be
routed onto a single output line.
4 )hat *% #%/ -ean "# '%-0arat%r
A co&parator is a special co&binational circuit designed pri&arily to co&pare the
relative &agnitude of two binary nu&bers.
Unit III
1 List "asi' t#0es %! 0r%&ra--a"$e $%&i' *e,i'es
. $ead only &e&ory
. *rogra&&able logic Array
. *rogra&&able Array %ogic
2 E80$ain ROM
A read only &e&ory2$#+3 is a device that includes both the decoder and the #$ gates
within a single -C pac'age. -t consists of n input lines and & output lines. ,ach bit co&bination
of the input variables is called an address. ,ach bit co&bination that co&es out of the output
lines is called a word. The nu&ber of distinct addresses possible with n input variables is .
n
.
3 De!ine a**ress an* w%r*9
-n a $#+, each bit co&bination of the input variable is called on address. ,ach bit
co&bination that co&es out of the output lines is called a word.
+ State the t#0es %! ROM
. +as'ed $#+.
. *rogra&&able $ead only +e&ory
. ,rasable *rogra&&able $ead only &e&ory.
. ,lectrically ,rasable *rogra&&able $ead only +e&ory.
. )hat is 0r%&ra--a"$e $%&i' arra#( 7%w it *i!!ers !r%- ROM(
-n so&e cases the nu&ber of don@t care conditions is excessive, it is &ore econo&ical to
use a second type of %)- co&ponent called a *%A. A *%A is si&ilar to a $#+ in conceptA
however it does not provide full decoding of the variables and does not generates all the
&inter&s as in the $#+.
B. )hi'h &ate is e:/a$ t% AND6in,ert Gate(
!A!" gate.
7. )hi'h &ate is e:/a$ t% OR6in,ert Gate(
!#$ gate.
3 ;/""$e* OR &ate is e:/a$ t%66666666666666
!A!" gate
4 ;/""$e* AND &ate is e:/a$ t%66666666666666
!#$ gate
10 E80$ain <ROM
*$#+ 2*rogra&&able $ead #nly +e&ory3
-t allows user to store data or progra&. *$#+s use the fuses with &aterial li'e
nichro&e and polycrystalline. The user can blow these fuses by passing around
. to : &A of current for the period : to .Cs.The blowing of fuses is called
progra&&ing of $#+. The *$#+s are one ti&e progra&&able. #nce
progra&&ed, the infor&ation is stored per&anent.
11 E80$ain E<ROM
,*$#+2,rasable *rogra&&able $ead #nly +e&ory3
,*$#+ use +#) circuitry. They store 1@s and @s as a pac'et of charge in a
buried layer of the -C chip. ;e can erase the stored data in the ,*$#+s by
exposing the chip to ultraviolet light via its 6uartz window for 1: to . &inutes.
-t is not possible to erase selective infor&ation. The chip can be reprogra&&ed.
12 E80$ain EE<ROM
,,*$#+2,lectrically ,rasable *rogra&&able $ead #nly +e&ory3
,,*$#+ also use +#) circuitry. "ata is stored as charge or no charge on an
insulated layer or an insulated floating gate in the device. ,,*$#+ allows
selective erasing at the register level rather than erasing all the infor&ation since
the infor&ation can be changed by using electrical signals.
13 )hat is RAM(
$ando& Access +e&ory. $ead and write operations can be carried out.
1+ )hat is 0r%&ra--a"$e $%&i' arra#( 7%w it *i!!ers !r%- ROM(
-n so&e cases the nu&ber of don@t care conditions is excessive, it is &ore econo&ical to
use a second type of %)- co&ponent called a *%A. A *%A is si&ilar to a $#+ in conceptA
however it does not provide full decoding of the variables and does not generates all the
&inter&s as in the $#+.
1. )hat is -ask 6 0r%&ra--a"$e(
;ith a &as' progra&&able *%A, the user &ust sub&it a *%A progra& table to the
&anufacturer.
16 )hat is !ie$* 0r%&ra--a"$e $%&i' arra#(
The second type of *%A is called a field progra&&able logic array. The user by &eans
of certain reco&&ended procedures can progra& the ,*%A.
17.List the -a=%r *i!!eren'es "etween <LA an*
<AL *%A:
Both A!" and #$ arrays are progra&&able and Co&plex
Costlier than *A%
*A%
A!" arrays are progra&&able #$ arrays are fixed
Cheaper and )i&pler
13 De!ine <LD
*rogra&&able %ogic "evices consist of a large array of A!" gates and #$ gates that
can be progra&&ed to achieve specific logic functions.
14 Gi,e the '$assi!i'ati%n %! <LDs
*%"s are classified as *$#+2*rogra&&able $ead #nly +e&ory3, *rogra&&able
%ogic Array2*%A3, *rogra&&able Array %ogic 2*A%3, and Deneric Array %ogic2DA%3
20 De!ine <ROM
*$#+ is *rogra&&able $ead #nly +e&ory. -t consists of a set of fixed A!" gates
connected to a decoder and a progra&&able #$ array.
21 De!ine <LA
*%A is *rogra&&able %ogic Array2*%A3. The *%A is a *%" that consists of a
progra&&able A!" array and a progra&&able #$ array.
22 De!ine <AL
*A% is *rogra&&able Array %ogic. *A% consists of a progra&&able A!" array and a
fixed #$ array with output logic.
23 )h# was <AL *e,e$%0e* (
-t is a *%" that was developed to overco&e certain disadvantages of *%A, such as
longer delays due to additional fusible lin's that result fro& using two progra&&able arrays and
&ore circuit co&plexity.
2+ )h# the in0/t ,aria"$es t% a <AL are "/!!ere*
The input variables to a *A% are buffered to prevent loading by the large nu&ber of
A!" gate inputs to which available or its co&ple&ent can be connected.
2. )hat *%es <AL 10L3 s0e'i!# (
*A% 4 *rogra&&able %ogic Array
1 4 Ten inputs
% 4 Active %#; #uput
E 4 ,ight #utputs
26 Gi,e the '%-0aris%n "etween <ROM an* <LA
*$#+ *%A
1. And array is fixed and #$ Both A!" and #$ arrays are
array is progra&&able. *rogra&&able.
.. Cheaper and si&ple to use. Costliest and co&plex than
*$#+).
Unit I>
1 )hat are the '$assi!i'ati%n %! se:/entia$ 'ir'/its(
The se6uential circuits are classified on the basis of ti&ing of their signals into two
types. They are,
13)ynchronous se6uential circuit.
.3Asynchronous se6uential circuit.
2 De!ine 2$i0 !$%0
The basic unit for storage is flip flop. A flip4flop &aintains its output state either at 1 or
until directed by an input signal to change its state.
3)hat are the *i!!erent t#0es %! !$i06!$%0(
There are various types of flip flops. )o&e of the& are &entioned below they are,
$) flip4flop
)$ flip4flop
" flip4flop
0= flip4flop
T flip4flop
+)hat is the %0erati%n %! D !$i06!$%0(
-n " flip4flop during the occurrence of cloc' pulse if "F1, the output G is set and if
"F, the output is reset.
. )hat is the %0erati%n %! ?@ !$i06!$%0(
;hen = input is low and 0 input is high the G output of flip4flop isset.
;hen = input is high and 0 input is low the G output of flip4flop isreset.
;hen both the inputs = and 0 are low the output does not change
;hen both the inputs = and 0 are high it is possible to set or reset the
flip4flop 2ie3 the output toggle on the next positive cloc' edge.
6 )hat is the %0erati%n %! T !$i06!$%0(
T flip4flop is also 'nown as Toggle flip4flop.
;hen TF there is no change in the output.
;hen TF1 the output switch to the co&ple&ent state 2ie3 the output
toggles.
1 De!ine ra'e ar%/n* '%n*iti%n
-n 0= flip4flop output is fed bac' to the input. Therefore change in the output results
change in the input. "ue to this in the positive half of the cloc' pulse if both 0 and = are high
then output toggles continuously. This condition is called Hrace around condition@.
3 )hat is e*&e6tri&&ere* !$i06!$%0(
The proble& of race around condition can solved by edge triggering flip flop. The ter&
edge triggering &eans that the flip4flop changes state either at the positive edge or negative edge
of the cloc' pulse and it is sensitive to its inputs only at this transition of the cloc'.
4 )hat is a -aster6s$a,e !$i06!$%0(
A &aster4slave flip4flop consists of two flip4flops where one circuit serves as a &aster
and the other as a slave.
10 De!ine rise ti-e
The ti&e re6uired to change the voltage level fro& 1I to JI is 'nown as rise
ti&e2tr3.
11De!ine !a$$ ti-e
The ti&e re6uired to change the voltage level fro& JI to 1I is 'nown as fall ti&e2tf3.
12De!ine skew an* '$%'k skew
The phase shift between the rectangular cloc' wavefor&s is referred to as s'ew and the
ti&e delay between the two cloc' pulses is called cloc' s'ew.
13De!ine set/0 ti-e
The setup ti&e is the &ini&u& ti&e re6uired to &aintain a constant voltage levels at the
excitation inputs of the flip4flop device prior to the triggering edge of the cloc' pulse in order for
the levels to be reliably cloc'ed into the flip flop. -t is denoted as tsetup.
1+ De!ine h%$* ti-e
The hold ti&e is the &ini&u& ti&e for which the voltage levels at the excitation inputs
&ust re&ain constant after the triggering edge of the cloc' pulse in order for the levels to be
reliably cloc'ed into the flip flop. -t is denoted as thold .
1.)hat is !/n*a-enta$ -%*e
A transition fro& one stable state to another occurs only in response to a change in the
input state. After a change in one input has occurred, no other change in any input occurs until
the circuit enters a stable state. )uch a &ode of operation is referred to as a funda&ental &ode.
16 )rite sh%rt n%te %n share* r%w state assi&n-ent
$aces can be avoided by &a'ing a proper binary assign&ent to the state variables. /ere,
the state variables are assigned with binary nu&bers in such a way that only one state variable
can change at any one state variable can change at any one ti&e when a state transition occurs. To
acco&plish this, it is necessary that states between which transitions occur be given ad5acent
assign&ents. Two binary are said to be ad5acent if they differ in only one variable.
11 )rite sh%rt n%te %n %ne h%t state assi&n-ent
The one hot state assign&ent is another &ethod for finding a race free state assign&ent.
-n this &ethod, only one variable is active or hot for each row in the original flow table, ie, it
re6uires one state variable for each row of the flow table. Additional row are introduced to
provide single variable changes between internal state transitions.
13 De!ine 0r%0a&ati%n *e$a#
A propagation delay is the ti&e re6uired to change the output after the application of the
input.
14 De!ine re&isters
A register is a group of flip4flops flip4flop can store one bit infor&ation. )o an n4bit register has a
group of n flip4flops and is capable of storing any binary infor&ation?nu&ber containing n4bits.
20 De!ine shi!t re&isters
The binary infor&ation in a register can be &oved fro& stage to stage within the register
or into or out of the register upon application of cloc' pulses. This type of bit &ove&ent or
shifting is essential for certain arith&etic and logic operations used in &icroprocessors. This
gives rise to group of registers called shift registers.
21)hat are the *i!!erent t#0es %! shi!t t#0e(
There are five types. They are,
)erial -n )erial #ut )hift $egister
)erial -n *arallel #ut )hift $egister
*arallel -n )erial #ut )hift $egister
*arallel -n *arallel #ut )hift $egister
Bidirectional )hift $egister
22.E80$ain the !$i06!$%0 e8'itati%n ta"$es !%r RS 11.
$) flip4flop
-n $) flip4flop there are four possible transitions fro& the present state to the next
state. They are,
transition: This can happen either when $F)F or when $F1 and )F.
1 transition: This can happen only when )F1 and $F. 1
transition: This can happen only when )F and $F1.
1 1 transition: This can happen either when )F1 and $F or )F and
$F.
23 De!ine se:/entia$ 'ir'/it(
-n se6uential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.
2+ Gi,e the '%-0aris%n "etween '%-"inati%na$ 'ir'/its an* se:/entia$ 'ir'/its
Co&binational circuits )e6uential circuits
+e&ory unit is not re6uired +e&ory unity is re6uired
*arallel adder is a co&binational circuit )erial adder is a se6uential circuit
2. )hat *% #%/ -ean "# 0resent state(
The infor&ation stored in the &e&ory ele&ents at any given ti&e define.s the present
state of the se6uential circuit.
26 )hat *% #%/ -ean "# ne8t state(
The present state and the external inputs deter&ine the outputs and the next state of
the se6uential circuit.
21 State the t#0es %! se:/entia$ 'ir'/its(
a. )ynchronous se6uential circuits
b. Asynchronous se6uential circuits
23 De!ine s#n'hr%n%/s se:/entia$ 'ir'/it
-n synchronous se6uential circuits, signals can affect the &e&ory ele&ents only at
discrete instant of ti&e.
Unit >
1 De!ine As#n'hr%n%/s se:/entia$ 'ir'/it(
-n asynchronous se6uential circuits change in input signals can affect &e&ory ele&ent
at any instant of ti&e.
2Gi,e the '%-0aris%n "etween s#n'hr%n%/s A As#n'hr%n%/s se:/entia$ 'ir'/its(
)ynchronous se6uential circuits Asynchronous se6uential circuits.
+e&ory ele&ents are cloc'ed flip4flops +e&ory ele&ents are either unloc'ed flip 4
flops or ti&e delay ele&ents.
,asier to design +ore difficult to design
3 The !%$$%win& wa,e !%r-s are a00$ie* t% the in0/ts %! SR $at'h Deter-ine the B
wa,e!%r- Ass/-e initia$$# B C 1
/ere the latch input has to be pulsed &o&entarily to cause a change in the latch output state,
and the output will re&ain in that new state even after the input pulse is over.
+ )hat is ra'e ar%/n* '%n*iti%n(
-n the 0= latch, the output is feedbac' to the input, and therefore changes in the output
results change in the input. "ue to this in the positive half of the cloc' pulse if 0 and = are
both high then output toggles continuously. This condition is 'nown as race around condition.
.Gi,e the '%-0aris%n "etween s#n'hr%n%/s A As#n'hr%n%/s '%/nters
Asynchronous counters )ynchronous counters
-n this type of counter flip4flops are -n this type there is no connection between
connected in such a way that output of 1st output of first flip4flop and cloc' input of
flip4flop drives the cloc' for the next flip4 the next flip 4 flop
flop.
All the flip4flops are !ot cloc'ed All the flip4flops are cloc'ed
si&ultaneously si&ultaneously
6 The t 0* !%r ea'h !$i06!$%0 is .0 ns Deter-ine the -a8i-/- %0eratin& !re:/en'# !%r
MOD 6 32 ri00$e '%/nter
f &ax 2ripple3 F : x : ns F 9 +/K
1 )hat are se'%n*ar# ,aria"$es(
4present state variables in asynchronous se6uential circuits
3)hat are e8'itati%n ,aria"$es(
4next state variables in asynchronous se6uential circuits
4 )hat is !/n*a-enta$ -%*e se:/entia$ 'ir'/it(
6input variables changes if the circuit is
stable
4inputs are levels, not pulses
4only one input can change at a given ti&e
10 )hat are 0/$se -%*e 'ir'/it(
4inputs are pulses
4width of pulses are long for circuit to respond to the input
4pulse width &ust not be so long that it is still present after the new state is reached
11 )hat are the si&ni!i'an'e %! state assi&n-ent(
-n synchronous circuits4state assign&ents are &ade with the ob5ective of circuit
reduction
Asynchronous circuits4its ob5ective is to avoid critical races
12 )hen *% ra'e '%n*iti%n %''/r(
4two or &ore binary state variables change their value in response to the change in i?p
variable
13)hat is n%n 'riti'a$ ra'e(
4final stable state does not depend on the order in which the state variable changes
4race condition is not har&ful
1+)hat is 'riti'a$ ra'e(
4final stable state depends on the order in which the state variable changes
4race condition is har&ful
1. )hen *%es a '#'$e %''/r(
4asynchronous circuit &a'es a transition through a series of unstable state
16)hat are the *i!!erent te'hni:/es /se* in state assi&n-ent(
4shared row state assign&ent
4one hot state assign&ent
11)hat are the ste0s !%r the *esi&n %! as#n'hr%n%/s se:/entia$ 'ir'/it(
6construction of pri&itive flow table
4reduction of flow table
4state assign&ent is &ade
4realization of pri&itive flow table
13)hat is haDar*(
4unwanted switching transients
14)hat is stati' 1 haDar*(
4output goes &o&entarily when it should re&ain at 1
20)hat is stati' 0 haDar*(
4output goes &o&entarily 1 when it should re&ain at
21 )hat is *#na-i' haDar*(
4output changes 8 or &ore ti&es when it changes fro& 1 to or to 1
22)hat is the 'a/se !%r essentia$ haDar*s(
4une6ual delays along . or &ore path fro& sa&e input
23)hat is !$%w ta"$e(
4state table of an synchronous se6uential networ'
2+ )hat is 0ri-iti,e !$%w 'hart( 6%ne
stable state per row
2.)hat is '%-"inati%na$ 'ir'/it(
#utput depends on the given input. -t has no storage ele&ent.
26De!ine -er&er &ra0h
The &erger graph is defined as follows. -t contains the sa&e nu&ber of vertices as the
state table contains states. A line drawn between the two state vertices indicates each co&patible
state pair. -t two states are inco&patible no connecting line is drawn.
21De!ine '$%se* '%,erin&
A )et of co&patibles is said to be closed if, for every co&patible contained in the set, all
its i&plied co&patibles are also contained in the set. A closed set of co&patibles, which
contains all the states of +, is called a closed covering.
23De!ine state ta"$e
1or the design of se6uential counters we have to relate present states and next states.
The table, which represents the relationship between present states and next states, is called
state table.
24 De!ine t%ta$ state
The co&bination of level signals that appear at the inputs and the outputs of the delays
define what is called the total state of the circuit.
30)hat are the ste0s !%r the *esi&n %! as#n'hr%n%/s se:/entia$ 'ir'/it(
1. Construction of a pri&itive flow table fro& the proble& state&ent.
.. *ri&itive flow table is reduced by eli&inating redundant states using the state
reduction
8. )tate assign&ent is &ade
9. The pri&itive flow table is realized using appropriate logic ele&ents.
31 De!ine 0ri-iti,e !$%w ta"$e 9
-t is defined as a flow table which has exactly one stable state for each row in the table.
The design process begins with the construction of pri&itive flow table.
8..)hat are the t#0es %! as#n'hr%n%/s 'ir'/its (
1. 1unda&ental &ode circuits
.. *ulse &ode circuits
33 Gi,e the '%-0aris%n "etween state Assi&n-ent S#n'hr%n%/s 'ir'/it an* state
assi&n-ent as#n'hr%n%/s 'ir'/it
-n synchronous circuit, the state assign&ents are &ade with the ob5ective of circuit
reduction. -n asynchronous circuits, the ob5ective of state assign&ent is to avoid critical races.
3+ )hat are ra'es(
;hen . or &ore binary state variables change their value in response to a change in an
input variable, race condition occurs in an asynchronous se6uential circuit. -n case of une6ual
delays, a race condition &ay cause the state variables to change in an unpredictable &anner.
3. De!ine n%n 'riti'a$ ra'e
-f the final stable state that the circuit reaches does not depend on the order in which the
state variable changes, the race condition is not har&ful and it is called a non critical race.
36 De!ine 'riti'a$ ra'e(
-f the final stable state depends on the order in which the state variable changes, the race
condition is har&ful and it is called a critical race.
31 )hat is a '#'$e(
A cycle occurs when an asynchronous circuit &a'es a transition through a series of
unstable states. -f a cycle does not contain a stable state, the circuit will go fro& one unstable to
stable to another, until the inputs are changed.
33 )rite a sh%rt n%te %n !/n*a-enta$ -%*e as#n'hr%n%/s 'ir'/it
1unda&ental &ode circuit assu&es that. The input variables change only when the
circuit is stable. #nly one input variable can change at a given ti&e and inputs are levels and not
pulses.
34 )rite a sh%rt n%te %n 0/$se -%*e 'ir'/it
*ulse &ode circuit assu&es that the input variables are pulses instead of level. The
width of the pulses is long enough for the circuit to respond to the input and the pulse width
&ust not be so long that it is still present after the new state is reached.
+0 De!ine se'%n*ar# ,aria"$es
The delay ele&ents provide a short ter& &e&ory for the se6uential circuit. The present
state and next state variables in asynchronous se6uential circuits are called secondary variables.
+1 De!ine !$%w ta"$e in as#n'hr%n%/s se:/entia$ 'ir'/it
-n asynchronous se6uential circuit state table is 'nown as flow table because of the
behaviour of the asynchronous se6uential circuit. The stage changes occur in independent of a
cloc', based on the logic propagation delay, and cause the states to .flow. fro& one to another.
+2 A 0/$se -%*e as#n'hr%n%/s -a'hine has tw% in0/ts I! 0r%*/'es an %/t0/t whene,er
tw% '%nse'/ti,e 0/$ses %''/r %n %ne in0/t $ine %n$# The %/t0/t re-ains at 1 /nti$ a 0/$se
has %''/rre* %n the %ther in0/t $ine )rite *%wn the state ta"$e !%r the -a'hine
+3 )hat is !/n*a-enta$ -%*e
A transition fro& one stable state to another occurs only in response to a change in
the input state. After a change in one input has occurred, no other change in any input
occurs until the circuit enters a stable state. )uch a &ode of operation is referred to as a
funda&ental &ode.
++ )rite sh%rt n%te %n share* r%w state assi&n-ent
$aces can be avoided by &a'ing a proper binary assign&ent to the state variables.
/ere, the state variables are assigned with binary nu&bers in such a way that only one state
variable can change at any one state variable can change at any one ti&e when a state
transition occurs. To acco&plish this, it is necessary that states between which transitions
occur be given ad5acent assign&ents. Two binary are said to be ad5acent if they differ in
only one variable.
+. )rite sh%rt n%te %n %ne h%t state assi&n-ent
The one hot state assign&ent is another &ethod for finding a race free state
assign&ent. -n this &ethod, only one variable is active or hot for each row in the original
flow table, ie, it re6uires one state variable for each row of the flow table. Additional row
are introduced to provide single variable changes between internal state transitions.
<art ;
Unit6I
13 ,xplain with neat diagra&s TT%.
"isadvantages of other
fa&ilies "iagra& of TT%
Theory
;or'ing principle
.. "iscuss all the characteristics of digital
-C@s. 1an out
*ower
dissipation
*ropagation
"elay !oise
+argin
1an -n
#perating te&perature
*ower supply
re6uire&ents
8. ,xplain with neat diagra& how an open collector TT%
operates. "isadvantages of other fa&ilies
"iagra& of open collector gate
TT% Theory
;or'ing principle
9. ,xplain the different applications of open collector
TT%. ;ired logic
Co&&on bus
syste& "rive a
la&p or relay
:. ,xplain in detail about schott'y TT%.
"isadvantages of other fa&ilies
"iagra& of schott'y TT%
Theory
;or'ing principle
Advantages
B.,xplain with necessary diagra&s +#) > C+#). *+#)
!+#)
C+#) "iagra&s
Unit6II
7."esign a 94bit binary adder?subtractor circuit. Basic e6uations
Co&parison of e6uations "esign using twos
co&ple&ent Circuit diagra&
E."esign and explain a co&parator to co&pare two identical words. Two nu&bers
represented by A F A8A.A1A > B F B8B.B1B -f two nu&bers e6ual * F Ai Bi
#btain the logic ,xpression . #btain the logic
diagra&.
J.,xplain in detail the loo' ahead carry generator. Bloc' diagra&
,xplanation %ogic diagra&
Unit6III
1. "esign a logic circuit to convert the BC" code to ,xcess L 8 code. Truth Table for
BC" to ,xcess L 8 conversion.
=4&ap si&plification
%ogic circuit i&ple&enting the Boolean ,xpression 11.,xplain in
detail about *%A and *A%.
%ogic difference between *ro& > *%A %ogic diagra&
i&ple&enting a function %ogic difference between *ro&
> *A% %ogic diagra& i&ple&enting a function
1.. -&ple&ent 12A,B,C,"3F 21,8,9,11,1.,18,19,1:3 using &ultiplexer.
-&ple&entation
Table
explanation
18. -&ple&ent ;2A,B,C,"3 F 2.,1.,183
M2A,B,C,"3 F 27,E,J,1,11,1.,18,19,1:3
N2A,B,C,"3 F 2,.,8,9,:,B,7,E,1,11,1:3
K 2A,B,C,"3 F 21,.,E,1.,183 using *A%21B3
Table
*A% i&ple&entation
Unit6I>
19.,xplain the wor'ing of BC" $ipple Counter with the help of state diagra& and logic
diagra&.
BC" $ipple Counter Count se6uence
Truth Table
)tate diagra& representing the Truth Table
Truth Table for the 04= 1lip 1lop
%ogic "iagra&
1:."esign a se6uential detector which produces an output 1 every ti&e the input se6uence
111 is detected.
Construct state diagra&
#btain the flow table
#btain the flow table > output table
Transition table
)elect flip flop
,xcitation table
%ogic diagra&
1B. ,xplain in detail about serial in serial out shift register.
Bloc' diagra&
Theoretical explanation
%ogic diagra& ;or'ing
Unit6>
17.,xplain with neat diagra& the different hazards and the way to eli&inate the&.
Classification of hazards
)tatic hazard > "yna&ic hazard definitions
= &ap for selected functions
+ethod of eli&ination
,ssential hazards
1E.)tate with a neat exa&ple the &ethod for the &ini&ization of pri&itive flow table.
Consider a state diagra&
#btain the flow table
(sing i&plication table reduce the flow table (sing
&erger graph obtain &axi&al co&patibles <erify closed
> covered conditions
*lot the reduced flow table
1J."esign a asynchronous se6uential circuit with . inputs T and C. The output attains a value of 1
when T F 1 > c &oves fro& 1 to . #therwise the output is .
#btain the state diagra&
#btain the flow table
(sing i&plication table reduce the flow table (sing
&erger graph obtain &axi&al co&patibles <erify closed
> covered conditions
*lot the reduced flow table
#btain transition table ,xcitation
table
%ogic diagra&
.. ,xplain in detail about $aces. Basics
of races
*roble& created due to races
Classification of races $e&edy for
races
cycles
.1. ,xplain the different &ethods of state assign&ent Three
row state assign&ent
)hared row state assign&ent 1our
row flow table
+ultiple row state assign&ent
*revention of races.