Helio Board SCH v1.22

5
Helio Board
PAGE
C
DESCRIPTION
C
Block Diagram
FPGA Package Top
Cyclone V SoC Bank 3 & 4
Cyclone V SoC Bank 7
Cyclone V SoC Transceivers & Clocks
PLL
Cyclone V SoC Configuration
JTAG
10
DDR3
11
HSMC
12
Ethernet PHY & RJ45
13
QSPI Flash & Reset Circuit
14
USB 2.0 OTG & Micro SD Card
15
User I/O ,RTC
16
UART
17
On-Board USB Blaster II
18
Power Monitor
19
Power1 - DC Input, 1.1V
20
Power2 - 3.3V
21
Power3 - 1.5V, DDR
22
Power4 - 2.5V, 5V, 1.8V
23
Power5 - 3.3V_EXT
24
Cyclone V SoC Power
25
Cyclone V SoC Capacitor
26
History
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN
Title
NOV. 20, 2013
Approval
Helio Board
Size Document Number
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Date: Wednesday, November 20, 2013
Sheet
1
of
Rev
STEP
1.22
26
FPGA Package Top View

D
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26

4
K
N
A
B
C
o
S
X
G
V
E
N
O
L
C
Y
C
U1B
U1A
D
CYCLONE V GX SoC BANK

BA NK 3
HSMA_PRSNTn
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_RX_D_P11
HSMA_RX_D_N11
AD5
AE4
AF4
AD10
AE9
T11
U11
AE7
AF8
AE8
AF9
AD11
AE11
Bank 3A
DIFFO_TX_B8p,DQ1B
Bank 3B
DIFFIO_TX_B25p,DQ2B,B_WE#
DIFFIO_TX_B32p,DQ2B,B_CAS#
DIFFIO_TX_B25n,GND
DIFFIO_TX_B32n,DQ2B,B_RAS#
DIFFIO_RX_B26p,DQ2B,B_A_14
DIFFIO_TX_B33p,DQ3B,B_BA_0
DIFFIO_RX_B26n,DQ2B,B_A_15
DIFFIO_TX_B33n,GND
DIFFIO_RX_B27p,DQS2B,B_CS#_0
DIFFIO_RX_B34p,DQ3B,B_BA_1
DIFFIO_RX_B27n,DQSn2B,B_CS#_1
DIFFIO_RX_B34n,DQ3B,B_BA_2
DIFFIO_TX_B28p,B_A_12
DIFFIO_RX_B35p,DQS3B,B_CK
DIFFIO_TX_B28n,DQ2B,B_A_13
DIFFIO_RX_B35n,DQSn3B,B_CK#
DIFFIO_TX_B29p,DQ2B,B_A_10
DIFFIO_TX_B36p,B_A_6
DIFFIO_TX_B40p,DQ3B,B_A_0
AF5
AF6
AF7
AG6
AF11
AF10
T13
T12
AH3
AH2
AE12
AD12
AH6
AH5
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P16
HSMA_TX_D_N16
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
5CSXFC6C6U23
2.5V
1.5V
C426 0.1uF
C427 0.1uF
R1
2K
R2
2K
AG8
AG13
AF13
U14
U13
AG9
AH8
AG10
AH9
AF15
AE15
AG11
AH11
AH12
DIFFIO_TX_B41p,DQ4B,B_DQ_2
DIFFIO_RX_B42p,DQ4B,B_DQ_1
DIFFIO_RX_B42n,DQ4B,B_DQ_0
DIFFIO_RX_B43p,DQS4B,B_DQS_0
DIFFIO_RX_B43n,DQSn4B,B_DQS#_0
DIFFIO_TX_B44p,B_ODT_0
DIFFIO_TX_B44n,DQ4B,B_DQ_3
DIFFIO_TX_B45n,DQ4B,B_ODT_1
DIFFIO_TX_B48p,DQ4B,B_DM_0
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_D2
AF17
AG16
W14
V13
AG14
AH13
AG15
AH14
AD17
AE17
AH17
AH16
AF18
DIFFIO_TX_B52p,B_CKE_1
DIFFIO_TX_B53n,DQ5B,B_CKE_0
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMA_TX_D_P3
HSMA_TX_D_N3
AE19
AD19
AA19
AA18
AG18
AH18
DIFFIO_TX_B60p,B_RESET#
AH7
HSMA_D3
DIFFIO_TX_B61n,DQ6B,GND
AG19
AH19
AE20
AD20
AF20
AG20
AG21
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_TX_D_P0
HSMA_TX_D_N0
HV_USB_B2_SCL
AF22
AF21
AD23
AE22
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMA_RX_D_P0
HSMA_RX_D_N0
AH21
AH23
AH22
AG23
AF23
AG24
AH24
AG26
HV_USB_B2_SDA
HSMA_TX_D_P1
HSMA_TX_D_N1
HV_USB_B2_DATA4
HV_USB_B2_DATA5
HV_USB_B2_DATA3
HV_USB_B2_DATA0
HV_USB_B2_DATA1
AE24
AE23
AC22
AC23
HV_USB_B2_DATA6
HV_USB_B2_DATA7
HV_USB_B2_RESETn
AH26
AG28
AH27
AF25
AG25
AF27
AF28
HV_USB_B2_OEn
Bank 4A
RZQ_0,DIFFIO_TX_B41n
VCC
8
1
2
VCC_IO1
VCC_IO2
GND
VL
TRI_STATE
HV_USB_B2_RDn
HV_USB_B2_WRn
HV_USB_B2_DATA2
HV_USB_B2_EMPTY
HV_USB_B2_FULL
VL_IO1
VL_IO2
5
4
USB_SCL 17
USB_SDA 17
HSMA_PRSNTn
HSMA_PRSNTn 11
HSMA_D[3..0]
HSMA_D[3..0] 11
HSMA_TX_D_P[16..0]
HSMA_TX_D_P[16..0] 11
HSMA_TX_D_N[16..0]
2.5V
1.5V
0.1uF
USB_B2_CLK 7,17
3
6
MAX3373EEKA+T
C1
OVERTEMP 18
5CSXFC6C6U23
U2
HV_USB_B2_SCL
HV_USB_B2_SDA
HSMA_D0
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_D1
U3
C2
16
VCC
20
19
18
17
14
13
12
11
IO_VCC1
IO_VCC2
IO_VCC3
IO_VCC4
IO_VCC5
IO_VCC6
IO_VCC7
IO_VCC8
15
GND
VL
HSMA_TX_D_N[16..0] 11
HSMA_RX_D_P[16..0]
0.1uF
FPGA USB INTERFACE
HSMA_RX_D_P[16..0] 11
HSMA_RX_D_N[16..0]
HSMA_RX_D_N[16..0] 11
HV_USB_B2_RESETn
HV_USB_B2_EMPTY
HV_USB_B2_RDn
HV_USB_B2_WRn
HV_USB_B2_OEn
HV_USB_B2_FULL
IO_VL1
IO_VL2
IO_VL3
IO_VL4
IO_VL5
IO_VL6
IO_VL7
IO_VL8
1
2
3
4
7
8
9
10
USB_RESETn 17
USB_EMPTY 17
USB_RDn 17
USB_WRn 17
USB_OEn 17
USB_FULL 17
1.5V
EN
R3
1K
MAX3013EUP
2.5V
C3
0.1uF
HV_USB_B2_DATA5
HV_USB_B2_DATA6
HV_USB_B2_DATA2
HV_USB_B2_DATA1
HV_USB_B2_DATA4
HV_USB_B2_DATA0
HV_USB_B2_DATA3
HV_USB_B2_DATA7
1.5V
U4
C4
16
VCC
20
19
18
17
14
13
12
11
IO_VCC1
IO_VCC2
IO_VCC3
IO_VCC4
IO_VCC5
IO_VCC6
IO_VCC7
IO_VCC8
15
GND
VL
IO_VL1
IO_VL2
IO_VL3
IO_VL4
IO_VL5
IO_VL6
IO_VL7
IO_VL8
0.1uF
5
1
2
3
4
7
8
9
10
USB_B2_DATA5
USB_B2_DATA6
USB_B2_DATA2
USB_B2_DATA1
USB_B2_DATA4
USB_B2_DATA0
USB_B2_DATA3
USB_B2_DATA7
R4
USB_B2_DATA[7..0] 17
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
1.5V
EN
1K
NOV. 20, 2013
Checked
MAX3013EUP
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
Cyclone V SoC Bank 5, 6

USER_PB_HPS[3..0]
USER_PB_HPS[3..0] 15
USER_DIPSW_HPS[3..0]
USER_DIPSW_HPS[3..0] 15
U1D
B ANK 6
U1C
BA NK 5
Y17
Y18
Y16
18 I2C_SCL_FPGA
18 I2C_SDA_FPGA
DIFFIO_RX_R4p,DQ1R
DIFFIO_RX_R4n,DQ1R
DIFFIO_RX_R6p,DQS1R
AA24
AA23
V16
V15
DIFFIO_TX_R7p,DQ1R
DIFFIO_TX_R7n
DIFFIO_RX_R8p,DQ1R
DIFFIO_RX_R8n,DQ1R
AB25
RZQ_2,DIFFIO_TX_R24n
Bank 5A
RZQ_1,DIFFIO_TX_R1p,DQ1R
R5
AF26
Bank 5B
100_1%
DDR3_HPS_A0
DDR3_HPS_A1
DDR3_HPS_A2
DDR3_HPS_A3
DDR3_HPS_A4
DDR3_HPS_A5
DDR3_HPS_A6
DDR3_HPS_A7
DDR3_HPS_A8
DDR3_HPS_A9
DDR3_HPS_A10
DDR3_HPS_A11
DDR3_HPS_A12
DDR3_HPS_A13
DDR3_HPS_A14
5CSXFC6C6U23
10 DDR3_HPS_CK_P
10 DDR3_HPS_CK_N
10 DDR3_HPS_CKE
DDR3_HPS_BA0
DDR3_HPS_BA1
DDR3_HPS_BA2
10 DDR3_HPS_RASn
10 DDR3_HPS_CASn
10 DDR3_HPS_WEn
10 DDR3_HPS_CSn
10 DDR3_HPS_ODT
DDR3_HPS_DM2
DDR3_HPS_DQS_P2
DDR3_HPS_DQS_N2
DDR3_HPS_DQ16
DDR3_HPS_DQ17
DDR3_HPS_DQ18
DDR3_HPS_DQ19
DDR3_HPS_DQ20
DDR3_HPS_DQ21
DDR3_HPS_DQ22
DDR3_HPS_DQ23
HPS_RZQ_0
HPS_DDR,HPS_A_0
HPS_DDR,HPS_A_1
HPS_DDR,HPS_A_2
HPS_DDR,HPS_A_3
HPS_DDR,HPS_A_4
HPS_DDR,HPS_A_5
HPS_DDR,HPS_A_6
HPS_DDR,HPS_A_7
HPS_DDR,HPS_A_8
HPS_DDR,HPS_A_9
HPS_DDR,HPS_A_10
HPS_DDR,HPS_A_11
HPS_DDR,HPS_A_12
HPS_DDR,HPS_A_13
HPS_DDR,HPS_A_14
HPS_DDR,HPS_A_15
N21
N20
L28
K28
A27
H25
G25
A25
A26
E25
L21
L20
D28
G26
HPS_DDR,HPS_CK
HPS_DDR,HPS_CK#
HPS_DDR,HPS_CKE_0
HPS_DDR,HPS_CKE_1
HPS_DDR,HPS_BA_0
HPS_DDR,HPS_BA_1
HPS_DDR,HPS_BA_2
HPS_DDR,HPS_RAS#
HPS_DDR,HPS_CAS#
HPS_DDR,HPS_WE#
HPS_DDR,HPS_CS#_0
HPS_DDR,HPS_CS#_1
HPS_DDR,HPS_ODT_0
HPS_DDR,HPS_ODT_1
W28
T19
T18
N24
N25
T28
U28
N26
N27
R27
V27
Bank 6B
HPS_DDR,HPS_DM_2
HPS_DDR,HPS_DQS_2
HPS_DDR,HPS_DQS#_2
HPS_DDR,HPS_DQ_16
HPS_DDR,HPS_DQ_17
HPS_DDR,HPS_DQ_18
HPS_DDR,HPS_DQ_19
HPS_DDR,HPS_DQ_20
HPS_DDR,HPS_DQ_21
HPS_DDR,HPS_DQ_22
HPS_DDR,HPS_DQ_23
DDR3_HPS_DM3
AB28
DDR3_HPS_DQS_P3 U19
DDR3_HPS_DQS_N3 T20
DDR3_HPS_DQ24
R26
DDR3_HPS_DQ25
R25
DDR3_HPS_DQ26 AA28
DDR3_HPS_DQ27
W26
DDR3_HPS_DQ28
R24
DDR3_HPS_DQ29
T24
DDR3_HPS_DQ30
Y27
DDR3_HPS_DQ31 AA27
Bank 6A
D25
C28
B28
E26
D26
J21
J20
C26
B26
F26
F25
A24
B24
D24
C24
G23
F24
HPS_DDR,HPS_DM_0
HPS_DDR,HPS_DQS_0
HPS_DDR,HPS_DQS#_0
HPS_DDR,HPS_DQ_0
HPS_DDR,HPS_DQ_1
HPS_DDR,HPS_DQ_2
HPS_DDR,HPS_DQ_3
HPS_DDR,HPS_DQ_4
HPS_DDR,HPS_DQ_5
HPS_DDR,HPS_DQ_6
HPS_DDR,HPS_DQ_7
G28
R17
R16
J25
J24
E28
D27
J26
K26
G27
F28
DDR3_HPS_DM0
DDR3_HPS_DQS_P0
DDR3_HPS_DQS_N0
DDR3_HPS_DQ0
DDR3_HPS_DQ1
DDR3_HPS_DQ2
DDR3_HPS_DQ3
DDR3_HPS_DQ4
DDR3_HPS_DQ5
DDR3_HPS_DQ6
DDR3_HPS_DQ7
HPS_DDR,HPS_DM_1
HPS_DDR,HPS_DQS_1
HPS_DDR,HPS_DQS#_1
HPS_DDR,HPS_DQ_8
HPS_DDR,HPS_DQ_9
HPS_DDR,HPS_DQ_10
HPS_DDR,HPS_DQ_11
HPS_DDR,HPS_DQ_12
HPS_DDR,HPS_DQ_13
HPS_DDR,HPS_DQ_14
HPS_DDR,HPS_DQ_15
P28
R19
R18
K25
L25
J27
J28
M27
M26
M28
N28
DDR3_HPS_DM1
DDR3_HPS_DQS_P1
DDR3_HPS_DQS_N1
DDR3_HPS_DQ8
DDR3_HPS_DQ9
DDR3_HPS_DQ10
DDR3_HPS_DQ11
DDR3_HPS_DQ12
DDR3_HPS_DQ13
DDR3_HPS_DQ14
DDR3_HPS_DQ15
HPS_GPI3
HPS_GPI2
HPS_GPI1
HPS_GPI0
R21
R20
K27
M25
HPS_DDR,HPS_DM_4
HPS_DDR,HPS_DQS_4
HPS_DDR,HPS_DQS#_4
HPS_DDR,HPS_DQ_32
HPS_DDR,HPS_DQ_33
HPS_DDR,HPS_DQ_34
HPS_DDR,HPS_DQ_35
HPS_DDR,HPS_DQ_36
HPS_DDR,HPS_DQ_37
HPS_DDR,HPS_DQ_38
HPS_DDR,HPS_DQ_39
AE28
V18
V17
T26
U25
AC28
V25
V19
V20
AE27
AD28
HPS_GPI13
HPS_GPI12
HPS_GPI11
HPS_GPI10
HPS_GPI9
HPS_GPI8
HPS_GPI7
HPS_GPI6
HPS_GPI5
HPS_GPI4
V24
AC27
U16
U15
Y26
Y28
T16
T17
P26
R28
USER_DIPSW_HPS0
USER_DIPSW_HPS1
USER_DIPSW_HPS2
USER_DIPSW_HPS3
USER_PB_HPS0
USER_PB_HPS1
USER_PB_HPS2
USER_PB_HPS3
V28
R429
HPS_DDR,HPS_DM_3
HPS_DDR,HPS_DQS_3
HPS_DDR,HPS_DQS#_3
HPS_DDR,HPS_DQ_24
HPS_DDR,HPS_DQ_25
HPS_DDR,HPS_DQ_26
HPS_DDR,HPS_DQ_27
HPS_DDR,HPS_DQ_28
HPS_DDR,HPS_DQ_29
HPS_DDR,HPS_DQ_30
HPS_DDR,HPS_DQ_31
HPS_DDR,HPS_RESET#
22
DDR3_HPS_RESETn 10
5CSXFC6C6U23
DDR3_HPS_A[14..0]
DDR3_HPS_A[14..0] 10
DDR3_HPS_BA[2..0]
DDR3_HPS_BA[2..0] 10
DDR3_HPS_DQS_P[3..0]
DDR3_HPS_DQS_P[3..0] 10
DDR3_HPS_DQS_N[3..0]
DDR3_HPS_DQS_N[3..0] 10
DDR_HPS_DQ[31..0]
DDR3_HPS_DQ[31..0] 10
DDR3_HPS_DM[3..0]
DDR3_HPS_DM[3..0] 10
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
ETHERNET INTERFACE
Cyclone V SoC Bank 7
ENET_HPS_TXD[3..0]
ENET_HPS_TXD[3..0] 12
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_MDC
ENET_HPS_GTX_CLK 12
ENET_HPS_TX_EN 12
ENET_HPS_MDC 12
3.3V
R6
4.7K_1%
ENET_HPS_RXD[3..0]
JTAG_HPS_TRST

BA NK 7
3.3V
13 HPS_RESETn
9 JTAG_HPS_TDO
R7
4.7K_1%
9 JTAG_HPS_TMS
9 JTAG_HPS_TCK
9 JTAG_HPS_TRST
9 JTAG_HPS_TDI
MICTOR_RSTn
HPS_RESETn
JTAG_HPS_TRST
7 CLK_OSC1
7 CLK_OSC2
TRACE_CLK_MIC
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
CLKSEL0
XJ4
J17
1
2
3
XJ8A-0211
3.3V
10K
UART_TX
R25
10K
ENET_HPS_RXD1
ENET_HPS_RX_CLK
ENET_HPS_TX_EN
ENET_HPS_RX_DV
ENET_HPS_MDC
ENET_HPS_MDIO
ENET_HPS_RXD0
ENET_HPS_TXD3
ENET_HPS_TXD2
ENET_HPS_TXD1
ENET_HPS_TXD0
R19
XG8S-0331
CLKSEL1
XJ6
XJ8A-0211
J19
3.3V
10K
1 R20
CLKSEL1
2
10K
3 R27
R9
R11
R13
R15
14 SD_CD_DAT3
14 SD_DAT2
14 SD_CLK
XG8S-0331
USB_DATA6
USB_DATA5
USB_DATA7
USB_CLK
USB_NXT
USB_DIR
USB_STP
0
22
22
22
A23
H19
B23
HPS_nRST
HPS_nPOR
HPS_TDO
C23
K19
C22
D22
E18
E20
D20
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
HPS_PORSEL
HPS_CLK1
HPS_CLK2
Bank 7A
CAN0_TX,CLKSEL0,UART0_TX,SPIM1_SS0,HPS_GPIO66
CAN0_RX,UART0_RX,SPIM1_MISO,HPS_GPIO65
I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64
I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63
UART0_TX,CLKSEL1,CAN0_TX,SPIM1_SS1,HPS_GPIO62
UART0_RX,CAN0_RX,SPIM0_SS1,HPS_GPIO61
SPIM0_SS0,BOOTSEL0,CAN1_TX,UART1_RTS,HPS_GPIO60
SPIM0_MISO,CAN1_RX,UART1_CTS,HPS_GPIO59
SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58
SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57
TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56
TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55
TRACE_D5,SPIS1_MOSI,CAN1_TX,HPS_GPIO54
TRACE_D4,SPIS1_CLK,CAN1_RX,HPS_GPIO53
TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52
C21
A22
B21
A21
TRACE_CLK,HPS_GPIO48
TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49
TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50
TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51
A11
J12
A12
J13
A13
E16
A14
D17
A15
J14
A16
NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25
Bank 7B
NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24
NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23
NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22
NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21
NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20
NAND_DQ0,RGMII1_RXD0,,HPS_GPIO19
NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18
NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17
NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16
NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15
B9
B11
B8
B12
B4
H12
SDMMC_D3,USB0_NXT,HPS_GPIO47
SDMMC_D2,USB0_DIR,HPS_GPIO46
SDMMC_CLK,USB0_STP,HPS_GPIO45
SDMMC_CLK_IN,USB0_CLK,HPS_GPIO44
SDMMC_D7,USB0_D7,HPS_GPIO43
C7
D4
F4
G4
D5
E5
C5
NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14
NAND_DQ7,RGMII1_RXD2,HPS_GPIO26
NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27
NAND_WE,BOOTSEL2,QSPI_SS1,,HPS_GPIO28
QSPI_IO0,USB1_CLK,HPS_GPIO29
QSPI_IO1,USB1_STP,HPS_GPIO30
QSPI_IO2,USB1_DIR,HPS_GPIO31
QSPI_IO3,USB1_NXT,HPS_GPIO32
QSPI_SS0,BOOTSEL1,HPS_GPIO33
QSPI_CLK,HPS_GPIO34
QSPI_SS1,HPS_GPIO35
Bank 7C
RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7
RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6
RGMII0_RX_CTL,USB1_D7,HPS_GPIO8
RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10
RGMII0_RXD3,USB1_NXT,HPS_GPIO13
RGMII0_RXD2,USB1_DIR,HPS_GPIO12
RGMII0_RXD1,USB1_STP,HPS_GPIO11
CLKSEL1
SPI_CSn
R8
R10
R12
R14
R16
22
22
22
22
22
D14
A5
C13
B6
H13
A4
RGMII0_RXD0,USB1_D4,HPS_GPIO5
RGMII0_TXD3,USB1_D3,HPS_GPIO4
RGMII0_TX_CLK,HPS_GPIO0
RGMII0_TX_CTL,HPS_GPIO9
C8
C4
C9
F5
C10
E4
C6
TRACE_DATA7
TRACE_DATA6
TRACE_DATA5
TRACE_DATA4
TRACE_DATA3
USER_HPS_GPIO61 15
SPI_CSn 15
SPI_MISO 15
SPI_MOSI 15
SPI_CLK 15
BOOTSEL0
3.3V
J16
R23
10K
SPI_CSn
R30
10K
XJ3
1
2
3
XJ8A-0211
XG8S-0331
BOOTSEL1
3.3V
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
J18
R24
10K
QSPI_SS0
R32
10K
13
13
13
13
13
13
XJ5
1
2
3
XJ8A-0211
XG8S-0331
C
BOOTSEL2
SD_CMD 14
3.3V
SD_DAT0 14
SD_DAT1 14
J20
R26
10K
BOOTSEL2
R34
10K
XJ7
1
2
3
XJ8A-0211
XG8S-0331
USB_DATA4
USB_DATA3
USB_DATA2
USB_DATA1
USB_DATA0
USB_RESET
CONV_HPS_USB_N 16
USB INTERFACE
USB_RESET
USB_CLK
USB_NXT
USB_DIR
USB_STP
USB_DATA[7..0]
3.3V
4.7K_1%
4.7K_1%
ENET_HPS_RX_CLK 12
ENET_HPS_RX_DV 12
ENET_HPS_MDIO 12
ENET_HPS_INTn 12
UART_TX 16
UART_RX 16
I2C_SCL_HPS 12,15,18
I2C_SDA_HPS 12,15,18
J15 ENET_HPS_GTX_CLK
ENET_HPS_RXD2
C15
ENET_HPS_RXD3
A9
BOOTSEL2
D15
A8
H16
A7
J16
QSPI_SS0
A6
C14
ENET_HPS_INTn
B14
SDMMC_CMD,USB0_D0,HPS_GPIO36
SDMMC_PWREN,USB0_D1,HPS_GPIO37
Bank 7D
UART_TX
C16
B19
B16
C19
H17
A17
J17
B18
C17
A18
C18
A19
J18
A20
K18
5CSXFC6C6U23
R17
R18
ENET_HPS_RXD[3..0] 12
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_MDIO
ENET_HPS_INTn
U1E
JTAG_MICTOR_TMS
JTAG_MICTOR_TDI
USB_RESET 14
USB_CLK 14
USB_NXT 14
USB_DIR 14
USB_STP 14
USB_DATA[7..0] 14
J1
9,13 MICTOR_RSTn
9 JTAG_MICTOR_TDI
9 JTAG_MICTOR_TCK
9 JTAG_MICTOR_TMS
9 JTAG_MICTOR_TDO
9 JTAG_MICTOR_TRST
R28
10K
MICTOR_RSTn
JTAG_MICTOR_TDI
JTAG_MICTOR_TCK
JTAG_MICTOR_TMS
JTAG_MICTOR_TDO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
5VDC
GND
CLKE
D15E
D14E
D13E
D12E
D11E
D10E
D9E
D8E
D7E
D6E
D5E
D4E
D3E
D2E
D1E
D0E
SCL
SDA
CLKO
D15O
D14O
D13O
D12O
D11O
D10O
D9O
D8O
D7O
D6O
D5O
D4O
D3O
D2O
D1O
D0O
GND1
GND2
GND3
GND4
GND5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
39
40
41
42
43
TRACE_CLK_MIC
R29
MICTOR_PWR1 R31
MICTOR_PWR2 R33
TRACE_DATA7
TRACE_DATA6
TRACE_DATA5
TRACE_DATA4
TRACE_DATA3
TRACE_DATA2
TRACE_DATA1
R35
10K
R36
10K
R37
10K
R38
10K
TRACE_DATA0
10K
3.3V
0
DNI_R1005
3.3V
Designed
3.3V
C5
C6
0.1uF
1000pF
NOV. 20, 2013

Drawn
ALTIMA Corporation
2-5767004-2
NOV. 20, 2013
Checked
Mictor38P
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
Cyclone V SoC Transceivers & Clocks

U1F
D
CYCLONE V GX SoC Transceiver

AF2
AF1
AB2
AB1
V2
V1
7 REFCLK_QL1_P
7 REFCLK_QL1_N
GXB_RX_L0p,GXB_REFCLK_L0p
GXB_RX_L0n,GXB_REFCLK_L0n
V5
V4
REFCLK0Lp
REFCLK0Ln
P2
P1
K2
K1
F2
F1
P8
N8
REFCLK1Lp
REFCLK1Ln
GXB_L0
GXB_L1
GXB_TX_L0p
GXB_TX_L0n
GXB_TX_L1p
GXB_TX_L1n
GXB_TX_L2p
GXB_TX_L2n
AD2
AD1
Y2
Y1
T2
T1
GXB_TX_L3p
GXB_TX_L3n
GXB_TX_L4p
GXB_TX_L4n
GXB_TX_L5p
GXB_TX_L5n
M2
M1
H2
H1
D2
D1
RREF_TL
B1
R39
2K
5CSXFC6C6U23
CAD Note:
Place resistor near
RREF_TL pins.
Route away frm aggressor
U1M
CYCLONE V GX SoC Clocks
Cl ocks
HSMA_CLK_IN0
V11
W11
Bank 3B
CLK0p,FPLL_BL_FBp,DIFFIO_RX_B31p,
CLK0n,FPLL_BL_FBn,DIFFIO_RX_B31n
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB,DIFFIO_TX_B37p,B_A_2
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn,DIFFIO_TX_B37n,B_A_3
7 CLK_100M_FPGA
V12
W12
CLK1p,DIFFIO_RX_B39p
CLK1n,DIFFIO_RX_B39n
7 CLK_50M_FPGA
Y13
AA13
0_1608
Y15
AA15
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
W21
W20
CLK5p,DIFFIO_RX_R21p
CLK5n,DIFFIO_RX_R21n
R440
Y24
W24
R439
AG5
AH4
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB,DIFFIO_TX_R22p
AB26
HSMA_CLK_OUT0
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn,DIFFIO_TX_R22n
AA26
Bank 4A
Bank 5B
0_1608
HSMA_CLK_OUT0
HSMA_CLK_OUT0 11
HSMA_CLK_OUT_P[2..1]
CLK4p,FPLL_BR_FBp,DIFFIO_RX_R23p
CLK4n,FPLL_BR_FBn,DIFFIO_RX_R23n
HSMA_CLK_OUT_N[2..1]
HSMA_CLK_IN0
Bank 8A
7 CLK_125M_FPGA_P
7 CLK_125M_FPGA_N
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
CLK7p,DIFFIO_RX_T1p
CLK7n,DIFFIO_RX_T1n
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn,DIFFIO_TX_T4n
D8
HSMA_CLK_OUT_N2
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB,DIFFIO_TX_T4p
CLK6p,FPLL_TL_FBp,DIFFIO_RX_T9p
CLK6n,FPLL_TL_FBn,DIFFIO_RX_T9n
E8
HSMA_CLK_OUT_P2
E11
D11
HSMA_CLK_OUT_N[2..1] 11
HSMA_CLK_IN0 11
HSMA_CLK_IN_P[2..1]
D12
C12
HSMA_CLK_OUT_P[2..1] 11
HSMA_CLK_IN_N[2..1]
HSMA_CLK_IN_P[2..1] 11
HSMA_CLK_IN_N[2..1] 11
5CSXFC6C6U23
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
PLL
3.3V
3.3V
2.5V
C7
C8
0.01uF
0.1uF
3.3V
C9
C10
2.5V
3.3V
X1
R41
1K
0.01uF
EN
GND
VCC
OUT
C12
0.1uF
0.1uF
U5
X2
22
CLK_50M_FPGA 6
1K
1
2
DUT25AT5-50MHz
2.5V
50MHz
C11
0.1uF
R43
R44
R40
1K
EN
VCC
GND
OUT
1
2
3
4
DUT35AT-25MHz
CLKIN
1G
Y0
GND
Y1
NC
VDD
Y2
C14
0.01uF
0.1uF
R42
22
R45
22
R46
22
CLK_OSC1 5
CLK_OSC2 5
CDCLVC1103PWR
25MHz
C13
8
7
6
5
CLK_25M_ENET 12
2.5V
X3
R47
1K
1
2
EN
VCC
GND
OUT
R48
22
CLK_100M_FPGA 6
DUT25AT-100MHz
100MHz
2.5V
2.5V
C482
C483
2.5V
C15
C16
0.01uF
10uF_6.3V
X5
2.5V
R443
X4
R49
1K
OE
DNI_R1005
VDD
6
CLK_125M_FPGA_N 6
CLK_125M_FPGA_P 6
NC
OUT-
GND
OUT+
DNI_C1005
EN
VCC
DNI_C0603
GND
OUT
R444
DNI_R1005
USB_B2_CLK 3,17
DNI_FCXO-03L 6.000MHz
CEM25AT5-L-125MHz
125MHz
DNI_FA-238_25MHz_50ppm_CL=18pF
DNI_C1608
Y1
4
C17
U6
2
1
4
5
XTAL_IN
RESERVED
OE
9 REFCLK_FSEL0
FSEL0
9 REFCLK_FSEL1
10
FSEL1
C18
DNI_C1608
2.5V
R50
1K
REFCLK_QL1_P 6
nQ
REFCLK_QL1_N 6
VCC
VEE
XTAL_OUT
2.5V
C19
C20
0.01uF
0.1uF
CEM20AT5-100MHz
100MHz
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
Cyclone V SoC Configuration

2.5V
R51
10K
U1G
CYCLONE V GX SoC C onfiguration

9 JTAG_FPGA_TMS
9 JTAG_FPGA_TCK
9 JTAG_FPGA_TDI
9 JTAG_FPGA_TDO
AC7
AB5
W10
Y9
TMS
TCK
TDI
TDO
U10
CLKUSR,DIFFIO_RX_B5p,DQ1B
U7
AA8
DCLK
AD7
AC6
AC5
AB6
AA6
Y4
Y8
Y5
W8
AB4
T8
AA4
U9
AD4
V10
AC4
AS_DATA0,ASDO,DATA0
AS_DATA1,DATA1
AS_DATA2,DATA2
AS_DATA3,DATA3
nCSO,DATA4
DATA5,DIFFIO_TX_B2n
DATA6,DIFFIO_RX_B1n,DQ1B
DATA7,DIFFIO_TX_B2p,DQ1B
DATA8,DIFFIO_RX_B1p,DQ1B
DATA9,DIFFIO_TX_B4n,DQ1B
DATA10,DIFFIO_RX_B3n,DQSn1B
DATA11,DIFFIO_TX_B4p
DATA12,DIFFIO_RX_B3p,DQS1B
DATA13,DIFFIO_TX_B6n,DQ1B
DATA14,DIFFIO_RX_B5n,DQ1B
DATA15,DIFFIO_TX_B6p,DQ1B
3.3V
2
C21
0.1uF
VCC
10
GND
3
4
5
6
DCLK
DATA0
DATA1
DATA2
DATA3
nCS
16
15
8
9
1
7
NC
NC
NC
NC
14
13
12
11
NC
NC
NC
NC
USER_PB_FPGA0
USER_PB_FPGA1
USER_PB_FPGA2
USER_DIPSW_FPGA0
USER_DIPSW_FPGA1
USER_DIPSW_FPGA2
USER_DIPSW_FPGA3
USER_LED_FPGA0
USER_LED_FPGA1
USER_LED_FPGA2
USER_LED_FPGA3
EPCQ256SI16N
Bank 3A
Bank 5A
TestPAD
3.3V
R52
R54
R56
TP1
TP2
AB23
AC24
DEV_CLRn,DIFFIO_TX_R5n,DQ1R
DEV_OE,DIFFIO_TX_R5p
TP3
AA20
INIT_DONE,DIFFIO_RX_R2p
10K
10K
10K
Reconfig Switch
SW3
F7
H8
J8
nCONFIG
nSTATUS
CONF_DONE
E6
nCE
PR_READY,DIFFIO_TX_B8n,DQ1B
PR_DONE,DIFFIO_RX_B7n
PR_ERROR,DIFFIO_RX_B7p
AE6
AA11
Y11
PR_REQUEST,DIFFIO_TX_R1n,DQ1R
CvP_CONFDONE,DIFFIO_TX_R3n,DQ1R
CRC_ERROR,DIFFIO_RX_R2n
AE26
AD26
Y19
nPERSTL1,DIFFIO_RX_R6n,DQSn1R
nCEO,DIFFIO_TX_R3p,DQ1R
MSEL4
MSEL3
MSEL2
MSEL1
MSEL0
Bank 9A
5CSXFC6C6U23
HSMA_SDA 11
HSMA_SCL 11
C
W15
AE25
K9
K10
G6
H9
J10
3.3V
R53
R55
R57
R58
R59
0
0
0
0
0
MSEL[4..0] : 10010
Configuratiom mode : Active Serial x4
POR Delay : Fast
SKQMBAE010
3.3V
R60
220
Green_LED
LED1
TR1
R441
100_1%
RUE002N02
USER_LED_FPGA[3..0]
15 USER_LED_FPGA[3..0]
USER_PB_FPGA[2..0]
15 USER_PB_FPGA[2..0]
USER_DIPSW_FPGA[3..0]
15 USER_DIPSW_FPGA[3..0]
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
3.3V
R61
1K
J2
2
4
6
8
10
17 USB_DISABLEn
1
3
5
7
9
JTAG_TCK 17
JTAG_BLASTER_TDI 17
JTAG_TMS 17
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
3.3V
R62
Logic 0 = pin 10 <--> pin 9 (HPS Bypass)

Logic 1 = pin 10 <--> pin 2 (HPS Enable)
1K
R65
JTAG_BLASTER_TDO R67
JTAG_MUX_HPS_TDI R63
1K
DNI_R1005
IN1
NO1
JTAG_MUX_TMS
4
5
On = not-in-chain
Off = in-chain
SW4
1
2
3
4
HPS_JTAG_EN
FPGA_JTAG_EN
HSMA_JTAG_EN
HSMA_JTAG_OE
8
7
6
5
R70
R71
R72
R80
JTAG Select
1
2
3
4
3.3V
1K
2.5V
1K
DNI_R1005
DNI_R1005
JTAG_SEL
R73
JTAG_HPS_SEL R74
R21
R22
8
7
6
5
KHS42C
JTAG_MUX_HPS_TMS
JTAG_MUX_TMS
JTAG_MUX_TCK
I0A
I1A
JTAG_MUX_TMS
JTAG_MICTOR_TMS
I0B
JTAG_HPS_TMS
I1B
JTAG_MUX_HPS_TDI
11
I0C
JTAG_MICTOR_TDO
10
DNI_R1005
0
JTAG_MICTOR_TMS
VCC
JTAG_MICTOR_TCK
R447
R448
HV_JTAG_FPGA_TDI
JTAG_MICTOR_TDI
14
13
YA
YB
C27
0.1uF
R356
R357
JTAG_HPS_TCK
DNI_R1005
DNI_R1005
YC
FPGA_JTAG_EN
HV_JTAG_FPGA_TDO
I1C
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
YD
I1D
GND
JTAG_HPS_TDO
12
1
15
IN2
COM2
R445
DNI_R1005
DNI_R1005
R353
IN1
COM1
NO1
GND
NO2
IN2
Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)

Logic 1 = pin 10 <--> pin 2 (HSMA Enable)
JTAG_HPS_TDI
HSMA_JTAG_EN
HV_JTAG_HSMA_TDO
JTAG_HPS_TDO
NC1
V+
NC2
COM2
R69
JTAG_HPS_TDO 5
JTAG_MUX_TCK
HV_JTAG_FPGA_TMS
HV_JTAG_FPGA_TDI
HV_JTAG_FPGA_TDO
VCCB
10
9
8
7
B1
B2
B3
B4
VCCA
A1
A2
A3
A4
2
3
4
5
JTAG_MUX_TMS
C23
IN1
COM1
NO1
GND
12
OE
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
R76
10
NC1
V+
NC2
COM2
3.3V
1K
HV_JTAG_FPGA_TMS
R359
R361
R362
R364
GND
NO2
IN2
1
2
5 JTAG_MICTOR_TRST
0 JTAG_MUX_TDI
HV_JTAG_HSMA_TDI
C24
HV_JTAG_HSMA_TMS
R370
R371
COM1
NO1
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
R78
10
NC1
V+
NC2
COM2
3.3V
1K
R77
R368
R369
IN1
0.1uF
JTAG_HPS_TRST 5
JTAG_TRST
3.3V
JTAG_FPGA_TCK 8
JTAG_FPGA_TMS 8
JTAG_FPGA_TDI 8
JTAG_FPGA_TDO 8
GND
NO2
IN2
C25
0.1uF
B
2.5V
R79
DNI_TXB0104RUTR
0.1uF
R75
U12
DNI_C1005
JTAG_MUX_TCK
HV_JTAG_FPGA_TMS
HV_JTAG_FPGA_TDI
HV_JTAG_FPGA_TDO
HV_JTAG_HSMA_TDI
HV_JTAG_FPGA_TDI
3.3V
Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)

Logic 1 = pin 6 <--> pin 4 (HSMA Enable)
JTAG_HPS_SEL
11
JTAG_MUX_HPS_TMS
DNI_R1005
DNI_R1005
10
U10
Logic 0 : pin 10 <--> pin 9 (TRST from JTAG)

Logic 1 : pin 10 <--> pin 2 (TRST from MICTOR)
C29
0 JTAG_HPS_TMS
DNI_R1005
R354
R355
TS5A23157DGSR
U13
3.3V
1K
R68
TS5A23157DGSR
2.5V
DNI_C1005
0.1uF
D
NC2
NO2
C22
QS3VH257PAG
3.3V
Logic 0 : Yx <-> I0x

C28
GND
JTAG_HPS_TMS
JTAG_HPS_SEL
0 HV_JTAG_FPGA_TDI
3.3V
JTAG_MUX_TMS
JTAG_HPS_TDI 5
HV_JTAG_FPGA_TDI R366
JTAG_MICTOR_TDI
R367
I0D
V+
R64
JTAG_HPS_TCK
JTAG_HPS_TMS 5
JTAG_HPS_TDI
U9
JTAG_HPS_TCK 5
R358
R360
JTAG_MUX_HPS_TDI R363
JTAG_MICTOR_TDO R365
3.3V
C26
2.2uF
Logic 0 = pin 10 <--> pin 9 (FPGA Bypass)

Logic 1 = pin 10 <--> pin 2 (FPGA Enable)
U11
16
NC1
DNI_R1005
Logic 0 = pin 6 <--> pin 7 (FPGA Bypass)

Logic 1 = pin 6 <--> pin 4 (FPGA Enable)
JTAG_MUX_TCK
JTAG_MICTOR_TCK
TS5A23157DGSR
REFCLK_FSEL1 7
REFCLK_FSEL0 7
KHS42C
3.3V
JTAG_MUX_TDO
10
R446
SW1
3.3V 2.5V
1K
1K
DNI_R1005
DNI_R1005
COM1
DNI_R1005
DNI_R1005
3.3V
Logic 0 = pin 6 <--> pin 7 (HPS Bypass)

Logic 1 = pin 6 <--> pin 4 (HPS Enable)
MICTOR_RSTn 5,13
JTAG Chain Control
R351
R352
JTAG_BLASTER_TDI
JTAG_TRST
U8
HPS_JTAG_EN
JTAG_BLASTER_TDO 17
XG4C-1031
R66
0
JTAG
3.3V
DNI_R1005
TS5A23157DGSR
3.3V
3.3V
16
JTAG_TCK
17 JTAG_TCK
5 JTAG_MICTOR_TCK
17 JTAG_TMS
5 JTAG_MICTOR_TDI
YA
I1A
JTAG_TMS
I0B
I1B
JTAG_BLASTER_TDI
11
I0C
JTAG_MICTOR_TDI
10
I1C
14
I0D
13
C33
0.1uF
YC
JTAG_MUX_TCK
JTAG_MUX_TMS
R376
R377
DNI_R1005
DNI_R1005
JTAG_MUX_TDI
JTAG_BLASTER_TDO R378
JTAG_MICTOR_TDO R379
DNI_R1005
DNI_R1005
JTAG_MUX_TDO
11
JTAG_MUX_TCK
10
HV_JTAG_HSMA_TMS 9
HV_JTAG_HSMA_TDI
8
HV_JTAG_HSMA_TDO 7
JTAG_MUX_TMS
JTAG_MUX_TDI
JTAG_SEL
15
C31
VCCA
B1
B2
B3
B4
A1
A2
A3
A4
2
3
4
5
GND
OE
12
VCCB
XJ1
DNI_XJ8A-0211
DNI_XG8S-0331
DNI_C1005
JTAG_HSMA_TCK 11
JTAG_HSMA_TMS 11
JTAG_HSMA_TDI 11
JTAG_HSMA_TDO 11
HSMA_JTAG_OE
DNI_TXB0104RUTR
3.3V
Designed
3.3V
R342
10K
NOV. 20, 2013

Drawn
R343
10K
ALTIMA Corporation
JTAG_TRST
NOV. 20, 2013
Checked
QS3VH257PAG

17 JTAG_BLASTER_TRST
R344
TR3
RUE002N02
Title
TR4
DTC114EUA
NOV. 20, 2013

Approval
Helio Board
A3
NOV. 20, 2013

5
J3
1
2
3
C30
3.3V
DNI_C1005
DNI_R1005
DNI_R1005
12
I1D
DNI_R1005
DNI_R1005
U15
R374
R375
JTAG_MUX_TDO
YD
GND
R372
R373
JTAG_MUX_TCK
JTAG_BLASTER_TDI
JTAG_MICTOR_TDI
3.3V
C32
2.2uF
JTAG_TMS
JTAG_MICTOR_TMS
YB
JTAG_MICTOR_TDO
5 JTAG_MICTOR_TDO
I0A
JTAG_BLASTER_TDO
JTAG_TCK
JTAG_MICTOR_TCK
VCC
JTAG_MICTOR_TCK
JTAG_MICTOR_TMS
5 JTAG_MICTOR_TMS
2.5V
U14
ALTHEL10SOC-R1.2
Sheet
1
of
Rev
STEP
1.22
26
DDR3_HPS_CK_P R81
DDR3
DDR3_HPS_CK_N
100_1%
VTT_HPS_DDR3
VTT_HPS_DDR3
DDR3_HPS_BA[2..0]
4 DDR3_HPS_BA[2..0]
DDR3_HPS_DM[3..0]
4 DDR3_HPS_DM[3..0]
VTT_HPS_DDR3
VTT_HPS_DDR3
C34
47nF
C35
47nF
C36
47nF
C37
47nF
C38
47nF
C39
47nF
C40
47nF
C41
47nF
C42
47nF
C43
47nF
C44
47nF
C45
47nF
DDR3_HPS_A0
DDR3_HPS_A1
DDR3_HPS_A2
DDR3_HPS_A3
DDR3_HPS_A4
DDR3_HPS_A5
DDR3_HPS_A6
DDR3_HPS_A7
R82
R85
R88
R91
R93
R96
R98
R100
DDR3_HPS_A8
DDR3_HPS_A9
DDR3_HPS_A10
DDR3_HPS_A11
DDR3_HPS_A12
DDR3_HPS_A13
DDR3_HPS_A14
62
62
62
62
62
62
62
62
R83
R86
R89
R92
R94
R423
R424
R102
DDR3_HPS_CKE R103
DDR3_HPS_DQS_N[3..0]
4 DDR3_HPS_DQS_N[3..0]
62
62
62
62
62
62
62
DDR3_HPS_BA0 R84
DDR3_HPS_BA1 R87
DDR3_HPS_BA2 R90
62
62
62
DDR3_HPS_CSn R95
DDR3_HPS_WEn R97
DDR3_HPS_RASn R99
DDR3_HPS_CASn R101
62
62
62
62
DDR3_HPS_ODT R430
62
DDR3_HPS_CKE R428
62
1.5V
DDR3_HPS_DQS_P[3..0]
4 DDR3_HPS_DQS_P[3..0]
VTT_HPS_DDR3
VTT_HPS_DDR3
4.7K_1%
DDR3_HPS_RESETn
2K
DDR3_HPS_DQ[31..0]
4 DDR3_HPS_DQ[31..0]
DDR3_HPS_A[14..0]
4 DDR3_HPS_A[14..0]
U16
4 DDR3_HPS_CKE
4 DDR3_HPS_CK_P
4 DDR3_HPS_CK_N
4 DDR3_HPS_CSn
4 DDR3_HPS_WEn
4 DDR3_HPS_RASn
4 DDR3_HPS_CASn
4 DDR3_HPS_RESETn
4 DDR3_HPS_ODT
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
DDR3_HPS_CKE
DDR3_HPS_CK_P
DDR3_HPS_CK_N
K9
J7
K7
DDR3_HPS_DM2
DDR3_HPS_DM3
E7
D3
DDR3 Device
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
A10/AP
DQ9
DQ10
A11
A12/BC#
DQ11
NC
DQ12
NC
DQ13
DQ14
CKE
DQ15
CK
LDQS
CK#
LDQS#
LDM
UDQS
UDM
UDQS#
DDR3_HPS_CSn
DDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_CASn
L2
L3
J3
K3
CS#
WE#
RAS#
CAS#
DDR3_HPS_BA0
DDR3_HPS_BA1
DDR3_HPS_BA2
DDR3_HPS_RESETn
DDR3_HPS_ODT
M2
N8
M3
T2
K1
L8
BA0
BA1
BA2
RESET#
ODT
ZQ
H1
M8
VREFDQ
VREFCA
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF_HPS_DDR3
R104
240
U17
DDR3_HPS_A0
DDR3_HPS_A1
DDR3_HPS_A2
DDR3_HPS_A3
DDR3_HPS_A4
DDR3_HPS_A5
DDR3_HPS_A6
DDR3_HPS_A7
DDR3_HPS_A8
DDR3_HPS_A9
DDR3_HPS_A10
DDR3_HPS_A11
DDR3_HPS_A12
DDR3_HPS_A13
DDR3_HPS_A14
C46
C484
0.1uF 0.01uF
1.5V
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3_HPS_DQ17
DDR3_HPS_DQ23
DDR3_HPS_DQ21
DDR3_HPS_DQ19
DDR3_HPS_DQ20
DDR3_HPS_DQ22
DDR3_HPS_DQ16
DDR3_HPS_DQ18
DDR3_HPS_DQ29
DDR3_HPS_DQ30
DDR3_HPS_DQ28
DDR3_HPS_DQ27
DDR3_HPS_DQ24
DDR3_HPS_DQ31
DDR3_HPS_DQ25
DDR3_HPS_DQ26
F3
G3
C7
B7
DDR3_HPS_DQS_P2
DDR3_HPS_DQS_N2
DDR3_HPS_DQS_P3
DDR3_HPS_DQS_N3
NC
NC
NC
NC
NC
J1
J9
L1
L9
M7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
DDR3_HPS_A0
DDR3_HPS_A1
DDR3_HPS_A2
DDR3_HPS_A3
DDR3_HPS_A4
DDR3_HPS_A5
DDR3_HPS_A6
DDR3_HPS_A7
DDR3_HPS_A8
DDR3_HPS_A9
DDR3_HPS_A10
DDR3_HPS_A11
DDR3_HPS_A12
DDR3_HPS_A13
DDR3_HPS_A14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
DDR3_HPS_CKE
DDR3_HPS_CK_P
DDR3_HPS_CK_N
K9
J7
K7
DDR3_HPS_DM0
DDR3_HPS_DM1
E7
D3
DDR3 Device
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
A10/AP
DQ9
DQ10
A11
A12/BC#
DQ11
NC
DQ12
NC
DQ13
DQ14
CKE
DQ15
CK
LDQS
CK#
LDQS#
LDM
UDQS
UDM
UDQS#
DDR3_HPS_CSn
DDR3_HPS_WEn
DDR3_HPS_RASn
DDR3_HPS_CASn
L2
L3
J3
K3
CS#
WE#
RAS#
CAS#
DDR3_HPS_BA0
DDR3_HPS_BA1
DDR3_HPS_BA2
DDR3_HPS_RESETn
DDR3_HPS_ODT
M2
N8
M3
T2
K1
L8
BA0
BA1
BA2
RESET#
ODT
ZQ
H1
M8
VREFDQ
VREFCA
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF_HPS_DDR3
R105
240
C47
C485
0.1uF 0.01uF
1.5V
MT41J64M16JT-125
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3_HPS_DQ0
DDR3_HPS_DQ6
DDR3_HPS_DQ4
DDR3_HPS_DQ7
DDR3_HPS_DQ1
DDR3_HPS_DQ3
DDR3_HPS_DQ5
DDR3_HPS_DQ2
DDR3_HPS_DQ8
DDR3_HPS_DQ14
DDR3_HPS_DQ9
DDR3_HPS_DQ12
DDR3_HPS_DQ11
DDR3_HPS_DQ15
DDR3_HPS_DQ10
DDR3_HPS_DQ13
F3
G3
C7
B7
DDR3_HPS_DQS_P0
DDR3_HPS_DQS_N0
DDR3_HPS_DQS_P1
DDR3_HPS_DQS_N1
NC
NC
NC
NC
NC
J1
J9
L1
L9
M7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J64M16JT-125
1.5V
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
4.7nF
4.7nF
4.7nF
4.7nF
1Gbit : MT41J64M16JT-125
2Gbit : MT41J128M16JT-125
4Gbit : MT41J256M16RE-125
Designed
1.5V
A
C481
0.01uF
C59
0.01uF
C60
0.01uF
C61
0.01uF
C486
0.01uF
C487
0.01uF
C62
0.1uF
C63
0.1uF
C64
0.1uF
C65
0.1uF
C66
0.47uF
C67
0.47uF
C68
0.47uF
C69
NOV. 20, 2013
Drawn
0.47uF
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
10
of
Rev
STEP
1.22
26
HSMC
J4
8 HSMA_SDA
9 JTAG_HSMA_TCK
9 JTAG_HSMA_TDO
6 HSMA_CLK_OUT0
HSMA_D0
HSMA_D2
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P1
HSMA_TX_D_N1
C
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
B
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
3.3V
L1
3.3V_HSMA
HSMA_TX_D_P14
HSMA_TX_D_N14
DNI_L1608
3.3V_EXT
HSMA_TX_D_P15
HSMA_TX_D_N15
L2
3A_30 Ohm FB
HSMA_TX_D_P16
HSMA_TX_D_N16
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
12V
3.3V_HSMA
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
BANK1
3.3V_HSMA
HSMA_D[3..0]
HSMA_D[3..0] 3
HSMA_TX_D_P[16..0]
HSMA_TX_D_N[16..0]
HSMA_RX_D_P[16..0]
HSMA_RX_D_N[16..0]
HSMA_SCL 8
JTAG_HSMA_TMS 9
JTAG_HSMA_TDI 9
HSMA_CLK_IN0 6
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMA_D1
HSMA_D3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_D_P8
HSMA_RX_D_N8
BANK2
BANK3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND1_1
GND1_2
GND1_3
GND1_4
GND2_1
GND2_2
GND2_3
GND2_4
GND3_1
GND3_2
GND3_3
GND3_4
HSMA_CLK_OUT_P[2..1]
HSMA_CLK_OUT_N[2..1]
HSMA_CLK_IN_P[2..1]
HSMA_CLK_IN_N[2..1]
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_TX_D_P[16..0] 3
HSMA_TX_D_N[16..0] 3
HSMA_RX_D_P[16..0] 3
HSMA_RX_D_N[16..0] 3
HSMA_CLK_OUT_P[2..1] 6
HSMA_CLK_OUT_N[2..1] 6
HSMA_CLK_IN_P[2..1] 6
HSMA_CLK_IN_N[2..1] 6
HSMA_RX_D_P1
HSMA_RX_D_N1
C
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_RX_D_P9
HSMA_RX_D_N9
B
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PRSNTn 3
12V
C71
22uF_25V
22uF_6.3V
161
162
163
164
165
166
167
168
169
170
171
172
ASP-122953-01
C70
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
11
of
Rev
STEP
1.22
26
10/100/1000 Ethernet - HPS

ETHERNET INTERFACE
ENET_HPS_TXD[3..0]
LED14
DNI_Yellow_LED
ENET_HPS_MDC
ENET_HPS_MDIO
36
37
MDC
MDIO
ENET_HPS_RESETn
42
RESET_N
3.3V
ENET_HPS_LED2_LINK
R106
220
11
ENET_HPS_INTn
J5
YA
YK
12
VCC
Yellow
17
GP1
GA
13
Green
14
GK
GP2
1
2
TD1_P
TD1_N
3
6
TD2_P
TD2_N
4
5
TD3_P
TD3_N
7
8
MDI_HPS_P0
MDI_HPS_N0
MDI_HPS_P1
MDI_HPS_N1
MDI_HPS_P2
MDI_HPS_N2
MDI_HPS_P3
MDI_HPS_N3
10
15
16
R108
10
2
3
5
6
7
8
10
11
4.99K
R109
C73
48
TXRXP_A
TXRXM_A
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
TXRXP_D
TXRXM_D
R110
17
15
LED1_PHYAD0
LED2_PHYAD1
46
45
XI
XO
ENET_HPS_RXD[3..0]
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_MDIO
ENET_HPS_INTn
ENET_HPS_GTX_CLK
TX_EN
25
ENET_HPS_TX_EN
RX_DV_CLK125_EN
33
ENET_HPS_RX_DV
TXD3
TXD2
TXD1
TXD0
22
21
20
19
ENET_HPS_TXD3
ENET_HPS_TXD2
ENET_HPS_TXD1
ENET_HPS_TXD0
RXD0_MODE0
RXD1_MODE1
RXD2_MODE2
RXD3_MODE3
32
31
28
27
ENET_HPS_RXD0
ENET_HPS_RXD1
ENET_HPS_RXD2
ENET_HPS_RXD3
7 CLK_25M_ENET
LED15
DNI_Green_LED
R348
SHELL_GND1
0.01uF
0.01uF
C79
0.01uF
A0
A1
A2
GND
VCC
WP
SCL
SDA
C72
8
7
6
5
0.1uF
I2C_SCL_HPS 5,15,18
I2C_SDA_HPS 5,15,18
I2C Address = 0x51
C74
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
C75
10uF_6.3V 10uF_6.3V
Place near KSZ9021RN PHY

3.3V
L3
3.3V_AVDDH
MDI_HPS_P0
MDI_HPS_N0
MDI_HPS_P1
MDI_HPS_N1
MDI_HPS_P2
MDI_HPS_N2
MDI_HPS_P3
MDI_HPS_N3
3.3V_AVDDH
3A_30 Ohm FB
C80
U18B
4.7uF_16V
3.3V_DVDDH
C78
4.7K_1% 1
2
3
4
3.3V
1.2V_AVDDL_PLL
C77
3.3V
24LC32Ax-I/SN
1M
C430
R111
R112
R113
R114
R115
R116
R117
R118
ENET_HPS_RX_CLK 5
ENET_HPS_RX_DV 5
ENET_HPS_MDIO 5
ENET_HPS_INTn 5
U19
CLK125_NDO_LED_MODE
KSZ9021RN
0.01uF
ENET_HPS_RXD[3..0] 5
220
C76
3.3V
R107
41
ENET_HPS_GTX_CLK 5
ENET_HPS_TX_EN 5
ENET_HPS_MDC 5
ENET_HPS_RESETn 13
ENET_HPS_RX_CLK
24
CLK125_NDO_LED_MODE
ENET_HPS_LED1_LINK
ENET_HPS_LED2_LINK
35
GTX_CLK
ISET
0.01uF
7499111121A SHELL_GND1
3.3V
ENET_HPS_LED1_LINK
INT_N
DNI_R1005
9 R442
TD0_P
TD0_N
GND
GND_TAB
GND_TAB
38
RX_CLK_PHYAD2
MDI INTERFACE
18
3.3V
ENET_HPS_TXD[3..0] 5
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_MDC
ENET_HPS_RESETn
U18A
47
12
1
AVDDH
AVDDH
AVDDH
40
16
34
DVDDH
DVDDH
DVDDH
49
13
29
P_GND
VSS_PS
VSS
AVDDL_PLL
LDO_O
9
4
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
18
14
39
30
26
23
C82
0.1uF
C83
22uF_25V
44
43
AVDDL
AVDDL
C81
2.2uF
1.2V_AVDDL_PLL
C84
2.2uF
C85
0.1uF
22uF_25V
1.2V_AVDDL
L4
3.3V_DVDDH
L5
1.2V_AVDDL
1.2V_DVDDL
C86
3A_30 Ohm FB
C87
2.2uF
C88
0.1uF
C89
3A_30 Ohm FB
22uF_25V
C90
2.2uF
C91
0.1uF
22uF_25V
L6
1.2V_DVDDL
KSZ9021RN
3A_30 Ohm FB
C92
C93
2.2uF
C94
0.1uF
22uF_25V
3.3V
3.3V
R119
R120
R121
R122
4.7K_1%
4.7K_1%
4.7K_1%
4.7K_1%
R123
R125
R127
R129
R131
R133
R135
R137
R139
ENET_HPS_MDIO
ENET_HPS_MDC
ENET_HPS_INTn
ENET_HPS_RESETn
DanP:no dedicated reset Consider to connect expander and pull down
DNI_R1005 ENET_HPS_LED2_LINK R124

DNI_R1005 ENET_HPS_LED1_LINK R126
4.7K_1% ENET_HPS_RXD3
R128
R130
ENET_HPS_RXD1
4.7K_1%
R132
R134
DNI_R1005 ENET_HPS_RX_DV
R136
4.7K_1% ENET_HPS_RX_CLK
R138
CLK125_NDO_LED_MODE
4.7K_1%
R140
1K
1K
DNI_R1005
DNI_R1005
DNI_R1005
DNI_R1005
4.7K_1%
DNI_R1005
DNI_R1005
BOOT-STRAPS
5.0V
C95
1.2V_AVDDL_PLL
U20
2.2uF
2.5V
C98
2.2uF
BST
OUT
OUT
9
10
1
2
IN
IN
ADJ
PG
8
7
R141
SW
SHDN
GND
EP_GND
4
3
11
R142
10K
20K
C96
22uF_6.3V
C97
2.2uF
Designed
A
LTC3026EDD#PBF
NOV. 20, 2013
Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
12
of
Rev
STEP
1.22
26
QSPI Flash & Reset Circuit

D
Not Mount
3.3V
U21
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
15
8
9
1
DQ0
DQ1
DQ2/VPP/W#
DQ3/HOLD#
5 QSPI_CLK
16
5 QSPI_SS0
S#
5
5
5
5
3.3V
VCC
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
3
4
5
6
11
12
13
14
VSS
10
3.3V
LED2
3.3V
3.3V
C99
R143
220
0.1uF
Red_LED
R144
20K
U22
4
VCC
MR
GND
RESET
R145
10K
SW5
MAX6315US29D3+T
SKQMBAE010
COLD_RESETn
R146
100_1%
R147
DNI_N25Q512A13GSF40G
ENET_HPS_RESETn 12
HPS_RESETn 5
TG1
3.3V
3.3V
3.3V
PLACE NEAR QSPI FLASH
C101
C102
4.7uF_16V
0.1uF
C100
R148
20K
0.1uF
3.3V
U23
4
VCC
GND
RESET
R149
10K
SW6
3
SKQMBAE010
MR
MAX6315US29D3+T
WARM_RESETn
R150
100_1%
MICTOR_RSTn 5,9
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
13
of
Rev
STEP
1.22
26
USB 2.0 OTG, Micro SD Card

5.0V
USB_5.0V
C103 C104 C105
U24
1
3
9
2.2uF 2.2uF 2.2uF
USB 2.0 OTG
USB_EXTVBUS
USB_5.0V
USB_VDD
R151
DNI_R1005
3.3V
DNI_R1005
14
11
12
13
CLKOUT
NXT
DIR
STP
USB_RESET_PHY
R165
12.0K
32
RBIAS
RESET
29
15
26
C109
0.1uF
0.1uF
3.3V
R153
100K
REG_EN
31
CPEN
EXTVBUS
3
10
USB_CPEN
USB_EXTVBUS
4
8
7
5
USB_VBUS
USB_DM
USB_DP
USB_ID
VBUS
DM
DP
ID
XO
XI
GND
GND
GND_FLAG
C110
4.7uF_16V
J6
R160
820_1%
56579-0519
1
2
3
4
5
C111 24pF
27
28
Y2
4
1
2
33
USB3300-EZK
USB_5.0V
USBmini-AB
6
7
USB_CLK
USB_NXT
USB_DIR
USB_STP
R163
C108
0.1uF
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
ON
C107
0.1uF
3.3V
VDD1.8
24
23
22
21
20
19
18
17
GND
FAULT
C106
R164
1M
SHELL_GND2
3.3V
10K
10K
10K
10K
10K
10K
10K
10K
VDD3.3
VDD3.3
VDD3.3
VDD3.3
R154
R155
R156
R157
R158
R159
R161
R162
VDD1.8
VDD1.8
30
25
16
6
R152
DNI_R1005
U25
OUT1
OUT2
OUT3
OUT4
MAX1693HEUB+x
USB_VDDA
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
IN1
IN2
IN3
2
4
8
10
C112 24pF
R349
SEG35-24MHz
1M
R166
10K
USB_RESET R167
USB_RESET_PHY
C431
SHELL_GND2
4.7uF_16V
USB INTERFACE
USB_RESET
USB_CLK
USB_NXT
USB_DIR
USB_STP
USB_DATA[7..0]
5 USB_RESET
5 USB_CLK
5 USB_NXT
5 USB_DIR
5 USB_STP
5 USB_DATA[7..0]
3.3V
Micro SD Card
J7
CLK
SD_CMD
CMD
SD_DAT0
SD_DAT1
SD_DAT2
SD_CD_DAT3
7
8
1
2
DAT0
DAT1
DAT2
CD/DAT3
K1
K2
ESD5V3U2U
3
ESD5V3U2U D3
3
K2
1
K1
2
K2
ESD5V3U2U D2
3
D1
K1
SD_CLK
VDD
CAGE
CAGE
CAGE
CAGE
VSS
C113
C114
C115
2.2uF
0.1uF
0.1uF
4
9
10
11
12
6
TG2
B
693071010811
Micro SD INTERFACE
SD_DAT0
SD_DAT1
SD_DAT2
SD_CD_DATA3
SD_CMD
SD_CLK
SD_DAT0 5
SD_DAT1 5
SD_DAT2 5
SD_CD_DAT3 5
SD_CMD 5
SD_CLK 5
PLACE NEAR USB3300

3.3V
USB_VDD
USB_VDDA
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
4.7uF_16V
0.1uF
0.1uF
0.1uF
0.1uF 4.7uF_16V
0.1uF
0.1uF 4.7uF_16V
0.1uF
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
14
of
Rev
STEP
1.22
26
User I/O, RTC

5.0V
R169
DNI_R1005
R168
DNI_R1005
DISP_SPI_CLK
DISP_SPI_MOSI
5.0V
LED INTERFACE
2.5V
8 USER_LED_FPGA[3..0]
USER_LED_FPGA0
LED3
Green_LED R170
49.9
USER_LED_FPGA1
LED4
Green_LED R171
49.9
USER_LED_FPGA2
LED5
Green_LED R172
49.9
USER_LED_FPGA3
LED6
Green_LED R173
49.9
J8
5.0V
3.3V
1
2
3
4
5
6
7
8
9
10
DISP_SPI_CSn
DISP_SPI_MISO
DISP_SPI_CLK
DISP_SPI_MOSI
C428 0.1uF
U26
DISP_SPI_CSn
DISP_SPI_MISO
DISP_SPI_MOSI
DISP_SPI_CLK
VCCB
10
9
8
7
6
SSW-110-01-G-S
C429 0.1uF
11
VCCA
B1
B2
B3
B4
A1
A2
A3
A4
2
3
4
5
GND
OE
12
R451
R452
R453
R454
0
0
0
0
SPI_CSn
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CSn 5
SPI_MISO 5
SPI_MOSI 5
SPI_CLK 5
TXB0104RUTR
LCD Socket
1.5V
SW7
3.3V
USER_PB_HPS0
SKQMBAE010
R174
USER_PB_HPS1
SKQMBAE010
R175
4.7K_1%
USER_PB_HPS2
SKQMBAE010
R179
4.7K_1%
USER_PB_HPS3
SKQMBAE010
R180
4.7K_1%
4.7K_1%
U27
C126
0.1uF
VCC
VBACKUP
14
16
1
SDA
SCL
SQW/INT
15
13
12
11
10
GND
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
4
5
6
7
8
9
SW8
5,12,18 I2C_SDA_HPS
5,12,18 I2C_SCL_HPS
SW9
R176
R178
0
0
SW10
R177
4.7K_1%
3.3V
BT1
SMTU1225
DS1339C-33#
B4
I2C Address = 0x68

2.5V
SW11
USER_PB_FPGA0
SKQMBAE010
R181
4.7K_1%
USER_PB_FPGA1
SKQMBAE010
R182
4.7K_1%
USER_PB_FPGA2
SKQMBAE010
R183
4.7K_1%
CR1225
SW12
B
SW13
1.5V
SW INTERFACE
SW14
1
2
3
4
8
7
6
5
USER_DIPSW_HPS0
USER_DIPSW_HPS1
USER_DIPSW_HPS2
USER_DIPSW_HPS3
R184
R185
R186
R187
4.7K_1%
4.7K_1%
4.7K_1%
4.7K_1%
8
7
6
5
USER_DIPSW_FPGA0
USER_DIPSW_FPGA1
USER_DIPSW_FPGA2
USER_DIPSW_FPGA3
R188
R189
R190
R191
4.7K_1%
4.7K_1%
4.7K_1%
4.7K_1%
USER_PB_HPS[3..0]
USER_DIPSW_HPS[3..0]
USER_PB_HPS[3..0] 4
USER_DIPSW_HPS[3..0] 4
KHS42C
2.5V
SW15
1
2
3
4
USER_PB_FPGA[2..0]
USER_DIPSW_FPGA[3..0]
USER_PB_FPGA[2..0] 8
USER_DIPSW_FPGA[3..0] 8
KHS42C
Designed
A
GPIO
SPI_MISO
SPI_MOSI
SPI_CLK
GPIO59
GPIO58
GPIO57
GPIO1
GPIO2
GPIO3
GPIO4
R192
R193
R194
R195
100_1%
100_1%
100_1%
100_1%
SPI_MISO
SPI_MOSI
SPI_CLK
USER_HPS_GPIO61 5
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
15
of
Rev
STEP
1.22
26
UART
3.3V_USB is CP2103
supply voltage.
D
3.3V_USB
3.3V_USB
C128
2.2uF
C130
4.7uF_16V
VDD
C127
0.1uF
REGIN
C129
2.2uF
VBUS
DD+
8
4
3
NC
NC
NC
NC
NC
NC
GND
SGND
21
20
15
14
13
10
2
29
U28
DNI_Green_LED
LED7 R196
220
DNI_Green_LED
LED8 R197
220
R198
5 CONV_HPS_USB_N
DNI_R1005
R199
R200
5 UART_RX
5 UART_TX
0
0
19
18
17
16
12
11
25
24
GPIO0
GPIO1
GPIO2
GPIO3
SUSPEND
SUSPEND
TXD
RXD
VIO
J9
R201
DNI_R1005
J10
R202
4.7K_1%
1
2
XJ8A-0211
XG8S-0231
DCD
DTR
DSR
RTS
CTS
RI
RST
VBUS
ID
D+
DGND
NC
CP2103-GM
C131
0.1uF
USB mini-B
SHELL_GND3
6
3
1
2
5
XJ2
28
27
26
23
22
1
6
7
3.3V_USB
54819-0519
1
2
3
4
5
R350
1M
TG3
C
C432
SHELL_GND3
4.7uF_16V
TPD4S012DRYR
U29
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
16
of
Rev
STEP
1.22
26
On-Board USB BlasterII

FPGA USB INTERFACE
USB_B2_DATA[7..0]
FX2_SDA
R203
USB_B2_DATA[7..0] 3
MAX_SDA
U31B
3.3V
3.3V
USB mini-B
J11
54819-0519
MAX II
BANK 1
FX2_PA2
FX2_FLAGC
FX2_PA7
FX2_FLAGA
FX2_PA3
FX2_PA4
EXTRA_SIG0
FX2_PB4
FX2_PA6
FX2_PB2
FX2_FLAGB
FX2_PB0
FX2_PA1
FX2_PB5
USB_DISABLEn
FX2_PB6
0.1uF
U30
R205
10K
VBUS_5V
FX2_D_N
FX2_D_P
R204
DNI_R1005
1
2
3
4
5
FX2_RESETn
GND
RESET
VCC
MR
MAX6315US29D3+T
7
6
C132
U32
SHELL_GND4
R206
1M
GND
D+
D-
1
2
3.3V
U33
TPD2EUSB30DRxx
3
7
C133
SHELL_GND4
4.7uF_16V
11
17
27
32
43
55
9
8
3
Y3
1
USB_B2_CLK
C135
C134
24pF
FX2_PA1
FX2_PA2
FX2_PA3
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
24pF
SEG35-24MHz
3.3V
RESET
SCL
SDA
42
15
16
FX2_RESETn
FX2_SCL
FX2_SDA
WAKEUP
44
FX2_WAKEUP
29
30
31
FX2_FLAGA
FX2_FLAGB
FX2_FLAGC
1
2
FX2_SLRDn
FX2_SLWRn
AVCC
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
CTL0
CTL1
CTL2
DMINUS
DPLUS
RDY0
RDY1
C136
20K
0.1uF
FX2_SLWRn
FX2_SLRDn
FX2_PD7
FX2_PD5
FX2_PA5
C_JTAG_TDO
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TCK
33
34
35
36
37
38
39
40
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
18
19
20
21
22
23
24
25
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
14
RESERVED
6
10
57
12
26
28
41
53
56
AGND
AGND
EP_PAD
GND
GND
GND
GND
GND
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
45
46
47
48
49
50
51
52
FX2_PD0
FX2_PD1
FX2_PD2
FX2_PD3
FX2_PD4
FX2_PD5
FX2_PD6
FX2_PD7
C_USB_MAX_TCK
C_USB_MAX_TDI
C_USB_MAX_TDO
C_USB_MAX_TMS
J7
IO1/DEV_OE IO1/DEV_CLRn
K9
FX2_RESETn
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
C_USB_MAX_TDI
C_USB_MAX_TCK
C_USB_MAX_TMS
C_USB_MAX_TDO
H2
H3
J1
J2
TDI
TCK
TMS
TDO
E2
E1
F8
E10
USB_B2_CLK
FX2_PB7
USB_CFG7
M570_CLOCK
IO1/GCLK0p
IO1/GCLK1p
IO2/GCLK2p
IO2/GCLK3p
54
R209
R210
R211
R212
R215
R217
R219
R221
JTAG_TX
A1
JTAG_RX
A2
FACTORY_REQUESTA3
USB_CFG5
A4
USB_RESETn
A7
USB_OEn
B8
USB_RDn
D10
USB_WRn
D9
FACTORY_STATUS A9
SC_RX
A10
SC_TX
B2
USB_CFG4
B3
EXTRA_SIG1
B4
USB_CFG6
B5
USB_B2_DATA0
B9
USB_B2_DATA1
C9
USB_B2_DATA2
C8
USB_B2_DATA3
B7
USB_B2_DATA4
C7
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
IO_B2
C3
C4
A6
F10
F9
B10
E8
C10
D8
B6
E9
A8
A5
G8
G9
G10
H9
H10
J10
USB_CFG3
M570_PCIE_JTAG_EN
USB_B2_DATA7
USB_B2_DATA5
USB_B2_DATA6
RST
USB_CFG8
JTAG_BLASTER_TRST
USB_FULL
USB_EMPTY
USB_CFG11
USB_SCL
USB_SDA
EXTRA_SIG2
USB_CFG10
USB_CFG0
USB_CFG1
USB_CFG2
USB_CFG9
EXTRA_SIG1
EXTRA_SIG2
USB_CFG0
USB_CFG1
USB_CFG2
USB_CFG3
DNI_R1005
JTAG_BLASTER_TDI
USB_CFG4
USB_CFG6
U31A
1.5V
USB_SCL
USB_SDA
USB_FULL
USB_EMPTY
LED9
RESn_JTAG_TX
R226
R225
R413
DNI_R1608 FACTORY_REQUEST
DNI_R1608
R416
R418
DNI_R1608 FACTORY_STATUS
DNI_R1608
USB_CFG7
LED10
DNI_LED
1V8
C5
E6
F5
H5
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
C6
E7
F4
H6
D5
D7
E5
F6
G5
G7
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
E4
G4
G6
VCCIO2
VCCIO2
VCCIO2
D4
D6
F7
USB_CFG8
USB_CFG9
3.3V
USB_CFG10
JTAG_TCK 9
JTAG_TMS 9
JTAG_BLASTER_TDI 9
JTAG_BLASTER_TDO 9
JTAG_BLASTER_TRST 9
USB_CFG11
PLACE NEAR MAXII

3.3V
1.5V
DNI_R1005
R380
R381
R382
R383
R384
R385
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
R386
R387
R388
R389
R390
R391
R392
R393
R394
R395
R396
R397
R398
R399
R400
R401
R402
R403
R404
R405
R406
R407
R408
R409
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
R410
R411
R412
R414
R415
R417
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
DNI_R1608
1.5V
M570_PCIE_JTAG_EN
M570_CLOCK
EPM570GF100C5N
DNI_R1005
DNI_LED
JTAG_TX
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
3.3V
EXTRA_SIG0
C137 C138 C139 C140 C141 C142 C143 C144
1V8
0
0
0
0
1.5V
3.3V
MAX II
POWER
R224
FX2_PD0
FX2_PD2
FX2_PD3
FX2_PD1
MAX II
BANK 2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RESn_JTAG_RX
0
0
0
0
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
JTAG_BLASTER_TRST
USB_CFG5
JTAG_RX
USB_DISABLEn 9
U31D
PLACE NEAR CY7C68013A
1K
1K
1K
1K
JTAG INTERFACE
EPM570GF100C5N
R216
R218
R220
R222
USB_FULL 3
USB_EMPTY 3
USB_SCL 3
USB_SDA 3
USB_B2_CLK 3,7
USB_RESETn 3
USB_OEn 3
USB_RDn 3
USB_WRn 3
USB_DISABLEn
MAX II
CONFIGURATION
MAX_SDA
R227
R214
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
EPM570GF100C5N
IFCLK
XTALIN
XTALOUT
3.3V
B
FX2_PB1
FX2_PB3
FX2_SCL
FX2_PD6
FX2_PD4
2K
2K
FX2_WAKEUP
10K
H8
J3
J4
J5
J6
J8
J9
K1
K2
K3
K4
K5
K6
K7
K8
K10
EPM570GF100C5N
R207
R208
CY7C68013A-56LTXC
VBUS_5V R213
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
IO_B1
U31C
13
5
4
CLKOUT
B1
C1
C2
D1
D2
D3
E3
F1
F2
F3
G1
G2
G3
H1
H4
H7
RST
1V8
LED11
SC_RX
RESn_SC_RX
R229
3.3V
J12
DNI_R1005
DNI_LED
A
3.3V
R228
1K
R230
1K
LED12
SC_TX
RESn_SC_TX
R231
C_USB_MAX_TDI
DNI_R1005
DNI_LED
C_USB_MAX_TCK
C_USB_MAX_TDO
C_USB_MAX_TMS
1
3
5
7
9
2
4
6
8
10
C145 C146 C147 C148
C149 C150
0.1uF 0.1uF 0.1uF 0.1uF
0.1uF 0.1uF
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
XG4C-1031
NOV. 20, 2013
Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
17
of
Rev
STEP
1.22
26
Power Monitor
12V
J13
1
2
DNI_22-23-2021
D
TR2
OVERTEMP 3
FDV305N
3.3V
V4
1 RSNS SNS 2
3.3V_HPS
SENSE_PAD
V5
1 RSNS SNS 2
2.5V
SENSE_PAD
V6
1 RSNS SNS 2
SENSE_PAD
2.5V_FPGA
V7
1 RSNS SNS 2
1.5V
1.5V_HPS
1.1V
1.1V_VCC
SENSE_PAD
V8
1 RSNS SNS 2
SENSE_PAD
V9
1 RSNS SNS 2
SENSE_PAD
V10
1 RSNS SNS 2
SENSE_PAD
V11
1 RSNS SNS 2
R232
R233
100_1%
100_1%
C151
0.1uF
C152
0.1uF
R234
R235
100_1%
100_1%
C153
0.1uF
C154
0.1uF
R236
R237
100_1%
100_1%
C155
0.1uF
C156
0.1uF
R238
R239
100_1%
100_1%
C157
0.1uF
C158
0.1uF
R240
R241
100_1%
100_1%
C159
0.1uF
C160
0.1uF
R242
R243
100_1%
100_1%
C162
0.1uF
C163
0.1uF
R244
R245
100_1%
100_1%
C164
0.1uF
C165
0.1uF
R246
R247
100_1%
100_1%
C166
0.1uF
C167
0.1uF
12V
U34
SENSE_PAD
3.3V_PM
R248
R249
5,12,15 I2C_SCL_HPS
5,12,15 I2C_SDA_HPS
4 I2C_SCL_FPGA
4 I2C_SDA_FPGA
R250
R251
0_1608
0_1608
R449
R450
0_1608
0_1608
10K
10K
SCL_PM
SDA_PM
ASEL0
ASEL1
PM_CNTL0
PM_CNTL1
PM_CNTL1 R427
0
0
28
27
32
33
30
31
22
SCL
SDA
ASEL0
ASEL1
CONTROL0
CONTROL1
WDI/RESET
10K
10K
10K
10K
23
24
25
26
FAULTB00
FAULTB01
FAULTB10
FAULTB11
R263
10K
21
SHARE_CLK
19
65
WP
E-PAD
PM_ALERTB
PM_CNTL0
ASEL0
ASEL1
98424-G52-12LF
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
R258
R259
R261
R262
SDA_PM
SCL_PM
R425
R426
36
37
42
43
46
47
48
49
52
53
62
63
64
1
2
3
10K
10K
10K
J15
2
4
6
8
10
12
VIN_SNS
R253
R254
R256
3.3V_PM
1
3
5
7
9
11
14
VIN_EN
12
C161
REFP
REFM
NC
34
35
13
0.1uF
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
39
38
40
41
44
45
50
51
55
54
56
57
59
58
60
61
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
4
5
6
7
8
9
10
11
ALERTB
PWRGD
VPWR
VDD25
29
20
15
18
VDD33_OUT
VDD33_IN
16
17
R419
R420
R421
R422
VDAC_3.3V 20
VDAC_2.5V 22
VDAC_1.5V 21
VDAC_1.1V 19
3.3V_PM
R252
10K
R255
10K
R257
10K
R260
10K
EN_3.3V 20,23
EN_2.5V 22
EN_1.5V 21
EN_1.1V 19
3.3V_PM
PM_ALERTB R264
R265
10K
10K
3.3V_PM
LTC2978CUP#PBF
C168
C169
C170
I2C Address = 0x5C
0.1uF
0.1uF
0.1uF
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
Rev
ALTHEL10SOC-R1.2
Sheet
1
1.22
18
of
26
STEP
-
Power 1 - DC Input, 1.1V

12V
J14
RAPC722X
C171
2
1
3
C172
47uF_25V
47uF_25V
PL03B
Center Plus
12V
SNS_1.1V_P
C174
SNS_1.1V_M
R266
100K
V12
D4
BOOST
INTVCC_1.1V
11
2
3
4
5
6
7
8
9
59
16
17
19
28
29
PVIN2
PVIN3
PVIN4
PVIN5
PVIN6
PVIN7
PVIN8
PVIN9
PVIN10
PVIN11
PVIN12
PVIN13
PVIN14
SGND2
SGND3
SGND4
SGND5
SGND6
SGND7
SW2
C176
58
SNS_1.1V_M R270
SW3
SW4
SW5
SW6
SW7
SW8
SW9
NC
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
51
50
49
48
47
46
45
52
44
43
42
41
40
39
38
37
SW_1.1V
10
14
1000pF15
SNS+
1.1V
18
R272
13.7K
1%
R273
16.5K
1%
R274
18 VDAC_1.1V
C186
C188
10
35
PGND1
36
VOSNS-
21
VOSNS+
TRACK/SS
INTVCC1
34
INTVCC2
33
PVIN1
SVIN1
32
LTC3613EWKH#PBF
SGND11
INTVCC_1.1V
R279
0.1uF
R268
TP5
1.1V_VCC
1.1V
L7
SW_1.1V
R269
1.1V_VCCEL
0.001
Isat = 20A
0.0015
R271
C177
C179
C178
0
100uF_6.3V
100uF_6.3V
3A_30 Ohm FB
C180
4.7uF_16V
L20
1.1V_HPS
3A_30 Ohm FB
INTVCC_1.1V
12V
C181
C182
C183
C184
C185
22uF_25V 22uF_25V 47uF_25V 47uF_25V
0.1uF
47pF
470pF R276
23
ITH
24
VRNG
25
RT
MODE/PLLIN
31
R275
EXTVCC
NC
30
27
C189
R277
DNI_C1005
RUN
26
30.1K
SGND11
TP4
0.47uH
SGND11
75K_1608
C187
3300pF
SD107WS-TP L8
VOUT
20
22
SW1
SW2
SNS-
DNI_R1005
SGND11
R282
115K
1%
12
R281
0
SGND
57
56
55
54
53
10
C175
SNS_1.1V_P R267
U35B
10TPE330M
12V
PGOOD
V13
U35A
13
20,21,22,23 PGOOD_1.1V
SENSE_PAD
Regulator input caps

Place near regulator
controller
RSNS SNS 2
INTVCC_1.1V
SENSE_PAD
22uF_25V 22uF_25V
RSNS SNS 2
C173
10K
INTVCC_1.1V
DNI_R1005
SGND11
R278
EN_1.1V 18
LTC3613EWKH#PBF
R280
DNI_R1005
SGND11
SGND11
TP6
TP7
5.0V
SW16
R284
1K
Power LED
LED13
Rxxx
2
3
12V
R283
100K
0_1608
RUN_1.1V
R285
51K
DNI_EG1206A
Power Switch
Green_LED
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
19
of
Rev
STEP
1.22
26
Power 2 - 3.3V
D
SNS_3.3V_P
D5
PGOOD
BOOST
INTVCC_3.3V
11
U36B
PVIN2
PVIN3
PVIN4
PVIN5
PVIN6
2
3
4
5
6
7
8
9
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
NC
PVIN7
PVIN8
PVIN9
PVIN10
PVIN11
PVIN12
PVIN13
PVIN14
59
SGND2
16
17
19
28
29
SGND3
SGND4
SGND5
SGND6
SGND7
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
10
14
SNS_3.3V_M R290
10
1000pF15
C191
58
51
50
49
48
47
46
45
52
44
43
42
41
40
39
38
37
SW_3.3V
SNS+
3.3V
18
20
R292
11.5K
1%
18 VDAC_3.3V
R293
2.55K_1%
1%
21
R294
SW1
SW2
10
35
PGND1
36
INTVCC1
34
INTVCC2
33
SNS-
0.1uF
3.3V TP8
3.3uH
R288
TP9
3.3V_HPS
SW_3.3V
R289
0.001
Isat = 11A
0.007
R291
C192
C194
6TPF330ML
C193
0
47uF_10V 47uF_10V
VOUT
SGND33
VOSNSVOSNS+
20K_1608
22
TRACK/SS
23
ITH
PVIN1
SVIN1
32
MODE/PLLIN
31
C195
4.7uF_16V
INTVCC_3.3V
12V
C196
0.1uF
C197
C198
C199
C200
22uF_25V 22uF_25V 47uF_25V 47uF_25V
C201 100pF
C202
3300pF
SGND33
INTVCC_3.3V
LTC3613EWKH#PBF
C203 470pF R296
75K
1%
SGND33
R299
DNI_R1005
24
VRNG
25
RT
SGND33
R302
115K
1%
12
R301
0
12V
R295
INTVCC_3.3V
10K
C204
SGND
57
56
55
54
53
SNS_3.3V_P R287
SD107WS-TP L9
C190
U36A
13
12V
V15
SENSE_PAD
V14
SENSE_PAD
R286
100K
RSNS SNS 2
SNS_3.3V_M
RSNS SNS 2
INTVCC_3.3V
EXTVCC
NC
30
27
RUN
26
LTC3613EWKH#PBF
R297
DNI_C1005
DNI_R1005
SGND33
R298
R300
EN_3.3V 18,23
DNI_R1005
PGOOD_1.1V 19,21,22,23
SGND33
C205
C206
SGND33
22uF_25V 22uF_25V
B

controller
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
20
of
Rev
STEP
1.22
26
Power3 - 1.5V, DDR3 VREF & VTT

D
C207
D6
SD107WS-TP
1uF_10V
12V
C208
2.2uF
R303
10
1
R304
19
BOOST
C210
C211
22uF_25V 22uF_25V
0.1uF
SVIN
20
21
INTVCC
22
SGND
23
CLKOUT
CLKIN
SGND15
24
C209
Cad Note:
controller
C212
0.1uF_50V
RT
PVIN
18
PVIN
17
PHMODE
MODE
SW
16
FB
SW
15
SW
14
SW
13
Design Note:
Prefer 0603 size cap
25V rated voltage is sufficent
TP11
1.5V TP10
162K
SGND15
L10
1.2uH
Isat = 11A
C213
ITH
18 EN_1.5V
19,20,22,23 PGOOD_1.1V
R311
R312
39pF
R306
C215
C216
C217
C218
15K
22uF_6.3V
1%
22uF_6.3V
22uF_6.3V
22uF_6.3V
R345
Cad Note:
Place output caps
near inductor
PGND
SGND15
R309
56K_1608
VDAC_1.5V 18
U37
LTC3605EUF
25
SW
SW
12
SGND15
11
33pF
PGND
C220
C214
0.003
24K
10
1200pF R308
EXPOSED PAD
RUN
C219
DNI_R1005
TRACK/SS
VON
R307
PGOOD
SGND15
3300pF
1.5V_HPS
R305
R310
10K_1608
DNI_R1005
3.3V
SGND15
R313
100K
PGOOD_1.5V
1.5V
C221
C223
10uF_6.3V
10uF_6.3V
3.3V
U38
C222
10K
TP14
VREF_HPS_DDR3 TP15
1uF_10V
6
C225
VLDOIN
REFIN
VIN
EN
PGOOD
REFOUT
11
4
8
TPS51200DRCx
0.1uF
2
1
R314
10K
VTT_HPS_DDR3 TP12 TP13

GND_PAD
PGND
GND
R315
10
7
9
C224
VO
VOSNS
3
5
R316
10K
1000pF
C226
C227
C228
10uF_6.3V
10uF_6.3V
10uF_6.3V
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
21
of
Rev
STEP
1.22
26
Power4 - 2.5V, 5V, 1.8V
C231
D7
SD107WS-TP
1uF_10V
12V
C232
2.2uF
R317
10
R318
19
C234
0.1uF
BOOST
0.1uF_50V
RT
PVIN
18
PHMODE
PVIN
17
MODE
SW
16
FB
SW
15
Design Note:
25V rated voltage is
sufficent
162K
SGND25
DNI_R1005
ITH
R326
SW
13
2.5V_FPGA
2.5V_HPS
L11
R319
0.001
3A_30 Ohm FB
1.2uH
Isat = 11A
C238
39pF
R320
C239
C240
C241
C242
15K
22uF_6.3V
22uF_6.3V
1%
22uF_6.3V
22uF_6.3V
2.5V_HPS_FILT
L13
3A_30 Ohm FB
R346
0
L14
PGND
25
SW
12
SW
10
7
19,20,21,23 PGOOD_1.1V
R325
14
L12
TP17
2.5V TP16
2.5V_FPGA_FILT
SGND25
18 EN_2.5V
SW
Cad Note:
Place output caps
near inductor
24K
33pF
11
C244
EXPOSED PAD
PGND
1200pF R322
TRACK/SS
RUN
C243
VON
R321
3300pF
PGOOD
C237
SGND25
Cad Note:
controller
C236
C235
22uF_25V 22uF_25V
SVIN
20
21
INTVCC
22
SGND
23
CLKOUT
CLKIN
SGND25
24
C233
SGND25
R323
36K_1608
U39
LTC3605EUF
3A_30 Ohm FB
VDAC_2.5V 18
R324
4.7K_1608
DNI_R1005
3.3V
SGND25
R327
100K
PGOOD_2.5V
12V
5.0V
U40
C245
5.0V
TP18
TP19
L15
VIN
BOOST1
BD
BOOST2
12
6
C247
0.1uF
SW1
SW2
C250 DNI_C1005
R332
16.2K
D9
1
14
13
DA1
FB1
RUN/SS1
11
10
SYNC
RT
DA2
FB2
RUN/SS2
GND
L16
6.5uH
Isat = 6A
D8 DFLS230
22uF_25V
R330
10K
C246
0.1uF
6.5uH
R328 Isat = 6A
52.3K
C248
22uF_25V
25V
7
8
9
DFLS230
TP21
TP20
1V8
R329
12.4K
C249
22uF_6.3V
C251 DNI_C1005
R331
10K
15
LT3509EDE
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
22
of
Rev
STEP
1.22
26
Power5 - 3.3V_EXT
D
C252
1uF_10V
C253
2.2uF
D10
SD107WS-TP
12V
R334
19
C255
C256
0.1uF
22uF_25V
22uF_25V
C258
0.1uF_50V
RT
PVIN
18
PHMODE
PVIN
17
MODE
SW
16
FB
SW
15
SW
14
SW
13
Design Note:
25V rated voltage is
sufficent
ITH
18,20 EN_3.3V
19,20,21,22 PGOOD_1.1V
R339
R340
TP23
TP22
3.3V_EXT
L17
1.2uH
Isat = 11A
C259
39pF
R335
C260
C261
C262
C263
11.5K
1%
22uF_10V
22uF_10V
22uF_10V
22uF_10V
R347
PGND
25
SW
SW
12
SGND3E
11
33pF
PGND
C265
Cad Note:
Place output caps
near inductor
24K
10
1200pF R337
EXPOSED PAD
RUN
C264
DNI_R1005
TRACK/SS
VON
R336
PGOOD
SGND3E
3300pF
Cad Note:
controller
C257
162K
SGND3E
10
C254
SVIN
20
BOOST
21
INTVCC
22
SGND
23
CLKOUT
CLKIN
SGND3E
24
R333
0
SGND3E
U41
LTC3605EUF
DNI_R1005
R338
2.55K_1%
3.3V
B
SGND3E
R341
100K
PGOOD_3.3V_EXT
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
23
of
Rev
STEP
1.22
26
Cyclone V SoC Power

U1H
1.1V_VCC
U1I
CYCLONE V GX SoC
So C Power
J11
K13
K15
L11
L12
L14
M12
M13
M15
M9
N10
N11
N12
N14
N9
P11
P13
P14
P15
R10
R12
R14
R9
T15
T9
U26
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPD3A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
A2
B2
U8
AE14
D23
E12
DNU
DNU
DNU
DNU
DNU
DNU
AA14
AD13
AD16
AD18
AD21
AD9
Y21
VCCPD5B
W19
VCCPD8A
VCCPGM
VCCPGM
VCCPGM
VCCBAT
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
E10
AA5
W9
AE5
3.3V_HPS
Y10
AD24
H10
D7
2.5V_FPGA_FILT
2.5V_HPS_FILT
AC21
AC8
AD15
E15
F8
F21
U1J
VCCIO3A
VCCIO3A
VREFB3AN0
AA12
AE10
AE13
AG4
AF12
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VREFB3BN0
AA16
AE21
AF14
AF19
AG12
AG22
AH15
AH25
W13
AF16
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREFB4AN0
M5
N5
R5
T5
2.5V_FPGA
VCCIO5A
VCCIO5A
VREFB5AN0
AC25
W17
AC26
VCCIO5B
VREFB5BN0
W25
AA25
VCCIO8A
VREFB8AN0
E7
D9
1.5V_HPS
5CSXFC6C6U23
2.5V_VCCAUX_SHARED
2.5V_FPGA_FILT
VREF_HPS_DDR3
5CSXFC6C6U23
L18
VCCE_GXBL
VCCE_GXBL
VCCE_GXBL
VCCE_GXBL
1.1V_VCCL
VCCL_GXBL
VCCL_GXBL
L4
T4
VCCH_GXBL
VCCH_GXBL
M4
R4
1.1V_HPS
K5
P4
U4
W5
J4
AA21
2.5V_HPS
CYCLONE
CYCLO NE V GX SoC
Transceiver & HPS Power
1.1V_VCCEL
CYCLONE V GX SoC
S oC Power
2.5V_FPGA
AA10
VCCPD5A
VCC_AUX_SHARED
C
2.5V_FPGA
2.5V_FPGA_FILT
3.3V_HPS
U21
K17
L16
L18
M17
M18
M19
N16
N18
P17
P19
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
C25
C27
F27
G24
H21
H26
L26
M21
H28
AD27
P27
T21
T25
U18
W27
T27
VCCIO7A_HPS
VCCIO7A_HPS
C20
D18
VCCIO7B_HPS
VCCIO7B_HPS
B13
H14
VCCIO7C_HPS
B10
VCCIO7D_HPS
VCCIO7D_HPS
D6
G5
VREFB7A7B7C7DN0_HPS
D19
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VREFB6AN0_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
K21
K24
M24
P21
P24
VCCPD7A_HPS
E21
VCCPD7B_HPS
E17
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VREFB6BN0_HPS
VCCPD7C_HPS
E14
VCCPD7D_HPS
E13
VCCPLL_HPS
H23
VCCRSTCLK_HPS
VCCRSTCLK_HPS
F22
J19
2.5V_HPS
3.3V_HPS
C
2.5V_HPS_FILT
3.3V_HPS
5CSXFC6C6U23
2.5V_VCCAUX_SHARED
3A_30 Ohm FB
U1K
U1L
CYCLONE V GX
SoC GND
F23
E23
D21
F6
A10
A3
AA1
AA17
AA2
AA3
AA9
AB24
AB27
AB3
AC1
AC2
AC3
AD14
AD22
AD25
AD3
AD6
AD8
AE1
AE16
AE18
AE2
AE3
AF24
AF3
AG1
AG17
AG2
AG27
AG3
AG7
AH10
AH20
B15
B17
B20
B22
B25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CYCLONE V GX
SoC GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B27
B3
B5
B7
C1
C11
C2
C3
D10
D13
D16
D3
E1
E19
E2
E22
E24
E27
E3
E9
F3
G1
G2
G3
H11
H15
H18
H20
H24
H27
H3
H4
H5
H6
J1
J2
J3
J5
J9
K11
K12
K14
K16
K20
K3
K4
K8
L1
L10
L13
L15
L17
L19
L2
L24
L27
L3
L5
L8
L9
M10
M11
M14
M16
M20
M3
M8
N1
N13
N15
N17
N19
N2
N3
N4
P10
P12
P16
P18
P20
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P25
P3
P5
P9
R1
R11
R13
R15
R2
R3
R8
T10
T14
T3
U1
U12
U17
U2
U20
U24
U27
U3
U5
V14
V3
V8
V9
W1
W16
W18
W2
W3
W4
Y12
Y14
Y20
Y25
Y3
V26
V21
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
5CSXFC6C6U23
NOV. 20, 2013
Checked
Title
5CSXFC6C6U23
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
24
of
Rev
STEP
1.22
26
Decoupling
1.1V_VCC
1.1V_VCCEL
L19
C266
C267
C268
C289
C290
C291
C292
C293
C276
C277
C278
C279
C280
0.47uF
0.22uF
1.1V_VCCL
2.5V_FPGA_FILT
C283
C282
C281
1uF_10V
47nF
47nF
220 Ohm FB
330uF_2.5V
330uF_2.5V
4.7uF_16V
4.7uF_16V
2.2uF
330uF_2.5V
100uF_6.3V
4.7uF_16V
22uF_6.3V
1uF_10V
1uF_10V
C306
C294
C295
C296
C301
C302
C303
C304
0.47uF
0.47uF
0.47uF
0.22uF
0.22uF
0.22uF
0.22uF
C311
C312
C313
C314
C315
47nF
47nF
47nF
47nF
47nF
C346
C347
C348
C349
C350
C351
C352
C353
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C284
C285
C286
C297
C298
C299
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
C307
100uF_6.3V
1uF_10V
C308
C309
C310
0.47uF
0.1uF
47nF
D
C324
C325
C326
C327
C433
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C328
C343
C344
C345
22nF
4.7nF
4.7nF
4.7nF
C367
2.5V_FPGA
C318
C319
330uF_2.5V
C359
C360
C361
C362
C363
C364
C365
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C320
C321
C322
C323
0.47uF
0.22uF
0.1uF
47nF
1.5V_HPS
4.7uF_16V
C366
C335
C336
C337
C338
C339
C340
C434
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C438
C439
C440
C441
C442
C443
C446
C447
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C368
C369
C370
C371
330uF_2.5V
2.5V 4.7uF_16V
0.47uF
0.22uF
0.1uF
47nF
C378
C379
C380
C436
C437
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C454
C455
C456
C381
C382
C341
C342
C457
C354
C355
C356
C357
C358
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
22nF
22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C396
C397
C398
C399
C400
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C409
C410
C411
C412
10uF_6.3V
47nF
0.01uF
22nF
C458
C459
C460
C461
C462
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
1.1V_HPS
2.5V_HPS_FILT
C383
C384
C385
C386
C387
C388
2.5V_HPS
100uF_6.3V
100uF_6.3V
2.2uF
0.47uF
0.22uF
0.1uF
C372
C401
C402
C403
C404
47nF
47nF
47nF
47nF
C463
C464
C465
C466
22nF
22nF
22nF
22nF
C373
100uF_6.3V
4.7uF_16V
C467
22nF
C374
C375
C376
C377
0.47uF
0.1uF
47nF
47nF
47nF, 0.01uF,
22nF, 4.7nF caps
are place near the
pin of the FPGA
C389
C390
C393
C394
C395
C407
C408
0.01uF
0.01uF
22nF
22nF
22nF
4.7nF
4.7nF
C468
22nF
STANDOFF1 STANDOFF2 STANDOFF3 STANDOFF4 STANDOFF5
M3x25
M3x25
M3x25
M3x25
M3x25
SCREW1
SCREW2
SCREW3
SCREW4
SCREW5
3.3V_HPS
C415
C416
100uF_6.3V
1uF_10V
2.5V_VCCAUX_SHARED
C413
C414
1uF_10V 4.7uF_16V
C417
C418
C419
0.22uF
0.1uF
22nF
M3x8 B SEMS M3x8 B SEMS M3x8 B SEMS M3x8 B SEMS M3x8 B SEMS
VREF_HPS_DDR3
C469
C470
C471
C472
C473
C474
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C475
C476
C477
C478
C479
C480
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C420
C421
C422
C423
C424
C425
0.01uF
0.01uF
0.01uF
4.7nF
4.7nF
22nF
C488
0.01uF
Designed
A
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
25
of
Rev
STEP
1.22
26
History
REV
DATE
PAGES
All
0.0
DESCRIPTION
INITIAL REVISION A RELEASE
Add C426-C429
Add R344-R343, TR3, TR4, R223
Add J15
0.1
01/23/2013
Add Bypass Cap

Modify JTAG_TRST Line
Add I2C Connector
0.2
01/24/2013
U33 CY7C68013A VBGA56 to QFN56

U15,U13 MAX13042E UCSP12 to TDFN14
Add Component
LED14,15
"," to "_"
Replace char
Change Component TP4-TP6
0.3
0.4
0.5
Package change
01/25/2013
01/28/2013
01/28/2013
Page 25
Page 13
Page 19-23
Page 12,14,
16,17
Page 9
Page 17
Change net
Add GND net
Separete GND
Separete Shell GND
1.5HPS to 1.5V_HPS
C101, C102
Add R345-R347
Add R348-R350, C430-C432
Add bypass Circuit

Add Jumper R
Add R351-R379
Add R380-R418
Page 15
Page 15,17
Page 5
Page 3
Change Component
Change Component
Change net
Change Component
Page 22
Page 21
Page 12
Page 9
Page 17
Page 18
Page 16
Change Value
R324 4.7K_1% to 4.7K_1608
R310 10K to 10K_1608
Change Value
Boot Strap Signal GTX_CLK to RX_CLK
Change net
U20 SHDN Pin Pullup 5.0V to 2.5V
Change net
Change Boot Sel
Change SW2 to J16,J18,J20 Change SW1 to J17,J19
Add SW1 to J17,J19
Switch
Change Dipsw
Change SW4 KHS62C to KHS42C Move from SW1
Change MAXII setting line Change DNI_R1005 to DNI_R1608 Change R418 1K to 1K_1608
Add 0 ohrm
Add R419-R422
Change Component
Change U28 CP2104 to CP2103
Page 5
BT1 SMTU2032 to SMTU1225, B4 CR2032 to CR1225

U22,U23 MAX811 to MAX6315 R145,R149,R205 100K to 10K
J1-34pin Logic 0 to Logic 1
R1,R2 10K to 2K
REV
DATE
PAGES
1.1b
03/07/2013
Page 19-23
Page 15
Page 17
Change Value Change CheckLand to TP at even number Reference from TP4 to TP23.
Change Value Change TH_GPIO to DNI_TH_GPIO.
Rotate Component
Rotate Y3 to 90deg.
DESCRIPTION
1.1c
03/08/2013
Page 7
Change Component
1.1d
03/11/2013
Page 19
Page 20
Page 7
Not Connect
Not Connect
Fix Component
1.1e
03/25/2013
Page 7
Page 9
Page 15
Page 17
Page 18
Not Mount Component

Not Mount Component
Not Mount Component
Not Mount Component
Not Mount Component
X5,R443,R444,C482,C483,Y1,C17,C18
R21,R22
R168,R169
LED9-LED12,R224-R226,R229,R231
R419-R422
1.2
05/01/2013
Page 1
All
Change
Change
block diagram
Title block
1.21
09/13/2013
Page 18-23
Change Value
R419-R422, R278, R280, R298, R300, R311. R312, R325, R326, SW16
1.22
11/20/2013
All
Change/Remove Comment
X5 16MHz to 6MHz
U35 52pin Not Connect.

U36 52pin Not Connect.
X5 FCXO-03L 6.000MHz
0.6
01/28/2013
Page 12
Page 10
Change Component
Add DDR3 Address
U12 LTC3026EDD-1 to LTC3026EDD C95 0.1uF to 2.2uF

DDR3_HPS_A13, DDR3_HPS_A14 Add R423, R424
0.6a
01/29/2013
Page 7
Change Component
X4 4MA to CL20VBC
0.6b
01/29/2013
Page 19
Page 15
Page25,10
Add Component
Change net
Change Component
L20
LED3-LED6
Cap Size 1005 to 0603
0.6c
01/29/2013
Page18-24
Change net
Remove C229,C230
0.6d
01/29/2013
Page18
Change connector pin assign
0.6e
01/30/2013
Page9
Page4,10
Page21-23
Page7,14,18
Change Component
U12,U15 MAX13042 to TXB0104
Add Component
R428,R429,R430
L10,L12,L17 PCMC053T-1R2MN to PCMB053-1R2MS
Change Component
Change x'tal CL 12pF to 24pF
C7,C9,C13,C15,C19 0.1uF to 0.01uF
Add R445-R447
0.6f
01/31/2013
Page6,11
Add Component
R431-R440
0.6g
01/31/2013
Page8
Change Component
TR1 DTC114EUA to RUE002N02
0.6h
01/31/2013
Page6,3
Page10
Pin Swap HSMC

Add Component
C481
0.6j
02/01/2013
Page6,3
Page12
Page7
Pin Swap HSMC

Change Component
Add OSC
R111-R118 49.9 to DNI_1005

ADD X5,R443,C482,C483,R444
Add R441
Add R442
B
0.6k
02/01/2013
Page18
Page10
All
Page14,3
Change net
Change net
Rename Ref
Pin Swap
J15.5 NC to 3.3V_PM
Swap DDR DQ bus
TP4-6 to TG1-3
D1,D2, HSMC
0.6m
02/02/2013
Page17
Page9
Change power net

Add 0ohm jumper
Pullup 2.5V to Pullup 3.3V

R445-R448
U11.14 JTAG_FPGA_TDI to HV_JTAG_FPGA_TDI
0.6n
02/04/2013
Page9
Page4,18
Page5,15
Page10
Modify net
Modify net
Modify net
Change net
Change net
U15.12 connects to SW4.5

U34.I2C bus connects to FPGA I/O
SPI bus connects to LCD module
Swap DDR DQ bus
0.6p
02/05/2013
Page15
Add Component
R451-R454
0.6q
02/05/2013
Page4,10
Change Component
R428 10 to 51
DDR Terminal R 51 to 62
Move Page4 to 10
0.6r
02/05/2013
Page10,4
Change Component
0.6s
02/06/2013
Page25
Page10,25
FPGA
DDR
0.6t
02/07/2013
Page18-23
Change Component
R232-R247, C188, C203, R276, R296, C201, C192,

C193, C260-C263, L8, R268, R288
1.0
02/23/2013
Page14
Change Component
R167 DNI to 0
Dump R 10 to 22
Adjust a quantity of bypass cap

Adjust a quantity of bypass cap
Designed
A
Board Release
1.1
1.1a
03/04/2013
03/04/2013
Page17
Page22
Page9
Page18
Change Component
J12 DNI_XG4C-1031 to XG4C-1031
Change net
Connect U40.13, U40.9 to PGOOD_1.1V
Do Not Insert Component
U13, U15, C28-C31, R79, J3, XJ1, R72, R80
Change Component
R449, 450 DNI to 0
Page19-23
Page15
Add Component
Add Check Land TP6 to TP23
Remove Component B1 to B3
NOV. 20, 2013

Drawn
ALTIMA Corporation
NOV. 20, 2013

Checked
Title
NOV. 20, 2013
Approval
Helio Board
A3
NOV. 20, 2013

5
ALTHEL10SOC-R1.2
Sheet
1
26
of
Rev
STEP
1.22
26

Helio Board SCH v1.22

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5

FPGA Package Top

Cyclone V SoC Bank 3 & 4

Cyclone V SoC Bank 5 & 6

Cyclone V SoC Bank 7

Cyclone V SoC Transceivers & Clocks

Cyclone V SoC Configuration

Ethernet PHY & RJ45

QSPI Flash & Reset Circuit

USB 2.0 OTG & Micro SD Card

User I/O ,RTC

On-Board USB Blaster II

Power1 - DC Input, 1.1V

Power3 - 1.5V, DDR

Power4 - 2.5V, 5V, 1.8V

Cyclone V SoC Power

Cyclone V SoC Capacitor

NOV. 20, 2013

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

FPGA Package Top View

NOV. 20, 2013

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

Cyclone V SoC Bank 3 & 4

CYCLONE V GX SoC BANK

FPGA USB INTERFACE

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

Cyclone V SoC Bank 5, 6

NOV. 20, 2013

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

Cyclone V SoC Bank 7

CYCLONE V GX SoC BANK

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

Cyclone V SoC Transceivers & Clocks

CYCLONE V GX SoC Transceiver

NOV. 20, 2013

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

NOV. 20, 2013

NOV. 20, 2013

1-5-5, Shin-Yokohama, Kouhoku-ku, Yokohama, 222-8563 JAPAN

NOV. 20, 2013

Date: Wednesday, November 20, 2013

Cyclone V SoC Configuration

CYCLONE V GX SoC C onfiguration

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