ECE 3060

VLSI and Advanced Digital Design

Logical Effort: Asymmetric Gates, Bundles
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More Notation
It turns out, we do not need to x p-fets to be twice as
wide as n-fets (See chapter 7)
Let be dened as the ratio of p-fet width to n-fet
width in an inverter. Then LE can be dened in terms
of .
So far we have dened LE specically on a per input
basis.
The text introduces additional terms:
The logical effort per bundle is the sum of the logical efforts of
related signals
Example: A signal and its complement are both inputs to a
gate. This input bundle is called .
Total logical effort is the sum of the logical effort of all inputs to a
gate.

s s
s*
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Asymmetric Gates
Consider an AOI21:
Note that input has lower logical effort (5/3 vs 2) than
or .
c
a b
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Multiplexors
There are many styles of MUX design. They can be
designed using logic networks, or they can be
designed using tri-state devices.
Consider the inverting MUX shown here:
What is logical effort per select bundle, data input,
and total logical effort?
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XOR2 Gate
Consider the two input XOR
Total logical effort?
Logical effort/bundle?
Logical effort/input ( )? g
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Symmetric XOR3
Total logical effort?
Logical effort/bundle?
Logical effort/input ( )? g
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Asymmetric XOR3
Total logical effort?
Logical effort/bundle?
Logical effort/input ( )? g
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Layout of Sized Gates
Inverter chain ( driving )
Reduce drain (parasitic output) capacitance by about
1/2 (and total area) by sharing drain regions
2C
inv
8C
inv