module crc5_tf;

// Inputs
reg clk;
reg rst;
reg en;
reg din;

// Outputs
wire [4:0] crc;
// wire [7:0] count;

// Instantiate the Unit Under Test (UUT)
crc5 uut (
.clk(clk),
.rst(rst),
.en(en),
.din(din),
.crc(crc)
//.count(count)
);

initial begin
// Initialize Inputs
clk = 0;
rst = 0;
en = 1;
#15 rst=1;
din=1;
#20 din=1;
#20 din=1;
#20 din=1;
#20 din=1;
#20 din=1;
#20 din=1;
#20 din=1;
#20 rst=0;
#20 din=0;
end

always #10 clk=~clk;

endmodule











UUT CODE




module crc5(clk,rst,en,din,crc);
input clk,rst,en;

input din;
//output count;
//reg [7:0]count;
output reg [4:0]crc;


wire crc4_out;
assign crc4_out=din|crc[4];

always@(posedge clk)
begin
if(~rst)
crc=0;
else if(en)
begin
crc[4]=crc[3];
crc[3]=crc[2];
crc[2]=crc[1]^crc4_out;
crc[1]=crc[0];
crc[0]=crc4_out;
end
end



endmodule