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7. Block Diagram
7-1 Overall Block Diagram
Y Main Board
X Main Board
1366x768 Pixels
1366x768x3 Cells (R,G,B)
Deinterlac-
er (220V)
Image CPU
Scaler Decoder
Micom
CN804-1(Main SMPS) CN803(Main SMPS) CN810(Main SMPS) CN2(DC-DC SMPS) CN4(DC-DC SMPS)
↔ ↔ ↔ ↔ ↔
CN102(Main Board) CN101(Main Board) CN2013(Logic Board) CN5007(Y B'D) CN4001(X B'D)
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1 5.3V 1 6.5V 1 STBY 1 Vs 1 D5.3V
2 RTN 2 RTN 2 VS_ON 2 Vs 2 Vg
3 N/C 3 12V 3 N/C 3 RTN 3 RTN
4 N/C 4 RTN 4 PS_ON 4 RTN 4 RTN
5 RTN 5 18Vamp 5 RTN 5 Vset 5 Ve
6 RTN 6 18Vamp 6 5.3V 6 RTN 6 RTN
7 12V 7 RTN_amp 7 RTN 7 Vscan 7 RTN
8 PS_ON 8 RTN_amp 8 RTN 8 RTN 8 Vs
9 RTN 9 Vt 9 5.3V 9 Vg 9 Vs
10 STBY 10 RTN 10 5.3V 10 D5.3V
11 FAN_ON
12 FAN_D
CN6(DC-DC SMPS)
↔
CN2509(E-Buffer)
Pin No. Signal
1 RTN
2 N.C
3 D5.3V
4 N/C
5 Va
Auxiliary
Control
Power
and
Switching Block Feedback
Block
Vset Output
Rectification
Transformer
Block
(175~210)
Control Auxiliary
and Power
Switching Block Feedback
Block
Ve Output
Rectification
Transformer
Block
Control Auxiliary
and Power
Switching Block Feedback
Block
1. Y Drive Board
2. X Drive Board
SDA, SCL
4pin (I2C)
TX, RX
DDR
(MA)
DATA : 32bit
DDR
SPS-H102 ADDR : 12bit
DQS, CLK, nCLK
(ASIC 580P)
50pin Connector
Y-MAIN (FA)
40pin Connector
CONTROL DDR
SIGNAL
(MB) X-MAIN
CONTROL
SIGNAL
DRIVE
CONTROL
RESET
SIGNAL
MICOM
7029_EN