EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

University of California
Berkeley
College of Engineering
Department of Electrical Engineering
and Computer Science

Robert W. Brodersen
EECS140
Analog Circuit Design

Lectures
on
OP AMPS
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp OP-1

VDD

M3 M4
V d1
Vd1 V d2 Vd2 M5
νOUT
ν1
v1 ν2
v2
M1
M2 Rc

M13 M12
M6

-V dd -Vdd -V dd
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-2

ν OUT
ν1 -
ν OUT ν id +- R OUT

ν2 + a ⋅ν ν id

R id = ∞ ν ν ν
------ ⋅ --------- = --------
-
d2 OUT OUT

νid ν d2 νid
R OUT = r o5 || r o6
g m2 ⋅ ( r o2 || r o4 ) g m5 ⋅ R OUT
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-3

What is the DC voltage at Vd2?
I DS1 = I DS2 = I DS3 = I DS4

I DS3 = k'
--- ⋅ W
----- ⋅ ( V SG3 – V T )2 ⋅ ( 1 + λ ⋅ V SD3 )
2 L

I DS4 = k'
--- ⋅ W
----- ⋅ ( V SG4 – V T )2 ⋅ ( 1 + λ ⋅ V SD4 )
2 L
I DS3 = I DS4

( V SG3 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD3 ) = ( V SG4 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD4 )

V SG3 = V SG4

( V SG3 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD3 ) = ( V SG3 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD4 )

V SD3 = V SD4 = V SG3 = V T + V DSAT3

V D 1 = V D D – V SG3 = V D D – V T – V DSAT 3 = V D2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-4

To set offset at output or 2nd stage M5, M6 to near zero,
set IDS5 = IDS6
--- ⋅  W
I SD5 = k' ----- ⋅ ( V SG5 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD5 )
2  L5

--- ⋅  W
I SD6 = k' ----- ⋅ ( V GS6 – V T ) 2 ⋅ ( 1 + λ ⋅ V DS6 )
2  L6
I DS5
Since V SD4 = V SG3 = V SG5

I SD5 = I DS3 if W
----- =  W
----- 
 L  L
5 3

I SD6 = 1-- ⋅ I SD13 if W

----- = 2 ⋅  W -----
I DS6 2  L  L
13 6

then I DS6 = I DS5 or,

W-----  W ----- 2 ⋅ W ----- 
I---DS5  L  L  L
---- = ------------5 = -------------------- = -------------------6
6

I DS3 W-----  W ----

-  ⁄2 W ----
- 
 L  L  L
3 13 13
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-5

What happens if I1 = α ⋅ I 2

--- ⋅  W
-----  ⋅ ( V SG1 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD1 )
k'
2  L 1

M2 --- ⋅  W
= α ⋅ k' ----- ⋅ ( V SG2 – V T ) 2 ⋅ ( 1 + λ ⋅ V SD'2 )
M1 2  L2
1 + λ ⋅ V SD1 = α ⋅ ( 1 + λ ⋅ V SD2 )
I1 I2 1
--- + V SD1
λ 1--
V SD2 = ------------------ –
α λ

α = 1 V SD2 = V SD1
1 100 + V SD1
α = --- V SD2 = ------------------------ – 100
2 1⁄2
λ = 0.01 = 100 + 2 ⋅ V SD1 Big Offset
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-6

Gain :
First Stage

ν
-----ds = – g m1 ⋅ ( r o4 || r o2 )
ν id

Second Stage
ν
--------- = – g m5 ⋅ ( r o6 || r o5 )
OUT

ν d2

Overall

A ν = g m 1 ⋅ g m5 ⋅ ( r o4 || r o2 ) ⋅ ( r o5 || r o6 )
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-7

⋅ I DS1 ⋅  2--------------
⋅ I DS5 ⋅ --------------------------------
A ν = 2-------------- 1 1
⋅ --------------------------------
V DSAT1  V DSAT5  ( λn + λp ) ⋅ I DS1 ( λn + λp ) ⋅ I DS5

4
= -----------------------------------------------------------------2
( V DSAT1 ) ⋅ ( V DSAT 5 ) ⋅ ( λ n + λ p )

4
A ν = -------------------------------------------------------------------------------------------------------
1-- 1--
2 ⋅ I SD1   2 ⋅ I DS5  2
 ---------------------------- 2
⋅ ⋅ ( λ n + λp )
2
----------------------------
 k'n ⋅ ( W ⁄ L ) 1  k' P ⋅ ( W ⁄ L ) 5

1-- 1--

2 ⋅ ( k' n ⋅ k' P ) ⋅  W ----- ⋅  W -----

1-- 2 2
2

L 1 L 5
= ----------------------------------------------------------------
1--

( λ n + λ p ) ⋅ ( I SD1 ⋅ IDS5 ) 2
2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-8

1
R OUT = r o5 || r o6 = --------------------------------
( λ p + λ n ) ⋅ I DS5

Add output stage if this is too high.

M1
What is the
V IN V OUT
output resistance of this ?
M2 RL
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Miller Op Amp (Cont.) OP-9

You need to choose an operating point since the R out is
very non-linear.

1
R OUT = ------
gm 1 V IN > V Tn

1
------
= g m2 V I N < – V Tp

1-- 1--

g m =  2 ⋅ W
----- ⋅ k' ⋅ I DS =  2 ⋅ W
----- ⋅ k' ⋅ I OUT
2 2

L L
1--

=  2 ⋅ W
----- ⋅ k' ⋅ V OUT
2
---------
L RL 
EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION

OP-10
Empty Slide
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

OP-11
+ V DD
You could use a level shifter

4V
W/L << 1
4V

– 4V
( – 4 )V

–V D D
– 5V
ν id
How to connect these?
+-

dc offset V id
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

OP1.SW0
∆
VOUT2 VOUT1 DIFF PAIR - GATE VOLTAGE SWEEP
96 / 10 / 03 18:13:44
OP-12
4.50
4.0
3.50
3.0
2.50 V
2.0 O
1.50 L
1.0 T

500.0M L
0. I
-500.0M N
-1.0
-1.50
-2.0
-2.50
-3.0
-3.50
-4.0
-4.50
-5.0
-10.0M -5.0M 0. VOLTS [LIN] 5.0M 10.0M
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Area Calculation (L=.5 micron minimum channel Length)OP-13

W/L=3
W

Resistor Area = # of squares * 1.0 µ2

1.0µ Resistor
W × 〈 L + 1µ 2〉 ≈ TransistorArea
1.5µ × ( 0.5 + 1 ) = 2.25µ 2

0.5µ
0.5µ
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Sheet Resistance OP-14

T W

1 ⋅T⋅σ
Conductance = ---------------------------- = W mhos
------------ -------------
Resis tan ce L cm 3

L- ⋅ ρ
R = ---- bl ρ1 = σ ⋅ T
W
{

ohms ⁄
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS

Sheet Resistance (Cont.) OP-15

TOP VIEW

count as 1/2 square

1 1 1
1 1 .5
}
}

1 15 SQUARES
W W
W 1
1 R = 15 ⋅ ρ bl
1 Ω
ρ 1 = 100 ----
1 1
R = 1.5kΩ
.
1 1 1 1 15