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5

SYSTEM PAGE REF.

01. Block Diagram


02. System Setting
03. CPU(1)_DMI,PEG,FDI,CLK,MISC
04. CPU(2)_DDR3
05. CPU(3)_CFG,RSVD,GND
06. CPU(4)_PWR
07. CPU(5)_XDP
16. DDR3(1)_SO-DIMM0
17. DDR3(2)_SO-DIMM1
18. DDR3(3)_CA/DQ Voltage
19. VID Controller
20. PCH(1)_SATA,IHDA,RTC,LPC
21. PCH(2)_PCIE,CLK,SMB,PEG
22. PCH(3)_FDI,DMI,SYS PWR
23. PCH(4)_DP,LVDS,CRT
24. PCH(5)_PCI,NVRAM,USB
25. PCH(6)_CPU,GPIO,MISC
26. PCH(7)_POWER,GND
27. PCH(8)_POWER,GND
28. PCH(9)_SPI,SMB
29. CLK_ICS9LPR362
30. EC_IT8512(1)
31. EC_IT8512(2)KB,TP,FP
32. RST_Reset Circuit
33. LAN_AR8131
34. LAN_RJ45
36. AUD(1)_ALC663VD
37. AUD(2)_AMP,JACK
38. AUD(3)_FM2010
40. CB(1)_R5U230
43. CB(4)_NewCard
44. BUG_Debug
45. CRT(1)_LVDS
46. CRT(2)_D-Sub
47. CRT(3)_Display Port
48. TV(1)_HDMI
50. FAN_Fan,Sensor
51. XDD_HDD,ODD
52. USB_USB Port
53. MINICARD_WLAN
56. LED_Indicator
57. DSG_Discharge
60. DC_DC/BAT CONN
61. BT_Bluetooth
64. TUN_TV Tuner
65. ME_CONN,Skew Hole
66. ESA_ESATA
69. OTH_GAME-LED
70. VGA(1)_MXM Slot
71. VGA(2)_LVDS Switch
80_PWR(1)_VCORE
81_PWR(2)_SYSTEM_+12VSUS
82_PWR(3)_VTT_CPUS & 1.05VS
83_PWR(4)_I/O_DDR & VTT
84_PWR(5)_****
85_PWR(6)_+1.8VS
86_PWR(7)_****
88_PWR(9)_CHARGER
90_PWR(11)_DETECT
91_PWR(12)_LOAD SWITCH
92_PWR(13)_PROTECT
93_PWR(14)_SIGNAL
94_PWR(15)_FLOWCHART
95. System History
98. Power On Sequence
99. Power On Timing

G60J Schematics for Calpella Platform Rev. 1.5


BLOCK DIAGRAM
D

HDMI

HDMI

Page 48

CRT

CLARKFIELD/AUBURNDALE
(DC&QC)

nVIDIA N10E-GT1

CRT

DDR3 1333MHz

CPU

PCIE x16

MXM
Page 70

Page 16~18

Page 3~7

Page 46

LCD Panel

DDR3 SO-DIMM

LVDS
4x
ID
F

Page 45

4x
IM
D

MiniCard
2

WLAN
Shirley Peak/ Echo Peak
Page 53

Debug Conn.

PCIEx1

Page 44

Touchpad
Keyboard

LPC

EC
ITE IT8512E

SPI ROM
Page 30

su
B
MS

Page 64

su
B
MS

CPU_VCORE

Ricoh R5U230

Page 65

Audio Jack

Azalia

Page 45

System
Page 81

USB Port(2)
Page 65

VTT
Page 82

USB Port(3)

HDD(2)

Page 52

DDR
Page 83

USB Port(4)

eSATA

Page 52
Page 66

12

Realtek ALC663

+1.8VS

Bluetooth

Page 85
Page 61

Page 36

13

Page 65

Array Mic

HDD(1)

Page 51

Page 80

USB Port(1)

ODD

Page 51

Azalia Codec

Power

Page 43

Page 40~41

ExpressCard

AT
A
S

PCIEx1

Page 34

Page 33~34

Page 51

CardReader+1394

RJ45

AR8131

Page 20~28

Page 50

Page 37

GigaLAN

SPI ROM
Page 28

TV Tuner

USB

Thermal Sensor
PWM Fan

Audio Amp
Speaker

MiniCard

PCH
Ibex Peak-M

Page 30

Page 31

Array Mic.DSP

Clock Generator

Fortemedia FM2010

ICS ICS9LPR362

GFX_CORE
Page 86

CMOS Camera
Page 45

Charger
Page 88

Page 29

Page 38

Detect
Page 90

Discharge Circuit
Reset Circuit

Load Switch

DC & BATT. Conn.

Page 57

Page 60

Page 91

Power Protect

Skew Holes

Page 32

Page 65

Page 92

Title : Block Diagram


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

PCH_IBEX
GPIO

PCH_IBEX
GPIO
GPIO 00
GPIO 01
GPIO [2:5]
GPIO 06
GPIO 07
GPIO 08
GPIO 09
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24
GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29

GPO
Native
GPI
GPI
Native
Native
GPI
Native
GPO
GPO
GPO
GPO
Native
GPI
Native
GPI
GPO
GPO
Native
Native
GPO
Native

GPIO 30

Native

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

Native
Native
Native
Native
GPO
GPI
GPI
GPI
Native
Native
Native
Native
Native
-

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

GPIO 49

Use As

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
72
73
74
75

GPO
Native
GPO
Native
Native
GPO
Native
Native
GPO
Native
Native
Native

Internal &
External
Pull-up/down

Signal Name
PCH_GPIO0_R
PCI_INT[E:H]#
DGPU_PWR_EN
EXT_SMI#
USB_OC5#
USB_OC6#
EXT_SCI#
PM_LANPHY_EN
CB_SD#
WLAN_ON
DGPU_HOLD_RST#
DGPU_PWROK
CLKREQ1_TV#
SATA_DET#1_R
CLKREQ2_WLAN#
SATA_DET#0_R
WLAN_LED
OC_LAN_RST#
CLKREQ3_NEWCARD#
CLKREQ4_ESATA#
BT_LED/SPI_CS#2
ME_PM_SLP_LAN#
ME_SUSPWRDNACK /
RTLAN_DSM#
ME_AC_PRESENT
PM_CLKRUN#
STP_PCI#
SATA_CLK_REQ#
DGPU_PWR_EN#
DGPU_PRSNT#
PCB_ID0
PCB_ID1
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
CLKREQ_PEG#
GPU_RST# /
CRIT_TEMP_REP#_R
PCI_GNT1#
DGPU_SELECT#
PCI_GNT3#
CLKREQ_GLAN#
BT_ON
SML1_CLK
USB_OC0#
RTLAN_DSM_EN
CLK_OUT0
CLK_OUT1
SML1_DAT

Power

+3VS
+3VS
+5VS
TBD
+3VS
TBD
+3VS
PU & INT PU
+3VSUS
PU
+3VSUS
PU
+3VSUS
PU
+3VSUS
PU
+3VSUS
+3VSUS
PU(DIODE DNI) +3VSUS
PD
+3VSUS
+3VS
PD & INT TBD
+3VS
PU(DNI)/PD
+3VS
+3VS
PU(DNI)/PD
+3VS
+3VS
PD
+3VS
+3VS
PU
+3VSUS
PU(DNI)/PD
+3VSUS
PU(Not used)
+3VSUS
WEAK PU
+3VSUS
PD
+3VSUS
PU(DNI)/PD(DNI) +3VSUS

INT TBD
EXT PU
INT
INT
EXT
EXT
EXT
EXT
EXT

EXT
INT

EXT
EXT

EXT

EXT

EXT
EXT
EXT
INT
EXT
EXT

EXT PU

+3VSUS

EXT PU

+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS

+3VS

EXT PU (Not used)

+5VS
+3VS
+5VS
+3VS
+5VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS

EXT PU

EXT PU
EXT PU/PD(DNI)
EXT PU
EXT PU
EXT PD
EXT PD
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PD

INT PU

EXT PU
INT PU

INT PU

EXT PU(DNI)/PD
EXT PU(DIODE)
EXT PU
EXT PU (Not used)
EXT PU

INT TBD
INT TBD
INT TBD
INT TBD

EXT PU (Not used)


EXT PU (Not used)
EXT PU

EC
IT8512

EC GPIO

Use As

Signal Name

GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
GPD0
GPD1
GPD2
GPD3
GPD4
GPD5
GPD6
GPD7
GPE0
GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPF0
GPF1
GPF2
GPF3
GPF4
GPF5
GPF6
GPF7
GPG0
GPG1
GPG2
GPG6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPJ0
GPJ1
GPJ2
GPJ3
GPJ4
GPJ5

O
O

PWR_LED#
CHG_LED#
GAME_LED_EC#
LCD_BL_PWM
FAN_PWM
SUSC_EC#
SUSB_EC#
SMB0_CLK
SMB0_DAT
A20GATE
RCIN#
PM_RSMRST#
SMB1_CLK
SMB1_DAT
PM_PWRBTN#
AC_IN_OC#
OP_SD#
BAT1_IN_OC#
RFON_SW#
PWRLIMIT#
PM_SUSC#
BUF_PLT_RST#
EXT_SCI#
EXT_SMI#
LCD_BACKOFF#
FAN0_TACH
VSUS_ON
EGAD (IT8301 Address/Data connect)
EGCS# (IT8301 Cycle Start connect)
EGCLK (IT8301 Clock connect)
PWR_SW#
LID_SW#
CAP_ACK#
EXP_GATE#
TP_CLK
TP_DAT
THRO_CPU
H_PECI
PM_SUSB#
PM_CLKRUN#
GFX_VR_ON
BAT_LEARN
HSCK
NUM_LED#
CAP_LED#
SUS_PWRGD
ALL_SYSTEM_PWRGD
VRM_PWRGD
GFX_VR
ALS_AD
CPU_VRON
PM_PWROK
VSET_EC
ISET_EC
TP_LED
-

O
O
O

O
O
IO
IO
O
O
O
IO
IO
O
I
O
I
I
I
I
I
O
O
O
I
O
O
O
O
I
I
I

I
I
IO
O
IO
I

IO
O
O
O
O
O
I
I
I
I
I

O
O
O
O
O

EC
IT8301

EC GPIO

Use As

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37

I
I

Signal Name

ME_PM_SLP_M#
ME_SUSPWRDNACK
ME_+VM_PWRGD
ME_PM_SLP_LAN#
ME_AC_PRESENT
ME_PWROK
ME_SLP_M_EC#
-

I
I
O

O
O

SM_BUS ADDRESS :
SM-Bus Device

SM-Bus Address

Clock Generator

1101001x

( D2h )

SO-DIMM 0

1010000x

( A0h )

SO-DIMM 1

1010001x

( A4h )

CPU Thermal IC(G780)

1001100x

( 98h )

VGA Thermal IC(G781-1)

1001101x

( 9Ah )

VGA Thermal Sensor(NB9E-GE1)

1001111x

( 9Eh )

VID Controller ASM8272

0011011x

( 36h )

DSP FM2010
PCIE 1

Minicard TV Tuner

USB 0

USB Port (1)

PCIE 2

Minicard WLAN

USB 1

USB Port (2)

PCIE 3

Newcard

USB 2

USB Port (3)

PCIE 4

N/A

USB 3

USB Port (4)

PCIE 5

PCIE to SATA (SR)

USB 4

CMOS Camera

PCIE 6

GLAN

USB 5

Newcard

PCIE 7

N/A

USB 6

Minicard TV Tuner

PCIE 8

N/A

USB 7

N/A

SATA0

SATA HDD(1)

USB 8

OLED

SATA1

SATA ODD

USB 9

WLAN

SATA2

N/A

SATA3

N/A

SATA4

SATA HDD(2)

SATA5

eSATA

USB 10

N/A

USB 11

USB Port (5)

USB 12

Bluetooth

USB 13

Finger Print

Title : System Setting


Engineer:

BU2/RD1
Size
C
Date:

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

+VTT_CPU

U0301A

<22>
<22>
<22>
<22>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

D25
F24
E23
G23

F17
E17

FDI_INT

C17

FDI_LSYNC0
FDI_LSYNC1

F18
D17

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]

For Intel GFX display

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

2 49.9Ohm

2 750OHM
PCIENB_RXN[15:0]

+1.5V

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PCIENB_RXN0
PCIENB_RXN1
PCIENB_RXN2
PCIENB_RXN3
PCIENB_RXN4
PCIENB_RXN5
PCIENB_RXN6
PCIENB_RXN7
PCIENB_RXN8
PCIENB_RXN9
PCIENB_RXN10
PCIENB_RXN11
PCIENB_RXN12
PCIENB_RXN13
PCIENB_RXN14
PCIENB_RXN15

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PCIENB_RXP0
PCIENB_RXP1
PCIENB_RXP2
PCIENB_RXP3
PCIENB_RXP4
PCIENB_RXP5
PCIENB_RXP6
PCIENB_RXP7
PCIENB_RXP8
PCIENB_RXP9
PCIENB_RXP10
PCIENB_RXP11
PCIENB_RXP12
PCIENB_RXP13
PCIENB_RXP14
PCIENB_RXP15

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PCIENB_TXN0
PCIENB_TXN1
PCIENB_TXN2
PCIENB_TXN3
PCIENB_TXN4
PCIENB_TXN5
PCIENB_TXN6
PCIENB_TXN7
PCIENB_TXN8
PCIENB_TXN9
PCIENB_TXN10
PCIENB_TXN11
PCIENB_TXN12
PCIENB_TXN13
PCIENB_TXN14
PCIENB_TXN15

CX0301
CX0302
CX0303
CX0304
CX0305
CX0306
CX0307
CX0308
CX0309
CX0310
CX0311
CX0312
CX0313
CX0314
CX0315
CX0316

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V

PCIEG_RXN0
PCIEG_RXN1
PCIEG_RXN2
PCIEG_RXN3
PCIEG_RXN4
PCIEG_RXN5
PCIEG_RXN6
PCIEG_RXN7
PCIEG_RXN8
PCIEG_RXN9
PCIEG_RXN10
PCIEG_RXN11
PCIEG_RXN12
PCIEG_RXN13
PCIEG_RXN14
PCIEG_RXN15

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PCIENB_TXP0
PCIENB_TXP1
PCIENB_TXP2
PCIENB_TXP3
PCIENB_TXP4
PCIENB_TXP5
PCIENB_TXP6
PCIENB_TXP7
PCIENB_TXP8
PCIENB_TXP9
PCIENB_TXP10
PCIENB_TXP11
PCIENB_TXP12
PCIENB_TXP13
PCIENB_TXP14
PCIENB_TXP15

CX0317
CX0318
CX0319
CX0320
CX0321
CX0322
CX0323
CX0324
CX0325
CX0326
CX0327
CX0328
CX0329
CX0330
CX0331
CX0332

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V

PCIEG_RXP0
PCIEG_RXP1
PCIEG_RXP2
PCIEG_RXP3
PCIEG_RXP4
PCIEG_RXP5
PCIEG_RXP6
PCIEG_RXP7
PCIEG_RXP8
PCIEG_RXP9
PCIEG_RXP10
PCIEG_RXP11
PCIEG_RXP12
PCIEG_RXP13
PCIEG_RXP14
PCIEG_RXP15

U0301B

PCIENB_RXP[15:0]

<70>

20Ohm

1%

1 R0303

H_COMP3

AT23

20Ohm

1%

1 R0304

H_COMP2

AT24

49.9Ohm

1%

1 R0305

H_COMP1

G16

49.9Ohm

1%

1 R0306

H_COMP0

AT26

1TP_SKTOCC#

T0301
49.9Ohm 2
H_CATERR#

+VTT_CPU

1%

AH24

COMP3
COMP2
COMP1
COMP0
SKTOCC#

1 R0307
AK14

<25,30>

PCIEG_RXN[15:0]

2 R0317 1
H_PECI_ISO
0Ohm @
AT15
2
1
H_PECI
0402
SL305
R0322
2
1
+VTT_CPU
68Ohm
H_PROCHOT_S#_R AN26
H_PROCHOT_S# 2
1
0402
SL306

CATERR#

THRO_CPU

<70>

<25,32> H_THRMTRIP#

<7>

0402

H_THRMTRIP#_R
SL307

AK15

AP26

H_CPURST#
2

<22> PM_SYNC#

<70> <7,25> H_CPUPWRGD

<22> H_DRAM_PWRGD

PM_SYNC#_R
SL308

AL15

0402

1VCCPWRGOOD_1_R
SL309

AN14

0402

1VCCPWRGOOD_0_R
SL310

AN27

0402

1VDDPWRGOOD_R
SL311

AK13

0402

PCIEG_RXP[15:0]

<92> H_VTTPWRGD

AM15

<7> H_PWRGD_XDP

AM26

<7,24,30,32,33,38,40,43,53,64,70>

BUF_PLT_RST#

PLT_RST#_R

2
R0318
1.5KOHM

AL14

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD

BCLK
BCLK#

PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]

CLK selection

AR30 CLK_ITP_BCLK_R
AT30 CLK_ITP_BCLK#_R

2
2

TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

CLK_ITP_BCLK <7>
CLK_ITP_BCLK# <7>
120MHz from PCH.
IF NOT USED,
PULL-LOW FOR POWER SAVING.

A18 CLKDREF
A17 CLKDREF#
R0367 1
R0366 1

CFD
CFD

2 1KOhm
2 1KOhm

F6

M_DRAMRST#

AL1 SM_RCOMP0 R0331 1


AM1 SM_RCOMP1 R0332 1
AN1 SM_RCOMP2 R0333 1
AN15
AP15

1%
1%
1%

<16,17>

2 100Ohm
2 24.9Ohm
2 130Ohm
PM_EXTTS#0 <16,17>

PM_EXTTS#1

+VTT_CPU
RN0301A 2 10KOHM
RN0301B 4 10KOHM
AT28
PRDY#
AP27
PREQ#
TCK
TMS
TRST#

1
1 SL312
SL313

0402
0402

E16 CLK_EXP_P
D16 CLK_EXP_N

1
3
XDP_PRDY#
XDP_PREQ#

AN28
AP28
AT27

<7>
<7>

XDP_TCLK <7>
XDP_TMS <7>
XDP_TRST# <7>

AT29
AR27
AR29
AP29

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

AN25

H_DBR#_R

AJ22 XDP_OBS0_R
AK22 XDP_OBS1_R
AK24 XDP_OBS2_R
AJ24 XDP_OBS3_R
AJ25 XDP_OBS4_R
AH22 XDP_OBS5_R
AK23 XDP_OBS6_R
AH23 XDP_OBS7_R

R0336 1
RX03371
RX03381
RX03391
RX03401
RX03411
RX03421
RX03431
RX03441

2 0Ohm
2
2
2
2
2
2
2
2

@
@
@
@
@
@
@
@

0Ohm
0Ohm
0Ohm
0Ohm
0Ohm
0Ohm
0Ohm
0Ohm

XDP_DBRESET#

<7,22>

XDP_OBS[7:0]

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

<7>

RSTIN#

R0319
750OHM
2

+VTT_CPU
1
1 SL301
SL302

CLK_CPU_BCLK
CLK_CPU_BCLK#

2
2

0402
0402

1
1 SL303
SL304

H_PROCHOT_S#
@

CLK_EXP_P
CLK_EXP_N

H_CPURST#

R0313

1 68Ohm

XDP_TMS

R0345

2 51OHM

XDP_TDI_R

R0346

2 51OHM

XDP_PREQ#

R0347

2 51OHM

XDP_TCLK

R0348

2 51OHM

2
D0301

<30,90> PWRLIMIT#

1
RB751V-40
3

0402
0402

S 2

R1.2--2

XDP_TDI_R

Choose either one solution: -->Choose solution 2

FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON

FDI_FSYNC1

~15mW power saving.(DG R0.8 P.70)

FDI_LSYNC0

FDI_LSYNC1

3. Connected to GND:
VCCAXG,DPLL_REF_CLK,DPLL_REF_CLK#

1KOhm
1
SL316
1
SL317
1
SL318
1
1KOhm

0402
0402
0402

FDI_INT

2
R0364

XDP_TDO_M

THRO_CPU

R0350 1

1
SL314
2 0Ohm
CPU_XDP@

0402

XDP_TDI

<30>

<7>

XDP_TDO <7>
XDP_TRST#

R0351
R0320
1.1KOhm

VDDPWRGOOD_R

R0354
51OHM

0Ohm
XDP_TDI_M
XDP_TDO_R

2
R0363

+1.5V

FDI_FSYNC0

1. This pin should have an external pull-up of 1K Ohms


to 10K Ohms to a rail of 1.05/1.1V which is ON in S0-S3
2. Connect this pin through a voltage divider circuit;
recommend 4.75K Ohms pull-up to DDR3 Power Rail
(VDDQ) of +V1.5U and a 12K Ohms pull-down to
ground to convert to processors VTT level.

VCC_AXGSENSE,VSS_AXGSENSE
2. Pull-down to GND via 1K 5% resistor:

THRO_CPU

JTAG MAPPING

DRAMPWROK: (WW35 MoW)

FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7]

Q0301
H2N7002
11

FDI disable: (For discrete graphic)


1. NC:

2
2

R0352 1
2

2 0Ohm
CPU_XDP@
1
SL315

0402

3.01KOHM
R0321

4. Can be connected to GND directly:


2

BCLK_ITP
BCLK_ITP#

A16 CLK_CPU_BCLK
B16 CLK_CPU_BCLK#

SOCKET989

R1.2--1

<21> CLK_DMI_PCH
<21> CLK_DMI#_PCH

<6,16,57,69,83>

SKTOCC#:pulled to ground on processor.


may use to determine if CPU is present

SOCKET989

<25> BCLK_CPU_P_PCH
<25> BCLK_CPU_N_PCH

+1.5V

<70>

PWR MANAGEMENT

FDI_FSYNC0
FDI_FSYNC1

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

1%

THERMAL

D22
C21
D20
C18
G22
E20
F20
G19

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

Intel(R) FDI

E22
D21
D19
D18
G21
E19
F21
G18

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

1%

D24
G24
F23
H23

R0302

CLOCKS

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

R0301

EXP_RBIAS

DDR3
MISC

<22>
<22>
<22>
<22>

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

PEG_IRCOMP_R

JTAG & BPM

B24
D23
B23
A22

B26
A26
B27
A25

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

PCI EXPRESS -- GRAPHICS

<22>
<22>
<22>
<22>

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

MISC

A24
C23
B22
A21

DMI

<22> DMI_TXN0
<22> DMI_TXN1
<22> DMI_TXN2
<22> DMI_TXN3

+VTT_CPU <6,7,25,26,27,29,32,57,82>

DPLL_REF_CLK,DPLL_REF_CLK#
5. Connect to +V1.05S rail:

R1.4--1

WW14_2009_WOM

VCCFDIPLL

Title : CPU(1)_DMI,PEG,FDI,CLK,MISC
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

U0301C

U0301D

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

<16> M_A_DQ[63:0]

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

<16>
<16>
<16>

M_A_BS0
M_A_BS1
M_A_BS2

AC3
AB2
U7

<16>
<16>
<16>

M_A_CAS#
M_A_RAS#
M_A_WE#

AE1
AB3
AE9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

AA6
AA7
P7

M_CLK_DDR0 <16>
M_CLK_DDR#0 <16>
M_CKE0
<16>

Y6
Y5
P6

M_CLK_DDR1 <16>
M_CLK_DDR#1 <16>
M_CKE1
<16>

AE2
AE8

M_CS#0
M_CS#1

<16>
<16>

AD8
AF9

M_ODT0
M_ODT1

<16>
<16>

B9
D7
H7
M7
AG6
AM7
AN10
AN13

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

DDR SYSTEM MEMORY A

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

C9
F8
J9
N9
AH7
AK9
AP11
AT13

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

C8
F9
H9
M9
AH8
AK10
AN11
AR13

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

<17> M_B_DQ[63:0]

M_A_DM[7:0]

M_A_DQS#[7:0]

M_A_DQS[7:0]

M_A_A[15:0]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

<16>

<16>

<16>

<16>

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

<17>
<17>
<17>

M_B_BS0
M_B_BS1
M_B_BS2

AB1
W5
R7

<17>
<17>
<17>

M_B_CAS#
M_B_RAS#
M_B_WE#

AC5
Y7
AC6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#

SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

W8
W9
M3

M_CLK_DDR2 <17>
M_CLK_DDR#2 <17>
M_CKE2
<17>

V7
V6
M2

M_CLK_DDR3 <17>
M_CLK_DDR#3 <17>
M_CKE3
<17>

AB8
AD6

M_CS#2
M_CS#3

<17>
<17>

AC7
AD1

M_ODT2
M_ODT3

<17>
<17>

D4
E1
H3
K1
AH1
AL2
AR4
AT8

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DM[7:0]

<17>

DDR SYSTEM MEMORY - B

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

D5
F4
J4
L4
AH2
AL4
AR5
AR8

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

C5
E3
H4
M5
AG2
AL5
AP5
AR7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQS#[7:0]

M_B_DQS[7:0]

M_B_A[15:0]

<17>

<17>

<17>

SOCKET989

SOCKET989

Title : CPU(2)_DDR3
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

U0301H
RSVD32
RSVD33

<18> DIMM0_VREF_DQ
<18> DIMM1_VREF_DQ

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
10mil trace
J17
10mil trace H17
G25
G17
E31
E30

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39

RSVD40
RSVD41

T0578
T0567
T0566
T0565
T0569
T0568
T0571
T0572
T0574
T0570
T0575
T0573
T0576
T0577
T0592
T0581
T0580
T0579
T0583

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

B19
A19
SL0500
SL501

2
2

0402
0402

1H_RSVD17_R
1H_RSVD18_R

R2.0--1

A20
B20
U9
T9
AC9
AB9

T0513
T0510

1
1

C1
A3

J29
J28

T0511
T0512

1
1

A34
A33

T0514
T0515

1
1

C35
B35

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]

RESERVED

RSVD42
RSVD43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
RSVD59
RSVD60
RSVD61
RSVD62
RSVD63
RSVD64
RSVD65

AJ13
AJ12
AH25
AK26
AL26
AR2

T0504

AP1
AT2

1
1

T0501
T0506

AT3
AR1

1
1

T0507
T0503

1
1
1
1

T0508
T0509
T0502
T0505

AJ26
AJ27

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15 RSVD64_R SL502
AH15 RSVD65_R SL503

RSVD17
RSVD18

RSVD21
RSVD22

RSVD23
RSVD24

RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31

2
2

0402
0402

1
1

R2.0--1

RSVD15
RSVD16

RSVD19
RSVD20

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

RSVD66
RSVD67
RSVD68
RSVD69
RSVD70
RSVD71
RSVD72
RSVD73
RSVD74
RSVD75
RSVD76
RSVD77
RSVD78
RSVD79
RSVD80
RSVD81
RSVD82
RSVD83
RSVD84
RSVD85
RSVD86

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

U0301I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

NCTF

U0301E

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35 TP_MCP_VSS_NCTF1
AT1 TP_MCP_VSS_NCTF2
AR34
B34
B2
TP_MCP_VSS_NCTF6
B1
A35 TP_MCP_VSS_NCTF7

1
1

T0564
T0561

1
1

T0563
T0562

SOCKET989
SOCKET989

SOCKET989

CFG strapping information:

CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only)


- 11 = 1 x 16 PEG (Default)
- 10 = 2 x 8 PEG
CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only)
- 1:Normal Operation (Default)
- 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG[4]: Embedded DisplayPort Detection.(Auburndale Only)
- 1:Disabled - No Physical Display Port attached to Embedded DisplayPort
- 0:Enabled - An external Display Port device is connected to the Embedded Display Port
CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfield)
Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistor
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not impact AUB functionality.
Unmount if Intel has fixed this issue.

@
CFG0

R0535

1 3.01KOHM

2
1%
@

CFG3

R0536

1 3.01KOHM

2
1%
@

CFG4

R0537

1 3.01KOHM

1%
@
CFG7

Note: (Auburndale)Hardware Straps are sampled on


the asserting edge of VCCPWRGOOD_0 and
VCCPWRGOOD_1 and latched inside the processor.

R0538

1 3.01KOHM

2
1%

Note: (Clarksfield)Hardware Straps are sampled


after RSTIN# de-assertion.

Title : CPU(3)_CFG,RSVD,GND
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

+VTT_CPU

U0301F

+VTT_CPU <3,7,25,26,27,29,32,57,82>

+1.5V
+VCORE
+VCORE

+1.8VS

+VTT_CPU

R0602
100Ohm
1%

2
330UF/2V

22UF/6.3V 2

22UF/6.3V 2

C0627
10UF/6.3V

10UF/6.3V

+VTT_CPU
C0626

C0659
1

VTT63
VTT64
VTT65
VTT66
VTT67
VTT68

J22
J20
J18
H21
H20
H19

1
C0664
22UF/6.3V

C0658
1

22UF/6.3V 2

+VTT_CPU

Intel use 22u


VCCPLL1
VCCPLL2
VCCPLL3

L26
L27
M26

+1.8VS

2
1UF/10V
2
1UF/10V
2
2.2UF/10V
2
4.7UF/6.3V
2
22UF/6.3V

Intel 1.8V CAP.


1u: 2/2
2.2u: 1/1
4.7u: 1/1
330u:1/1
B

1
C0638
22UF/6.3V

1
C0645
22UF/6.3V

1
C0644
22UF/6.3V

1
2

1
C0643
22UF/6.3V

C0647
22UF/6.3V

1
C0675
10UF/6.3V

C0676
10UF/6.3V

1
C0683
10UF/6.3V

1
C0682
10UF/6.3V

C0681
10UF/6.3V

1
C0680
10UF/6.3V

1
2

C0679
10UF/6.3V

1
C0674
10UF/6.3V

1
C0673
10UF/6.3V

1
C0672
10UF/6.3V

1
2

C0671
10UF/6.3V

1
2

1
2

1
2

C0678
10UF/6.3V

C0639
22UF/6.3V

C0677
10UF/6.3V

1
2

1
2

C0637
22UF/6.3V

1
2

1
C0670
10UF/6.3V

1
2

C0669
10UF/6.3V

C0642
22UF/6.3V

C0636
22UF/6.3V

1
C0641
22UF/6.3V

1
C0640
22UF/6.3V

1
2

SOCKET989

C0635
22UF/6.3V

1
C0634
22UF/6.3V

1
C0633
22UF/6.3V

1
C0632
22UF/6.3V

C0684
10UF/6.3V

Title : CPU(4)_PWR
C
Date:

Engineer:

BU2/RD1

Size

CE0604
1

C0686
1

C0685
1

1
C0621
1
C0622
1
C0623
1
C0624
1
C0625
2
1UF/10V
2
1UF/10V
2
1UF/10V
2
1UF/10V
2
1UF/10V

P10
N10
L10
K10

R0603
100Ohm
1%

T0632
T0631

1
1

+VCORE

VTT_SENSE
B15
A15 TP_VSS_SENSE_VTT

VCORE 22uF * 16pcs


10uF * 16pcs
470uF * 6pcs (2 no stuff)

VCCSENSE <80>
VSSSENSE <80>

VTT_SENSE
VSS_SENSE_VTT

Decoupling guide from Intel

VCCSENSE
VSSSENSE

2 4.7KOhm

DG R0.8,P367
1xbuck Stuffing option

SOCKET989

2
AJ34
AJ35

<30>

R0606 1

C0657
1

22UF/6.3V 2

VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58

Intel use 22u

<80>

GFX_VR

2
1
C0665
22UF/6.3V

1.1V

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

1.8V

C0656
1

22UF/6.3V 2

<80>

<82>

VCC_SENSE
VSS_SENSE

I_MON

20Ohm

+1.5V

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

+VCORE

AN35

@
0402

PANASONIC/EEFSX0D331XE
ESR=6mOhm/Ir=3A

SENSE
LINES

GRAPHICS VIDs

R0617 1
AR25 GFX_VRON_EN
AT25 GFXVR_DPRSLPVR_RSL0600 2
AM24
R2.0--1

VTT_TEST TBD

ISENSE

2 4.7KOhm
CFD

C0655
1

C0654
1

R0605 1

1
C0628
1
C0629
1
C0667
1
C0668
1
C0666

1
C0618
2
22UF/6.3V

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

22UF/6.3V 2

22UF/6.3V 2

Intel use 22u

R2.0--1

H_VTTVID1

AM22
AP22
AN22
AP23
AM23
AP24
AN24

1 R0613 2
1KOhm CFD

VTT59
VTT60
VTT61
VTT62

<19>

PM_DPRSLPVR

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

AR22
AT22

+VTT_CPU

<80>

CPU_VID[0:6]

22UF/6.3V 2

POWER

CPU VIDS

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
PM_DPRSLPVR_R

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

PEG & DMI

G15

PM_PSI#

VTT45
VTT46
VTT47

FDI

R1.4--5

AN33

J24
J23
H25

VCCAXG_SENSE
VSSAXG_SENSE

- 1.5V RAILS

C0617
1
22UF/6.3V
2

+VTT_CPU

R2.0--1

VTT_SELECT

VCCAXG1
VCCAXG2
VCCAXG3
VCCAXG4
VCCAXG5
VCCAXG6
VCCAXG7
VCCAXG8
VCCAXG9
VCCAXG10
VCCAXG11
VCCAXG12
VCCAXG13
VCCAXG14
VCCAXG15
VCCAXG16
VCCAXG17
VCCAXG18
VCCAXG19
VCCAXG20
VCCAXG21
VCCAXG22
VCCAXG23
VCCAXG24
VCCAXG25
VCCAXG26
VCCAXG27
VCCAXG28
VCCAXG29
VCCAXG30
VCCAXG31
VCCAXG32
VCCAXG33
VCCAXG34
VCCAXG35
VCCAXG36

DDR3

0Ohm
1
C0687
1
C0688
1
C0689

DG R0.8,P368

Intel use 22u

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

<26,38,57,70,85>

+VGFX_CORE

POWER

CFD

R0607
1

+VTT_CPU

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

<57,69,80>

+1.8VS

1
C0601
1
C0602
1
C0604
1
C0606
1
C0608
1
C0611
1
C0613
1
C0615
1
C0616
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V
@

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

+VTT_CPU

PSI#

<3,16,57,69,83>

+VCORE

U0301G

2
10UF/6.3V
2
10UF/6.3V
2
10UF/6.3V

1.1V RAIL POWER

+VGFX_CORE

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

+1.5V

GRAPHICS

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44

CPU CORE SUPPLY

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

SENSE LINES

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

+VTT_CPU

+VTT_CPU <3,6,25,26,27,29,32,57,82>

J0701

<3>
<3>

XDP_OBS0
XDP_OBS1

<3>
<3>

XDP_OBS2
XDP_OBS3
T0715
T0714

<3>
<3>

XDP_OBS4
XDP_OBS5

<3>
<3>

XDP_OBS6
XDP_OBS7

<3,25> H_CPUPWRGD
<22> PM_PWRBTN#_R
+VTT_CPU
<3> H_PWRGD_XDP
<16,17,28,29,38,44,53,69>
<16,17,28,29,38,44,53,69>
<3>

1
1

XDP_OBS21
XDP_OBS20

2 1KOhm 1 R0708 CPUPWRGD_XDP


2 0Ohm 1 R0714 PM_PWRBTN#_XDP
@
2 @0Ohm 1 R0709 PCIE_CLK_XDP_P
PCIE_CLK_XDP_N
1
@ T0701
SMB_DAT_S
SMB_CLK_S
XDP_TCLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
NP_NC1
NP_NC2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

XDP_OBS16
XDP_OBS17

1
1

T0710
T0711

XDP_OBS8
XDP_OBS9

1
1

T0702
T0703

XDP_OBS10
XDP_OBS11

1
1

T0704
T0705

XDP_OBS18
XDP_OBS19

+VTT_CPU
1
1

T0712
T0713

XDP_OBS12
XDP_OBS13

1
1

T0706
T0707

XDP_OBS14
XDP_OBS15

1
1

T0708
T0709

CLK_ITP_BCLK_XDP
CLK_ITP_BCLK#_XDP
XDP_RST#_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61

R0710 1
R0712 1

0Ohm 2
0Ohm 2
@
R0707 1 @ 1KOhm2

R0711
51Ohm

CLK_ITP_BCLK <3>
CLK_ITP_BCLK# <3>
1

<3> XDP_PREQ#
<3> XDP_PRDY#

H_CPURST#

<3>
XDP_DBRESET#

<3,22>

XDP_TDO <3>
XDP_TRST# <3>
XDP_TDI <3>
XDP_TMS <3>

62

BtoB_CON_60P
@
XDP_RST#_R

R0715 1 0Ohm

BUF_PLT_RST#

<3,24,30,32,33,38,40,43,53,64,70>

CPU_XDP@

CPU XDP connector

Title : CPU(5)_XDP
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

Title : NB(1)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

Title : NB(2)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

of

99

Title : NB(3)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

10

of

99

Title : NB(4)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

11

of

99

Title : NB(5)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

12

of

99

Title : NB(6)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

13

of

99

Title : NB(7)_****
Engineer:

BU2/RD1
Size

Project Name

Date: Friday, July 31, 2009


4

Rev

G60J

A
5

Kenny Wu

1.4
Sheet

14
1

of

99

Title : NB(8)_****
Engineer:

BU2/RD1
Size

Project Name

Date: Friday, July 31, 2009


4

Rev

G60J

A
5

Kenny Wu

1.4
Sheet

15
1

of

99

+1.5V

+1.5V

+1.5V_DDR3

<3,6,57,69,83>

+1.5V_DDR3

+0.75VS
+3VS

<17,18>

+0.75VS

<17,57,83>

+3VS

<29,48,80,91,92>

M_VREFCA_DIMM0

M_VREFCA_DIMM0

<18>

M_VREFDQ_DIMM0

M_VREFDQ_DIMM0

<18>

M_A_DQ[63:0]

2 R1605 1
10KOhm
2 R1606 1
10KOhm

SMBus Slave Address: A0H


<7,17,28,29,38,44,53,69>
<7,17,28,29,38,44,53,69>

ODT0
ODT1
RAS#
RESET#

114
121

S#0
S#1

197
201

SA0
SA1

202
200

SCL
SDA

125

C1606
0.1UF/10V

Layout Note: Place these caps near SO DIMM 0


C1605
0.1UF/10V

C1607
0.1UF/10V

C1608
0.1UF/10V

+3VS

@
C1614
2.2UF/10V

TEST

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

+1.5V_DDR3

C1615
0.1UF/10V

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

199

M_VREFCA_DIMM0

VDDSPD

126
1

R2.0--1

DDR3_DIMM_204P

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

@
C1624
2.2UF/10V

VTT1
VTT2

VREFCA
VREFDQ
WE#

C1623
0.1UF/10V

203
204

+0.75VS

113

M_A_WE#

<4>

DDR3_DIMM_204P

R2.0--1
M_VREFDQ_DIMM0

H:5.2mm

@
C1622
2.2UF/10V

SMB_CLK_S
SMB_DAT_S

NP_NC1
NP_NC2

6
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

M_CS#0
M_CS#1

<4>
<4>

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

<4>
M_A_RAS#
<3,17> M_DRAMRST#

110
30

10
27
45
62
135
152
169
186

116
120

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_ODT0
M_ODT1

<4>
<4>

12
29
47
64
137
154
171
188

NC1
NC2

205
206

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

CAS#
CK#0
CK#1
CK0
CK1
CKE0
CKE1

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

GND1
GND2

77
122

<4> M_A_DQS#[7:0]

11
28
46
63
136
153
170
187

EVENT#

207
208

<4> M_A_DQS[7:0]

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

BA0
BA1
BA2

198

<4> M_A_DM[7:0]

0Ohm @

PLACE CLOSE TO SODIMM

115
103
104
101
102
73
74

<4>
M_A_CAS#
<4> M_CLK_DDR#0
<4> M_CLK_DDR#1
<4> M_CLK_DDR0
<4> M_CLK_DDR1
<4>
M_CKE0
<4>
M_CKE1

R1602
2

<3,17> PM_EXTTS#0

1%
R1604
150Ohm
@

109
108
79

M_A_BS0
M_A_BS1
M_A_BS2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

C1626
10PF/50V
@

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

M_A_DQ5
M_A_DQ1
M_A_DQ7
M_A_DQ6
M_A_DQ0
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ9
M_A_DQ13
M_A_DQ11
M_A_DQ14
M_A_DQ12
M_A_DQ8
M_A_DQ10
M_A_DQ15
M_A_DQ21
M_A_DQ20
M_A_DQ18
M_A_DQ22
M_A_DQ16
M_A_DQ17
M_A_DQ23
M_A_DQ19
M_A_DQ24
M_A_DQ25
M_A_DQ30
M_A_DQ31
M_A_DQ28
M_A_DQ29
M_A_DQ26
M_A_DQ27
M_A_DQ36
M_A_DQ33
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ32
M_A_DQ35
M_A_DQ34
M_A_DQ41
M_A_DQ44
M_A_DQ45
M_A_DQ47
M_A_DQ40
M_A_DQ43
M_A_DQ42
M_A_DQ46
M_A_DQ49
M_A_DQ53
M_A_DQ54
M_A_DQ51
M_A_DQ52
M_A_DQ48
M_A_DQ55
M_A_DQ50
M_A_DQ56
M_A_DQ57
M_A_DQ63
M_A_DQ58
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ62

<4>
<4>
<4>

M_CLK_DDR#1

M_CLK_DDR1

J1601B
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

C1621
10PF/50V
@

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

1%
R1603
150Ohm
@

M_CLK_DDR#0

M_CLK_DDR0

<4>

J1601A

<4> M_A_A[15:0]

C1625
0.1UF/10V

R2.0--1
+1.5V

+1.5V_DDR3
+0.75VS
+1.5V_DDR3

@
C1618
1UF/6.3V

@
C1617
1UF/6.3V

C1616
1UF/6.3V

220UF/4V
@
ESR=40mOhm/Ir=1.9A

CE1603

JP1601
3MM_OPEN_5MIL
1
2
1 2

C1619
1UF/6.3V

R2.0--1
+1.5V_DDR3

1
C1613
10UF/6.3V

@
C1612
10UF/6.3V

@
C1611
10UF/6.3V

@
C1610
10UF/6.3V

@
C1609
10UF/6.3V

Layout Note: Place these caps near SO DIMM 0

C1620
10UF/6.3V

R2.0--1
A

Title : DDR3(1)_SO-DIMM0
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

16

of

99

+1.5V

+1.5V

+1.5V_DDR3

<3,6,16,57,69,83>

+1.5V_DDR3

+0.75VS
+3VS

<16,18>

+0.75VS

<16,57,83>

+3VS

<29,48,80,91,92>

M_VREFCA_DIMM1

M_VREFCA_DIMM1

<18>

M_VREFDQ_DIMM1

M_VREFDQ_DIMM1

<18>

J1701B
M_B_DQ[63:0]

RX1704
2

<4>
<3,16> PM_EXTTS#0

198

EVENT#

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

0Ohm @
J1701A

SMB_CLK_S
SMB_DAT_S

197
201
202
200
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

+1.5V_DDR3

C1706
0.1UF/10V

1
C1707
0.1UF/10V

C1705
0.1UF/10V

Layout Note: Place these caps near SO DIMM 1


C1708
0.1UF/10V

+3VS

@
C1714
2.2UF/10V

C1715
0.1UF/10V

199

M_VREFCA_DIMM1

126
1

R2.0--1

NP_NC1
NP_NC2
ODT0
ODT1
RAS#
RESET#
S#0
S#1
SA0
SA1
SCL
SDA
TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

VTT1
VTT2

VREFCA
VREFDQ
WE#

@
C1724
2.2UF/10V

VDDSPD

C1723
0.1UF/10V

203
204

+0.75VS

113

M_B_WE#

<4>

DDR3_DIMM_204P

R2.0--1
M_VREFDQ_DIMM1
B

<7,16,28,29,38,44,53,69>
<7,16,28,29,38,44,53,69>

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

+3VS

114
121

NC1
NC2

DDR3_DIMM_204P

H:9.2mm

@
C1722
2.2UF/10V

+0.75VS
C1725
0.1UF/10V

+1.5V_DDR3

1
C1718
1UF/6.3V

@
C1717
1UF/6.3V

@
C1716
1UF/6.3V

R2.0--1

10
27
45
62
135
152
169
186

2
1
R1705 10KOhm
2
1
R1706 10KOhm

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

M_CS#2
M_CS#3

SMBus Slave Address: A4H

12
29
47
64
137
154
171
188

<4>
M_B_RAS#
<3,16> M_DRAMRST#

110
30

<4>
<4>

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

116
120

<4> M_B_DQS#[7:0]

11
28
46
63
136
153
170
187

M_ODT2
M_ODT3

<4>
<4>

<4> M_B_DQS[7:0]

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

CAS#
CK#0
CK#1
CK0
CK1
CKE0
CKE1

205
206

<4> M_B_DM[7:0]

77
122

GND1
GND2

PLACE CLOSE TO SODIMM

BA0
BA1
BA2

115
103
104
101
102
73
74

<4>
M_B_CAS#
<4> M_CLK_DDR#2
<4> M_CLK_DDR#3
<4> M_CLK_DDR2
<4> M_CLK_DDR3
<4>
M_CKE2
<4>
M_CKE3

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

1%
R1708
150Ohm
@

109
108
79

M_B_BS0
M_B_BS1
M_B_BS2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

C1721
10PF/50V
@

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

<4>
<4>
<4>

M_CLK_DDR3

M_CLK_DDR#3

1%
R1707
150Ohm
@

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

207
208

C1720
10PF/50V
@
2

M_CLK_DDR#2

M_CLK_DDR2

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQ1
M_B_DQ0
M_B_DQ7
M_B_DQ6
M_B_DQ4
M_B_DQ5
M_B_DQ2
M_B_DQ3
M_B_DQ12
M_B_DQ9
M_B_DQ15
M_B_DQ13
M_B_DQ8
M_B_DQ10
M_B_DQ11
M_B_DQ14
M_B_DQ16
M_B_DQ21
M_B_DQ19
M_B_DQ23
M_B_DQ20
M_B_DQ17
M_B_DQ22
M_B_DQ18
M_B_DQ29
M_B_DQ24
M_B_DQ26
M_B_DQ31
M_B_DQ28
M_B_DQ25
M_B_DQ27
M_B_DQ30
M_B_DQ33
M_B_DQ37
M_B_DQ35
M_B_DQ38
M_B_DQ36
M_B_DQ32
M_B_DQ39
M_B_DQ34
M_B_DQ41
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ45
M_B_DQ40
M_B_DQ47
M_B_DQ46
M_B_DQ48
M_B_DQ50
M_B_DQ54
M_B_DQ55
M_B_DQ52
M_B_DQ53
M_B_DQ51
M_B_DQ49
M_B_DQ57
M_B_DQ60
M_B_DQ63
M_B_DQ62
M_B_DQ58
M_B_DQ56
M_B_DQ59
M_B_DQ61

<4> M_B_A[15:0]

C1719
1UF/6.3V

R2.0--1

1
2

CE1703
220UF/4V
@
ESR=40mOhm/Ir=1.9A

+1.5V_DDR3

R2.0--1

@
C1713
10UF/6.3V

1
C1712
10UF/6.3V

@
C1711
10UF/6.3V

@
C1710
10UF/6.3V

1
C1709
10UF/6.3V

Layout Note: Place these caps near SO DIMM 1

@
C1726
10UF/6.3V

R2.0--1

Title : DDR3(2)_SO-DIMM1
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

17

of

99

+1.5V_DDR3

DDR3 Vref

<16,17>

M_VREFCA_DIMM0

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

M_VREFDQ_DIMM0

<16>

M_VREFCA_DIMM1

M_VREFCA_DIMM1

<17>

M_VREFDQ_DIMM1

M_VREFDQ_DIMM1

<17>

+3V

Intel Document Number: 400755


Calpella Clarksfield DDR3 SO-DIMM VREFDQ
Platform Design Guide Change Details

+1.5V_DDR3

+5VSUS
+5VA

<16>

+3V

<24,33,43,45,57,61,64,69,91>

+5VSUS

<27,56,81,91>

+5VA

<31,56,81,82,83>

Default

M1
M_VREF
<83>

R1809

M_VREF

R2.0--1

M_VREF_DDR3
2 0Ohm

M_VREFCA_DIMM1

R0402

SP1801 1

M1: Fixed SO-DIMM VREF_DQ (Default Stuffing)


*Option:

M_VREFCA_DIMM0

SP1800 1

R0402
For DDR3_VREF command
& address.

Mount=R1801,R1802,R1803,R1804,R1809
Unmount=R1805,R1806,R1807,R1808,C1801

R1802,R1803 are always mount.

+1.5V_DDR3
2

M_VREFDQ_DIMM1
SP1802 1

SP1803 1

2
R0402

C1801
0.1UF/10V
@

2
R0402

1
2

R1808
1KOHM
C

<5> DIMM0_VREF_DQ

M_VREFDQ_DIMM0

R2.0--1
R1807
1KOHM

<5> DIMM1_VREF_DQ

M2

R1805

2 0Ohm

R1806

2 0Ohm

M3

M2: Programmable SO-DIMM VREFDQ on


motherboard New Requirement

M3: Processor Generated SO-DIMM VREFDQ


New Requirement

*Option:

Option:

Mount=R1801,R1802,R1803,R1804,R1807,R1808,C1801
Unmount=R1805,R1806,R1809
*Range from 600 to 900 mV

Mount=R1802,R1803,R1805,R1806
Unmount=R1801,R1804,R1809,R1807,R1808,C1801

*Default startup value needs to adhere to JEDEC spec.


(power sequencing and +/-1% of Vdd/2)
Note: Use voltage divider instead of I2C solution.

R1.4--1

Title : DDR3(3)_CA/DQ Voltage


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

18

of

99

SMB_CLK_S3
SMB_DAT_S3

Block Diagram

SB

CPU_VID0~6

VR_ID0~6

CPU

ASM8272

OC

Voltage Regulator

UC

CLK Gen.
OC/UC pin Internal Pull Down

Reserved 0 ohm
R to bypass
C

+VTT_CPU
+3VS

<6>
<6>
<6>
<6>
<6>
<6>
<6>

CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

2
2
2
2
2
2
2

0402
0402
0402
0402
0402
0402
0402

1
1
1
1
1
1
1

SL1900
SL1901
SL1902
SL1903
SL1904
SL1905
SL1906

VR_VID6
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0

VR_VID6
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0

+VTT_CPU <3,6,7,25,26,27,29,32,57,82>
+3VS

<29,48,80,91,92>

<80>
<80>
<80>
<80>
<80>
<80>
<80>

R1.4--2

Title : VID Controller


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

19

of

99

RTC battery
+RTCBAT

+3VA

+VCC_RTC
D2001

R2001
1KOhm

4
2
1
3

+1.05VS
3

+RTC_BAT

C2003
1UF/10V

BAT54C

+3VM_SPI

JRST2001

Clear CMOS

Shunt
Open
(Default)

Keep CMOS

JRST2001
SGL_JUMP

2
GND

C2001
18PF/50V

X2001
32.768Khz

R2002
10MOhm

3
C2002
18PF/50V
2
1

X1_RTC
X2_RTC

<36>

GND

C14

SRTCRST#

D17

SM_INTRUDER#

A16

2
1KOhm

A30

ACZ_SYNC

D29
P1

SB_SPKR

HDA_SYNC: Select VCCVRM 1.5V or 1.8V

JRST2002

G30

<36> ACZ_SDIN0_AUD

+3VS

Shunt

T2007

ACZ_SDIN1_MDC

F30
E32

<70> ACZ_SDIN2_VGA

FWH4/LFRAME#
SRTCRST#
INTRUDER#
INTVRMEN

F32
R2030
10KOhm
@

ACZ_SDOUT

T2001

B29

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

HDA_SYNC
SPKR
HDA_RST#

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

HDA_SDO

33OHM
33OHM
33OHM
33OHM

2
4
6
8

RNX2000A
RNX2000B
RNX2000C
RNX2000D

ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT

1
T2002

H32

DGPU_PWR_EN_R

J30

PCH_JTAG_TCK_BUF

M3

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO13

Q2001
1

<30> PCH_SPI_OV

RNX2001A
RNX2001B
RNX2001C
RNX2001D

2 S

2N7002ET1G

GND

R2.0--1

1
T2003
1
T2004
1
T2008
1
T2009
1
T2010

K3
K1
J2
J4

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_RST#

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

JTAG

2
4
6
8

SATAICOMPO
SATAICOMPI

D33
B33
C32
A32

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

C34
A34
F34

<30,44>
<30,44>
<30,44>
<30,44>

LPC_FRAME#
PCH_DRQ#0
LPC_DRQ#1

1
1

<30,44>

T2005
T2006

AB9

INT_SERIRQ

AK7
AK6
AK11
AK9

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

<51>
<51>
<51>
<51>

HDD1

AH6
AH5
AH9
AH8

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

<51>
<51>
<51>
<51>

ODD

<30>

AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1

EDS 1.0: SATA port2,port3 may not be available in all PCH SKUs.

AD9
AD8
AD6
AD5

SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4

<51>
<51>
<51>
<51>

HDD2

AD3
AD1
AB3
AB1

SATA_RXN5
SATA_RXP5
SATA_TXN5
SATA_TXP5

<66>
<66>
<66>
<66>

ESATA

SATA_LED#

<56>

+VTT_PCH_VCCIO

AF16
SATA_COMP

AF15

1 37.4Ohm 2 1%
R2007
+3VS

<28>
B

SB_SPICLK

SPI_CLK
SPI_CS#0

15Ohm

2 RN2003A

SB_SPICS0#

AV3

<28>

SPI_CS#1

15Ohm

4 RN2003B

SB_SPICS1#

AY3

R2.0--1
<28>

SPI_SI
<28>

+3VM_SPI

BA2

<28>

2
R2015

SPI_MOSI

AY1
AV1

SPI_SO

1
1KOhm

SPI_CLK

1 10KOhm 2
R2025

SPI_CS0#
SPI_CS1#

SATALED#

SPI_MOSI

SATA0GP/GPIO21

SPI_MISO

SPI

1
3
5
7

<70> ACZ_BCLK_VGA
<70> ACZ_SYNC_VGA
<70> ACZ_RST#_VGA
<70> ACZ_SDOUT_VGA

33OHM
33OHM
33OHM
33OHM

SATA

HDA_DOCK_EN#

1
1
3
5
7

<36> ACZ_BCLK_AUD
<36> ACZ_SYNC_AUD
<36,37> ACZ_RST#_AUD
<36> ACZ_SDOUT_AUD

LDRQ0#
LDRQ1#/GPIO23

HDA_BCLK

Open
(Default)

C30

RTCRST#

Clear ME RTC
Registers
Keep ME RTC
Registers

A14

ACZ_BCLK

ACZ_RST#

TPM Settings

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LPC

1
1
2

1
C

1
R2020

RTCRST#

1 330KOhm

@
+3VS

GND

R2006

+VCC_RTC

JRST2002
SGL_JUMP

C2005
1UF/10V

RTCX1
RTCX2

GND

R2005
1MOhm

B13
D13

RTC

GND

U2001A
2

1
2

CMOS Settings

C2004
1UF/10V

R2004
20KOhm
1%
1

1
R2003
20KOhm
1%

GND

<26,27>

+3VM_SPI <28>

Request by CSC
for CMOS clear
function

RTCRST# RC delay
should be 18ms~25ms
2

<27>

+VTT_PCH_VCCIO

+VCC_RTC

GND

1217-001K000

<27>
<29,48,80,91,92>

+1.05VM_ORG

+VTT_PCH_VCCIO

GND
D

+3VS

+1.05VM_ORG

GND

<26,27,57,69,91>

+VCC_RTC

+3VS

IHDA

WtoB_CON_2P

+1.05VS

+VCC_RTC

SIDE2
2
1
SIDE1

1
1

J2001

SATA1GP/GPIO19

T3
Y9

SATA0GP

V1

SATA1GP

IBEXPEAK-M

R2.0
HDA_DOCK_EN#

1
R2029

+3VS

2
1KOhm

MoW_WW20_09'

INT_SERIRQ

1 10KOhm 2
R2026

SATA0GP

1 10KOhm 2
R2027

SATA1GP

1 10KOhm 2
R2028

GND

Strap information:

HDA_SPKR: No reboot strap


Low: Disable.
High:Enable

HDA_DOCK_EN#:
1.Flash descriptor security:
Sampled low: override
Sampled high: in effect.
2.GPIO33 low on the rising edge of PWROK,
Will also disable Intel ME.

SPI_MOSI: iTPM strap.


Mount R2015: Enable
Unmount R2015: Disable(default)

Title : PCH(1)_SATA,IHDA,RTC,LPC
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

20

of

99

PCIE5: PCIE-->CB

+3VSUS
+3VS
+VTT_PCH_ORG

PCIE_TXN2_WLAN
PCIE_TXP2_WLAN

<43> PCIE_RXN3_NEWCARD
<43> PCIE_RXP3_NEWCARD
<43> PCIE_TXN3_C
<43> PCIE_TXP3_C

0.1UF/10V 2
0.1UF/10V 2

1 CX2105
1 CX2106

PCIE_TXN3_NEWCARD
PCIE_TXP3_NEWCARD

AU30
AT30
AU32
AV32
BA32
BB32
BD32
BE32

R1.2--5

<40> PCIE_RXN5_CR
<40> PCIE_RXP5_CR
<40> PCIE_TXN5_C
<40> PCIE_TXP5_C

0.1UF/16V 2
0.1UF/16V 2

<33> PCIE_RXN6_GLAN
<33> PCIE_RXP6_GLAN
<33> PCIE_TXN6_C
<33> PCIE_TXP6_C

0.1UF/10V 2
0.1UF/10V 2

1 CX2115
1 CX2116

1 CX2111
1 CX2112

PCIE_TXN5_CR
PCIE_TXP5_CR

BF33
BH33
BG32
BJ32

PCIE_TXN6_GLAN
PCIE_TXP6_GLAN

BA34
AW34
BC34
BD34

EDS 1.0:
PCIE7,8 may not be availiable in all PCH SKUs.

AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36
AK48
AK47

T2101

CLK_REQ0#
CLK_PCH_SRC1_N
CLK_PCH_SRC1_P

<64> CLK_PCIE_TV#_PCH
<64> CLK_PCIE_TV_PCH

P9
AM43
AM45
U4

<64> CLKREQ1_TV#
CLK_PCH_SRC2_N
CLK_PCH_SRC2_P

<53> CLK_PCIE_WLAN#_PCH
<53> CLK_PCIE_WLAN_PCH

AM47
AM48
N4

<53> CLKREQ2_WLAN#
CLK_PCH_SRC3_N
CLK_PCH_SRC3_P

<43> CLK_PCIE_NEWCARD#_PCH
<43> CLK_PCIE_NEWCARD_PCH

AH42
AH41

<43,44> CLKREQ3_NEWCARD#

R1.2--5

CLK_PCH_SRC4_N
CLK_PCH_SRC4_P

<40> CLK_PCIE_CR#
<40> CLK_PCIE_CR
CLKREQ4_CR#

EXT_SCI# <30>

SCL_3A

SCL_3A

C8

SDA_3A

SDA_3A <28>

J14

SML0ALERT#

T2106

C6

SML0_CLK

T2107

G8

SML0_DAT

T2108

M14

SML1ALERT#

E10

SML1_CLK

SML1_CLK <28>

G12

SML1_DAT

SML1_DAT <28>

AM51
AM53

R1.4--2

M9
CLK_PCH_SRC5_N
CLK_PCH_SRC5_P

<33> CLK_PCIE_LAN#
<33> CLK_PCIE_LAN
CLK_REQ5_LAN#

<33> CLK_REQ5_LAN#

AJ50
AJ52
H6
AK53
AK51

T2104

CLKREQ_GLAN#_R

P13

+3VSUS_ORG

<22,26,27>

<22,24,25,27>

<28>

SML0ALERT#/GPIO60

PERN3
PERP3
PETN3
PETP3

SML0CLK

PERN4
PERP4
PETN4
PETP4

SML0DATA
SML1ALERT#/GPIO74
SML1CLK/GPIO58

PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6

SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#

PEG_A_CLKRQ#/GPIO47
PERN7
PERP7
PETN7
PETP7

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PERN8
PERP8
PETN8
PETP8

CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P

CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0#/GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P

PCIECLKRQ2#/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

REFCLK14IN

PCIECLKRQ3#/GPIO25

CLKIN_PCILOOPBACK

T2105

T13

CL_CLK

T11

CL_DATA

T9

CL_RST# <53>

To EC

<53>
<53>

H1

CLKREQ_PEG#

AD43
AD45

CLK_PCIE_PEG#_PCH
CLK_PCIE_PEG_PCH

AN4
AN2

CLK_DMI#_PCH <3>
CLK_DMI_PCH <3>

<70>

<70>
<70>

AT1
AT3

+3VSUS_ORG

AW24
BA24

CLK_DMI# <29>
CLK_DMI <29>

AP3
AP1

CLK_PCH_BCLK# <29>
CLK_PCH_BCLK <29>

F18
E18

CLK_DOT96# <29>
CLK_DOT96 <29>

AH13
AH12

CLK_SATA# <29>
CLK_SATA <29>

P41

CLK_ICH14

J42

CLK_PCI_FB

<29>

CLKOUT_PCIE4N
CLKOUT_PCIE4P

XTAL25_IN
XTAL25_OUT

PCIECLKRQ4#/GPIO26

XCLK_RCOMP

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLKOUTFLEX0/GPIO64

<24>

AH51
AH53
AF38

EXT_SCI#

SCL_3A

SDA_3A

1
C2101

AUB

2
27PF/50V

10KOhm
2.2KOhm
2.2KOhm
10KOhm

2 R2130
2 R2132
2 R2133

SML1ALERT#

SML0_CLK

1 2.2KOhm 2 R2140

SML0_DAT

SML1_DAT

1 2.2KOhm 2 R2138
4.7KOhm
1
2 R2136
4.7KOhm
1
2 R2137

SML1ALERT#

1 10KOhm 2 R2142

SML1_CLK

2 R2131

R1.2 --6

XCLK_COMP

1 R2117

2 90.9Ohm 1%

1MOhm
R2151

+VTT_PCH_ORG

X2101
25Mhz

<40> CLK_REQ4#_CB

EXT_SCI#

H14

A8

SMBDATA
PERN2
PERP2
PETN2
PETP2

B9

<29,48,80,91,92>

1 CX2103
1 CX2104

SMBCLK

<27,30,33,34,37,53,81,82,92>

+3VS

0.1UF/10V 2
0.1UF/10V 2

SMBALERT#/GPIO11

SMBus

AW30
BA30
BC30
BD30

<53> PCIE_RXN2_WLAN
<53> PCIE_RXP2_WLAN
<53> PCIE_TXN2_C
<53> PCIE_TXP2_C

PERN1
PERP1
PETN1
PETP1

Link

BG30
BJ30
BF29
BH29

Controller

PCIE_TXN1_TV
PCIE_TXP1_TV

PEG

1 CX2101
1 CX2102

PCI-E*

0.1UF/10V 2
0.1UF/10V 2

From CLK BUFFER

PCIE_RXN1_TV
PCIE_RXP1_TV
PCIE_TXN1_C
PCIE_TXP1_C

T45 CLK_OUT0

R2118

47Ohm

CLK_1394

<41>

C2102
AUB AUB

AUB

PCH CLKREQ Setting:

2
27PF/50V

GND

PCIECLKRQ5#/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56

Clock Flex

<64>
<64>
<64>
<64>

+3VSUS

+VTT_PCH_ORG

+3VSUS_ORG

U2001B

CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67

P43

CLK_OUT1

T2112

T42

CLK_OUT2

T2109

N50

CLK_OUT3

T2110

R2.0

Not connected to device.


CLK_REQ0#
CLKREQ_GLAN#_R

R2126
R2129

+3VSUS_ORG
2 10KOhm
2 10KOhm

1
1

R1.4--2
B

IBEXPEAK-M

Connected to device.
Default : Clock free run. (PD 10K).
Reserver 10K PU for power saving purpose.
+3VS
CLKREQ1_TV#
CLKREQ2_WLAN#

R2122
R2123

1
1

@
@

2 10KOhm
2 10KOhm

2 10KOhm

+3VSUS_ORG
CLKREQ3_NEWCARD#

R2124

CLK_REQ4#_CB

R2127

CLK_REQ5_LAN#

R2147

2 10KOhm
@
2 10KOhm
@

CLKREQ1_TV#
CLKREQ2_WLAN#
CLKREQ3_NEWCARD#
CLK_REQ5_LAN#
CLK_REQ4#_CB
CLKREQ_PEG#

R2145
R2144
R2143
R2146
R2141
R2139

1
1
1
1
1
1

2
2
2
2
2
2

10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm

R1.4--2

GND

Title : PCH(2)_PCIE,CLK,SMB,PEG
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

21

of

99

pre-ES1 not support


Reversal Feature
R1.2 --7

8.2KOhm
R2259
PM_PWROK

10KOhm

GND

BC24
BJ22
AW20
BJ20

<3>
<3>
<3>
<3>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

BD24
BG22
BA20
BG20

<3>
<3>
<3>
<3>

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

BE22
BF21
BD20
BE18

<3>
<3>
<3>
<3>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

BD22
BH21
BC20
BD18
BH25
DMI_COMP

2 R2203 1
49.9Ohm
1%

+VTT_PCH_ORG

<3,7> XDP_DBRESET#

R2251
1

2
<30> PM_PWROK

10KOhm
R2252
PM_BATLOW#
C

ME_PWROK

8.2KOhm
R2253
PCIE_WAKE#

GND

1KOhm

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP

FDI_FSYNC1
DMI_IRCOMP

R1.2 --11

SYS_RESET#

FDI_LSYNC1

T6
M6
B17

R2.0--1
MPWROK_R

K5

@
2
1
R2267
0Ohm
2
1 AUXPWROK_R
R2255
10KOhm

A10
D9

<3> H_DRAM_PWRGD

SYS_RESET#

WAKE#

SYS_PWROK

CLKRUN#/GPIO32

PWROK
MEPWROK
LAN_RST#
DRAMPWROK

SL2206
<30> PM_RSMRST#
ME_PM_SLP_M#

ME_SUSPWRDNACK

R2254
IAMT@2

<30> ME_SUSPWRDNACK

<7> PM_PWRBTN#_R
<30> PM_PWRBTN#

10KOhm
R2265
2

0402
SL2204
0402
SL2205
0402

ME_AC_PRESENT

BJ14
BF13
BH13
BJ12
BG14

C16
M1

R1.4--2
1

P5

R2.0--1
ME_AC_PRESENT

<30> ME_AC_PRESENT

P7

RSMRST#
SUS_PWR_ACK/GPIO30
PWRBTN#
ACPRESENT/GPIO31

SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63

J12

PCIE_WAKE#

Y1

<33,44,53>

PM_CLKRUN#

P8

PM_SUS_STAT#

T2203

F3

SUS_CLK

T2204

E4

SLP_S5#

T2205

H7

SLP_S4#_R

P12

SLP_S3#_R

K8

SLP_M#_R

N2

PM_SLP_DSW#

<30>

SL2201
SLP_S4#
SLP_S3#
SLP_M#
TP23

0402
SL2202
0402
SL2203
0402

PM_SUSC#

<30>

PM_SUSB#

<30>

ME_PM_SLP_M#

R2.0--1
1

T2206

10KOhm
ME_PM_SLP_LAN#

PM_RSMRST#_R

10KOhm
R2264

FDI_INT
FDI_FSYNC0

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

1KOhm
R2256
1

@
2
1
R2258
0Ohm
2
1
0402
SL2207
SL2200
2
1
0402

<30,92> ALL_SYSTEM_PWRGD
PM_RI#

R2262
0Ohm
@

D2201
1SS355
+3VSUS_ORG

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

+3VS

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

FDI_LSYNC0
+3VS

2 R2263 1
1KOhm

BF25

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI

R2248
PM_CLKRUN#

U2001C

<3>
<3>
<3>
<3>

System Power Management

+3VS

R1.4--2

R2266
IAMT@2

T2201

PM_BATLOW#

T2202

PM_RI#

A6
F14

BATLOW#/GPIO72

PMSYNCH

RI#

SLP_LAN#

BJ10
F6

PM_SYNC#
ME_PM_SLP_LAN#

<3>

ME_PM_SLP_LAN#

<57,91>

10KOhm
IBEXPEAK-M

STUFF for IAMT

+3VSUS_ORG
+3VS
+VTT_PCH_ORG

+3VSUS_ORG
+3VS

<21,24,25,27>

<29,48,80,91,92>

+VTT_PCH_ORG

<21,26,27>

Title : PCH(3)_FDI,DMI,SYS PWR


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

22

of

99

+3VS

+3VS

<29,48,80,91,92>

R2.0--2
U2001D

AB46
V48
AP39
AP41

L_CTRL_CLK

R2322 1 10KOhm 2

L_CTRL_DATA

R2323 1 10KOhm 2

AT43
AT42
AV53
AV51
BB47
BA52
AY48
AV47
BB48
BA50
AY49
AV48
AP48
AP47
AY53
AT49
AU52
AT53
AY51
AT48
AU50
AT51

AA52
AB53
AD53
V51
V53
Y53
Y51
R2321

2 1KOHM 1
0.5%

AD48
AB51

SDVO_INTN
SDVO_INTP

BJ48
BG48
BF45
BH45

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

R1.4--2

IBEXPEAK-M

GND

SDVO

L_CTRL_CLK
L_CTRL_DATA

1
1

L_DDC_CLK
L_DDC_DATA

BJ46
BG46

Display Port B

T2301
T2302

SDVO_STALLN
SDVO_STALLP

Display Port C

+3VS

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

Display Port D

AB48
Y45

L_BKLTEN
L_VDD_EN

Digital Display Interface

Y48

LVDS

CRT

T48
T47

GND

CRB R0.9,DG R0.8: 1K+/-0.5%


Intel checklist recommand:
1.02K PD resistor to 0.5%

DisPlay Port Disable: (For discrete graphic)


1. NC:
ALL

LVDS Disable: (For discrete graphic)


1. NC:
LVDSA_DATA [3:0], LVDSA_DATA# [3:0],
LVDSA_CLK, LVDSA_CLK#, LVDSB_DATA [3:0],
LVDSB_DATA# [3:0], LVDSB_CLK, LVDSB_CLK#
L_VDD_EN, L_BKLTEN, L_BKLTCTL, LVD_VREFH
LVD_VREFL, LVD_IBG, LVD_VBG
2. Connected to GND:
VccALVDS,VccTX_LVDS

CRT Disable: (For discrete graphic)


1. NC:
CRT_RED,CRT_GREEN,CRT_BLUE
CRT_HSYCN,CRT_VSYNC
2. 1-k 0.5% pull-down to GND:
DAC_IREF
A

3. Connected to GND:
CRT_ITRN
4. Connect to +V3.3:
VCCADAC

Title : PCH(4)_DP,LVDS,CRT
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

23

of

99

+3VSUS

+3VSUS

+3VS

J50
G42
H47
G34

T2412

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

G38
H51
B37
A44

PCI_REQ0#
PCI_REQ1#

F51
A46
B45
M53

DGPU_SELECT#_R

PCI_REQ3#

T2403

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#

F48
K45
F36
H53

PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#

B41
K53
A36
A48

PCI_SERR#
PCI_PERR#

E44
E50

PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

PCI_LOCK#

D49

K6

PCI_STOP#
PCI_TRDY#

change to PCI_CLK4 to sync ICS364

D41
C48
M7

PLT_RST#
22Ohm 2
22Ohm 2
22Ohm 2
22Ohm 2
22Ohm 2

<38> CLK_DSPPCI
<21> CLK_PCI_FB
<30> CLK_KBCPCI_PCH
<44> CLK_DEBUG
<44> CLK_DBGPCI2

1
1
1
1
1

RX2405
RX2401
RX2404
RX2406
RX2407

CLK_DSPPCI_R
CLK_PCI_FB_R
CLK_KBCPCI_PCH_R
CLK_DEBUG_R
CLK_DBGPCI2_R

R2.0

D5
N52
P53
P46
P51
P48

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1

NVRAM

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

NV_RCOMP
NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#

NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
NV_ALE
NV_CLE

USB

R1.4--2

U2001E

PCI

R1.2 --5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

PLOCK#
USBRBIAS#
STOP#
TRDY#

USBRBIAS

PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

+3V

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

+V_NVRAM_VCCQ

AY9
BD1
AP15
BD8

<27,30,33,34,37,53,81,82,92>

+3VS

<29,48,80,91,92>

+3V

<33,43,45,57,61,64,69,91>

+V_NVRAM_VCCQ

+3VSUS_ORG

+3VSUS_ORG

<26>

<21,22,25,27>

AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USB_PN7
USB_PP7
USB_PN8
USB_PP8

1
1
1
1
1
1

USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
T2410
T2411
T2401
T2402
T2406
T2407

USB_PN10
USB_PP10
USB_PN11
USB_PP11

1
1
1
1

USB_PN9
USB_PP9
T2404
T2405
T2408
T2409
USB_PN12
USB_PP12
USB_PN13
USB_PP13

<65>
<65>
<65>
<65>
<52>
<52>
<52>
<52>
<64>
<64>
<43>
<43>

<53>
<53>

USB port(IO/B)
USB port(IO/B)

+3VS

USB port
C

USB port
PCI_INTG#
PCI_INTA#
PCI_INTC#
PCI_STOP#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_SERR#
PCI_INTE#
PCI_IRDY#
PCI_INTD#

TV turner
Newcard R1.4--1

WiFi/WiMax

<61>
<61>
<45>
<45>

PCI_REQ0#
PCI_INTB#
PCI_INTF#
PCI_REQ3#
PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCI_INTH#

BT
Camera

R1.2--10
+3VSUS_ORG

B25
D25

USBRBIAS_PN

1 R2411 2
22.6Ohm 1%

GND

1
5
3
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7

DGPU_SELECT#_R

R2403

8.2KOHM2
8.2KOHM6
8.2KOHM4
8.2KOHM8
8.2KOHM2
8.2KOHM4
8.2KOHM6
8.2KOHM8
8.2KOHM2
8.2KOHM4
8.2KOHM6
8.2KOHM8
8.2KOHM2
8.2KOHM4
8.2KOHM6
8.2KOHM8
8.2KOHM2
8.2KOHM4
8.2KOHM6
8.2KOHM8

RN2401A
RN2401C
RN2401B
RN2401D
RN2402A
RN2402B
RN2402C
RN2402D
RN2403A
RN2403B
RN2403C
RN2403D
RN2404A
RN2404B
RN2404C
RN2404D
RN2405A
RN2405B
RN2405C
RN2405D

1 10KOhm

Place within 500 mils of PCH

N16
J16
F16
L16
E14
G16
F12
T15

1
5
1
3
3
7
5
7

10KOHM 2
10KOHM 6
10KOHM 2
10KOHM 4
10KOHM 4
10KOHM 8
10KOHM 6
10KOHM 8

RN2408A
RN2408C
RN2407A
RN2408B
RN2407B
RN2408D
RN2407C
RN2407D
B

1
2
10PF/50V C2403

1
2
10PF/50V C2401

1
2
10PF/50V C2402
1
2
10PF/50V C2404
1
2
10PF/50V C2405

IBEXPEAK-M

GND

GND

GND GND GND

GNT0#,GNT1#: Boot BIOS Strap.


Boot BIOS Strap
PCI_GNT1#

PCI_GNT0#

Boot BIOS Location

LPC

PCI

Reserved

SPI (PCH)

GNT3#: A16 swap override Strap/


Top-Block swap override jumper
Low=Enabled A16 swap override/
Top-Block swap override
High=Default
+3V

Sampled on rising edge of PWROK.


A

PCI_GNT0#
PCI_GNT1#

R2440 1

2 1KOhm

R2441 1

PCI_GNT3#

R2444 1

U2401
1 A
VCC

2 1KOhm

PLT_RST#

PLT_RST#

2 1KOhm

5
A

2 B

GND

3 GND

4
Y
NC7SZ08P5X_NL

GND

BUF_PLT_RST#

<3,7,30,32,33,38,40,43,53,64,70>

GND
R2413

2 0Ohm

Title : PCH(5)_PCI,NVRAM,USB
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

24

of

99

<30>
2

T2593

Y3

T2590
1
T2501
1
TPC26T
T2592
1

R2538
10KOhm

DOCKING_DET#

C38

DGPU_PWR_EN

D37

XIDE_BAY_IN#

J32

<56>

T2594

PM_LANPHY_EN

AA2

DGPU_PWROK

F38

R1.4--4
<53>

GPIO 27:Enable VCCVRM,Low=disable.


Default internal pull up.

R1.2--11

<29>

T2596

OC_LAN_RST#

T2595

VRM_EN

GND

R1.2--3

T2600

<61>

V3
P3

T2597

CLK_REQ6#

H3

T2598

CLK_REQ7#

F1

T2599
1
T2500
1
TPC26T
BT_ON

EMAIL_LED

AB6

TEMP_ALERT#

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

TACH0/GPIO17

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

MEM_LED/GPIO24

PECI
RCIN#

GPIO27
GPIO28

PROCPWRGD
THRMTRIP#

TP1

SATA3GP/GPIO37

TP2

SLOAD/GPIO38

TP3

SDATAOUT0/GPIO39

TP4

PCIECLKRQ6#/GPIO45

TP5

PCIECLKRQ7#/GPIO46

TP6

SDATAOUT1/GPIO48

TP7

SATA5GP/GPIO49

TP8

GPIO57

TP9
TP10

+3VSUS_ORG

EXT_SMI#

2 10KOhm 1 R2532

+3VS

1
1
1
1
1
1

TP_VSS_NCTF10
TP_VSS_NCTF11
TP_VSS_NCTF12
TP_VSS_NCTF13
TP_VSS_NCTF14
TP_VSS_NCTF15

T2549
T2550
T2551
T2552
T2553
T2554
T2555
T2556
T2557
T2558
T2559
T2560
T2562
T2561

1
1
1
1
1
1
1
1
1
1
1
1
1
1

TP_VSS_NCTF18
TP_VSS_NCTF19
TP_VSS_NCTF20
TP_VSS_NCTF21
TP_VSS_NCTF22
TP_VSS_NCTF23
TP_VSS_NCTF24
TP_VSS_NCTF25
TP_VSS_NCTF26
TP_VSS_NCTF27
TP_VSS_NCTF28
TP_VSS_NCTF29
TP_VSS_NCTF30
TP_VSS_NCTF31

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

TP11

NCTF

T2540
T2541
T2542
T2543
T2544
T2545

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

RSVD

TP_VSS_NCTF1
TP_VSS_NCTF2
TP_VSS_NCTF3
TP_VSS_NCTF4
TP_VSS_NCTF5
TP_VSS_NCTF6
TP_VSS_NCTF7
TP_VSS_NCTF8

TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24

AM3
AM1
SL2500
BG10

PECI

0402

T1

R2.0--1

BE10

BCLK_CPU_N_PCH

<3>

BCLK_CPU_P_PCH

<3>

H_PECI
RCIN#

<3,30>
<30>

H_CPUPWRGD
PM_THRMTRIP#

BD10

<3,7>

H_THRMTRIP#

56Ohm
R2501
1

SATA2GP/GPIO36

F8

1
1
1
1
1
1
1
1

A20GATE <30>

SATACLKREQ#/GPIO35

AA4

T2531
T2532
T2533
T2534
T2535
T2536
T2537
T2538

U2

STP_PCI#/GPIO34

AB13

PCB_ID1

AF48
AF47
D

A20GATE

SATA4GP/GPIO16

SCLOCK/GPIO22

STP_PCI#
M11
SL2501
2
1SATA_CLK_REQ#_R V6
0402
DGPU_PWR_EN#
AB7

PCB_ID0

CLKOUT_PCIE7N
CLKOUT_PCIE7P

GPIO15

H10

DGPU_PRSNT#

R1.2--3

LAN_PHY_PWR_CTRL/GPIO12

V13

STP_PCI#

AH45
AH46

GPIO8

AB12

WLAN_ON

<29> SATA_CLK_REQ#
GND

TACH3/GPIO7

Y7

<56> WLAN_LED
R2537
10KOhm
@

TACH2/GPIO6

T7
DGPU_HOLD_RST#

CLKOUT_PCIE6N
CLKOUT_PCIE6P

TACH1/GPIO1

K9

BT_LED

R1.2--3
PCB_ID1

R2535
10KOhm
@

BMBUSY#/GPIO0

F10

EXT_SMI#

R1.4--4
PCB_ID0

U2001F

R1.2--3

MISC

1
R2536
10KOhm

CPU

ID0
ID1
SKU
------------------------------0
0
CFD_Non-IAMT
0
1
CFD_IAMT
1
0
AUB_Non-IAMT
1
1
AUB_IAMT

+3VS

+3VS

GPIO

BA22

T2588

AW22

T2589

BB22

T2582

AY45

T2584

AY46

T2583

AV43

T2585

AV45

T2587

AF13

T2586

M18

TP9_PCH 1

T2563

N18

TP10_PCH 1

T2564

AJ24

TP11_PCH 1

T2566

AK41

T2580

AK42

T2581

<3,32>

+VTT_CPU

56Ohm
R2525

close to U2001.BD10

M32

TP14_PCH

T2565

N32

TP15_PCH

T2567

M30

TP16_PCH

T2568

N30

TP17_PCH

T2569

H12

TP18_PCH

T2570

AA23

TP19_PCH

T2571

AB45

TP_PCH_NC1 1

T2572

AB38

TP_PCH_NC2 1

T2573

AB42

TP_PCH_NC3 1

T2574

AB41

TP_PCH_NC4 1

T2575

T39

TP_PCH_NC5 1

T2576

P6

INT3_3V#

T2579

T2577

C10 TP_PCH_SST

IBEXPEAK-M
DGPU_PWR_EN

2 10KOhm 1 R2539
@

R1.4--5
DGPU_HOLD_RST#

2 10KOhm 1 R2540
@

DGPU_PRSNT#

2 10KOhm 1 R2543

+3VS
+3VSUS

R1.2--3

+VTT_CPU
+3VSUS_ORG

R1.2--11
R2506

R2533

1 10KOhm

SATA_CLK_REQ# R2531

1 10KOhm

DGPU_PWROK

1 0Ohm
@

PWR_OK_VGA

+3VS

<29,48,80,91,92>

+3VSUS

<27,30,33,34,37,53,81,82,92>

+VTT_CPU <3,6,7,26,27,29,32,57,82>
+3VSUS_ORG

<21,22,24,27>

<92>

R1.4--1 08'WW50 MoW


GND

Title : PCH(6)_CPU,GPIO,MISC
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

25

of

99

U2001H
+VTT_PCH_ORG

5.172A

JP2601

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

69mA +VCCA_DAC_1_2
S0 max

BJ24

VCC3_3[2]

2
1UF/6.3V

2
1UF/6.3V

2
1UF/6.3V

C2607 C2606 C2605 C2604 C2603

GND

+VTT_PCH_VCCAPLL_FDI

+VTT_PCH_ORG

L2605

R2.0--2

1 1KOhm/100Mhz
C2608
10UF/6.3V

GND

+3VM

2 0Ohm
R2645
@

+3VS

1 SP2604

AN30
AN31
+3VS_VCCA3GBG
AN35

R0402
R2.0--1

AT22

+VCCAFDI_VRM
+VTT_PCH_VCCDPLL_FDI

BJ18

+VTT_PCH_VCCIO
GND

1 SP2613

AM23

1
2

0.1UF/10V

10UF/6.3V

1
2

AF53

S0 max
+3VS

AF51

SP2607
R0402
CFD

AH38
AH39

59mA
S0 max

GND

R2.0--1
+1.8VS_VCCT_LVD

GND

AP43
AP45
AT46
AT45

SP2608
R0402
CFD

R2.0--1

VCC3_3[3]

AB35
AD35

GND

+3VS_VCC_GIO

357mA
S0 max

1 SP2609 +3VS

VCC3_3[4]

AB34

R0402
R2.0--1

C2613
0.1UF/10V

GND

VCCVRM[2]

VCC3_3[1]
VCCVRM[1]
VCCFDIPLL

R0402

R1.2--11

GND

+1.5VS

+1.8VS_VCCADMI_VRM

VCCIO[54]
VCCIO[55]

VCCIO[1]

GND

L2610 @
2

300mA +3VS_VCCA_LVDS

VCCDMI[1]
VCCDMI[2]

AT24
AT16
AU16

+VTT_CPU_VCC_DMI

61mA
S0 max

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

1 SP2610

+VTT_PCH_ORG

R0402
R2.0--1

1UF/6.3V

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

+VTT_CPU

C2648

+VTT_PCH_VCCIO

HVCMOS

GND
+VTT_PCH_VCC_EXP

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

DMI

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

PCI E*

C2602
10UF/6.3V

NAND / SPI

@
+VTT_PCH_VCCAPLL_EXP

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCCAPLLEXP

FDI

GND

1KOhm/100Mhz

1 1KOhm/100Mhz

VCCIO[24]

L2601

AK24

LVDS

R0402
+VTT_PCH_ORG

2mA
S0 idle

R2.0--1

+3VS

VCCALVDS
VSSA_LVDS

+VTT_PCH_VCCDPLL_EXP
1 SP2605

VSSA_DAC[2]

AE52

GND

+VTT_PCH_VCCDPLL_EXP

+VTT_PCH_VCCIO

VSSA_DAC[1]

GND

AE50

2
R0603

C2610

VCCADAC[2]

1UF/6.3V

GND

VCCADAC[1]

10UF/6.3V

GND

2MM_OPEN_5MIL

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

0Ohm
R2643
@

GND

156mA
S0 max

+V_NVRAM_VCCPNAND

+V_NVRAM_VCCQ
1 SP2611

C2601

C2650

C2616

R0402
C2614
0.1UF/10V

GND
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AM8
AM9
AP11
AP9

85mA
S0 max

IBEXPEAK-M

+3VS
+3VM_VCCPEP
1 SP2612

+VTT_PCH_VCCIO

POWER

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

+VTT_PCH_VCC

3.208A
S0 max

JP2603
1

U2001G

CRT

1.524A
S0 max

1MM_OPEN_5MIL

C2609

+VTT_PCH_VCC

VCC CORE

1.524A
S0 max

JP2602
2

R2648
0Ohm
@

0.01UF/16V

+VTT_PCH_ORG

IBEXPEAK-M
GND

SP2614
1

3MM_OPEN_5MIL

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

2
1UF/6.3V

+1.05VS

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

2
10UF/6.3V

VSS[0]

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

AB16

+3VM

R0402
C2615
0.1UF/10V

R2.0--1

0Ohm
R2644
@

GND

R2.0--2
+1.5VS

+VTT_PCH_1.5VS_1.8VS
R2619

+VCCAFDI_VRM

1 0Ohm

1 SP2600

+1.8VS

1 SP2601
+1.8VS_VCCADMI_VRM

R0402
2

+VTT_PCH_ORG

R0402
R2.0--1
R2646

1 SP2602

+1.05VS

R0402
R2.0--1

+1.05VS

+VTT_PCH_VCCIO

1 0Ohm

+VTT_PCH_ORG

+VTT_PCH_ORG

+VTT_CPU

+1.8VS

+V_NVRAM_VCCQ

R0402

<20,27>
<21,22,27>

+VTT_CPU <3,6,7,25,27,29,32,57,82>

+1.8VS

+1.8VS

<6,38,57,70,85>

+1.5VS

+1.5VS

<43,53,57,64,91>

+3VS

<29,48,80,91,92>

+3VS

1 SP2603

<27,57,69,91>

+VTT_PCH_VCCIO

R1.4--5
+V_NVRAM_VCCQ

+V_NVRAM_VCCQ

Title : PCH(7)_POWER,GND
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

26

of

99

U2001I

VCCME[10]
VCCME[11]

2
1

Y42

R0402

VCCME[12]

GND

R2.0--1

GND

1 DCPRTC
C2722
0.1UF/10V

V9

AU24

+VTT_PCH_1.5VS_1.8VS

72mA
S0 max
+VTT_PCH_VCCA_A_DPL

73mA
S0 max

C2723

BD51
BD53
AH23
AJ35
AH35

+VTT_PCH_VCCA_B_DPL

BB51
BB53

C2724
AF34

1UF/6.3V

1UF/6.3V

GND

GND

AH34

+VTT_PCH_SSCVCC

C2729
1UF/6.3V

+VTT_PCH_VCCIO

AF32

GND

1 +VCCSST
C2725
0.1UF/10V

GND

1+V1.05A_INT_VCCSUS Y22
C2726
0.1UF/10V

VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[56]
V5REF_SUS

+VTT_PCH_VCCIO

U23
GND

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

DCPSST

DCPSUS
VCCIO[9]

100Ohm

L38

+3VS_VCCPPCI

GND

M36

C2740

N36

0.1UF/10V

P36
U35

GND
AD13

+3VS_VCC3_3

0.1UF/10V

AK3
AK1

+VTT_PCH_VCCAPLL

AH22

V15
V16

GND
+3VS_VCCPCORE

Y16

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

AT18

GND

AU18

V_CPU_IO[2]

VCCRTC

GND

GND

IBEXPEAK-M

VCCSUSHDA

+VTT_PCH_ORG

@
C2742
10UF/6.3V

+VCCPLLVRM

AH19

GND

+VTT_PCH_VCC_SATA

AD20

+VTT_PCH_VCCIO

AF22

C2744

AD19
AF20
AF19
AH20

1UF/6.3V

GND
AB19
AB20
AB22
AD22

AA34 +1.05VM_ORG_R1
Y34 +1.05VM_ORG_R2
Y35 +1.05VM_ORG_R3
AA35 +1.05VM_ORG_R4
10mil trace

R0402
R0402
R0402
R0402

2
2
2
2

1 SP2706
1 SP2707
1 SP2708
1 SP2709

+1.05VM_ORG

+3VSUS_HDA
SP2705

R2.0--1

L30

A12

HDA

0.1UF/10V

0.1UF/10V

GND

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

C2730

RTC

C2731

C2752
4.7UF/6.3V

V_CPU_IO[1]

0.1UF/10V

>1mA
S0 max
1

+VTT_CPU_VCCPCPU
SP2703
1

CPU

C2728

+VTT_CPU

AT20

C2743
10UF/6.3V

GND
VCCIO[10]

+3VS_VCC3_3

VCCSUS3_3[32]

VCCVRM[4]

L2705
1KOhm/100Mhz
2

U22
C2727
0.1UF/10V

+3VS_VCC3_3

VCCSUS3_3[29]

VCCSUS3_3[31]

2 R2732

2
R0402
R2.0--1

+5VS
GND

1UF/6.3V

C2741

VCCIO[4]

SATA

U20

SP2702
+3VSUS_ORG

C2738
1UF/6.3V

J38

VCCIO[3]

VCCSUS3_3[30]

D2702
BAT54C

K49
C2739

VCC3_3[8]

VCC3_3[13]

PCI/GPIO/LPC

P18

+3VA_VCCPSUS

+5VSUS_ORG
10Ohm
1 R2731 2

F24
+5VS_PCH_VCC5REF

V5REF

VCCIO[2]

IBEXPEAK-M

+3VSUS_ORG

R0402

C2745

2mA
S0 max

R2.0--1

1UF/6.3V

GND

+VCC_RTC
C2733

C2732

GND
2

0.1UF/10V

0.1UF/10V

GND

GND

+1.05VS
+3VS

+VTT_PCH_VCCA_A_DPL

1UF/6.3V

C2746

@
0Ohm
R2748

+VTT_PCH_ORG

+VTT_PCH_ORG

+VTT_PCH_VCCA_A_DPL

+VTT_CPU

L2706
2

+VTT_PCH_VCCIO

1KOhm/100Mhz

+3VSUS

CE2703
@
220UF/4V

+VCC_RTC

+5VSUS

ESR=40mOhm/Ir=1.9A
GND

GND

+5VS

+VTT_PCH_VCCA_B_DPL
1

C2747

+VTT_PCH_VCCA_B_DPL
2

1UF/6.3V

+5VSUS_PCH_VCC5REFSUS

V23

GND

U19

R0402
R2.0--1

GND

D2701
BAT54C

0.1UF/10V

GND

V12

DCPRTC

VCCSUS3_3[28]

+3VS

C2737

VCCME[9]

Y41
1UF/6.3V

VCCME[8]

Y39

VCCME[7]

+3VSUS_ORG

V41

C2721

+VTT_PCH_1.5VS_1.8VS
SP2700
2

VCCME[6]

V39
GND

@
GND

V42

+VCCPLLVRM

VCCME[5]

GND

22UF/6.3V

R2.0--1
GND

VCCME[4]

+3VSUS_ORG
D

AF42
1UF/6.3V

VCCME[3]

0.1UF/10V

1MM_OPEN_5MIL

AF41

C2720

C2702

VCCME[2]

1
R0402

R2.0--1

C2700
10UF/6.3V

1
+5VSUS_ORG

JP2704
2

AF43

+1.05VM_ORG

1MM_OPEN_5MIL
+5VSUS

AD41

SP2704
2

C2735

VCCME[1]

GND
+1.1VM_VCCEPW

S0 max

1
2

+3VSUS_ORG

JP2703

DCPSUSBYP

+3VSUS_VCCPUSB

163mA
S0 max

GND

AD38
AD39

+3VSUS

1UF/6.3V

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

C2751
0.1UF/10V

GND

1MM_OPEN_5MIL

Y20

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCLAN[2]

TP_PCH_VCCDSW

VCCLAN[1]

AF24

+VTT_PCH_VCCIO
C2734

V24
V26
Y24
Y26

357mA +3VS_VCC3_3
S0 max

AF23

344mA
S0 max

+3VS

VCCACLK[2]

GND

R2701
0Ohm

R2.0--1
@
JP2702

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

USB

2 R2702 1
0Ohm @

+1.05VM_ORG

AP53

GND
1

2MM_OPEN_5MIL

+VTT_PCH_VCCUSBCORE

VCCACLK[1]

AP51

+1.05VM_VCCAUX

JP2705
2

C2717
1UF/6.3V

Clock and Miscellaneous

2MM_OPEN_5MIL

POWER

U2001J

C2718
10UF/6.3V

PCI/GPIO/LPC

@
1

+1.05VM

JP2701
2

+VTT_PCH_VCCA_CLK

52mA
S0 max

L2704
1KOhm/100Mhz
1

+VTT_PCH_ORG

+1.05VM_ORG

+1.05VS

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

1.998A+344mA
S0 max R2.0--2

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

GND

GND

L2707
2

1KOhm/100Mhz
CE2704
@
220UF/4V

+1.05VS

<26,57,69,91>

+3VS

<29,48,80,91,92>

+VTT_PCH_ORG

+VTT_PCH_VCCIO
+3VSUS
+VCC_RTC

<20,26>

<30,33,34,37,53,81,82,92>
<20>
A

+5VSUS

<56,81,91>

+5VS

<30,31,37,45,46,48,50,51,56,57,70,80,91>

+1.05VM_ORG

+1.05VM_ORG

+3VSUS_ORG

+3VSUS_ORG

+5VSUS_ORG

+5VSUS_ORG

+1.05VM

<21,22,26>

+VTT_CPU <3,6,7,25,26,29,32,57,82>

+1.05VM

<21,22,24,25>

<57,69,91,92>

Title : PCH(8)_POWER,GND

?
ESR=40mOhm/Ir=1.9A

Size
C
Date:
5

Engineer:

BU2/RD1

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

27

of

99

SL2613

PCH SPI ROM

+3VS

0402

+3VM_SPI
D2801

+3VM_SPI

+3VM

+3VM_SPI

2 0Ohm
R2647
@

1
3
2

2
1

2
<20>
<20>

SPI_CS#0
SPI_SO

U2801
1
2
3
4

+3VM_SPI_0

R2829
15Ohm

0Ohm 2

+12VS

<45,91>

+12VSUS

<81,91>

+3VM

<26,53,57,91,92>

+3VM
1 R2847

+3VM_SPI

<16,17,20,21,22,23,24,25,26,27,29,30,32,36,37,40,43,44,45,46,48,50,51,53,56,57,64,65,66,69,70,80,91,92>

+3VM_SPI <20>
D

R2.0--1

R2831
3.3KOhm

BAT54C

R2.0--2
C2802
0.1UF/16V

+3VS

+12VSUS

@
R2833
3.3KOhm

+3VS
+12VS

CE#
VDD
SO HOLD#
WP# SCK
VSS
SI

8
7
6
5

+3VM_SPI_00
SPICLK
SPISI

SPI_CLK
SPI_SI

<20>
<20>

SST25VF040B-50-4C
SPISO

(4Mb)

+3VM_SPI

+3VM_SPI

2
U2802
1
2
3
4

+3VM_SPI_1

R2823
15Ohm

CE#
VDD
SO HOLD#
WP# SCK
VSS
SI

8
7
6
5

+3VM_SPI_11

+12VS

SST25VF032B
@ (32Mb)

R2.0--1

+3VS

4.7KOhm
R2802

SPI FROM EC

<21> SCL_3A

For EC request.

SMB_CLK_S

Q2801A
UM6K1N

PCH

4.7KOhm
R2803

<7,16,17,29,38,44,53,69>

SPI_CS#1

<20>

SPD
CLKGEN
DEBUG
WLAN
CPU XDP
PCH XDP
VID CONTROLLER
DSP FM2010
GAME LED

@
C2803
0.1UF/16V

@
R2832
3.3KOhm

SMBUS Link device


R2834
3.3KOhm
@

<21> SDA_3A

SMB_DAT_S <7,16,17,29,38,44,53,69>

Q2801B
UM6K1N

+12VSUS

<30,56> SMB1_CLK

@
SPI_CS#1

15Ohm

SPI_CS#0

15Ohm

+3VM_SPI

2 R2836
@
SPI_CS#_CON
SPISO

J2801 @
1
2
3
4
5
6
7

SML1_CLK

Q2802A
UM6K1N

EC

2 R2835

<30,56> SMB1_DAT

SPICLK
SPISI

<21>

PCH

SPI FLASH CON

SML1_DAT <21>

Q2802B
UM6K1N

HEADER_2X4P_K8

1206-000C000

Put near U2801,U2802

SPI Setting for layout:

+3VS

4.7KOhm
R2806
1

4.7KOhm
R2807

2
6

+12VS

SMB1_CLK_S

Branch as short as possible.

<50,70>

CPU,VGA Thermal

Q2803A
UM6K1N

PCH
3

SMB1_DAT_S

U2001
A

Flash CON
J2801

<50,70>

Q2803B
UM6K1N

PCH SPI
B
C

U2801
U2802

EC 8512
U3001

Title : PCH(9)_SPI,SMB
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

28

of

99

Reserved for new CLK GEN.

CPU_STOP#

VDDA
CPUT_L1F
GNDA
CPUC_L1F

CPUT_L0

CPUC_L0

X2_CLK

57

X2
CPUITPT_L2/PCIeT_L8
CPUITPC_L2/PCIeC_L8

17

27FIX/LCD_SSCGT/PCIeT_L0

PEREQ1#/PCIeT_L7
PEREQ2#/PCIeC_L7

R1.2--4

18

PCIeT_L6
27SS/LCD_SSCGC/PCIeC_L0
PCIeC_L6
PCIeT_L5

FSLA

R2902

1 2.2KOhm

12

FSLA/USB_48MHz

PCIeC_L5
PCIeT_L4

FSLB

16

PCIeC_L4

PCIeC_L3
5

*SELPCIEX0_LCD#PCICLK3
PCIeT_L2
PCIeC_L2

PCICLK2

PCIeT_L1
PCIeC_L1

CK-505 recommend 22ohm


3

SATACLKT_L
PCICLK1
SATACLKC_L
PCIeT_L9/DOTT_96MHzL

64

STP_PCI#_R

62

STP_CPU#

1
2

63

33PCIF5

PCICLK0/REQ_SEL**

PCIeC_L9/DOTC_96MHzL

*PEREQ3#
*SELLCD_27#/PCICLK_F5
PEREQ4#*
VttPWR_GD/PD#

0Ohm 2 R2921
@

STP_PCI#

0 : Pin 43/44 = SRC CLK


<25>

C2920
10UF/10V

1 : Pin 43/44 = CPU_ITP CLK

C2918
0.1UF/16V

+3VS

55

SMB_DAT_S

47

R2908

48
52

33PCIF4

R1.2--2

51

CLKPCHBCLK

1
RX2914
CLKPCHBCLK#
1
RX2915

2
33Ohm
2
33Ohm

CLK_PCH_BCLK

2 10KOhm

<21>

CLK_PCH_BCLK#

Pin9 desides pin14/15,17/18:

<21>

0 : Pin 14/15 = PCIe_L9

44

Pin 17/18 = 27FIX/27SS

43

1 : Pin 14/15 = DOT_96MHz


41

SATA_CLK_REQ#

<25>

40

Pin 17/18 = LCD_SSCG/PCIe_L0

PEREQ1# Control:(Byte8,R/W)

+3VS

SATACLK[bit2]: 0=Not controlled,1=controlled.


PCIEX6 [bit1]: 0=Not controlled,1=controlled.
PCIEX0 [bit0]: 0=Not controlled,1=controlled.

39

CLKDMI

35

CLKDMI#

1
RX2920
1
RX2919

2
33Ohm
2
33Ohm

CLK_DMI

<21>

CLK_DMI#

<21>

R2910

2 10KOhm
@

33PCIF5

38
36

R2934

2 10KOhm

Pin64 desides pin40/41:


1 : Pin 40/41 = PEREQ1#,PEREQ2#

31

+3VS

24

R2911

2 10KOhm

25
33PCI0

23
+3VS

19
20

R1.2--2

26

SATACLK

27

SATACLK#

14

CLK_PCIE9

15

CLK_PCIE9#

1
RX2928
1
RX2929
1
RX2930
1
RX2931

2
33Ohm
2
33Ohm

CLK_SATA

2
33Ohm
2
33Ohm

<21>

CLK_SATA#

<21>

CLK_DOT96

<21>

CLK_DOT96#

33

REF1
REF0

61
60

2
10KOhm

STP_CPU#

1
RX2936

2
10KOhm

BCLK

+3VS

R2905
10KOhm
CLK_PWRGD

1
RX2935

Reserved for R1.0 Debug

<21>

32

10

STP_PCI#_R

FSB

FSLC FSLB FSLA


0

166

200

266

D
SCLK
REF1/FSLC/TEST_SEL
REF0

RX2906 1
RX2907 1

2 10KOhm
2 33Ohm

FSLC
CLK_ICH14

<21>
S 2

+VTT_CPU
Q2901
11
G 2N7002

CLK_EN#

<80>

VREF

R2912
1KOhm

R2914
1KOhm
@
2
1

FSLA
FSLB
FSLC

GND1
GND2
GND3
GND4
GND7
GND6
GND5

R2913
1KOhm
@

ICS9LPR362AGLF-T

R2916
1KOhm
@

R2915
1KOhm

R2917
1KOhm

133

R2904
330Ohm
1%

2 10KOhm

22

ITP_EN/PCICLK_F4

SDATA

R2928

1
1

CK505_VREF

2
6
13
29
37
53
59

0 : Pin 40/41 = PCIe_L7

30

1%
1KOhm
R2903

2 10KOhm

49

+3VS

<7,16,17,28,38,44,53,69>

8
54

R2933

33PCIF4
SMB_CLK_S

Pin8 desides pin43/44:

<7,16,17,28,38,44,53,69>

2 10KOhm

C2919
0.1UF/16V

33PCI0

+3VS_VDDREF

2 10KOhm

FSLB/TEST_MODE
PCIeT_L3

33PCI3

+3VS_VDD48

56

R2907

X1

X2901
14.318Mhz

C2908
24PF/50V
2
1

1
PCI/PCIEX_STOP#

VDDCPU

C2921
10UF/10V

PWRSAVE#*

11

58

33PCI3

R2909

46
X1_CLK

+3VS_VDDPCI

C2922
0.1UF/16V

C2907
24PF/50V
2
1

C2906
0.1UF/16V

VDD48
VDDREF

+3VS

1 : Pin 17/18 = PCIe_L0

C2917
0.1UF/16V

C2905
10UF/10V

45

C2916
0.1UF/16V

C2926
0.1UF/16V

0402

SL2900

50

C2923
10UF/10V

0 : Pin 17/18 = LCD_SSCG

34

+3VS_VDDA

VDDPCIEX1
VDDPCIEX2
VDDPCIEX3

VDDPCI2

21
28
42

VDDPCI1

C2902
0.1UF/16V

R2.0--1

+3VS

+3VS_VDDPCI

U2901

1
2

C2901
0.1UF/16V

Pin5 desides pin17/18:

L2902
120Ohm/100Mhz
1
2

0.1UF/16V
2
0.1UF/16V
2

0Ohm 2 R2922
@
0Ohm 2 R2923
@

C2904
1
C2903
1

R2.0--1

Latched Input Select


+3VS

+VDDIO_42

1
1
C2927

+VDDIO_28

@ 2
10UF/10V

0402

0402

+VTT_CPU

1
C2924
10UF/10V

C2925
0.1UF/16V

+3VS_VDDPCIEX

L2901
120Ohm/100Mhz
1
2

SL2902

+3VS

+3VS SL2901

ICS9LPR364BGLF-T:06G011457011

363:VREF
+3VS
A

+3VS

+VTT_CPU

364:TURBO

<16,17,20,21,22,23,24,25,26,27,28,30,32,36,37,40,43,44,45,46,48,50,51,53,56,57,64,65,66,69,70,80,91,92>

R2904

R2925

1K

330
10K

@
@

364:NO TURBO

+VTT_CPU <3,6,7,25,26,27,32,57,82>

R2903

@
A

Title : CLK_ICS9LPR362
Engineer:

BU2/RD1
Size
C
Date:
5

Gary Tsai

Project Name

Rev

G50J

1.2

Friday, July 31, 2009

Sheet
1

29

of

99

For IT8752 Power

T3029

R2.0--1
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57
EC_XIN
128
EC_XOUT
2

1
EXP_GATE#
T3033
1DISTP#

<56> EXP_GATE#
<31>
<31>

<60> SMB0_CLK
<60> SMB0_DAT
<28,56> SMB1_CLK
<28,56> SMB1_DAT
<3> THRO_CPU
<3,25>
H_PECI

2 @ 0Ohm
1
R3072

110
111
115
116
117
118

TMRI1/WUI3/GPC6
PWUREQ#/GPC7

KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/GPC3
KSO17/GPC5

L80HLAT/GPE0
EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3
PWRSW/GPE4
WUI5/GPE5
LPCPD#/WUI6/GPE6
L80LLAT/GPE7
GPG1/ID7

SMCLK0/GPB3
SMDAT0/GPB4
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/GPF6
SMDAT2/GPF7
IT8512E-L

ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4
ADC5/GPI5
ADC6/GPI6
ADC7/GPI7
DAC0/GPJ0
DAC1/GPJ1
DAC2/GPJ2
DAC3/GPJ3
DAC4/GPJ4
DAC5/GPJ5

C3006
10UF/10V

1
2

1
2

C3004
0.1UF/10V

C3005
0.1UF/10V

SUSC_EC#_C
SUSB_EC#_C
CTX0

119

CRX0

2
2
T3008

0402
0402

SUSC_EC#
SUSB_EC#

AC_IN_OC#

124
16

BAT1_IN_OC# <90>
RFON_SW# <53,56,61>
PWRLIMIT#

COLOREN#

19
82
83
84
125
35
17
20

<88>

PWRLIMIT# <3,90>
PM_SUSC# <22>
LCD_BACKOFF# <45>
FAN0_TACH <50>

T3053

VSUS_ON
EGAD
EGCS#

VSUS_ON

1
1
R3027

1 10KOhm 2

EXP_GATE#

R3021

2 47KOhm

BAT1_IN_OC#

R3028

1 10KOhm 2

PWRLIMIT#

R3023

2 47KOhm

BAT2_IN_OC#

R3030

1 10KOhm 2

AC_IN_OC#

1
3
3
1

TP_CLK
TP_DAT
SUSB_EC#_C
SUSC_EC#_C

RN3001A
RN3001B
RN3001C
RN3001D

<81,93>

PWR_SW#

BAT2_IN_OC#

+3VA_EC

1
3
5
7

4.7KOHM
4.7KOHM
4.7KOHM
4.7KOHM

+5VS

SMB0_CLK
SMB0_DAT
SMB1_CLK
SMB1_DAT

2
4
6
8

RN3002A
RN3002B
RN3005B
RN3005A

<56>

4.7KOHM2
4.7KOHM4
4.7KOHM4
4.7KOHM2

R1.4--5

GND

LID_SW# <45,56>
CAP_ACK# <56>

107

PM_SUSB#

<22>

R3073
R3074

GFX_VR_ON

R3029
R3004

1
1

2 100KOHM
2 100KOHM

VSUS_ON
CPU_VRON

R3031
R3005

1
1

2 100KOHM
2 100KOHM

2
2

@
@

1 0Ohm
1 0Ohm

CAP_ACK#

<91>

+3VS

R3006

R1.4--5
SUSC_EC#
SUSB_EC#

PM_RSMRST#

R3022

R3025

1 10KOhm 2

A20GATE

R3026

1 10KOhm 2

RCIN#

2 100KOHM

+3VSUS

2 10KOhm

<57,91>
<36,43,57,91,92>

R3024

1 10KOhm 2

PM_PWRBTN#

NUM_LED# <56>
CAP_LED# <56>

66
67
68
69
70
71
72
73

NV_OVERT# 1

T3012

GFX_VR
1
1

SUS_PWRGD <81,92>
ALL_SYSTEM_PWRGD
<22,92>
VRM_PWRGD <80,92>
GFX_VR
<6>
ALS_AD
<56>
T3035
T3036

76
77
78
79
80
81

CPU_VRON

CPU_VRON <80>
PM_PWROK <22>
VSET_EC <88>
ISET_EC <88>
TP_LED
<31>
T3044

KB_ID0
KB_ID1

PM_SUSB#
PM_SUSC#

T3054

2 @ 0Ohm
1
R3062
BAT_LEARN
HSCK
NUM_LED#
CAP_LED#

<22>

iAMT EC strapping need to check


Note:
EXT_SMI#, EXT_SCI#, PU power plane
depend on ICH9 GPIO.

For X'tal

Note:

For EC Hardware Strap

Cload=12.5PF
place close to EC

I/O Base Address

R3046
10MOhm
2 @
1EC_XOUT

For iAMT pin name

Note: It can be programmable by EC fireware

X3001
32.768Khz
+/-20ppm/12.5PF

R3011 for IT8512BX & IT8512CX


C3009 & C3008 for IT8512DX

Note: It can be programmable by EC fireware.


PP Enable
4

C3016
15PF/50V

AC_PRESENT
PM_S4_STATE#
S4_STATE_ON
PM_SLP_M#
SLP_M_ON
EC_WLAN_PWR
MP_PWRGD
AC_PRESENT
LAN_WOL_EN
+3VM_PG
+1.5VM_+3VMCLK_PG
SUSPWR_ACK

2
1

GND

Note: Default Int. Pull-Low

1
2

EC_AGND

Share Memory

0.1UF/10V

C3001
0.1UF/10V

R2.0--1

C3002
0.1UF/10V

EC_AGND

+3VA_EC

EC_AGND
C3008

For PU / PD

EC_XIN

GND

0603

T3010

120

18
21
33
47
48

<57,91>
<36,43,57,91,92>

<22>

R2.0--1

1
1 SL3000
SL3001

PM_RSMRST#

0603

For +3VPLL
Put beside pin 121

+3VACC

SL3003
1

C3007
0.1UF/10V

SL3004

+3VS

GAME_LED_EC# <69>
LCD_BL_PWM <45>
FAN_PWM <50>
KB_LED# <31>

T3007

<45,56>
<56>

PWR_LED#
CHG_LED#

T3013

3G_ON 1

CK32K
CK32KE
PS2CLK0/GPF0
PS2DAT0/GPF1
PS2CLK1/GPF2
PS2DAT1/GPF3
PS2CLK2/GPF4
PS2DAT2/GPF5

BATSEL_3S#

108
109
123
112

93
94
95
96
97
98
99

C3003
10UF/10V

R2.0--1

24
25
28
29
30
31
32
34

PM_CLKRUN#

GPH0/ID0
GPH1/ID1
GPH2/ID2
GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6

@
2

11

74
AVCC

TMRI0/WUI2/GPC4

RI1#/WUI0/GPD0
RI2#/WUI1/GPD1
GINT/GPD5
TACH0/GPD6
TACH1/GPD7

SMBus

Battery
Thermal sensor

TP_CLK
TP_DAT

85
86
87
88
89
90

CRX/GPC0

PS/2

<20> PCH_SPI_OV
T3030

FLRST#/WUI7/GPG0/TM
FLCLK
FLAD3/GPG6
FLAD2/SO
FLAD1/SI
FLAD0/SCE#
FLFRAME#/GPG2

KBMX

<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<22> PM_PWRBTN#
<37> OP_SD#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

58
59
60
61
62
63
64
65

RXD/GPB0
TXD/GPB1
CTX/GPB2
RING#/PWRFAIL#/LPCRST#/GPB7

GPIO

T3028
SO
SI
SCE#

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/GPA6
PWM7/GPA7

FLASH ROM

1PM_THERM#_EC 106
105
1
104
103
102
101
1
100

T3032
SCK

LAD0
LAD1
LAD2
LAD3
LPCCLK
LFRAME#
LPCRST#/WUI4/GPD2
SERIRQ
ECSMI#/GPD4
ECSCI#/GPD3
GA20/GPB5
KBRST#/GPB6
WRST#

LPC

SL3002
R2.0--1
2
1
0402
<20,44> LPC_FRAME#
<3,7,24,32,33,38,40,43,53,64,70>
BUF_PLT_RST#
<20> INT_SERIRQ
<25> EXT_SMI#
<21> EXT_SCI#
<25> A20GATE
<25> RCIN#
<32>
EC_RST#

<24> CLK_KBCPCI_PCH
D

U3001

10
9
8
7
CLK_KBCPCI 13
6
22
5
15
23
126
4
EC_RST# 14

VCC

RNX3004D
RNX3004C
RNX3004B
RNX3004A

VBAT

8
6
4
2

+3VA_EC
L3001
120Ohm/100Mhz
1
2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
AVSS

47OHM
47OHM
47OHM
47OHM

+3VA

1
12
27
49
91
113
122
75

7
5
3
1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY

<20,44>
<20,44>
<20,44>
<20,44>

26
50
92
114
121
127

+3VS

+3VA_EC

+3VA_EC

+3VACC

+3VA_EC

C3017
15PF/50V

GND

+3VA_EC

R3053
3.3KOhm
ME_SUSPWRDNACK
<22>
ME_AC_PRESENT <22>

R3043
3.3KOhm

C3019
0.1UF/16V

1 0Ohm
1 0Ohm

SCE#
SO

@
@

2
2
2

R3066
R3067

+3VA_EC
EGAD
EGCS#

U3003
1
2
3
4

SO_ROM
ROM_WP#

R2.0--1

CE#
VDD
SO HOLD#
WP# SCK
VSS
SI

8
7
6
5

ROM_HD#
SCK
SI

SST25VF016B

(16Mb)

GND
A

+3VA_EC
+3VS
+3VSUS

+3VA_EC

<32>

+3VS

<16,17,20,21,22,23,24,25,26,27,28,29,32,36,37,40,43,44,45,46,48,50,51,53,56,57,64,65,66,69,70,80,91,92>

+3VSUS

<27,33,34,37,53,81,82,92>

Title : EC_IT8512(1)
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

30

of

99

EMI

D3101
D

KSO15

KSO14

KSO12

GND

1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
7
5
3
1

@
1
2
3

KSO10

PACDN045YB6
D3102
KSO7

KSO0

KSI1

GND

@
1

KSI7

2
3

KSO9

PACDN045YB6
D3103
KSI2

KSI4

KSO3

GND

@
1

KSI6

2
100PF/50V
4
100PF/50V
6
100PF/50V
8
100PF/50V
2
100PF/50V
4
100PF/50V
6
100PF/50V
8
100PF/50V
2
100PF/50V
4
100PF/50V
6
100PF/50V
8
100PF/50V
2
100PF/50V
4
100PF/50V
6
100PF/50V
8
100PF/50V
2
100PF/50V
4
100PF/50V
6
100PF/50V
8
100PF/50V
8
100PF/50V
6
100PF/50V
4
100PF/50V
2
100PF/50V

CN3101A
CN3101B
CN3101C
CN3101D
CN3102A
CN3102B
CN3102C
CN3102D
CN3103A
CN3103B
CN3103C
CN3103D
CN3104A
CN3104B
CN3104C
CN3104D
CN3105A
CN3105B
CN3105C
CN3105D
CN3106D
CN3106C
CN3106B
CN3106A

KSO7
KSO0
KSI1
KSI7
KSO9
KSI6
KSI5
KSO3
KSI4
KSI2
KSO1
KSI3
KSI0
KSO13
KSO5
KSO2
KSO4
KSO8
KSO6
KSO11
KSO15
KSO14
KSO12
KSO10

@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

2
3

KSI5

PACDN045YB6
D3104
KSO8

KSO6

KSO11

GND

@
1

KSO2

J3101
KSO4

PACDN045YB6
D3105

KSI0

KSO13

KSO5

GND

Keyboard

25
@
1

KSO1

2
3

KSI3

PACDN045YB6

26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SIDE2 19
20
21
22
23
24
SIDE1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

KSO15
KSO14
KSO12
KSO10
KSO11
KSO6
KSO8
KSO4
KSO2
KSO5
KSO13
KSI0
KSI3
KSO1
KSI2
KSI4
KSO3
KSI5
KSI6
KSO9
KSI7
KSI1
KSO0
KSO7

ZIF_CON_24P

<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>

R1.4--5

R2.0--1

+5V

J3103
5
1
2
3
4
6

KB_LED_MOS#
KB_LED_MOS#
D3107
TP_CLK

BT_LED_CON#

CHG_LED_CON#

@
1

GND

TP_DAT

R3110
R3113

1
1

@
@

2 0Ohm
2 0Ohm

SIDE2
1
2
3
4
SIDE1
FPC_4P

2
WLAN_LED_CON#

PACDN045YB6

+5V
2

R1.4--5

R3105
10KOhm

J3102
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

TP_LED

C3104
0.1UF/16V

<56>
<56>
<56>
<56>

PWR_LED_CON#
CHG_LED_CON#
BT_LED_CON#
WLAN_LED_CON#
<30>

TP_CLK

<30>
2

TP_DAT
1
L3101
120Ohm/100Mhz

+5VS

1
2

C3103
0.1UF/16V

+5V
+5VA

C3101
0.1UF/16V

16
15 SIDE2
14
13
12
11
10
9
8
7
6
5
4
3
2 SIDE1
1

18

<30>

KB_LED_MOS#

D
Q3102

<30>

KB_LED#

1
G

2 S

2N7002

R1.2--12
17

WTOB_CON_16P

Bottom Contact

TouchPAD/TP_LED
A

+3VA_EC
+3V

+3VA_EC

<30,32>

+3V

<24,33,43,45,57,61,64,69,91>

+3VS

+3VS

<29,48,80,91,92>

+5VA

+5VA

<56,81,82,83>

+5V

<36,44,45,52,56,57,65,69,91>

+5VS

<27,30,37,45,46,48,50,51,56,57,70,80,91>

+5V
+5VS

Title : EC_IT8512(2)KB, TP,FP


Size
C
Date:

Engineer:

BU2/RD1

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

31

of

99

Thermal Policy

+3VS

10KOhm
R3206

<50> CPU_THERM#

Force-OFF Switch

2
1
R3200 0Ohm @
SL3201
2
1
0402

<70> VGA_THERM#

CPU_VGA_THERM#

R2.0--1
IT8752 has built-in level detection for
power-on reset circuit

SW_FORCE_OFF#
SW3201
1

+3VA_EC

1
R3202
33Ohm
@

UM6K1N
Q3202B
3

TP_SWITCH_4P
@

<92> FORCE_OFF#

2
+VTT_CPU
2 R3201 1
330Ohm

1 B

1 100KOhm

D3202

1 1SS355

D3203

1 1SS355

R1.2

EC_RST#

<30>

C3201

Output Signal
4.7UF/6.3V

BUF_PLT_RST#

<3,7,24,30,33,38,40,43,53,64,70>

Q3202A
UM6K1N

R3204

3
C Q3201
PMBS3904
E
2

@
1 56Ohm

2
R3209

<3,25> H_THRMTRIP#

Input Signal

+VTT_CPU
+3VA_EC
+3VS

+VTT_CPU <3,6,7,25,26,27,29,57,82>
+3VA_EC

<30>

+3VS

<29,48,80,91,92>

Title : RST_Reset Circuit


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

32

of

99

+3VS
+3VSUS

+3VS

<29,48,80,91,92>

+3VSUS

<27,30,34,37,53,81,82,92>

AR8131:Remove C3322,C3321,L3303,L3304

AR8131:Remove R3301,C3318,C3319

AR8121:Remove C3337,R3324

AR8121:Remove L3302,C3317,R3302,C3336

SP3301

5.1KOHM
@

R2.0--1

C3330

2
2

VDD_+2.5V

1UF/10V

VDD_+2.5V
C3305

C3304

0.1UF/16V

C3306

0.1UF/16V

C3307

0.1UF/16V

1UF/10V

C3303

1
C3302
10UF/6.3V

C3301
10UF/6.3V

RN3301A
RN3301B
RN3301C
RN3301D
RN3302A
RN3302B
RN3302C
RN3302D

1 0.1UF/25V2 CX3301A
C3305 close to pin15

3 0.1UF/25V4 CX3301B

C3301 C3302 C3303 C3304 close to pin2

5 0.1UF/25V6 CX3301C

+AVDDL

C3313

0.1UF/16V

C3312

0.1UF/16V

C3314

0.1UF/16V

C3315

0.1UF/16V

C3311

0.1UF/16V

C3310

0.1UF/16V
@

C3309

0.1UF/16V
@

1UF/10V

C3308

7 0.1UF/25V8 CX3301D

T3300

GND

GND

49.9OHM2
49.9OHM4
49.9OHM6
49.9OHM8
49.9OHM2
49.9OHM4
49.9OHM6
49.9OHM8

R2.0--1
AR8121:Remove C3328

GND

AR8131/25MHz: Remove C3328

GND

C3308 close to pin45/46

27PF/50V

27PF/50V

C3329

25Mhz

+2.5_Pin5
C3327
0.1UF/16V

R0402
R2.0--1

+3V_LAN

L3301
1

+3VSUS

10PF/50V

X3301
2
1

X1_LAN

+1.7_Pin6

0Ohm
2 VDD_+2.5V

GND

SP3303
1

C3328
2
1EXT_25/48 1
@

0Ohm
2
+3V_LAN

C3326
10UF/6.3V

GND

GND

For AR8131 : Remove R3309

C3325
0.1UF/16V
@

R3314
0Ohm
@

1
3
5
7
1
3
5
7

L_TRDP0
L_TRDN0
L_TRDP1
L_TRDN1
L_TRDP2
L_TRDN2
L_TRDP3
L_TRDN3

R3309
1
@

<21>

X2_LAN

GND

CLK_REQ5_LAN#

R3305
1
@
R3306
10KOhm
@

1
1

53
54
55

AR8131-AL1E

58
57
56

0402

61
60
59
GND12
GND11
GND10
GND4
GND5
GND6

GND

GND9
GND8
GND7

SL3302
2

+DVDDL

GND1
GND2
GND3

VDD_+2.5V

80Ohm/100Mhz

U3301B

50
51
52

+DVDDL
CLK_REQ_LAN

BC807-25
Q3301
@

GND

+3V

<34>
<34>
<34>
GND <34>
<34>
<34>
<34>
<34>

+AVDDL

Q3300
2N7002

GND

AR8131: Remove R3314

BUF_PLT_RST#

AR8121: Remove R3313

S 2

<3,7,24,30,32,38,40,43,53,64,70>

+DVDDL

AR8131-AL1E

GND
2

GND

C3324
0.1UF/16V
@

VDD_+2.5V
+AVDDL

0402

+AVDDL

R3311
2.37KOHM

GND

SL3312
1

36
35
34
33
32
31
30
29
28
27
26
25

13
14
15
16
17
18
19
20
21
22
23
24

GND
GND

AVDDL3
NOCONN
TESTMODE
SMDATA
DVDDL2
SMCLK
TWSI_DATA
TWSI_CLK
DVDDL1
CLKREQn
LED_LINK1000n
AVDDH2

AR8131/25MHz:Remove R3310 C3333

Q3301 close to Pin8

RBIAS

0.1UF/16V
2

1UF/10V

C3331

For AR8121: Remove C3327 R3308

C3332

AR8121:Remove R3310

C3333
1000PF/16V
@

R3310 @
4.7KOhm

+AVDDL
X1_LAN
X2_LAN
+AVDD_VCO1

For AR8131: Remove R3305,R3306,C3324,C3325,C3326,Q3301

+2.5_Pin5
+1.7_Pin6
SEL_25M

chip

PCIE Tx,Rx

Chip pin Tx,Rx

PCIE_WAKE#

LX
VDD3V
PERSTn
WAKEn
VDD25V
VDD17
SEL_25MHz
VDD11_REG
XTLO
XTLI
AVDD_REG
RBIAS

<21>
<21>

<22,44,53>

Not overclock:Remove R3304

+AVDDL

pin name 2.5V

pin#5

1
2
3
4
5
6
7
8
9
10
11
12

TRXP0
TRXN0
VDDHO
AVDDL1
TRXP1
TRXN1
AVDDH1
TRXP2
TRXN2
AVDDL2
TRXP3
TRXN3

+1.7_Pin1

With overclock:Remove R3303

GND

+3V_LAN

C3323
0.1UF/16V

C3334
0.1UF/16V

GND
LED_10_100n
LED_ACTn
DVDD_REG2
DVDD_REG1
RX_N
RX_P
AVDDL5
REFCLKP
REFCLKN
AVDDL4
TX_P
TX_N

U3301A

PCIE_RXP6_GLAN
PCIE_RXN6_GLAN

C3335
0.1UF/16V

49
48
47
46
45
44
43
42
41
40
39
38
37

GND

<21>
<21>

+AVDD_VCO2

0.1UF/16V
@

R2.0--1

+AVDDL
1
1

1
+DVDDL
+DVDDL
RXN
RXP
+AVDD_VCO2

C3336

C3319
1UF/10V
@

+1.7_Pin6

R0402
R2.0--1

2
R0402

R2.0--1

CLK_PCIE_LAN <21>
CLK_PCIE_LAN# <21>

2
2

GND

VDD_+2.5V

GND

PCIE_TXN6_C
PCIE_TXP6_C

R3315

R2.0--1
SP3300

ground pad

C3318
1UF/10V
@

C3337
0.1UF/16V

SP3302
1

+1.7_Pin1

1
2

C3317
10UF/6.3V

+AVDD_CEN_LAN

4.7UH

3
C

L3302
1

E
2

C3316
@
0.1UF/16V

R0402

AR8121:Remove R3315

+AVDD_VCO1

C3318 close to Pin 1

0Ohm
2
@

1 B

R3301
1

+AVDDL1 R3303
0Ohm

AR8131 with overclock: Remove R3315

GND

GND

R1.4--6

Title : LAN_AR8131
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

33

of

99

STUFF for NON_IAMT

STUFF for IAMT

R1.4-2

SP3400
+VLAN

+3VSUS

R0402
SL3400A
LTRLP0

24
23

L_CMT0
LTRLP0

RN3401A
75OHM 2

LTRLM0

L_TRDN1

L_TRDP1

4
5

IP4220CZ6

<33>

L_TRDN1

<33> L_TRDP2

L_TRDP2

+VLAN

21
20

L_CMT1
LTRLP1

19

LTRLM1

7
8

18
17

L_CMT2
LTRLP2

RN3401B
75OHM 4

LTRLP1

RN3401C
75OHM 6

L_TRDN2

<33> L_TRDN2

16

LTRLM2

<33> L_TRDP3

10
11

15
14

L_CMT3
LTRLP3

MOAT

L_TRLP1

0603

U3401

LX3402
90Ohm/100Mhz
@

LTRLP2

0603
SL3402A
0603

RN3401D
75OHM 8

L_TRLM1

L_TRLP2

LTRLP3

0603
SL3403A

LX3403
90Ohm/100Mhz
@

LAN_GND

0603

MODULAR_JACK_8P
L_TRLP0
L_TRLM0
L_TRLP1
L_TRLP2
L_TRLM2
L_TRLM1
L_TRLP3
L_TRLM3

L_TRLM2

L_TRLP3

1
2
3
4
5
6
7
8

LX3404
90Ohm/100Mhz
@

0603

L_TRLM3

NP_NC2
P_GND2

12
10

Title : LAN_HVL,RJ45
Engineer:

BU2/RD1
Size
C
Date:
3

9
11

J3401

R2.0--1

P_GND1
NP_NC1

SL3403B

LTRLM3

1
2
3
4
5
6
7
8

C3415
1500PF/2KV
@

C3411
1500PF/2KV

1
0.1UF/16V

1
0.1UF/16V

LTRLM2

IH-008

LTRLM3

13

2
C3404

IP4220CZ6

1
0.1UF/16V

L_TRDN3

2
C3403

1
1UF/10V

2
C3401

L_TRDP3

12

<33> L_TRDN3

2
C3402

GND

J3401

C3415

SL3402B

LAN_GND

GND

SL3401B

LTRLM1

0603
SL3401A

D3402

LTRLM0

L_TRDN0

<33>

GND
L_TRDP1

22

C3411

L_TRLM0

<33>

LAN layout note:

SL3400B

+VLAN

L_TRLP0

LX3401
90Ohm/100Mhz
@

1
2

L_TRDP0

<33>

U3401

L_TRDN0

0603

R2.0--1
4

L_TRDP0

+AVDD_CEN_LAN
D3401

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

34

of

99

Title : MDC_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

35

of

99

Not support 3G Voice.


(Pin43/44)

GND_AUDIO

+5V_AUDIO

SPDIF HDMI

R2.0--1

1
T3607

2
C3639
C3623
100PF/50V
@

SPDIFO
SPDIFI/EAPD
SIDE_R(port_H_R)
SIDE_L(Port_H_L)
LFE(Port_G_R)
CENTER(Port_G_L)
AVSS2
SURR_R(Port_A_R)
JDREF
SURR_L(Port_A_L)
AVDD2
PIN37_VREFO

LINE IN detect.

<65>

EXT MIC detect.

<65>

LINE1_JD
MIC1_JD

ALC663/660-VD_GR

R3623

1 10KOhm 1%

R3613

1 20KOhm 1%

FRONT-R
FRONT-L
Sense_B

C3645
C3646
R3611
R3612

1
1

C3630

1 1UF/10V

C3631

1 1UF/10V

PC_BEEP_C
2
47KOhm

R2.0--1

1
C3622

AC_SPK_R <37,38>
AC_SPK_L <37,38>
AC_HP_L
AC_HP_R

C3636

2 2.2UF/10V

C3621
100PF/50V

<37>
<37>

INT Speaker
HeadPhone Out

GND_AUDIO
MIC1_VREFOUT

INT MIC IN.

<65>

C3624
0.1UF/16V

C3611
10UF/10V

@
C3613
0.1UF/16V

C3612
1UF/10V

C3614
10UF/10V
C

R2.0--1
GND_AUDIO

GND_AUDIO

Sense_A

1
C3640
1
C3641

2
1UF/10V
2
1UF/10V

LINEIN_R

<65>

LINEIN_L

<65>

2
C3635
2
C3637

1
1UF/10V
1
1UF/10V

MIC_IN_AC_E

LINE IN.

<65>

EXT MIC IN.

R2.0--1
MIC2VREFOUT

R3602

R3603

2 0Ohm

R3604

2 0Ohm

R3609

2 0Ohm

R3610

2 0Ohm

MIC2_VREFOUT

+5V

<31,44,45,52,56,57,65,69,91>

+3VS

<29,48,80,91,92>

<38>

INT MIC Vref.

2 0Ohm

R3615
4.7KOhm

PC_BEEP
2
0.1UF/16V

1
R3614

SB_SPKR

<20>

Jack detect

+5V_AUDIO

+5V

SPDIF OUT detect.

<65>
<65>

AC_HP_L
AC_HP_R
2 2.2UF/10V

1
1

VREF_CODEC

+3VS

PC BEEP

LINE2_JD

2 63.4Ohm
2 63.4Ohm
C3638 1

MIC_IN_AC_E_L

<38> MIC_IN_AC_I

SPDIF_JD

2 5.1KOhm

2 1UF/10V
2 1UF/10V

MIC_IN_AC_E_R

INT MIC IN

2 10KOhm

MIC2_VREFOUT_660

13
14
15
16
17
18
19
20
21
22
23
24

C3619
22PF/50V
@

10UF/10V

1%

PC_BEEP

C3618

1
C3617
0.1UF/16V

1
2

1
2

C3616
0.1UF/16V

R3618

1 33Ohm
R3625

<20> ACZ_SDIN0_AUD
<20> ACZ_SYNC_AUD
<20,37> ACZ_RST#_AUD

FRONT_R(Port_D)
FRONT_L(Port_D)
Sense_B
AGPIO
MIC1_VREFO_R
LINE2_VREFO
MIC2_VREFO
LINE1_VREFO
MIC1_VREFO_L
VREF
AVSS1
AVDD1

36
35
34
33
32
31
30
29
28
27
26
25

+3VS_DVDD

DVDD
GPOI0/DMIC_CLK/SPDIFO2
GPIO1/DMIC_DATA
DVSS1
SDATA_OUT
BCLK
DVSS7
SDATA_IN
DVDD_IO
SYNC
RESET#
PCBEEP

R3607

1%

Sense_A
LINE2_L(Port_E_L)
LINE2_R(Port_E_R)
MIC2_L(Port_F_L)
MIC2_R(Port_F_R)
CD_L
CD_GND
CD_R
MIC1_L(Port_B_L)
MIC1_R(Port_B_R)
LINE1_L(Port_C_L)
LINE1_R(Port_C_R)

1
1

T3606
T3605

120Ohm/100Mhz

1
2
3
4
5
6
7
8
9
10
11
12

<38>

020J-000S000

GND_AUDIO

MONO_OUT

U3601

<20> ACZ_SDOUT_AUD
<20> ACZ_BCLK_AUD

1
1UF/10V
@

48
47
46
45
44
43
42
41
40
39
38
37

<65> SPDIF1_OUT

R2.0--1

L3602

EAPD

SPDIF OUT

C3608
0.1UF/16V

<70> SPDIF2_OUT

<37>

+3VS

C3610
1UF/10V

R2.0--1

2 1%
20KOhm

1
R3617

Audio Codec

GND_AUDIO

Audio Power
FOR ADJUST MODE:
Vo=1.25*(1+R3706/R3705)
=1.25*( 1+ 100K/34.8K) = 4.84
Check for fixed type.

T3602
+5V_AUDIO

2 0Ohm
1
2
3

1000PF/50V
1
2
@
C3606
1 R3606 2

0606-000X000

100KOhm

R3601
1

C3603
1UF/10V

0.1UF/16V

R3605
34.8KOhm

0.1UF/16V

C3609

G923-470T1UF

0.1UF/16V

10UF/10V

SET
OUT

C3605

C3602

C3601

>30 mil
or shape

SHDN#
GND
IN

2 0Ohm

R3622

+5V
A

U3602

R3624

SUSB_EC#

<30,43,57,91,92>

Title : AUD(1)_ALC663VD

2
0Ohm

Size
GND_AUDIO

C
Date:

Engineer:

BU2/RD1

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

36

of

99

+5VS_AMP

U3701

GND_AUDIO

AMP_LIN

C3704
1UF/10V

C3705
1UF/10V

GND_AUDIO

2 1UF/10V

AMP_RIN

GND_AUDIO

+5VS_AMP

+5VS_AMP

Reserved for EMI


INTSPKL-

R3713
10KOhm
@
2

R3701
10KOhm
@

R3715
0Ohm

R3714
0Ohm

GND_AUDIO

GND_AUDIO

INTSPKL+

D3703
0603-050E101NP-LF
@

GAIN0

GAIN1

CX3702 1

AMP_R

SIDE1

GND_AUDIO

2 10KOhm

SIDE2

WTOB_CON_4P

2 3KOhm

R3709

4
3
2
1

G1431F2U

C3706
0.22UF/16V

GND_AUDIO

RX3702 1

4
3
2
1

INTSPKR-

D3704
0603-050E101NP-LF
@

INTSPKR+
1

2 1UF/10V

J3701
INTSPKR+
INTSPKRINTSPKL+
INTSPKL-

INTSPKR-

D3705
0603-050E101NP-LF
@

D3706
0603-050E101NP-LF
@
2

2 10KOhm

CX3701 1

Internal Speaker Conn.


DE-POP#
INTSPKR+
AMP_RIN

R3708

AMP_L

21
20
19
18
17
16
15
14
13
12
11

2 3KOhm

RX3701 1

INTSPKL-

GND5
GND1
GND4
GAIN0
SHUTDOWN#
GAIN1
ROUT+
LOUT+
RINLINVDD
PVDD1
PVDD2
RIN+
ROUTLOUTGND3
LIN+
NC
BYPASS
GND2

GND_AUDIO

1
2
3
4
5
6
7
8
9
10

GAIN0
GAIN1
INTSPKL+
AMP_LIN

C3703
0.1UF/16V

C3702
0.1UF/16V

1
2

C3701
1UF/10V

GND_AUDIO

<36,38> AC_SPK_R

+5VS_AMP
L3701
80Ohm/100Mhz
1
2

<36,38> AC_SPK_L

+5VS

Gain0,Gain1 Short to GND?

R3706

+12V

<30>

OP_SD#

2
3

DE-POP#

Q3705A
UM6K1N

+5VS

+5VS

+3VSUS

Q3702A
UM6K1N
6

HP1_R

R3711

2 68OHM

AC_HP_R_CON

<65>

HP1_L

R3712

2 68OHM

AC_HP_L_CON

<65>

R2.0--1

C3707
0.1UF/16V
@

D3702
BAT54AW

Q3704A
UM6K1N
1

2 0Ohm

<36>

AC_HP_L

4
UM6K1N
Q3704B

3
Q3702B @
UM6K1N

AC_HP_R

MUTE_POP#
Q3705B
UM6K1N

5
4

<20,36> ACZ_RST#_AUD

<36>

EAPD

R3707
10KOhm

D3701
BAT54AW

<36>

R3710
2.2MOhm

1
R3702
100KOHM
2

R3704
10KOhm
@

+3VSUS

+3VS

+3VS

R3705

2 0Ohm
B

<27,30,31,45,46,48,50,51,56,57,70,80,91>

+3VSUS

<27,30,33,34,53,81,82,92>

+12V

+12V

<91>

+3VS

+3VS

<29,48,80,91,92>

Title : AUD(2)_AMP,JACK
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

37

of

99

<36>

MIC2_VREFOUT

R3803
330Ohm

<6,26,57,70,85>
1

+1.8VS

+1.8VS

1 0.1UF/10V

1 0.1UF/10V

RNX3800B

C3801

GND_AUDIO
3

R3801
1KOhm

R2.0--1

1 0.1UF/16V

CX3803 2

1 0.1UF/10V

C3802

1 0.1UF/16V

C3804

1 0.1UF/16V

1
2
3
4
5
6
7
8
9
10
11
12

C3803
0.01UF/16V

1%

1 0.1UF/10V

GND_AUDIO

<36> MIC_IN_AC_I
1

<24> CLK_DSPPCI

1KOhm

C3805
1UF/10V

4
3

1KOhm

RN3801B

NC11
MIC1_N
TEST
NC12
NC13
PWD#
NC14
NC15
NC16
SCK
NC17
NC18

1 0.1UF/10V

OMNI_MIC_N

<45>

36
35
34
33
32
31
30
29
28
27
26
25

R3807
2.2KOhm
TEST
PWD#

GND_AUDIO

+1.8VS
PWD#

R3808

2 10KOhm

SHI_S

R3810

2 10KOhm

TEST

R3809

2 100KOhm

FM2010-NE

+1.8VS

SMB_CLK_S <7,16,17,28,29,44,53,69>
SMB_DAT_S <7,16,17,28,29,44,53,69>

GND_AUDIO

R2.0--1

NC6
VREF
LINE_IN_P
NC7
LINE_IN_N
LINE_OUT
NC8
VCOM
VDD_CODEC
NC9
XTAL_IN(CLK_IN)
NC10

CLK_DSP

RN3801A

CX3807 2

<45>

10KOHM 4

U3801

OMNI_MIC_P

C3808
0.01UF/16V

RNX3800A

SHI_S

10KOHM 2

<45>

1
2+1.8VS_FM2010
L3801
120Ohm/100Mhz

49
48
47
46
45
44
43
42
41
40
39
38
37

CX3802 2

GND_AUDIO

GND2
NC19
VSS_CODEC
NC20
NC21
NC22
NC23
NC24
NC25
MIC0_P
MIC0_N
MIC1_P
NC26

<36,37> AC_SPK_L

1 0.1UF/10V

+1.8VS

1 10KOhm 1%

NC1
XTAL_OUT
NC2
IRQ_ANA
GND1
NC3
VDD
SHI_S
RESET#
NC4
SDA
NC5

CX3801 2

RX3805 2

13
14
15
16
17
18
19
20
21
22
23
24

<36,37> AC_SPK_R

1 0.1UF/10V

UNI_MIC_N
R3806
2.2KOhm

GND_AUDIO
1

CX3806 2
CX3808 2

<45>

R3805
2.2KOhm

<36> MONO_OUT

UNI_MIC_P

1 0.1UF/10V

CX3805 2

GND_AUDIO

C3807
0.01UF/16V

CX3804 2

C3809
1UF/10V

R3804
2.2KOhm

BUF_PLT_RST#

<3,7,24,30,32,33,40,43,53,64,70>

C3806
0.1UF/16V

Title : AUD(3)_FM2010
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

38

of

99

Title : AUD(4)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

39

of

99

<21> CLK_1394

R4014

0OHM

XIN_1394

R1.2,item L1

SL4001

X4001
2

0402

MFIO0/SDWP/MSBS/XDD7
2

XOUT_1394

MFIO1/SDD1/

/XDD6

GND

MFIO3/SDD7/

GND

XOUT_1394

GND

TPB0+_1

Guard GND

IEEE_1394_4P

12G130012043

TPA0+_1
TPA0-_1

R4007
56Ohm

1
R4005

1%

1
GND

+3VS_CR
<21> CLK_REQ4#_CB

+3VS_CR
SP4000
2

BUF_PLT_RST#

C4069

GND

GND

0402

TPBIAS0
AVCC_3V
UDIO0
MFCD0#
MFCD1#
UDIO1
UDIO2
UDIO3
PERST#
TEST
VCC_3V_1
PCIE_VOUT1

/XDCE#

MFIO13/

/MSD7/XDRE#

MFIO14/

/MSCLK/XDR/B#

+1.2VS_PCIE_CR
C4071
C4072
0.1UF/16V
0.1UF/16V
2

R5U230

13
14
15
16
17
18
19
20
21
22
23
24

GND
GND

0.1UF/16V

+3VS_CARD
GND +3VS_CARD_IC
SP4001
1
2

MF_VOUT
MFIO10
MFIO09
MFIO08
MFIO07
MFIO06
MFIO05
MFIO04
MFIO03
MFIO02
MFIO01
MFIO00

0.1UF/16V

C4078
1UF/25V

CR_UDIO0
SD_CD0#
MS_CD1#
CR_UDIO1
1
CR_UDIO2
T4023 TPC26T
1
CR_UDIO3
T4024 TPC26T
1
T4025 TPC26T
1
2
0402
SL4002 GND
+3VS_CR

1
SL4003

1
2
3
4
5
6
7
8
9
10
11
12

<3,7,24,30,32,33,38,43,53,64,70>

R0603

/XDCLE

MFIO12/

C4073

TPBIAS0

MFIO11/SDD2/

+3VS_CR

2
5.1KOhm

C4067 270PF/50V

+3VS

MFIO10/SDD3/MSD3/XDALE

MFIO11/SDD2/XDCLE

GND
U4003

R2.0--1

MFIO12/XDCE#

MFIO9/SDD4/MSD6/XDWE#

XDR/B#
MS_CLK

Guard GND

R4006
1% 56Ohm 1%

RN4000C 6
4R8PS

TPA0+_1
TPA0-_1

IEEE1394
RN4000D 8
4R8PS

MFIO13/MSD7/XDRE#

2 10Ohm
2 10Ohm

Common
Choke

TPB0+_1

MFIO8/SDCMD/MSD2/XDWP#

49
48
47
46
45
44
43
42
41
40
39
38
37

GND
TPAP0
TPAN0
TPBP0
TPBN0
XI
XO
PCIE_VOUT2
MFIO14
MFIO13
MFIO12
MFIO11
VCC_3V_2

P_GND2

1
2
3
4

36
35
34
33
32
31
30
29
28
27
26
25

MFIO10/SDD3/MSD3/XDALE
R0603
MFIO9/SDD4/MSD6/XDWE#
MFIO8/SDCMD/MSD2/XDWP#
MFIO7/SDD5/MSD4/XDD0
MFIO6/XDD1
MFIO5/SDCLK/MSD0/XDD2
MFIO4/SDD6/MSD5/XDD3
MFIO3/SDD7/XDD4
MFIO2/SDD0/MSD1/XDD5
MFIO1/SDD1/XDD6
MFIO0/SDWP/MSBS/XDD7

R4013 1
R4012 1
R4009 1

2 10Ohm
2 10Ohm
2 10Ohm

MSD0
SD_CLK
XDD2
C

REFCLKP
REFCLKN
RXP
RXC
RXN
PCIE_VIN2
TXP
TXN
AGND
CPO
PCIE_VIN1
RREF

1
2
3
4

GND

P_GND1

TPB0-_1

C4033
10UF/6.3V
GND

R4010 1
R4011 1

MFIO14/MSCLK/XDR/B#

Guard GND

TPB0-_1

/XDD1

MFIO7/SDD5/MSD4/XDD0

R4002
56Ohm
1%

C4070
0.1UF/16V

1
R4003
56Ohm
1%
2

@ L4001
LTPB0LTPB0+
LTPA0LTPA0+

MFIO5/SDCLK/MSD0/XDD2

+1.2VS_PCIE_CR

GND

XIN_1394
J4002

/XDD4

MFIO4/SDD6/MSD5/XDD3

TPBIAS0

0.33UF/16V

RN4000A 2
4R8PS

C4040
22PF/50V

MFIO6/
1

C4039
RN4000B 4
4R8PS

C4066
22PF/50V

Closed to Chip

Closed to 1394 Connector


Co-Layout

MFIO2/SDD0/MSD1/XDD5

24.576Mhz

+1.2VS_PCIE_CR
+1.2VS_PCIE_CR

8
7
6
5

R4034
100KOhm

VCC A0
WP
A1
SCL A2
SDA GND

<21> PCIE_RXP5_CR
<21> PCIE_RXN5_CR

C4018 2
1 0.1UF/16V
C4019 2
1 0.1UF/16V

1
2
3
4

C4077

C4076
J4001

0.1UF/16V

R4008
5.1KOhm
1%

1 0.1UF/16V
2

CR_UDIO2
CR_UDIO3

GND

C4068

1
2
@

R4040
R4039
@ 10KOhm @ 10KOhm
CR_UDIO1

C4006

1500PF/50V

<21> PCIE_TXN5_C
+3VS_CR

R4033
100KOhm

0.022UF/16V
2
1 C4036

GND

GND

GND

PCIE_TXP_CR
PCIE_TXN_CR
MFIO11/SDD2/XDCLE
MFIO10/SDD3/MSD3/XDALE
MFIO8/SDCMD/MSD2/XDWP#

GND

+3VS_CARD

U4002
AT24C02N
@

MFIO8/SDCMD/MSD2/XDWP#

GND

GND

XDR/B#
MFIO13/MSD7/XDRE#
MFIO12/XDCE#
MFIO11/SDD2/XDCLE
MFIO10/SDD3/MSD3/XDALE
MFIO9/SDD4/MSD6/XDWE#
MFIO8/SDCMD/MSD2/XDWP#
MFIO7/SDD5/MSD4/XDD0
MFIO6/XDD1
SDD2
1 SL4018 2
0402 2
SDD3
1 SL4011
0402 2
SDCMD
1 SL4012
0402

0.1UF/16V

2
GND

+3VS_CR

<21> PCIE_TXP5_C
+3VS_CR

<21> CLK_PCIE_CR
<21> CLK_PCIE_CR#

PU:Disable SROM
PD:Enable SROM

MFIO2/SDD0/MSD1/XDD5
MFIO0/SDWP/MSBS/XDD7

GND

1 SL4020
0402
1 SL4013
0402
1 SL4014
0402
1 SL4017
0402

MS_CLK
MSD3

MSD2

2
2

MSD0
MSD1
MFIO0/SDWP/MSBS/XDD7_C

MS_CD1#

+3VS_CARD

MFIO1/SDD1/XDD6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

SD_CLK

1 SL4015 2
0402

SDD0

1 SL4016 2
0402

SDD1

XDD2
MFIO4/SDD6/MSD5/XDD3
MFIO3/SDD7/XDD4
MFIO2/SDD0/MSD1/XDD5
MFIO1/SDD1/XDD6
MFIO0/SDWP/MSBS/XDD7

+3VS_CARD

XD_CD#
MFIO0/SDWP/MSBS/XDD7
SD_CD0#

MS_CD1#

GND CARD_READER_36P

D4012
SD_CD0#

XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-D0
XD-D1
SD-DAT2
SD-DAT3
SD-CMD
4in1-GND1
MS-VCC
MS-SCLK
MS-DATA3
MS-INS
MS-DATA2
MS-DATA0
MS-DATA1
MS-BS
4in1-GND2
SD-VCC
SD-CLK
SD-DAT0
XD-D2
XD-D3
XD-D4
SD-DAT1
XD-D5
XD-D6
XD-D7
XD-VCC
XD-CD-SW
SD-WP-SW
SD-CD-SW
GROUND1
GROUND2
NP_NC1
NP_NC2

12G340003605

XD_CD#

3
2
BAT54C

+3VS_CARD

+3VS_CARD

C4074

0.1UF/16V

GND

C4034
10UF/6.3V

GND

put at J4002.14

put at J4002.23

Title : R5U230
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

40

of

99

+3VS

+3VS

<29,48,80,91,92>

Title : CB(2)_R5C833
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

41

of

99

+3VS

+3VS

<29,48,80,91,92>

+12V

+12V

<37,91>

Title : CB(3)_4in1 CardReader


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

42

of

99

@
0Ohm

CLKREQ3_NEWCARD#

3 RNX4300B
3

USB_P5+
NWCLK_EN

@
0Ohm

<21,44>

NewCard Header
Q4301
2N7002
@

J4301

<44> LPC_FRAME#_DBCARD

D4301

1
RNX4300A
1

<44> SMB_CLK_R
<44> SMB_DAT_R
+1.5VS_NW

<44>

1
20
8

+3VS

2
4

+1.5VS

14
12

STBY#
SHDN#
PERST#

OC#
1.5VOUT_1
1.5VOUT_2

3.3VIN_1
3.3VIN_2

AUXOUT

1.5VIN_1
1.5VIN_2

3.3VOUT_1
3.3VOUT_2

19
11
13

+1.5VS_NW

15

+3V_NW

3
5

+3VS_NW

<3,7,24,30,32,33,38,40,53,64,70>

6
7
21

BUF_PLT_RST#

AUXIN
SYSRST#
GND1
GND2

CPPE#
CPUSB#
RCLKEN
NC

10
9
18

CP_USB#
NWCLK_EN

+3V
+3VS

+1.5VS

<26,53,57,64,91>

+3V

<24,33,45,57,61,64,69,91>

+3VS

<29,48,80,91,92>

<21> PCIE_RXN3_NEWCARD
<21> PCIE_RXP3_NEWCARD
<21> PCIE_TXN3_C
<21> PCIE_TXP3_C

C4307
10UF/10V

1.35V~1.65V
Ave= 500 mA
Max= 650 mA

28
30

EXPRESS_CARD_26P

C4308
0.1UF/16V

+3V_NW

3.0V~3.6V
Ave= 200mA
Max= 275 mA

NewCard Ejecter

<44>

C4309
1UF/10V
@

P_GND1
P_GND2

C4310
0.1UF/16V

1
2

CARD_EJECTOR_2P
@

16

R5538D001

+1.5VS

C4304
0.1UF/16V

29
27

J4302
CP_PE#

17

+3V

2
1

2
+3V

If AUXIN use +3VSUS.


It would leakage from AUXIN to STBY,SHDN#,PERST#.

1 1KOhm

+1.5VS_NW

PE_RST#

+3VS_NW
<44> CLKREQ#_R
<44>
CP_PE#_R
<21> CLK_PCIE_NEWCARD#_PCH
<21> CLK_PCIE_NEWCARD_PCH

GND1
USB_DGND5
USB_D+ NP_NC1
CPUSB#
RESERVED1
RESERVED2
SMBCLK
SMBDATA
+1.5V_1
+1.5V_2
WAKE#
+3.3VAUX
PERST#
+3.3V_1
+3.3V_2
CLKREQ#
CPPE#
REFCLKREFCLK+
GND2
PERn0
PERp0
GND3
PETn0
NP_NC2
PETp0
GND6
GND4

R4301

C4303
10UF/10V

+1.5VS

C4306
0.1UF/16V
@

3.0V~3.6V
Ave= 1000mA
Max= 1300 mA

PE_RST#

C4305
10UF/10V
@

C4302
0.1UF/16V
@

SUSB_EC#

<44>

U4301

C4301
10UF/10V
@

+3VS_NW

IP4220CZ6
@

+3VS

WAKE#_R
+3V_NW

<30,36,57,91,92>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

USB_P5USB_P5+
CP_USB#

2 S
2

USB_P5-

<24> USB_PN5
2

11
G

90Ohm/100Mhz
LX4301

USB_PP5

4
<24>

R2.0--1

Title : CB(4)_NewCard
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

43

of

99

For NewCard Debug Card

LPC Debug Port

Block C
D

+3VS

2 0Ohm
LPC_AD0
LPC_AD1

U4401

<43>
CP_PE#
<21,43> CLKREQ3_NEWCARD#
<22,33,53> PCIE_WAKE#
<7,16,17,28,29,38,53,69>
SMB_CLK_S
<7,16,17,28,29,38,53,69>
SMB_DAT_S

PCIE_WAKE#_DBG

4
8
14
18
22

PE_DEBUGEN#

1
13

A0
A1
A2
A3
A4

C0
C1
C2
C3
C4

B0
B1
B2
B3
B4

D0
D1
D2
D3
D4

BE#
BX

VCC
GND

2
6
10
16
20
5
9
15
19
23
24
12

CP_PE#_R <43>
CLKREQ#_R <43>
WAKE#_R <43>
SMB_CLK_R <43>
SMB_DAT_R <43>

LPC_AD2
LPC_AD3
LPC_FRAME#
<24> CLK_DEBUG

1
2
3
4
5
6
7
8
9
10
11
12

+5V

C4401
0.1UF/16V

SN74CBT3383PWR

11

+3V_NW
Q4402
2N7002

Block A

1
2
3
4
5
6
7
8
9
10
11
12

15
16

3
7
11
17
21

<24> CLK_DBGPCI2
<20,30> LPC_AD3
<20,30> LPC_AD0
<20,30> LPC_AD1
<20,30> LPC_AD2

@
J4401

13
14

RN4401A
RN4401B
RN4401C
RN4401D

SIDE1
SIDE2

R4405 1

2
4
6
8

0OHM
0OHM
0OHM
0OHM

SIDE3
SIDE4

1
3
5
7

FPC_CON_12P

@
@
@
@

+3VS

PCIE_WAKE#_DBG

S 2

PCIE_WAKE#

R4404
100KOhm

R4402
47KOhm
2

1 B

C4403
0.1UF/16V

R4403
47KOhm
@

3
C Q4401
PMBS3904

1
2
3

OE# VCC
A
GND
Y

5
4

LPC_FRAME#_DBCARD

<43>

74LVC1G125GV
+5V

E
2

+3VS

+5V

<31,36,45,52,56,57,65,69,91>

+3VS

<29,48,80,91,92>

R4401
10KOhm

PE_DEBUGEN#
<20,30> LPC_FRAME#

PE_RST#

D4401
1SS355
1

<43>

C4402
2200PF/50V
1
2

+3VS
U4402

If don't support NewCard Debug Card,Pls do


(a) DNI all components of Block A
(b) Mount Block C (RN4401,R4405)

Title : BUG_Debug
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

44

of

99

+12VS

100KOhm 5

+3V

100KOhm 3

2 S

<71> LVDS_U2N
<71> LVDS_U2P
<71> LVDS_UCLKN
<71> LVDS_UCLKP

1
2

C4507
0.1UF/16V
@

+5V
+5VS
C4508
0.1UF/16V
@

WTOB_CON_40P

LVDS_L0N
LVDS_L0P

<71>
<71>

LVDS_L1N
LVDS_L1P

<71>
<71>

LVDS_L2N
LVDS_L2P

<71>
<71>

LVDS_LCLKN
LVDS_LCLKP

<71>
<71>
PWR_LED# <30,56>
GAME_LED# <69>

C4516
2
1

<71> LVDS_U1N
<71> LVDS_U1P

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

0.1UF/16V

<71> LVDS_U0N
<71> LVDS_U0P

Q4503
2N7002

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SIDE1

0.1UF/16V

EDID_CLK
EDID_DATA

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SIDE2

C4517
2
1

J4501
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

0.1UF/16V
C4518
2
1

+3VS_LCD

C4510
0.1UF/16V
@

100KOhm 1

<71>
<71>

11

RN4501A

R4501
330Ohm

3 2.2KOHM
RN4500B

1 2.2KOHM 2
RN4500A

1
C4505
0.1UF/16V

C4504
1UF/10V

C4503
10UF/10V
@

C4502
0.1UF/16V

C4501
0.1UF/25V

Q4501B
UM6K1N

L4501
80Ohm/100Mhz
1
2

6
D
5
S 4
G
SI3456BDV

Q4501A
UM6K1N

L_VDDEN

<70>

1
2
3

+3VS_LCD

RN4501C

R2.0--1
+3VSLCD
Q4502

RN4501B

100KOhm 7
8

RN4501D

+3VS
+3VS

R1.4--2
C

SL4500B
3

AC_BAT_SYS_INV

USB_PP13

<24>

USB_PN13

<24>

LX4501
90Ohm/100Mhz
@

SL4500A
USB_P13AC_BAT_SYS_INV

3
2
+3VS

0603

USB_P13+

0603

R2.0--1

<88>

<70> LCD_BACKEN

L4503
80Ohm/100Mhz
1
2 AC_BAT_INV

1 D4502
RB751V-40

This setting is for M52J/G50J colay:

C4509
22UF/25V
@

2
10KOhm
1
L4507
1KOhm/100Mhz

BL_EN

A_MIC1_P
A_MIC1_N
A_MIC2_P
A_MIC2_N

<38> UNI_MIC_P
<38> UNI_MIC_N
<38> OMNI_MIC_P
<38> OMNI_MIC_N

1
3
5
7
9
11
13
15
17
19
21

R2.0--1

1
3
5
7
9
11
13
15
17
19
SIDE1

2
4
6
8
10
12
14
16
18
20
SIDE2

2
4
6
8
10
12
14
16
18
20
22

G50J: USB portx1,Camerax1.

L4502
80Ohm/100Mhz
1
2

J4502

1 R4505
<30> LCD_BL_PWM

M52J:Camera*1 (F4501,L4502 can cost down)

C4512
0.1UF/25V
+5V_USB13

+5V_USB13_F
1

C4506
1UF/10V
1
2@

R1.2--10

F4501

1 1.5A/6V

+5V

C4511
0.1UF/16V

<30> LCD_BACKOFF#

3 D4501
BAT54AW

LID_SW#

<30,56>

R4504
100KOhm

USB_P13USB_P13+

D4503

Camera

USB_P13+

USB_P13-

WTOB_CON_20P
+5V_USB13

Reserved for EMI


A_MIC2_N

+3VS
+3V

<29,48,80,91,92>

+3V

<24,33,43,57,61,64,69,91>

+12VS

<28,91>

+5V

<31,36,44,52,56,57,65,69,91>

+5VS

<27,30,31,37,46,48,50,51,56,57,70,80,91>

D4507
0603-050E101NP-LF
@

+12VS
+5V

IP4220CZ6
@

R1.2--10

D4506
0603-050E101NP-LF
@
2

D4505
0603-050E101NP-LF
@
2

D4504
0603-050E101NP-LF
@

+3VS

A_MIC2_P
1

A_MIC1_N

A_MIC1_P

+5VS

Title : CRT(1)_LVDS
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

45

of

99

LX4601
120Ohm/100Mhz
1
2

CRT_R_55

CRT_R_CON

D4601
BAV99

C4601
10PF/50V

C4602
10PF/50V

R4601
150Ohm

JP4601
SHORT_PIN

CRT_RED

+3VS
D

CRT_G_55

C4603
10PF/50V

CRT_R_CON
C4604
10PF/50V

CRT_G_CON
CRT_B_CON

D4602
BAV99

J4601
HSYNC_CON

D4607
1

VSYNC_CON

D4608
1

CRT_G_CON
1

R4602
150Ohm

1
JP4602
SHORT_PIN

LX4602
120Ohm/100Mhz
1
2

CRT_GREEN

16

+3VS
@

EGA10603V05A1

6
1
7
2
8
3
9
4
10
5

11
12

DDC_DATA_CON

13

HSYNC_CON

14

VSYNC_CON

15

DDC_CLK_CON

EGA10603V05A1
D4609
DDC_CLK_CON 1

EGA10603V05A1
CRT_B_CON

17

CRT_B_55

D_SUB_15P3R

C4605
10PF/50V

C4606
10PF/50V

D4603
BAV99

EGA10603V05A1

R4603
150Ohm

1
JP4603
SHORT_PIN

D4610
DDC_DATA_CON 1

CRT_BLUE

LX4603
120Ohm/100Mhz
1
2

+3VS
@
<70> DDC_DATA_VGA
<70> DDC_CLK_VGA
<70> CRT_VSYNC_VGA

Q4603A
UM6K1N
1
6

CRT_HSYNC

SL4609
HSYNC_CRT

<70> CRT_HSYNC_VGA

HSYNC_CON

<70> CRT_R_VGA

0603

C4611
47PF/50V
c0402
@

<70> CRT_G_VGA
<70> CRT_B_VGA

2
SL4608
2
SL4602
1
CFD
1
CFD
2
SL4605
2
SL4606
1
CFD

CRT_DDC_DATA
1
0402 CFD
CRT_DDC_CLK
1
0402 CFD
CRT_VSYNC
2
0402 SL4603
CRT_HSYNC
2
0402 SL4604
CRT_RED
1
0402 CFD
CRT_GREEN
1
0402 CFD
CRT_BLUE
2
0402 SL4607

+3VS
5

GND
SL4610

CRT_VSYNC

VSYNC_CRT

0603

VSYNC_CON

UM6K1N
Q4603B

C4612
47PF/50V
c0402
@

GND

Q4602A
UM6K1N
1
6

SL4600
DDC_DATA

0603

DDC_DATA_CON

CRT_DDC_DATA

C4609
22PF/25V
@

+3VS

SL4601
4

+3VS

+3VS
+5V
+5VS

DDC_CLK

1
3
1
3

+3VS

<29,48,80,91,92>

+5V

<31,36,44,45,52,56,57,65,69,91>

+5VS

<27,30,31,37,45,48,50,51,56,57,70,80,91>

RN4603A
4.7KOHM2
RN4603B
4.7KOHM4
RN4602A
2.2KOHM2
RN4602B
4
2.2KOHM

0603

DDC_CLK_CON

2
1

UM6K1N
Q4602B

D4606
1SS355
+5VS

DDC_DATA
DDC_CLK
CRT_DDC_DATA
CRT_DDC_CLK

CRT_DDC_CLK

C4610
22PF/25V
@

Title : CRT(2)_D-Sub
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

46

of

99

R2.0

+3VS

+3VS

<29,48,80,91,92>

+5VS

+5VS

<27,30,31,37,45,46,48,50,51,56,57,70,80,91>

Title : CRT(3)_Display Port


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

47

of

99

CAP do GND voiding

HDMI_CLKP_CON
HDMI_CLKN_CON

SL4801A
HDMI_TXP2

HDMI_TXP0_CON

C4805
1
2

0603

HDMI_TXP2_CON

0.1UF/16V
HDMI_TXN0_CON
HDMI_TXP1_CON
HDMI_TXN1_CON
HDMI_TXP2_CON

SL4801B
4
0603

HDMI_TXN2

R4827

R4822

R4824

R4828

R4823

R4825

R4829

R4826

HDMI_TXN2_CON

L4801
90Ohm/100Mhz
@
C4806
1
2

HDMI_TXN2_CON

0.1UF/16V
SL4802A
2
0603

HDMI_TXP1

C4807
1
2

HDMI_TXP1_CON

+5VS

11
G

2 S

2
3

SL4802B
4
0603

HDMI_TXN1

L4802
90Ohm/100Mhz
@
C4808
1
2

Q4802
2N7002

HDMI_TXN1_CON

0.1UF/16V
SL4803A

R4832
1MOhm

499Ohm

499Ohm

499Ohm

499Ohm

499Ohm

499Ohm

499Ohm

499Ohm

0.1UF/16V

HDMI_TXP0

C4809
1
2

0603

HDMI_TXP0_CON

0.1UF/16V

GND

R1.4--8

SL4803B
4
0603

HDMI_TXN0

L4803
90Ohm/100Mhz
@
C4818
1
2

HDMI_TXN0_CON

0.1UF/16V
SL4804A
HDMI_CLKP

C4819
1
2

0603

HDMI_CLKP_CON

0.1UF/16V
C

SL4804B
4
0603

HDMI_CLKN

L4804
90Ohm/100Mhz
@
C4820
1
2

CFD

<70> HDMI_HPD_DGPU

CFD 1

2R4PS

HDMI_HPD
1
CFD
2 RN4805A HDMI_CLKN

CFD 3

2R4PS

4 RN4805B HDMI_CLKP

2R4PS

2 RN4806A HDMI_TXN0

2R4PS

4 RN4806B HDMI_TXP0

2R4PS

2 RN4807A HDMI_TXN1

SL4800

<70> HDMI_CLKN_DGPU
<70> HDMI_CLKP_DGPU

0402

<70> HDMI_TXN0_DGPU

CFD
CFD1

<70> HDMI_TXP0_DGPU

CFD
CFD3

<70> HDMI_TXN1_DGPU

CFD
CFD1

<70> HDMI_TXP1_DGPU

CFD 3

2R4PS

4 RN4807B HDMI_TXP1

<70> HDMI_TXN2_DGPU

CFD 1

2R4PS

2 RN4808A HDMI_TXN2

<70> HDMI_TXP2_DGPU

CFD
CFD3

2R4PS

4 RN4808B HDMI_TXP2

J4801

HDMI_TXP2_CON

0402

1
CFD
@

UM6K1N
Q4801A
CFD

HDMI_SCL
C4801
22PF/25V

HDMI_TXN1_CON
HDMI_TXP0_CON

RN4800A
CFD

HDMI_TXN0_CON
HDMI_CLKP_CON
HDMI_CLKN_CON
D4801
RB551V_30

4.7KOHM

+5VS

HDMI_DDCCLK

HDMI_DDC_CLK_DGPU

2
0.1UF/16V

1
C4803

HDMI_SCL
HDMI_SDA

F4801
0.35A/6V
+5VS_F

+5VS_HDMI
1
2

HDMI_HPD

P_GND3
P_GND1

21
23

22
20

3
1

4
4.7KOHM

P_GND2
P_GND4

R4804
10KOhm
D4802
BAV99

RN4800B
CFD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMI_CON_19P

R4803
1KOhm

+5VS_HDMI

+3VS

+3VS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMI_TXN2_CON
HDMI_TXP1_CON

SL4817
<70> HDMI_DDC_CLK_DGPU

R1.4--8

R2.0--1

+3VS

HDMI_CLKN_CON

0.1UF/16V

R2.0--1

SL4818
HDMI_DDC_DATA_DGPU

HDMI_DDCDATA

0402

1
CFD

<70> HDMI_DDC_DATA_DGPU

UM6K1N
Q4801B
CFD

R2.0--1

HDMI_SDA
A

C4802
22PF/25V

+3VS

+3VS

<29,80,91,92>

+5VS

+5VS

<27,30,31,37,45,46,50,51,56,57,70,80,91>

Title : TV(1)_HDMI
Size

R1.4--7

C
Date:

Engineer:

BU2/RD1

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

48

of

99

Title : TV(2)_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

49

of

99

+3VS

+3VS

<29,48,80,91,92>

+5VS

+5VS

<27,30,31,37,45,46,48,51,56,57,70,80,91>

CPU Thermal Sensor


+3VS

PHILIP PMBS3904

Pleace in the center


of CPU socket.
CPU_THRM_DA
Q5001 C
@

0.1UF/10V
C5007
@

U5002
1
2
3
4

1
2

C5001
2200PF/50V
@

PMBS3904

VCC
SMBCLK
DXP SMBDATA
DXN
ALERT#
THERM# GND
G781

8
7
6
5

SMB1_CLK_S
SMB1_DAT_S

<28,70>
<28,70>

E
CPU_THRM_DC

O/D
CPU_THERM#

<32>

SMBUS addr=1001100x (98)


U5002: Remote(Local) thermal sensor,use remote mode.
C

PWM Fan
C5002 put besides J5001.4

C5002
10UF/10V

+3VS

+5VS

CE5001
47UF/6.3V
@

Remove diode(+5Vs to GND)


for using 4-wires PWM FAN.

R5001
10KOhm
J5001
1

4
3
2
1

<30> FAN_PWM

1
2

C5003
100PF/50V
@

<30> FAN0_TACH
C5004
100PF/50V
@

4
3
2
1

SIDE2
SIDE1

6
5

WtoB_CON_4P

Title : FAN_Fan,Sensor
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

50

of

99

ODD

+3VS

+3VS

<29,48,80,91,92>

+5VS

+5VS

<27,30,31,37,45,46,48,50,56,57,70,80,91>

J5101

NP_NC1
NP_NC3

S1
S2
S3
S4
S5
S6
S7

P1
P2
P3
P4
P5
P6

S1
S2
S3
S4
S5
S6
S7

P1
P2
P3
P4
P5
P6

SATA_TXP1_C
SATA_TXN1_C

CX5109 1
CX5112 1

2 0.01UF/16V
2 0.01UF/16V

SATA_TXP1 <20>
SATA_TXN1 <20>

SATA_RXN1_C
SATA_RXP1_C

CX5111 1
CX5110 1

2 0.01UF/16V
2 0.01UF/16V

SATA_RXN1 <20>
SATA_RXP1 <20>

T5101

T5102

+5VS

NP_NC2

C5108
0.01UF/16V
@

NP_NC4

R2.0--1

C5107
10UF/10V

SATA_CON_13P

1224-000D000

HDD (1st)

HDD (2nd)

J5103

J5102

23

26

NP_NC4

1224-000W000

C5101
0.1UF/16V
@

1
2

1
2

C5111
1000PF/50V
@

C5102
10UF/10V
@

C5103
0.1UF/16V

+5VS
C5112
1000PF/50V

C5109
10UF/10V

R2.0--1

NP_NC2

SATA_CON_22P

NP_NC1

+3VS

24

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

NP_NC3

R2.0--1

24
26

NP_NC2
NP_NC4

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7

SATA_TXP4_C
SATA_TXN4_C

CX5105 1
CX5108 1

2 0.01UF/16V
2 0.01UF/16V

SATA_TXP4 <20>
SATA_TXN4 <20>

SATA_RXN4_C
SATA_RXP4_C

CX5107 1
CX5106 1

2 0.01UF/16V
2 0.01UF/16V

SATA_RXN4 <20>
SATA_RXP4 <20>

R1.2--14
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_CON_22P

1224-001G000

+3VS
C5113
1000PF/50V
@

C5104
0.1UF/16V
@

25

SATA_RXN0 <20>
SATA_RXP0 <20>

C5106
10UF/10V
@

+5VS

C5114
1000PF/50V

C5105
0.1UF/16V

SATA_TXP0 <20>
SATA_TXN0 <20>

2 0.01UF/16V
2 0.01UF/16V

C5110
10UF/10V

R2.0--1

2 0.01UF/16V
2 0.01UF/16V

CX5103 1
CX5104 1

CX5101 1
CX5102 1

SATA_RXN0_C
SATA_RXP0_C

SATA_TXP0_C
SATA_TXN0_C

1
2
3
4
5
6
7

1
2
3
4
5
6
7

NP_NC1

NP_NC3

23

25

R2.0--1

Title : XDD_HDD,ODD
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

51

of

99

+5V

+5V

<31,36,44,45,56,57,65,69,91>

USB ports
+5V

+5V_USB
F5201

Combine power because these two ports are nearby.

+5V_USB_C

L5201
80Ohm/100Mhz
1
2

1.6A
2

J5201
USB_P3USB_P3+

C5201
0.1UF/16V
@

4
3
2
1

4
3
2
1

P_GND4
P_GND3
P_GND2
P_GND1

8
7
6
5

USB_CON_1X4P

1213-000L000
2

USB_PP3

1 RNX5201A

0Ohm

USB_PN3

USB_P3+

<24>

CE5201
47UF/6.3V

C5203
0.1UF/16V
@

R2.0--1
<24>

0Ohm

90Ohm/100Mhz
LX5201
USB_P3-

3
RNX5201B

D5201

+5V_USB_C

USB_P2+

USB_P2-

IP4220CZ6

+5V_USB_C
4

3 RNX5202B

0Ohm

1
4

J5202
USB_P2USB_P2+

USB_PN2

<24>

LX5202
90Ohm/100Mhz

4
3
2
1

4
3
2
1

P_GND4
P_GND3
P_GND2
P_GND1

8
7
6
5

USB_CON_1X4P
<24>

1213-000L000

USB_PP2
2

0Ohm

1
RNX5202A

Title : USB_USB Port


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

52

of

99

+3VS

+3VS

<29,48,80,91,92>

+3VSUS

+3VSUS

<27,30,33,34,37,81,82,92>

+1.5VS

+1.5VS

<26,43,57,64,91>

+3VM

<26,28,57,91,92>

+3VM

R2.0--1

+3VAUX_WLAN

R0805

WLAN

2 SP5300

+3VS

R5322

1 0Ohm

+3VSUS

R5327

1 0Ohm

+3VM

+1.5VS

Shirley Peak/ Echo Peak


J5302

<21> CLK_PCIE_WLAN#_PCH
<21> CLK_PCIE_WLAN_PCH

WLAN RF Control by H/W:

RFON_SW#

<30,56,61> H=RF disable; L=RF on.


GPIO power plane: +3VA

Q5301B
UM6K1N

R5301
10KOhm
@

WLAN RF Control by S/W:


WLAN_ON

<25>

L=RF disable; H=RF on.


GPIO power plane: +3VSUS
C

+3VAUX_WLAN
<21> CL_CLK
<21> CL_DATA
<21> CL_RST#

53
54

GND13
GND14

SMBC
SMBD

R5319
R5309

1
1

USB_PN9_C
USB_PP9_C

SMB_CLK_S <7,16,17,28,29,38,44,69>
SMB_DAT_S <7,16,17,28,29,38,44,69>
USB_PN9
USB_PP9

<24>
<24>

L5303

SL5301A
2
0603

56
55

NP_NC2
NP_NC1

@
2 0Ohm
@
2 0Ohm
SL5301B
4
3
0603
@

<3,7,24,30,32,33,38,40,43,64,70>

<21> PCIE_TXN2_C
<21> PCIE_TXP2_C

BUF_PLT_RST#

<21> PCIE_RXN2_WLAN
<21> PCIE_RXP2_WLAN

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Reserved/UIM_C8
GND8
Reserved/UIM_C4 W_DISABLE#
GND3
PERST#
PERn0
+3.3Vaux
PERp0
GND9
GND4
1.5V_2
GND5
SMB_CLK
PETn0
SMB_DATA
PETp0
GND10
GND6
USB_DReserved3
USB_D+
Reserved4
GND11
Reserved5
LED_WWAN#
Reserved6
LED_WLAN#
Reserved7
LED_WPAN#
Reserved8
1.5V_3
Reserved9
GND12
Reserved10
3.3V_2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Q5301A
UM6K1N

R2.0--1

2
4
6
8
10
12
14
16

3.3V_1
GND7
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

<21> CLKREQ2_WLAN#

WAKE#
Reserved1
Reserved2
CLKREQ#
GND1
REFCLKREFCLK+
GND2

1
3
5
7
9
11
13
15

PCIE_WAKE#

<22,33,44>

WLAN_ON_C

R2.0--1

MINI_CARD_LATCH_52P

1244-000J000

WLAN +3VAUX bypass capactor:

WLAN +1.5VS bypass capactor:

WLAN nuts:

Place 0.1UF near pin 2,24,52,39 41.

Place 0.1UF near pin 6,28,48.

Minicard spec R1.2:

Place 10UF near +3VAUX_WLAN source side.

Place 10UF near +1.5VS source side.

Full size card= 2pcs.

Half size card= 2pcs.

R2.0--1

C5304

0.1UF/10V

H5303
A40M20-64AS

H5304
A40M20-64AS

C5328

0.1UF/10V
@

R2.0--1

C5318

0.1UF/10V

C5329

10UF/6.3V

C5311

0.1UF/10V

C5310

0.1UF/10V
@

C5309

0.1UF/10V

C5308

0.1UF/10V
@

C5312

10UF/6.3V

+1.5VS

+3VAUX_WLAN

R2.0--1

Title : MINICARD_WLAN
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

53

of

99

Title : BAR_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

54

of

99

Title : SIO_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

55

of

99

<30> NUM_LED#

<30>

CAP_LED#

33Ohm

4 RN5601B

NUM_LED_CON#

+3VA

33Ohm

2 RN5601A

CAP_LED_CON#

J5601
R5609
10KOhm

R2.0--1

SL5600
1

LID_SW#

0402

LID_SW_CON#

+3VS
+5VS

R2.0--1
SL5602
R5607
10KOhm

SL5601

2
11
2 S

<30>

Q5602
2N7002

PWR_SW#

0402

POWER_SW#

<30>

ALS_AD

1
R5620

0402

+5VA_LID

2
0Ohm

21

GND2

22

12G183402008

D5600
AZ2015-01H.R7F

SW5602

1
Q5604A
UM6K1N

1
+5VA_LID

2
4

TP_SWITCH_4P
2

LID_SW#

EXP_GATE#

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FPC_20P

G
Q5604B
UM6K1N

<30>

PWR_LED_CON#
LID_SW_CON#
POWER_SW#

GND

R2.0--1

+3VA

2
R5608
1MOhm

CAP_LED_CON#

+3VA

+5VA

R5605
1MOhm

HDD_LED_CON#
NUM_LED_CON#

+5VSUS

AC_BAT_SYS

C5602
0.1UF/10V
@

GND1

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND
<28,30> SMB1_CLK
<28,30> SMB1_DAT
<30> CAP_ACK#

<30,45>

POWER ON SWITCH
NO_STUFF AFTER PR

+3VA
1

Power LED

R5611
10KOhm

+5V
PWR_LED_CON#

<31>
<30,53,61>

SL5603
1

RFON_SW#

0402

SW5601
2

4
5
6

R2.0--1

PWR_LED_CON#
R5618
10KOhm

COM

COM

1
2
3

SLIDE_SWITCH_6P

Q5606A
UM6K1N

Q5606B
UM6K1N

5
4

2
1

<30,45> PWR_LED#

220 ohm on small board

C5603
0.1UF/10V

WLAN LED
WLAN_LED_CON#

+3VA

+3VA

<20,30,57,81,90,93>

+3VS

+3VS

<29,48,80,91,92>

+5VA
+5V
+5VS
AC_BAT_SYS

+5VSUS

<27,81,91>

+5VA

<31,81,82,83>

+5V

<31,36,44,45,52,57,65,69,91>

+5VS

<27,30,31,37,45,46,48,50,51,57,70,80,91>

AC_BAT_SYS

3
Q5605B
UM6K1N

BT_LED

<25>

1
R5604
100KOHM

R5606
100KOHM
2

Q5601B
UM6K1N

Q5605A
UM6K1N

WLAN_LED

<25>

HDD_LED_CON#

3
Q5601A
UM6K1N

2
1

SATA_LED#

1
R5603

2
330Ohm

Q5603B
UM6K1N

R5602
10KOhm

Q5603A
UM6K1N

+5VSUS

HDD LED
6

<31>

<20>

<31>

1
CHG_LED_CON#

1
R5614

CHG_LED#

BT_LED_CON#

R5616
330Ohm
2

1
6

2
330Ohm

<30>

R5617
330Ohm

+3VS
R5613
10KOhm

BT_LED_CON#
1

<31> WLAN_LED_CON#

+5VA

Charger LED

BT LED

<70,80,81,82,83,88>

Title : LED_Indicator
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

56

of

99

+3VA
+VCORE
+VGFX_CORE

+3VA

<20,30,56,81,90,93>

+VCORE

<6,69,80>

+VGFX_CORE

+VTT_CPU

+VTT_CPU <3,6,7,25,26,27,29,32,82>

+0.75VS

+0.75VS

<16,17,83>

+1.05VS

+1.05VS

<26,27,69,91>

+1.5VS

+1.5VS

<26,43,53,64,91>

+1.8VS

+1.8VS

<6,26,38,70,85>

+3VS

+3VS

<29,48,80,91,92>

+5VS

+5VS

<27,30,31,37,45,46,48,50,51,56,70,80,91>

+1.5V

+1.5V

<3,6,16,69,83>

+3V

+3V

<24,33,43,45,61,64,69,91>

+5V

+5V

<31,36,44,45,52,56,65,69,91>

+1.05VM_LAN

+3VM

<26,28,53,91,92>

+1.05VM

<27,69,91,92>

+5VS

+3VS

+1.8VS

+1.5VS
1

+3VM
+1.05VM

+1.05VM_LAN

+1.05VS

+VTT_CPU

+0.75VS

+VCORE

1
2

Q5707A
UM6K1N

1
2

2
1

2
6

@
Q5704B
UM6K1N

+VCORE_DISCHRG

@
Q5704A
UM6K1N

R5714
330Ohm

+0.75VS_DISCHRG

@
Q5703B
UM6K1N

R5713
330Ohm

+VTT_CPU_DISCHRG

@
Q5703A
UM6K1N

R5708
330Ohm

+VTT_PCH_DISCHRG

@
Q5702B
UM6K1N

R5707
330Ohm

+1.5VS_DISCHRG

@
Q5702A
UM6K1N

SUSB_EC#

R5706
330Ohm

+1.8VS_DISCHRG

@
Q5701B
UM6K1N

<30,36,43,91,92>

+3VS_DISCHRG

Q5701A
UM6K1N

R5705
330Ohm

+5VS_DISCHRG

R5701
100KOhm

R5704
330Ohm
2

R5703
330Ohm

+3VA

+5V_DISCHRG

1
3

3
4

Q5706B
UM6K1N

2
6

@
Q5706A
UM6K1N

+3VM

+1.05VM
1

<30,91> SUSC_EC#

+1.5V_DISCHRG

@
Q5705B
UM6K1N

+3V_DISCHRG

Q5705A
UM6K1N

R5712
330Ohm
2

1
R5702
100KOhm

R5711
330Ohm
2

R5710
330Ohm

+3VA

+1.5V

+3V

+5V

1
R5709
100KOhm

+3VM_DISCHRG

<22,91> ME_PM_SLP_LAN#

<91> ME_SLP_M_EC#

2
2

0Ohm
@

Q5708A
UM6K1N
@

Q5709B
UM6K1N

@
Q5709A
UM6K1N

2
R5720

+1.05VM_DISCHRG

2 0Ohm

R5721
SUSB_EC#

R5718
330Ohm
2

R5717
330Ohm

+3VA

@
R5719
2
0Ohm
@

R2.0--1
A

Title : DSG_Discharge
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

57

of

99

Title : PCI_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

58

of

99

Title : DJ_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

59

of

99

+VCC_RTC
+3VA_EC

DC Jack
Current setting=6A

+V_DCJACK
D

J6001

2 80Ohm/100Mhz

L6006 1

Irat=3A
2 80Ohm/100Mhz
1

C6003
1UF/25V
@

C6004
0.1UF/25V

C6002
10UF/25V
@

<20,27>

+3VA_EC

<30,32>

+3VA

<20,30,56,57,81,90,93>

+5VA

+5VA

<31,56,81,82,83>

+3VSUS

+3VSUS

<27,30,33,34,37,53,81,82,92>

+5VSUS

+5VSUS

<27,56,81,91>

+12VSUS

+12VSUS

<28,81,91>

+1.5V

<3,6,16,57,69,83>

+3V

+3V

<24,33,43,45,57,61,64,69,91>

+5V

+5V

<31,36,44,45,52,56,57,65,69,91>

GND

Irat=3A

D6001
SS0540
@

C6001
0.1UF/25V

DC_PWR_JACK_2P

2GND

+VCC_RTC

+3VA

+1.5V

1vcc

L6001 1

NP_NC
P_GND
P_GND
P_GND
P_GND

3
4
5
6
7

T6001
T6002
T6003
T6004

1
1
1
1

A/D_DOCK_IN

Depend on the current


of the adaptor.

1215-0003000

R2.0--1

T6005
T6006
T6007
T6008

1
1
1
1

+12V

R2.0--1
GND

GND

Battery Connector

+12V

<37,91>

+0.75VS

+0.75VS

<16,17,57,83>

+1.05VS

+1.05VS

<26,27,57,69,91>

+1.5VS

+1.5VS

<26,43,53,57,64,91>

+1.8VS

+1.8VS

<6,26,38,57,70,85>

+3VS

+3VS

+5VS

+5VS

<27,30,31,37,45,46,48,50,51,56,57,70,80,91>

+12VS

+12VS

<28,45,91>

AC_BAT_SYS_INV

For EC pin protection,


clamping=6.8V

AC_BAT_SYS
A/D_DOCK_IN

BATT_CON_9P
1
1
1
1

1220-000U000
GND

T6013
T6014
T6015
T6016

R2.0--3

+VCORE
+VGFX_CORE
+VTT_PCH_ORG
SMB0_CLK <30>
SMB0_DAT <30>
TS1#
<90>

C6006
47PF/50V
@

GND

GND

C6007
47PF/50V
@

1
1
1

1
DF5A6.8FU

L6002
L6003
L6004

1
1
1
2 120Ohm/100Mhz
120Ohm/100Mhz
2
2 120Ohm/100Mhz

T6017
T6018
T6019

10

AC_BAT_SYS

<45,88>

<56,70,80,81,82,83,88>

A/D_DOCK_IN

GND

Recommand max 47PF,


for BQ20Z90 rising time spec.

BAT_CON

<88>

<88>

+1.5V_DDR3

<16,17,18>

GND
+VTT_CPU

5
9
8
7
6
5
4
3
2
1

P_GND1

11

+1.5V_DDR3

9
8
7
6
5
4
3
2
1

T6009
T6010
T6011
T6012

C6005
2
1
1.5NF/50V
C6009
2
1
1.5NF/50V
C6010
2
1
1.5NF/50V
C6011
2
1
1.5NF/50V

P_GND2

BAT_CON

J6002

AC_BAT_SYS_INV

D6005

BAT_CON
C

1
1
1
1

<29,48,80,91,92>

C6008
47PF/50V
@

+VTT_PCH_VCCIO
+1.05VM_ORG

+VTT_CPU <3,6,7,25,26,27,29,32,57,82>
+VCORE

<6,57,69,80>

+VGFX_CORE
+VTT_PCH_ORG

<21,22,26,27>

+VTT_PCH_VCCIO
+1.05VM_ORG

<20,26,27>

<27>

+V_NVRAM_VCCQ

+V_NVRAM_VCCQ

M_VREFCA_DIMM0

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

M_VREFDQ_DIMM0

<16,18>

M_VREFCA_DIMM1

M_VREFCA_DIMM1

<17,18>

M_VREFDQ_DIMM1

M_VREFDQ_DIMM1

<17,18>

<26>
<16,18>

Title : DC_DC/BAT CONN


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

60

of

99

+3V

+3V

<24,33,43,45,57,64,69,91>

BLUETOOTH

+3V

C6102
0.1UF/16V

+3V

BT_ON

RB751V-40
D6101
2

1 BT_ON_D

J6101
<24>
<24>

<25>

R6104
10KOhm

RFON_SW#

2 S

T6101

BT_Link_LED

1
2
3
4
5
6

Q6102
2N7002
@

1
2
3
4
5
6

SIDE1

SIDE2

WTOB_CON_6P

1217-002K000

<30,53,56>

11

USB_PP12
USB_PN12

Title : BT_Bluetooth
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

61

of

99

Title : TPM_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

62

of

99

Title : FP_****
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

63

of

99

+3V
+3VS
+1.5VS

+3V

<24,33,43,45,57,61,69,91>

+3VS

<29,48,80,91,92>

+1.5VS

<26,43,53,57,91>

+3V

Max: 1200 mA

N/A
2
L6401

1
80Ohm/100Mhz
+3VS
@

+3V_TUN
1

C6402
10UF/10V

2
L6402

C6401
0.1UF/16V

J6401

<21> PCIE_RXN1_TV
<21> PCIE_RXP1_TV
<21> PCIE_TXN1_C
<21> PCIE_TXP1_C

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Reserved/UIM_C8
GND8
Reserved/UIM_C4 W_DISABLE#
GND3
PERST#
PERn0
+3.3Vaux
PERp0
GND9
GND4
1.5V_2
GND5
SMB_CLK
PETn0
SMB_DATA
PETp0
GND10
GND6
USB_DReserved3
USB_D+
Reserved4
GND11
Reserved5
LED_WWAN#
Reserved6
LED_WLAN#
Reserved7
LED_WPAN#
Reserved8
1.5V_3
Reserved9
GND12
Reserved10
3.3V_2

R2.0--1

+1.5VS

C6404
0.1UF/16V

C6405
10UF/10V R2.0--1

C6403
0.1UF/16V
@

Max: 375 mA

+1.5VS_TUN

2
4
6
8
10
12
14
16

C6406
22UF/6.3V
@

3.3V_1
GND7
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

<21> CLKREQ1_TV#
<21> CLK_PCIE_TV#_PCH
<21> CLK_PCIE_TV_PCH

WAKE#
Reserved1
Reserved2
CLKREQ#
GND1
REFCLKREFCLK+
GND2

1
3
5
7
9
11
13
15

1
80Ohm/100Mhz

R2.0--1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BUF_PLT_RST#

<3,7,24,30,32,33,38,40,43,53,70>

R2.0--1
USB_PN4
USB_PP4

<24>
<24>

R1.4--1

53
54

GND13
GND14

NP_NC2
NP_NC1

56
55

MINI_PCI_LATCH_52P

H6402
W5M-1A

H6403
W5M-1A
@

H6404
W5M-1A
@

J6403

H6401
W5M-1A

2
3

GND1
GND2

GND4
GND3

5
4

MCX_JACK_5P

Title : TUN_TV Tuner


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

64

of

99

H6501

@
0Ohm

1
RNX6500A
RNX6501B
<36>
<36>
<36>
<36>

USB_PP0

USB_P1USB_P1+

C6501
100PF/50V

MIC1_VREFOUT

<36>
GND_AUDIO

1
2
3

NP_NC
GND1 GND4
GND2 GND3

5
4

RT394x315CBD118N
RT394x315CBD118N

4
USB_PN1

<24>

USB_PP1

<24>

<24>

H6514

USB_P1+

@
0Ohm

1
RNX6501A

1
2
3

R2.0

NP_NC
GND1 GND4
GND2 GND3

1
2
3

5
4

NP_NC
GND1 GND4
GND2 GND3

5
4

RT394x315CBD118N

R6503
4.7KOhm

RT394x315CBD118N

GND_AUDIO

5
4

H6504
4

AC_HP_R_CON <37>
AC_HP_L_CON <37>
LINEIN_R <36>
LINEIN_L <36>

NP_NC
GND1 GND4
GND2 GND3

@
0Ohm

LX6501
90Ohm/100Mhz

<36>

H6508
1
2
3

USB_P1-

SPDIF1_OUT

<24>

LX6500
90Ohm/100Mhz

USB_P0USB_P0+

GND_AUDIO WTOB_CON_20P

4
USB_PN0

USB_P0+

LINE2_JD
SPDIF_JD
LINE1_JD
MIC1_JD

Screw Hole A

@
0Ohm

USB_P0-

C6513
0.1UF/16V

22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SIDE1 19
20
SIDE2

C6512
1000PF/50V
@

RNX6500B
C6510
0.1UF/16V

+3VS
1 2A/8V

J6501
21

+5V
F6501

1
2

C6511
1000PF/50V
@

L6501
80Ohm/100Mhz
2
1+5V_USB01_F

+5V_USB01

MIC_IN_AC_E

Screw Hole B

<36>

R1.2--11
D6501
USB_P0-

H6505
CT268B158D138

USB_P0+
1

+5V_USB01

H6507
CT268B158D138

H6510
CT268B158D138

H6509
CT268B158D138

Screw Hole C
USB_P1-

USB_P1+

IP4220CZ6

H6526
1
2
3
LINE2_JD

C6502

LINE1_JD

C6503

LINEIN_R

C6504

LINEIN_L

C6505

MIC_IN_AC_E

C6506

MIC1_JD

C6507

AC_HP_L_CON

C6508

AC_HP_R_CON

C6509

2
@
2
@
2
@
2
@
2
@
2
@
2
@
2
@

NP_NC
GND1 GND4
GND2 GND3

100PF/50V

5
4

Screw Hole F

Screw Hole H

Screw Hole I

Screw Hole J

100PF/50V
C110D110N
nb_h_crt413x413bd110n_v4

100PF/50V
100PF/50V
100PF/50V

H6523
H6527

100PF/50V
100PF/50V

1
2
3

100PF/50V

NP_NC
GND1 GND4
GND2 GND3

1
2
3

5
4

NP_NC
GND1 GND4
GND2 GND3

5
4

H6517

GND_AUDIO

1
2
3

RT425X346CBD110N

RT354X346CBD102N
nb_h_rt354x346cbd102n_p2_v4

NP_NC1GND5
NP_NC2GND4
GND2 GND3

6
5
4

2DRILL_D102N_D108N
B

+3VS
+5V

+3VS

<29,48,80,91,92>

+5V

<31,36,44,45,52,56,57,69,91>

H6524

H6525
1
2
3

NP_NC1GND5
NP_NC2GND4
GND2 GND3

6
5
4

1
2
3

Screw Hole K
NP_NC
GND1 GND4
GND2 GND3

5
4

H6519

H6518
1
2
3

CRT729X391DB110N
nb_h_crt729x391bd110n_p2_v4

2DRILL
nb_h_2d_do108x140n_v4

NP_NC
GND1 GND4
GND2 GND3

Screw Hole L
1
2
3

5
4

RT394x325BD110N

NP_NC
GND1 GND4
GND2 GND3

5
4

C110D110N

Screw Hole M
H6522
1
2
3

NP_NC
GND1 GND4
GND2 GND3

5
4

C315D110N

H6529

5
4

NP_NC
GND4 GND1
GND3 GND2

H6528
1
2
3

RT315X335CBD110N
nb_h_rt315x335cbd110n_p2_v4

1
2
3

NP_NC1GND5
NP_NC2GND4
GND2 GND3

6
5
4

2DRILL
nb_h_2d_do140x108n_p2_v4

Title : ME_CONN,Skew Hole


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

65

of

99

+3VS
+1.8VS

+3VS

<29,48,80,91,92>

+1.8VS

<6,26,38,57,70,85>

E-SATA connector
J6601
<20>
<20>

SATA_TXP5
SATA_TXN5

<20> SATA_RXN5
<20> SATA_RXP5

CX6601 2
CX6602 2

1 0.01UF/16V
1 0.01UF/16V

ESATA_TXP_C
ESATA_TXN_C

CX6603 2
CX6604 2

1 0.01UF/16V
1 0.01UF/16V

ESATA_RXN_C
ESATA_RXP_C

1
2
3
4
5
6
7

1
2
3
4
5
6
7

P_GND1
P_GND3
NP_NC1
NP_NC2
P_GND4
P_GND2

8
10
12
13
11
9

SATA_CON_7P

12G15110007P
D6601
ESATA_TXN_C

ESATA_TXP_C

+3VS

ESATA_RXN_C

ESATA_RXP_C

IP4220CZ6

Title : ESA_ESATA
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

66

of

99

+3VS
+1.8VS
+V_NVRAM_VCCQ

+3VS

<29,48,80,91,92>

+1.8VS

<6,26,38,57,70,85>

+V_NVRAM_VCCQ

<26>

Title : ONFI
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

67

of

99

Title : OTH_LCM
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

68

of

99

May to be deleted..
+3V
+3VS

+3V

<24,33,43,45,57,61,64,91>

+3VS

<29,48,80,91,92>

+3V

+3V

+VDD
+VDD

@
1
R6904

2
0Ohm

+VDD

1
R6905

C6901
0.1UF/10V
@

+VDD

2 MODE
10KOhm
U6901
<7,16,17,28,29,38,44,53>

+VDD

0Ohm

SMB_CLK_S

R6901

SCL_MCU
1 TXD_1
RST#
XOUT

T6901

1
2
3
4
5
6
7
8
9
10

XIN

XIN

XOUT

10KOhm
@

SBAR_LED_EN

0Ohm

T6902
1 R6903

MODE
RXD_1

P3_4/SCS#/SDA/CMP1_1
P3_3/TCIN/INT3#/SSI00/CMP1_0
P1_0/KI0#/AN8/CMP0_0
P1_1/KI1#/AN9/CMP0_1
P4_2/VREF
P1_2/KI2#/AN10/CMP0_2
P1_3/KI3#/AN11/TZOUT
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11#
P1_6/CLK0/SSI01

20
19
18
17
16
15
14
13
12
11

SDA_MCU

R6902 1
1
T6903
1
T6904
1
T6905
1

2 100Ohm

SMB_DAT_S <7,16,17,28,29,38,44,53>

T6906

R5F211A2SP
1

1
C6903
10PF/50V
@

1
2

RST#
20Mhz
C6904
10PF/50V
@

R6906
@
X6901
1
2

P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0#/SSO/TXD1
RESET#
XOUT/P4_7(1)
VSS/AVSS
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0#/RXD1
P1_7/CNTR00/INT10#

C6902
0.1UF/10V
@

+3VS

R6908

1
SL6900

10KOhm
@
C

0402

LED CONTROL For GAME LED


<30> GAME_LED_EC#

+VDD
1
C6906
0.1UF/10V
@

+VDD

C6905
0.1UF/10V
@

C6916
0.1UF/10V
@
SBAR_LED_EN

R2.0--1
Q6901

GAME_LED#

<45>

3
C

1 B

PMBS3904
@
E
2

For EMI request


+5V

C6907 @
1
2
0.1UF/10V

+1.05VS

C6923 @
1
2
0.1UF/10V

+5V

C6908 @
1
2
0.1UF/10V

+VCORE

+1.05VS

C6924 @
1
2
0.1UF/10V

+5V

C6909 @
1
2
0.1UF/10V

+VCORE

+VCORE

C6925 @
1
2
0.1UF/10V

+5V

C6910 @
1
2
0.1UF/10V

+5V

C6911 @
1
2
0.1UF/10V

+3VS

+VCORE

C6926 @
1
2
0.1UF/10V

+3VS

+VCORE

C6927 @
1
2
0.1UF/10V

+5V

C6912 @
1
2
0.1UF/10V

+3VS

+VCORE

C6928 @
1
2
0.1UF/10V

+5V

C6913 @
1
2
0.1UF/10V

+3VS

+3VS

C6929 @
1
2
0.1UF/10V

+1.5V

+1.05VM

C6914 @
1
2
0.1UF/10V

+3VS

C6930 @
1
2
0.1UF/10V

+1.5V

+1.05VM

C6915 @
1
2
0.1UF/10V

+3VS

C6931 @
1
2
0.1UF/10V

+1.5V

+1.05VM

C6917 @
1
2
0.1UF/10V

+3VS

C6932 @
1
2
0.1UF/10V

+1.5V

+1.05VM

C6918 @
1
2
0.1UF/10V

+3VS

C6933 @
1
2
0.1UF/10V

+1.5V

+1.05VM

C6919 @
1
2
0.1UF/10V

+3VS

+3VS

C6934 @
1
2
0.1UF/10V

+1.05VM

C6920 @
1
2
0.1UF/10V

+1.05VS

+3VS

C6935 @
1
2
0.1UF/10V

+1.05VM

C6921 @
1
2
0.1UF/10V

+1.05VS

+3VS

C6936 @
1
2
0.1UF/10V

+1.05VS

C6922 @
1
2
0.1UF/10V

+3VS

C6937 @
1
2
0.1UF/10V

+3VS

+3VS

Title : OTH_GAME-LED
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

69

of

99

Main Board
CLK_PCIE_PEG

2 SL7013

CLK_PCIE_PEG#

PCIENB_RXN[15:0]
<3>
PCIENB_RXP[15:0]
<3>
PCIEG_RXN[15:0] <3>
PCIEG_RXP[15:0] <3>

R1.2--2

R1.4--7

HDMI_TXP2
HDMI_TXN2
HDMI_CLKP
HDMI_CLKN

<48> HDMI_HPD_DGPU
LVDS_LCLKN_VGA
1
R7020

eDP_HPD_VGA
0Ohm

2
@

217
193

PEX_TX2
PEX_TX2#
PEX_RX2
PEX_RX2#

DDCB_CLK
DDCB_DAT
DDCA_CLK
DDCA_DAT

PEX_TX3
PEX_TX3#
PEX_RX3
PEX_RX3#

Place R as close as to LVDS_LCLKN net.


232
230
155
157

<48> HDMI_DDC_CLK_DGPU
<48> HDMI_DDC_DATA_DGPU
<46> DDC_CLK_VGA
<46> DDC_DATA_VGA

156
148
152
151
153

<46> CRT_B_VGA
<46> CRT_R_VGA
<46> CRT_G_VGA
<46> CRT_HSYNC_VGA
<46> CRT_VSYNC_VGA

Please set them near


the MXM connector.

SL7006
SL7007

<45>
L_VDDEN
<45> LCD_BACKEN
<71>
<71>
<71>
<71>
<71>
<71>

2
2

0402
0402

1
1

224
228
226
186
184
180
178
174
172
168
166

LVDS_U0P_VGA
LVDS_U0N_VGA
LVDS_U1P_VGA
LVDS_U1N_VGA
LVDS_U2P_VGA
LVDS_U2N_VGA

162
160

<71> LVDS_UCLKP_VGA
<71> LVDS_UCLKN_VGA
<71>
<71>
<71>
<71>
<71>
<71>

216
214
210
208
204
202
198
196

LVDS_L0P_VGA
LVDS_L0N_VGA
LVDS_L1P_VGA
LVDS_L1N_VGA
LVDS_L2P_VGA
LVDS_L2N_VGA

192
190

<71> LVDS_LCLKP_VGA
<71> LVDS_LCLKN_VGA

185
183
179
177
173
171
161
159

<20> ACZ_SDOUT_VGA
<20> ACZ_SDIN2_VGA

LVDS_U1P_VGA
LVDS_U1N_VGA
LVDS_U0P_VGA
LVDS_U0N_VGA

DVI_A_HPD
DVI_B_HPD/GND

3
1
3
1

@
0OHM
@
0OHM
@
0OHM
@
0OHM

4
2
4
2

RN7001B
RN7001A
RN7002B
RN7002A

eDP_L1P_VGA
eDP_L1N_VGA
eDP_L0P_VGA
eDP_L0N_VGA

Place RN as close as to LVDS_UX* net.

215
213
209
207
203
201
191
189

PEX_TX4
PEX_TX4#
PEX_RX4
PEX_RX4#

VGA_BLU
VGA_RED
VGA_GRN
VGA_HSYNC
VGA_VSYNC

VGA

LVDS_PPEN
LVDS_BLEN
LVDS_BL_BRGHT
LVDS_UTX0
LVDS_UTX0#
LVDS_UTX1
LVDS_UTX1#
LVDS_UTX2
LVDS_UTX2#
LVDS_UTX3
LVDS_UTX3#

1
1
1

140
136
144

LVDS

<28,50> SMB1_CLK_S
<28,50> SMB1_DAT_S

SL7008
SL7009

2
2

SL7010
SL7011

2
2

0402
0402
0402
0402

1
1

222
220

1
1

147
145

PEX_TX9
PEX_TX9#
PEX_RX9
PEX_RX9#
PEX_TX10
PEX_TX10#
PEX_RX10
PEX_RX10#
PEX_TX11
PEX_TX11#
PEX_RX11
PEX_RX11#

LVDS_LCLK
LVDS_LCLK#

PEX_TX12
PEX_TX12#
PEX_RX12
PEX_RX12#

IGP_11
IGP_10
IGP_8
IGP_7
IGP_5
IGP_4

IGP

IGP_2
IGP_1
IGP/DVI_B_TX0
IGP/DVI_B_TX0#
IGP/DVI_B_TX1
IGP/DVI_B_TX1#
IGP/DVI_B_TX2
IGP/DVI_B_TX2#
IGP/DVI_B_CLK
IGP/DVI_B_CLK#

TV_Y/HDTV_Y/TV_CVBS
TV_C/HDTV_Pr
TV_CVBS/HDTV_Pb

Shared with edP_AUX.


<71> EDID_CLK_VGA
<71> EDID_DAT_VGA

PEX_TX6
PEX_TX6#
PEX_RX6
PEX_RX6#

PEX_TX8
PEX_TX8#
PEX_RX8
PEX_RX8#

TV-OUT
T7708
T7707
T7706

PEX_TX5
PEX_TX5#
PEX_RX5
PEX_RX5#

PEX_TX7
PEX_TX7#
PEX_RX7
PEX_RX7#

LVDS_UCLK
LVDS_UCLK#
LVDS_LTX0
LVDS_LTX0#
LVDS_LTX1
LVDS_LTX1#
LVDS_LTX2
LVDS_LTX2#
LVDS_LTX3
LVDS_LTX3#

PEX

SMBUS
DDCC_CLK
DDCC_DAT

PEX_TX13
PEX_TX13#
PEX_RX13
PEX_RX13#
PEX_TX14
PEX_TX14#
PEX_RX14
PEX_RX14#
PEX_TX15
PEX_TX15#
PEX_RX15
PEX_RX15#
CLK_REQ#
PEX_RST#
PEX_REFCLK
PEX_REFCLK#
THERM#
PRSNT1#
PRSNT2#
1V8RUN_7

OTHER

NP_NC1
NP_NC2
PIN245
PIN246

120
118
117
115

PCIEG_RXP2
PCIEG_RXN2
PCIENB_RXP2
PCIENB_RXN2

114
112
111
109

PCIEG_RXP3
PCIEG_RXN3
PCIENB_RXP3
PCIENB_RXN3

108
106
105
103

PCIEG_RXP4
PCIEG_RXN4
PCIENB_RXP4
PCIENB_RXN4

102
100
99
97

PCIEG_RXP5
PCIEG_RXN5
PCIENB_RXP5
PCIENB_RXN5

96
94
93
91

PCIEG_RXP6
PCIEG_RXN6
PCIENB_RXP6
PCIENB_RXN6

90
88
87
85

PCIEG_RXP7
PCIEG_RXN7
PCIENB_RXP7
PCIENB_RXN7

84
82
81
79

PCIEG_RXP8
PCIEG_RXN8
PCIENB_RXP8
PCIENB_RXN8

78
76
75
73

PCIEG_RXP9
PCIEG_RXN9
PCIENB_RXP9
PCIENB_RXN9

72
70
69
67

PCIEG_RXP10
PCIEG_RXN10
PCIENB_RXP10
PCIENB_RXN10

66
64
63
61

PCIEG_RXP11
PCIEG_RXN11
PCIENB_RXP11
PCIENB_RXN11

60
58
57
55

PCIEG_RXP12
PCIEG_RXN12
PCIENB_RXP12
PCIENB_RXN12

54
52
51
49

PCIEG_RXP13
PCIEG_RXN13
PCIENB_RXP13
PCIENB_RXN13

48
46
45
43

PCIEG_RXP14
PCIEG_RXN14
PCIENB_RXP14
PCIENB_RXN14

42
40
39
37

PCIEG_RXP15
PCIEG_RXN15
PCIENB_RXP15
PCIENB_RXN15

137
139

+1.8VS

1
C7015
0.1UF/25V

+1.8VS_MXM
JP7001
1

3.5A

GND
C7016
4.7UF/6.3V

PCIEG_RXP1
PCIEG_RXN1
PCIENB_RXP1
PCIENB_RXN1

C7014
0.1UF/25V

1
3
5
7
9
11
13
15

3MM_OPEN_5MIL

6
8
10
12
14
16
18

HDMI_TXN1

126
124
123
121

C7013
10UF/25V

GND
VGA_PWR_EN

J7001B
PWR_SRC1
PWR_SRC2
PWR_SRC3
PWR_SRC4
PWR_SRC5
PWR_SRC6
PWR_SRC7
PWR_SRC8

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
IGP_3
GND45
GND46
IGP_6
GND47
IGP_9
GND48
GND49
GND50
GND51

1V8RUN_1
1V8RUN_2
1V8RUN_3
1V8RUN_4
1V8RUN_5
RUNPWROK
5VRUN

+5VS
+3VS

0.5A

1.5A
1

HDMI_TXP1

PEX_TX1
PEX_TX1#
PEX_RX1
PEX_RX1#

DVI
DVI_A_CLK
DVI_A_CLK#

221
219

4A
2

HDMI_CLKP
HDMI_CLKN

PCIEG_RXP0
PCIEG_RXN0
PCIENB_RXP0
PCIENB_RXN0

<48> HDMI_CLKP_DGPU
<48> HDMI_CLKN_DGPU

C7001

132
130
129
127

C7017
0.1UF/10V

C7018
4.7UF/6.3V

1
0.1UF/16V
@
1 @
2
R7010
300Ohm
2
1
C7002
0.1UF/16V
@
@
1
2
R7011
300Ohm
2
1
C7003
0.1UF/16V
@
1 @
2
R7012
300Ohm
2
1
C7004
0.1UF/16V
@

PEX_TX0
PEX_TX0#
PEX_RX0
PEX_RX0#

C7019
0.1UF/10V

238
240
242

2
234

GND

2V5_RUN: NV no use.

GND
141
143
165
167
169
195
197

<20> ACZ_SYNC_VGA
<20> ACZ_BCLK_VGA
+3VS
1

DVI_A_TX0
DVI_A_TX0#
DVI_A_TX1
DVI_A_TX1#
DVI_A_TX2
DVI_A_TX2#

R7000
1KOhm
2

R7009
HDMI_TXN0

2
300Ohm

239
237
233
231
227
225

SL7017

0402

241
236
235
229
223
218
212
211
206
205
200
199

1 @

HDMI_TXP0
HDMI_TXN0
HDMI_TXP1
HDMI_TXN1
HDMI_TXP2
HDMI_TXN2

D
Q7000
2N7002

11

<30,88> AC_IN_OC#

2 S

HDMI_TXP0

HDMI_TXP0_DGPU
HDMI_TXN0_DGPU
HDMI_TXP1_DGPU
HDMI_TXN1_DGPU
HDMI_TXP2_DGPU
HDMI_TXN2_DGPU

<48>
<48>
<48>
<48>
<48>
<48>

AC mode: AC/BATT# =HIGH


Battery mode: AC/BATT# =LOW

AC_BAT_SYS

J7001A
D

2 SL7012

0402

0402

3V3RUN_1
3V3RUN_2
3V3RUN_3

<21> CLK_PCIE_PEG#_PCH

<21> CLK_PCIE_PEG_PCH

1V8RUN_6
2V5RUN

RSVD1
RSVD2
RSVD3
RSVD4
AC/BATT#
RSVD5
RSVD6
GND63
GND62
GND61
GND60
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52

17
19
20
21
22
23
24
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
138
142
146
150
154
158
163
164
170
175
176
181
182
187
188
194

R1.0e

ACZ_RST#_VGA

1 SL7016
0402
1 SL7005
0402
1 SL7015
0402
1 SL7014
0402

<20>

2
2
2

SPDIF2_OUT

<36>

MXM_230P
GND
GND

R2.0--1

12G16180230V

GND
GND

SL7014,SL7015,SL7016:
to compatible with Z97V

H7005
CT217B67D47
CLKREQ_PEG#

H7006
CT217B67D47

<21>

PCIEG_RST#

135
133

CLK_PCIE_PEG
CLK_PCIE_PEG#

149
134
38
4

PRSNT2#

GND

VGA_THERM#

SL7002

243
244
245
246

+1.8VS

0402

<32>

GND

H7003
U5F-M-EXPREE

H7004
U5F-M-EXPREE

R2.0--1

GND

SMB_CLK
SMB_DAT
MXM_230P
GND

12G16180230V
PCIEG_RST#

1
SL7003

0402

BUF_PLT_RST#

<3,7,24,30,32,33,38,40,43,53,64>

VGA_PWR_EN

1
SL7004

0402

SUSB#_PWR

<81,82,83,85,91,93>

Title : VGA_MXM(2.1a)
Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

70

of

99

+5VS

<70> LVDS_LCLKP_VGA
D

<70> LVDS_LCLKN_VGA
<70> LVDS_L0N_VGA
<70> LVDS_L0P_VGA
<70> LVDS_L1P_VGA
<70> LVDS_L1N_VGA
<70> LVDS_L2N_VGA
<70> LVDS_L2P_VGA
<70> LVDS_UCLKP_VGA
<70> LVDS_UCLKN_VGA
<70> LVDS_U0N_VGA
<70> LVDS_U0P_VGA
<70> LVDS_U1P_VGA
<70> LVDS_U1N_VGA
<70> LVDS_U2N_VGA
<70> LVDS_U2P_VGA
<70> EDID_CLK_VGA
<70> EDID_DAT_VGA

1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD
1
CFD

2
0402 SL7100
2
0402 SL7101
2
0402 SL7102
2
0402 SL7103
2
0402 SL7104
2
0402 SL7105
2
0402 SL7106
2
0402 SL7107
2
0402 SL7108
2
0402 SL7109
2
0402 SL7110
2
0402 SL7111
2
0402 SL7112
2
0402 SL7113
2
0402 SL7114
2
0402 SL7115
2
0402 SL7116
2
0402 SL7117

LVDS_LCLKP

<45>

LVDS_LCLKN

<45>

+5VS

<27,30,31,37,45,46,48,50,51,56,57,70,80,91>

LVDS_L0N

<45>

LVDS_L0P

<45>

LVDS_L1P

<45>

LVDS_L1N

<45>

LVDS_L2N

<45>

LVDS_L2P

<45>

LVDS_UCLKP

<45>

LVDS_UCLKN

<45>

LVDS_U0N

<45>

LVDS_U0P

<45>

LVDS_U1P

<45>

LVDS_U1N

<45>

LVDS_U2N

<45>

LVDS_U2P

<45>

EDID_CLK

<45>

EDID_DATA

<45>

Title : VGA(2)_LVDS Switch


Engineer:

BU2/RD1
Size
C
Date:
5

Kenny Wu

Project Name

Rev

G60J

1.4
Sheet

Friday, July 31, 2009


1

71

of

99

Title : VGA(3)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

72

of

99

Title : VGA(4)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

73

of

99

Title : VGA(5)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

74

of

99

Title : VGA(6)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

75

of

99

Title : VGA(7)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

76

of

99

Title : VGA(8)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

77

of

99

Title : VGA(9)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

78

of

99

Title : VGA(10)_****
Engineer:

BU2/RD1
Size
Date:
5

Kenny Wu

Project Name

Custom

Rev

G60J

1.4

Friday, July 31, 2009

Sheet
1

79

of

99

1
2
3

Gm(IMON) = 2.4mS , Gm(IMON_MIN) = 2.36mS

1
2

1
2

c1206_h75

c1206_h75
2
1

c0805_h57
1

1
2

1000PF/25V

Close to
Phase 1
Inductor

2
40.2KOhm_0402
1%

1
1%

2.49KOhm_0402
R8063
1
2
1%

R8075

CE8015
470UF/2.5V_7343
NEC-TOKIN/TEPSGV0E477M9-12R

R8055
1.8KOHM_0402
1
2

SHORT_PIN
JP8001

2
1

SHORT_PIN
JP8000

2
1
1500PF/50V
C8027

SI7658ADP-T1-GE3

Q8005

1
2
3

09/04/17

CSP1
10KOHM
R8053

CSN1

3%
AC_BAT_SYS

R8064
R0603(0ohm)
1
2 2

1
2

+ 68UF/25V + 68UF/25V
CE8013
CE8014
@

1
2

C8056 10UF/25V_1206

1000PF/25V

5
S

C8052 10UF/25V_1206

C8054 1UF/25V_0805

1
2
3

TPC28T
T8060

09/06/05

09/07/01
(Thermal need to solve audio noise issue)

DCR = 1m OHM
L8000

1%

Close to
Phase 2
Inductor

1
2

C8060
0.1UF/10V_0402

1
2

2
1%

CE8009
220UF/2V_7343
PANASONIC/EEFSX0D221ER <G>

40.2KOhm_0402
R8073
1
2
1%
2.49KOhm_0402
R8047
10KOhm
R8083
1
2
1
2

CE8012 470UF/2.5V_7343
NEC-TOKIN/TEPSGV0E477M9-12R

1500PF/50V
C8028

(Typ: Rdson = 2.3m OHM)


(Max: Rdson = 2.8m OHM)

Fsw = 1/(CTON x (RTON + 6.5k))=271.5Hz


CTON=16.26pF,RTON=220K

09/04/17

SHORT_PIN
JP8002

2
R8022
2.2Ohm_1206

R8062
1.8KOHM_0402
1
2

5
D

0.36UH
TOKO/FDU1040-R36M
Irat=32A

SHORT_PIN
JP8003

SI7658ADP-T1-GE3

Q8006

VDD

1
2
3

0.22UF/25V_0805
C8047

1UF/10V
C8057

R8052
1KOhm1%
@

C8053

SIR474DP-T1-GE3

Q8003

09/05/04
D

1
2
3

+5VS

SIR474DP-T1-GE3

Q8004

R8077 R0603(0ohm)

SI7658ADP-T1-GE3

AC_BAT_SYS

3%

CSP2
TPC28T
T8070

CSN2

JP8004
A_GND

SHORT_PIN

C8036
1

1%

C8043
0.047UF/16V_0402

SI7658ADP-T1-GE3

Q8001

VDD

R8048

2009.07.01

2009.07.01

1
2

(Typ: Rdson = 2.3m OHM)


(Max: Rdson = 2.8m OHM)

2009.07.01

30
29
28
27
26
25
24
23
22
21

TPC28T
T8056

<6> PM_PSI#

2
1

0.22UF/10V

1000PF/50V_0402
2
1CSP2

1%
1 R8050 2 499Ohm_0402

<6> PM_DPRSLPVR

C8048

R8095
2Ohm_0402
1%

C8042 @

2
100KOhm_0402
1%

C8034
@

Close to
U8000
TPC28T
T8074

2
1
R8051 220KOhm_0402

C8024
@
1000PF/50V_0402

R8076

<30> CPU_VRON

1CSN2 0.1UF/10V_0402

A_GND

<93> CPU_VRON_PWR

MAX17030GTL

11
12
13
14
15
16
17
18
19
20

2
2

C8046
1000PF/50V_0402

1%

Rdroop

C8051
1000PF/50V_0402

R0402

R8066
100Ohm_0402
@

R8082
6.81KOhm

0.36UH
TOKO/FDU1040-R36M
Irat=32A

CE8010
220UF/2V_7343
PANASONIC/EEFSX0D221ER <G>

1
1

1%

<6> VSSSENSE

R8065
R0603(0ohm)
1
2

41
40
39
38
37
36
35
34
33
32
31
1

to 137K

C8044
1000PF/50V_0402
@
A_GND
TPC28T
T8087
2009.07.01
R8086
1
2

2 1

2
100Ohm_0402
1%

1%

09/04/17
BST1
LX1
DH1
DL1
VDD
VRHOT#
DL2
DH2
LX2
BST2

U8000A

1 1

1
2
10Ohm_0402 R8080 Change
1

R8074

1%
2

TPC28T
T8080

CSN3
CSP3
THRM
IMON
ILIM
TIME
VCC
FB
FBAC
GNDS

R8021
2.2Ohm_1206

1%

GND1
CSN1
CSP1
D6
D5
D4
D3
D2
D1
D0
PGD_IN

1
2

1
2
R8079
9.53KOhm
R8070
A_GND 1
R8084 2
21%
1
137KOHM
16.2KOHM
1%

<6> VCCSENSE

1
2
3
4
5
6
7
8
9
10

VSSSENSE

A_GND

R8072
1%
1
2
1KOhm_0402

(Max:51A)
+VCORE

0.22UF/25V_0805

CSN2
CSP2
SHDN#
DPRSLPVR
PSI#
TON
CLKEN#
PWRGD
DRVSKP#
PWM3

C8040
0.1UF/25V 2
1

10Ohm_0805
VCC
1

C8059
1UF/10V

+VCORE

1%

2
100KOhm

<19>
<19>
<19>
<19>
<19>
<19>
<19>

2009.07.01

1
R8061

+3VS

R8092
100KOhm_0402

RIMON
R8069
2

+5VS

Close to
Phase 1
Low_side
MOSFET
13KOhm_0402
1
2
R8068
1%

<6> I_MON

VR_VID6
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0

0.22UF/10V

1000PF/50V_0402

TPC28T
T8085
VCC

Q8002

1000PF/50V_0402

MAX17030GTL

C8038

1
2
3

A_GND

0.1UF/10V_0402
C8035
C8037 @
@
CSN1
2
1

CSP3

Close to
U8000

R8094
2Ohm_0402

R8093
2Ohm_0402

09/06/05

L8001

GND2
GND3
GND4
GND5

1
2
3

1%

@
1

CSP1

1000PF/50V_0402

C8069
2

42
43
44
45

C8070
0.22UF/10V

1%
A_GND

+ 68UF/25V + 68UF/25V
CE8008
CE8011
@
@

TPC28T
T8057

C8068
@

C8049 @
2
1

0.1UF/10V_0402

1000PF/50V_0402

Close to
U8000

U8000B

CSN3

C8071 @
2

C8041 10UF/25V_1206

C8050 10UF/25V_1206

C8039 1UF/25V_0805

RIMON = 0.9V / [ IMAX * Rsense(MIN) * Gm(IMON_MIN)]

C8045

Vcore=1.0125V

09/05/04
SIR474DP-T1-GE3

IMON=Gm(IMON) * [ (Vcsp1-Vcsn1) + (Vcsp2-Vcsn2) ]

09/04/17
Q8000

VR_VID6

AC_BAT_SYS
AC_BAT_SYS

1
2
3

2
47KOhm_0402
2
47KOhm_0402
2
47KOhm_0402
2
47KOhm_0402 @
2
47KOhm_0402 @
2
47KOhm_0402
2
47KOhm_0402 @

1
R8025
1
R8081
1
R8054
1
R8067
1
R8057
1
R8060
1
R8071

SIR474DP-T1-GE3

2
1KOhm_0402
2
1KOhm_0402
2
1KOhm_0402
2
1KOhm_0402
2
1KOhm_0402
2
1KOhm_0402
2
1KOhm_0402

1
R8026
1
R8096
1
R8056
1
R8098
1
R8058
1
R8085
1
R8097

+1.05VO

Q8007

TPC28T
T8035
TPC28T
VR_VID0
T8062
TPC28T
VR_VID1
T8069
TPC28T
VR_VID2
T8059
TPC28T
VR_VID3
T8064
TPC28T
VR_VID4
T8075
TPC28T
VR_VID5
T8066

1016

78PCS

R0402(0ohm)

1
2

1
2

1
2

09/06/05
+ 68UF/25V + CE8019
CE8018
68UF/25V
@
@

@
TPC28T
T8068

C8067
0.22UF/10V

C8063 10UF/25V_1206

1
2

1000PF/25V

C8055 10UF/25V_1206

1
2
3

C8061

R0402(0ohm)

SIR474DP-T1-GE3

Q8009

TPC28T
T8051

09/05/04

1
2
3

R0402(0ohm)
R8078
1
2

R8023

Q8008

2009.07.01
<30,92> VRM_PWRGD

09/04/17

2009.07.01
<29> CLK_EN#

TPC28T
T8079

SIR474DP-T1-GE3

R8000 2 100KOhm

C8062 1UF/25V_0805

AC_BAT_SYS
+3VS

(Max:51A)
+VCORE

DCR = 1m OHM
L8002

TPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28T
T8091 T8090 T8088 T8055 T8072 T8086 T8082 T8061 T8083 T8071 T8081 T8053 T8084

2.49KOhm_0402
R8090
1
2

CSP3

1%

R8087 10KOhm
2

Close to
Phase 3
Inductor

09/05/04
C8064
0.1UF/10V_0402

1
2

(Typ: Rdson = 2.3m OHM)


(Max: Rdson = 2.8m OHM)

1%
40.2KOhm_0402
R8089 2
1

1%

CE8016
220UF/2V_7343
PANASONIC/EEFSX0D221ER <G>

SHORT_PIN
JP8006
@

CE8017 470UF/2.5V_7343
NEC-TOKIN/TEPSGV0E477M9-12R

R8088
1.8KOHM_0402
1
2

1500PF/50V
C8029

+VCORE

2
1

09/04/17

SHORT_PIN
JP8005

1
1

Q8010

Q8011
@

TPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28TTPC28T
T8048 T8078 T8054 T8077 T8073 T8063 T8050 T8052 T8058 T8065 T8067 T8049 T8089

09/05/04

2
VDD

R8024
2.2Ohm_1206

U8003 SKIP#
MAX8791GTA

1KOhm_0402

R8004
1KOhm

<Variant Name>

3%

Title : POWER_VCORE

CSN3

@ C8065
30PF/50V_0402

Engineer:
1

@
1

PWM

SI7658ADP-T1-GE3

BST

R8002
2

PM_PSI#

1
2
3

SI7658ADP-T1-GE3

<15A

1
2
3

Three Phase

>15A

+5VS

C8066
1UF/10V

2009.07.01

LX

R8091
R0603(0ohm)

VO_action

One Phase

DL

<3A

IO_current

GND2
DH

GND1

PM_PSI#

9
8

PM_DPRSLPVR
2

1KOhm

R8003
1KOhm_0402
@

0.36UH
TOKO/FDU1040-R36M
Irat=32A

R8001
PM_DPRSLPVR

1
+1.05VO

Size

Rev

G50J

Date: Friday, July 31, 2009


5

Benson_Lin

Project Name

Custom

0.3
Sheet

80

of

99

TON:(5V/3.3V)
VCC:(200kHz/250kHz)
REF:(300kHz/375kHz)
GND:(400kHz/500kHz)

VENLDO:
Rising Edge:Max:2V;Typ:1.6V;Min:1.2V
Falling Edge:Max:1.06V;Typ:1V;Min:0.94V
350mil

82,83,85,91,93 SUSB#_PWR
2

R8141
0Ohm
@
1

1
2

C8126
1500PF/50V
MLCC/+/-10%
c0603
@

CE8104
2
1

220UF/6.3V
SANYO/6SVPC220MV
2
1

40mil

+3VA

(0.12A)
C

C8100
1UF/10V
@

09/05/04

(Typ: Rdson = 14.5m OHM)


(Max: Rdson = 17.5m OHM)

R8112
13.3KOhm
1%

C8135
39PF/50V
@
2

+15VO

*SECFB:2V(T=4%)

FB1=2V(T=1.25%)

U8101B

R8111
20KOhm
1%

09/05/20

RT8206AGQW

53PCS

GND_17020

GND_17020

(Max:0.02A)

C8124
1UF/25V
MLCC/+/-10%

@
2

1
1
1

TPC26TTPC26TTPC26TTPC26T
T8104 T8108 T8116 T8126

+12VSUS

1MM_OPEN_5MIL

D8103
BAT54S

TPC26TTPC26TTPC26TTPC26T
T8112 T8119 T8101 T8130
1

VOUT:Typ.=12.256V;Max.=12.962V;Min.=11.571V;T=5.76%

+15VO

JP8106

1
2
1
2

2
1

+3VSUS

1
C8104
1000PF/25V

5
1

TPC26TTPC26TTPC26TTPC26T
T8123 T8128 T8136 T8124

C8123
1UF/25V
MLCC/+/-10%

Q8106B
UM6K1N

1
<30,93> VSUS_ON

C8120
0.1UF/25V
MLCC/+/-10%

TPC26T
T8127

R8131
560KOhm

+5VAO 1
2
100KOhm_0402

Q8106A
UM6K1N

+10VO

09/07/01

R8135

TPC26TTPC26TTPC26TTPC26T
T8117 T8107 T8109 T8122
+3VO

R8133
R0603(0ohm)

20mil

Check have or not

2
R0603(0ohm)

09/07/01

DL1

2009/01/10

09/07/01 R8129

D8104
C8121
BAT54S
0.1UF/25V
MLCC/+/-10%

2
@
C8119
0.1UF/25V

Q8104

1
2
3
4

2
R8130
84.5KOhm
1%

FORCE_OFF#_PWR
<32,92>

TPC26T
T8129

+3VSUS (Max:0.919A)

IRF8707PBF
8
7
6
5

+5VSUS

C8122
1UF/25V
MLCC/+/-10%
@

09/07/01

+3VO

+5VO

09/07/01
1
3

+12VSUS

ENBL

1
SHORT_PIN

AC_BAT_SYS

TPC26TTPC26TTPC26TTPC26T
T8134 T8132 T8135 T8121

TPC26T
T8125

JP8107

JP8107 close to Q8104

+3VSUS

+5VO

TPC26TTPC26TTPC26TTPC26T
T8110 T8103 T8114 T8120

GND_17020

GND_17020
GND_17020
GND_17020

GND3
GND4
GND5
GND6

34
35
36
37

SHORT_PIN

C8138
0.1UF/25V
@

R8132
39KOHM
1%

+3VO_FB

2
R8127 1%
200KOhm

SECFB 1

GND_17020

1
2

09/04/17

R8116
2.2Ohm
5%
r1206
@

C8137 39PF/50V
1
2

JP8110 @

SUS_PWRGD

1MM_OPEN_5MIL

JP8104
SHORT_PIN
1
2

R8119
R0603(0ohm)
1
2

09/07/01

Q8103
SI4134DY-T1-GE3
C8111
0.1UF/25V
MLCC/+/-10%

+3VO

JP8101

400mil

Isat=16A
09/06/05

GND_17020

5
6
7
8

R0603(0ohm)
2 +5VAO

2.2UH

FB1=2V(T=1.25%)
R8109
20KOhm
1%

GND_17020

5
6
7
8
1

C8114
1UF/10V
MLCC/+/-10%

(Typ: Rdson = 14.5m OHM)


(Max: Rdson = 17.5m OHM)

<92> SUS_PWRGD

09/07/01

L8100
1

40mil

(3.3V:375kHz)

2
C8136
0.1UF/25V
@

1MM_OPEN_5MIL

R8108
30.9KOhm
1%
1

C8134
39PF/50V
@

+5VA

JP8108
1

SKIP#
R8113
1

+3VO
(Max:9.95A)

DCR:Typ=5.8mOhm;Max=7mOhm

R8124
422KOhm
2
1

GND_17020

+5VAO

OCP>12.2A=>OCP setting 8.2A

DL1

(5V:300kHz)

+5VAO

VOUT:Typ.=3.32V;Max.=3.388V;Min.=3.253V;T=2.05%

CE8103 150UF/4V_7343
@
PANASONIC/EEFCX0G151R
2
1

40mil

+3VO_FB

09/07/01

R8118
R0603(0ohm)
1
2

09/07/01

DC:LIR=0.25;Iripple=2.53A;Ipk=11.22A
09/05/04

1
NC2
LDO
VIN
NC1
ENLDO
VCC
TON
REF

BOOT1
LGATE1
PVCC
SECFB
GND1
PGND
LGATE2
BOOT2

C8110
0.1UF/25V
MLCC/+/-10%

Q8101
SI4134DY-T1-GE3

GND_17020

33
32
31
30
29
28
27
26
25

GND2
BYP
FB2
VOUT1
ILIM2
U8101A
FB1
RT8206AGQW VOUT2
ILIM1
SKIP#
PGOOD1
PGOOD2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2

OCP Set

C8125
1500PF/50V
MLCC/+/-10% @
c0603

8
7
6
5
4
3
2
1

SUS_PWRGD
ENBL

AC:LIR=0.33;Iripple=3.31A;Ipk=11.6A

40mil
09/07/01

17
18
19
20
21
22
23
24

R8125
160KOhm
GND_17020

8
7
6
5

R8115
2.2Ohm@
5%
r1206

JP8109
SHORT_PIN

2
1

JP8105
SHORT_PIN

40mil

C8117
10UF/25V_1206

9
10
11
12
13
14
15
16

C8109
0.22UF/16V
GND_17020

C8103
1UF/10V
MLCC/+80%-20%
2
1

09/06/05

Q8102
SI4134DY-T1-GE3

09/05/04

09/06/05

2
4.7UH

Isat=13A

Separate
10mil

L8101

C8102
0.1UF/50V
@

4
3
2
1

1
2
3
4

GND_17020

1
2
3
4

+5VO

CE8105 220UF/6.3V
SANYO/6SVPC220MV
2
1

CE8101 150UF/6.3V N/A


POSCAP 150UF/6.3V (7343/D) 20%
2
1

3MM_OPEN_5MIL

(0.01A)

R0603(0ohm)

GND_17020

40mil

DCR:Typ=13.2mOhm;Max=15mOhm

R8142
0Ohm
@

C8108
4.7UF/6.3V
MLCC/+/-10%
GND_17020
GND_17020

+5VO
160mil

GND_17020
2

4
3
2
1

2
D
S

Q8100
SI4134DY-T1-GE3

R8117

2
1

8
7
6
5

1
2

C8105
0.1UF/25V
MLCC/+/-10%

C8118
2
1

10UF/25V_1206

OCP>7.15A

09/04/17

09/07/01
2

2
1

+5VAO

R8146
150KOHM
1%
@

VOUT:Typ.=5.09V;Max.=5.217V;Min.=4.966V;T=2.5%

+5VSUS

190mil
GND_17020

09/04/17

C8113
1UF/10V
MLCC/+/-10%

C8112
0.1UF/25V
MLCC/+/-10%

+5VAO

R8122 @
1
2
0Ohm

160mil

AC:LIR=0.47;Iripple=2.61A;Ipk=6.8A
DC:LIR=0.29;Iripple=1.58A;Ipk=6.29A

JP8102

AC_BAT_SYS
D

GND_17020

09/05/04

R8105
0Ohm
r0402_h16
@

(Max:5.5A)

C8115
1UF/10V
MLCC/+/-10%

1
1

R8126
100KOhm
1%

R8114
R0603(0ohm)

SKIP#

R8139
0Ohm
@

09/07/01

R8123
R0402(0ohm)

09/04/17

R8128
10Ohm

09/07/01

SKIP:
GND : DEM operation;
REF : Ultrasonic Mode operation;
VCC : PWM operation.

R8136
470KOhm_0402

38 PCS

<Variant Name>

TOTAL COUNT

Title : POWER_SYSTEM
Engineer:
Size
Date:

Benson_Lin

Project Name

Custom

Rev

G50J

0.1
Sheet

Friday, July 31, 2009


1

81

of

94

Frequency setting
F=300KHz-->R8208=845K ohm
F=250KHz-->R8208=1M ohm

+5VA

RT8204AGQW-->0607-003Y000(06G113115010)
Don't use 0695-00210AS

R8256
100KOhm_0402

1
1

1
2

1
@

Function

<G>

U8204B

VDD

Diode-emulation

GND

Shutdown

18
19

R8254

GND1
GND2
RT8204AGQW

C8201
0.1UF/25V
@

2
100KOhm

(Typ: Rdson = 14.5m OHM)


(Max: Rdson = 17.5m OHM)

R8259
8.06KOhm

CCM

Floating

1%

09/05/04

1
2

EN/DEM

+1.05VO
(Max:7.514A)

CE8202
220UF/2V
PANASONIC/EEFSX0D221ER

JP8218
SHORT_PIN

JP8215
SHORT_PIN

09/07/01

4
3
2
1

1500PF/50V
C8221
@

JP8219
SHORT_PIN

5
6
7
8

Q8203
SI4134DY-T1-GE3

2
5
6
7
8

R8218
2.2Ohm_1206
@

LFB=0.75V

L8202
2.2UH
Irat=14A

CE8201 220UF/6.3V
SANYO/6SVPC220MV

09/06/05

C8252
4.7UF/6.3V

OCP>8.14A

DCR:Typ.=5.8mOhm;Max.=7mOhm

1
R8263
6.8KOHM 09/06/05

1
2

AC:LIR=0.24;Iripple=1.8A;Ipk=8.41A
DC:LIR=0.22;Iripple=1.69A;Ipk=8.36A
VOUT:Typ.=1.052V;Max.=1.069V;Min.=1.036V;T=1.62%

T8249
TPC28T

F=250KHz

09/04/28

C8247
10UF/25V_1206
@

4
3
2
1

2
12
11
10
9

RT8204AGQW

C8248
0.1UF/25V

1
UGATE
PHASE
OC
VDDP

LPGOOD
LFB
LDRV
LGATE

17
16
15
14
13
GND
TON
EN/DEM
LEN
BOOT

FB=0.75V

1.05VO_PWRGD

VOUT
VDD
FB
PGOOD

09/07/01

<92> 1.05VO_PWRGD

1
2
3
4

T8240
TPC28T

2
2
Q8200
SI4134DY-T1-GE3

U8204A

C8204
0.1UF/50V
@

09/04/17

R8260
R0603(0ohm)

C8250
1UF/6.3V

C8219 10UF/25V_1206

2009.07.01

1
1
2

09/05/04

1
1MOhm
1%

R8251
10Ohm

R8253
470KOhm
@
1%

D8205
RB751V-40

C8202
0.1UF/25V

AC_BAT_SYS
+5VO

R8264

+5VO

<80,93> SLP_LAN#_PWR

10mil
100KOhm
R8252

2
Q8212B
UM6K1N

5
6
7
8

R8200
1% 10KOhm

Q8212A
UM6K1N

D8200
1SS355

09/07/01

1
1%

+1.05VO

T8247
TPC28T

T8244
TPC28T

T8243
TPC28T

T8250
TPC28T

T8238
TPC28T

T8248
TPC28T

T8251
TPC28T

T8239
TPC28T

C8242
0.1UF/25V
@

R8262
20KOhm
1%

C8244
220PF/50V_0402
@

59pcs

09/07/01(don't need)

+5VA

Frequency setting
F=300KHz-->R8208=845K ohm
F=250KHz-->R8208=1M ohm
R8229
100KOhm_0402

10mil

C8220

1
2

C8218

10UF/25V_1206

10UF/25V_1206

1
2

1
2
3

<G>

@
2

0.1UF/25V

1
2

OCP>20.4A
(Max:18.062A)
+VTT_CPU
(1.05VS/+1.1VS)

H_VTTVID1=High;VOUT:Typ.=1.052V;Max.=1.069V;Min.=1.036V
R8250=127KOhm;R8255=0 Ohm;H_VTTVID1=Low;VOUT:Typ.=1.1V;Max.=1.118V;Min.=1.082V

@
C8217

1
+

CE8203
330UF/2V N/A
PANASONIC/EEFSX0D331ER

3MM_OPEN_5MIL

1
2

CE8204
330UF/2V
PANASONIC/EEFSX0D331ER

JP8212
SHORT_PIN

2
@

1500PF/50V
C8222
@

JP8202
SHORT_PIN

JP8213
SHORT_PIN

DCR=1.9m Ohm

4
G

JP8205

2
0.56UH
Irat=20A

09/06/05

@
2

3MM_OPEN_5MIL
L8201
TOKO/FDH1040B-R56M=P3

R8219
2.2Ohm_1206
@

Q8207
@
SI7170DP-T1-GE3

Q8206

09/07/01

09/07/01

LFB=0.75V

RT8204AGQW

C8207
0.1UF/50V

5
1
2
3

T8200
TPC28T

1
2
3

CCM

JP8208

1
R8247
3KOhm

C8240
4.7UF/6.3V

F=250KHz

GND1
GND2

+VTT_CPUO

1
2
3

Floating

RT8204AGQW
U8203B

18
19

AC:LIR=0.39;Iripple=7.09A;Ipk=21.61A
DC:LIR=0.37;Iripple=6.62A;Ipk=21.37A

4
S

Shutdown

5
6
7
8

Diode-emulation

GND

12
11
10
9

09/04/28

UGATE
PHASE
OC
VDDP

VOUT
VDD
FB
PGOOD

C8231
0.1UF/25V

SI7658ADP-T1-GE3

<92> VTT_CPU_PWRGD

Function

17
16
15
14
13
GND
TON
EN/DEM
LEN
BOOT

1
2
3
4

FB=0.75V

Q8201
SIR474DP-T1-GE3

1
T8202
TPC28T

09/05/04

09/04/17

VDD

Q8202
SIR474DP-T1-GE3
@

R8235
R0603(0ohm)

U8203A

LPGOOD
LFB
LDRV
LGATE

09/04/17

2009.07.01
1

C8234
1UF/6.3V

EN/DEM

D8202
RB751V-40

1
1MOhm
1%

R8216
10Ohm

R8226
470KOhm
@
1%

1
1

R8248

1
C8203
0.1UF/25V

+5VO
100KOhm
R8221

+5VO

<80,93> SUSB#_PWR

Q8208B
UM6K1N

R8201
1% 10KOhm

AC_BAT_SYS

@
1

RT8204AGQW-->0607-003Y000(06G113115010)
Don't use 0695-00210AS

Q8208A
UM6K1N

D8201
1SS355

09/07/01

R8250=63.4KOhm;R8255=63.4KOhm;H_VTTVID1=Low;VOUT:Typ.=1.1V;Max.=1.118V;Min.=1.082V
09/05/04

R8227
@ 1%
1 100KOhm2

G
3
C

R8228 1% @
<12> H_VTTVID1

1 B

C8225
0.1UF/25V
@

2 S

+VTT_CPU

T8218
TPC28T
T8230
TPC28T

T8209
TPC28T

T8210
TPC28T

T8234
TPC28T

T8223
TPC28T

T8227
TPC28T

T8226
TPC28T

T8217
TPC28T

T8235
TPC28T

T8232
TPC28T

T8207
TPC28T
+VTT_CPUO

C8224
0.1UF/25V
@

09/07/01(don't need)

(Typ: Rdson =3.6m OHM)


(Max: Rdson = 4.3m OHM)

C8227
220PF/50V_0402
@

Q8205
2N7002
@

Q8210
PMBS3904
E @
2

R8223
100KOhm_0402
@

H_VTTVID1

10KOhm_0402

R8237
20KOhm
1%

CPU change Voltage to 1.1V)

R8250
63.4KOhm
1% @

C8228
1000PF/50V
@

1
2

R8231
100KOhm_0402
@ 1%

1
2

R8222
100KOhm_0402
@

R8234
1%
9.53KOHM 09/07/01(Clarkfield

+VTT_CPU_FB

R8255
63.4KOhm
@ 1%

+3VSUS

09/07/01(Clarkfield CPU don't need)

VTT_CPU

CPU

R8255

Low (0V)

1.1V

Clarkfield

9.53K ohm

H(1.05V)

1.05V

Auburndale

8.06K ohm

Unmount/mount

Voltage Range
<Variant Name>

R8228;Q8210;R8231;R8250;
Q8205;R8255;C8228=>Unmount Vmax:1.126V;Vtyp:1.107V;Vmin:1.089V
R8228;Q8210;R8231;R8250;
Q8205;R8255;C8228=>mount

Title : POWER_I/O_1.5VS & 1.05VS


Engineer:
Size
Date:

Benson_Lin

Project Name

Rev

G50J

Custom
Friday, July 31, 2009
1

0.3
Sheet

82

of

99

09/04/28
U8300B

18
19

+5VA

GND1
GND2

RT8204AGQW

RT8204AGQW-->0607-003Y000(06G113115010)
Don't use 0695-00210AS
1

C8339
1UF/6.3V
@
C

T8339
TPC28T

TON=3.85p*RTON*VOUT/(VIN-0.5);
Frequency=VOUT/(VIN*TON)

T8341
TPC28T

1
T8340
TPC28T

C8334
0.1UF/25V
@

T8344
TPC28T

T8345
TPC28T
+1.5V

R8310
20KOhm
1%

T8343
TPC28T

T8336
TPC28T

220PF/50V_0402

CCM

Shutdown

+1.5VO

T8349
T8348
TPC28T TPC28T

VOUT=1.5V
C8330

GND

+1.5V
(Max:8A)

1%

Floating

09/05/04

@
+

2
JP8304
SHORT_PIN
1

2
JP8305
SHORT_PIN
1

2
SHORT_PIN
JP8306

3MM_OPEN_5MIL

CE8300
150UF/2V_7343
PANASONIC/EEFCD0D151ER

1
+
1500PF/50V
C8319
@

JP8301

2
CE8302
470UF/2.5V
NEC-TOKIN/TEPSGV0E477M9-12R

R8327
2.2Ohm_1206
@

R8345
@
100KOhm
2
1%
R8309
20KOhm

Function

1.5UH

CYNTEC/PCMC104T-1R5MN
Irat=16A

1
1

Diode-emulation

L8300
1

3MM_OPEN_5MIL

DCR:Typ.=3.8mOhm;Max.=4.2mOhm

1
1
2

(Typ: Rdson = 14.5m OHM)


(Max: Rdson = 17.5m OHM)

LFB=0.75V

SI4134DY-T1-GE3
Q8305

4
3
2
1

C8309
4.7UF/6.3V

5
6
7
8

09/06/05

Q8301
SI4134DY-T1-GE3
4
5
3
6
2
7
1
8

R8308
4.3KOhm

JP8302

12
11
10
9

F=250KHz

VDD

1
2

5
6
7
8
2
1

17
16
15
14
13
UGATE
PHASE
OC
VDDP

LPGOOD
LFB
LDRV
LGATE

VOUT
VDD
FB
PGOOD

RT8204AGQW

EN/DEM

VOUT:Typ.=1.5V;Max.=1.53V;Min.=1.47V;T=2%

+1.5VO
(Max:10.9A)
OCP>13.3A

T8338
TPC28T

1
2
3
4

FB=0.75V

<92> DDR_PWRGD

DC:LIR=0.31;Iripple=3.33A;Ipk=12.57A

C8336
0.1UF/25V

5
6
7
8

T8335
TPC28T

GND
TON
EN/DEM
LEN
BOOT

U8300A

C8332
1UF/6.3V

R8342
R0603(0ohm)
1
2

Q8300
SI4134DY-T1-GE3

C8304 10UF/25V_1206

1
2

2009.07.01

AC:LIR=0.34;Iripple=3.68A;Ipk=12.74A

C8310
0.1UF/50V
@

4
3
2
1

1MOhm
1%

09/04/17

09/05/04

R8307
10Ohm

D8303
RB751V-40

C8302
0.047UF/16V

1%

@
470KOhm
R8303
1%

R8306
2

2
1

39KOhm

09/04/28

C8303 10UF/25V_1206

+5VO

+5VO

AC_BAT_SYS

Q8306B
UM6K1N
5

R8317

<57,91,93> SUSC#_PWR

10mil

100KOhm
R8301

Q8306A
UM6K1N
2

100KOhm
R8302
D8301 @
1SS355
2
1

Frequency setting
F=300KHz-->R8305=845K ohm
F=250KHz-->R8305=1M ohm

39PCS
B

VO=0.5*Vin=0.5*1.5=0.75V

+5VO

+5VO

100KOhm
R8344

M_VREF

Q8307B
UM6K1N
5

R8314
22KOhm

09/05/04
1

09/04/16
Inrush current

+-18mA
<18>

100KOhm
R8343

C8331
0.1UF/16V

@ D8302
1SS355
1
2

6
1
1
SHORT_PIN
JP8307

09/04/16

09/07/01

100KOhm
R8337
Q8307A
UM6K1N
2

1
C8327
1UF/6.3V

C8308
10UF/6.3V_0805

RT9045GSP

+1.5VO

09/07/01

1
2

C8340

C8311
10UF/6.3V_0805

9
8
7
6
5

0.1UF/16V
1

09/07/01

CE8303 100UF/2.5V_7343

3MM_OPEN_5MIL

VIN
GND1
REFEN
VOUT

GND2
NC3
NC2
VCNTL
NC1

1
2
3
4

JP8300@
1
2
1 2

NEC-TOKIN/TEPSLA0E107M(35)8R
2
1

+0.75VS

R8339
R0402(0ohm)

U8301
T8328
TPC28T

+0.75VO
(Max:1A)

VF=0.75V;T=1%

+1.5VO

1%

SUSB#_PWR

SUSC#_PWR

SUSB#_PWR

<57,91,93>

R8340
C8321
0.033UF/16V

1
68KOHM

1% @

+0.75VREF for DDR3

09/07/01
Check E.E

T8329
T8325
TPC28T TPC28T

<Variant Name>

Title : POWER_I/O_DDR & VTT

+0.75VS

T8330
TPC28T

T8327
TPC28T

Engineer:
Size
Custom
Date:
5

Benson_Lin

Project Name

Rev

G50J

Friday, July 31, 2009

0.3
Sheet

83

of

99

<Variant Name>
A

Title : POWER_N/A
Engineer: Benson_Lin
Size

Project Name

G50J

Date: Friday, July 31, 2009


5

Rev

0.3
Sheet

84
1

of

99

@---R1.3(ASUS P.M Change K/P,E.E Change power budget)


8015_VDD

09/04/17

SHORT_PIN

J8361

1
2

1
1

VOUT:Typ.=1.8V;Max.=1.857V;Min.=1.745V
2

60mil

+5VO

3MM_OPEN_5MIL
@

+1.8VO

@
L8503

JP8504

100mil

DCR=16.2mOhm

2
1

2.2UH
Irat=8.3A

C8515 0.1UF/25V

C8517 22UF/25V
MLCC/+/-20%

Vout=0.8*(1+Ra/Rb)

1%

100mil

C8518 0.1UF/25V

C8512
10UF/6.3V_0805

C8509
0.33UF/10V

R8518

Rb 12KOHM

JP8506

60mil

2 S

+1.8VS_PWRGD <92>

R8523
0Ohm_0402
R8522
0Ohm_0402
@

8015_VDD

1%

R8566
1Ohm
5%

R8520

Ra 15KOhm

D
Q8505
2N7002

G
R8519
0Ohm_0402

100mil RT8015BGQW

1V8_EN 1

1
1

8015_COMP
8015_FB

SUSB#_PWR

11
10
9
8
7
6

SUSB#_PWR

<70,82,83,91,93>

GND2
COMP
FB
PGOOD
VDD
PVDD

C8527 22UF/25V
MLCC/+/-20%

D8502 @
1SS355
2
1

8015_LX

SHDN/RT
GND1
LX1
LX2
PGND

1V8_EN#

09/04/17

1
2
3
4
5

C8523
47PF/50V
MLCC/+/-5%
@

C8564
680PF/50V
R8565
MLCC/+/-10%
47KOhm 1%
1
2 CM 1
2

C8516 22UF/25V
MLCC/+/-20%

U8503

C8519 0.1UF/25V

Freq=1MHZ
R8562
1
28015_SHDN
330KOhm

+1.8VO_SENSE

C8524
@
47PF/50V
MLCC/+/-5%
1
2

Thermal &Voltage drop Issue

VF=0.8V;T=1.5%
R8521
1MOhm

100mil
2

+1.8VS

3MM_OPEN_5MIL
@

Imax=2.5A

12pcs

RT8015B=>R8523mount;R8522unmount;
RT8015A=>R8522mount;R8523unmount

<Variant Name>

Title :
Engineer:
Size

Project Name

Custom
Date: Friday, July 31, 2009
A

POWER_+1.8VS
Benson_Lin
Rev

G50J

0.3
Sheet
E

85

of

99

44pcs
A

G60J CPU use Clarkfiel,so don't need VGA power


<Variant Name>

Title :POWER_+VGFX_CORE
Engineer:
Size
Date:
5

Benson Lin

Project Name

Custom

Rev

G50J

0.3
Sheet

Friday, July 31, 2009


1

86

of

99

<Variant Name>
A

Title : POWER_N/A
Engineer: Jeff_Du
Size

Project Name

G50J

Date: Friday, July 31, 2009


5

Rev

0.3
Sheet

87
1

of

99

Adaptor =120W, 19V/6.32A


120W/90W:R8801=15m OHM(11G21DR01515110)

C8814
1500PF/50V

C8820
1.5NF/50V
@

C8813
1500PF/50V

@
2

BAT_CON

JP8801
BAT BAT

TPC8118

3MM_OPEN_5MIL
C8821
1.5NF/50V
@

A/D_DOCK_IN
1%
R8805
1KOhm_0402

0904

09/07/01(for EMI)

R8806
200KOhm
1%

JP8804
SHORT_PIN
2

AC_BAT_SYS

R8807
1.82KOhm
1%
1
2

@
2

TPC26T TPC26T TPC26T TPC26T


T8809
T8810
T8811
T8812

8
7
6
5

3MM_OPEN_5MIL

1
2
3
4

09/07/01

R8804
13.7KOhm
1%

AC_BAT_SYS_INV

SHORT_PIN
JP8803
1

2
2

C8801
1

0.1UF/25V

R8821
2.2Ohm
1%
@

2MOhm_0402
R8803
1%

JP8800

AC_BAT_SYS

2
SHORT_PIN
JP8802
1

2
1

1
D

C8811
1000PF/50V
@

2N7002
Q8803

T8808

Q8800

BAT

S 2

R8802
100KOHM
0.5%

ACIN

T8803

15mOhm
1%

SI4116DY-T1-GE3
R8831
10Ohm_0805
@

T8802

T8800

TPC26T TPC26T TPC26T TPC26T TPC26T

T8807

R8801

1
2
3
4

09.01.13

09/07/01(change 1206 size for cost down)

Q8801
D 8
7
6
5
G

T8806

T8801

T8805

TPC26T TPC26T TPC26T TPC26T

T8804

A/D_DOCK_IN

09/07/03(for EMI)

<60> A/D_DOCK_IN

65W:R8801=20m OHM(10G21DR02015110)

16.857V < ACIN <18.014V

AC_BAT_SYS_INV to Inverter connect,


Power trace =60mil(min), Put JP8804 close to Q8800

120W: R8807 = 1.82K


90W: R8807 = 6.98K
65W: R8807 = 17.8K

R8808
1%
200KOhm
2
1

2
0Ohm

ACIN

17

U8800
MAX17015BETP+T

C8805 0.1UF/25V

2
1

C8804

C8803

4.7UF/25V_0805
2
1

1
2

2
@

C8816 22UF/25V
MLCC/+/-20%

1
@

C8809 22UF/25V
MLCC/+/-20%

09/07/01

SHORT_PIN
JP8807
1

R8816
19

Q8805
IRF8707PBF

SHORT_PIN
JP8806
1

4
3
2
1

R8809
100KOhm Close
@

2P/3P, 2400mAh

to Q8805

09/07/28 PR

21

ACIN

4
3

BAT

BAT

CC
BP

ISET

ACOK#

10

R8818
1MOhm_0402
@

0113

C8812
0.1UF/25V

ISET

VCTL

R8817
R0402(0ohm)

1
2

R8814
750Ohm

20

ISET

2
1KOhm

IINP
BATT

VCTL

1
20mOhm
1%

11

CSIN
CSIP

R8812
2

6.8UH
Irat=8A

12

PGND
AGND

12.641V(min) < VBAT-12.515(Typ) < 12.768V(Max)

L8802
1

R8811
<30> ISET_EC

AD_IINP

<90> AD_IINP

09/07/01

16

5
6
7
8

DLO

TPC26T TPC26T TPC26T


T8813
T8814
T8815

09/07/01(change 1206 size for cost down)

15

SHORT_PIN
JP8805
1

9
CSSN

1
DCIN

LX

09/07/01

R8810
10KOhm
@

1%

DHI

Q8804
IRF8707PBF

LDO
GND1
GND2
GND3
VAA
GND4

R8822
1Ohm 1%
1
2

14

C8810
0.01UF/50V

C8808
1UF/10V
1
2 VAA

CSSP

13
22
23
24
18
25

BST

C8800
0.47UF/25V_0805

4
3
2
1

1
2

LDO

VAA

1027

C8807
0.1UF/25V

09/07/01

C8806
4.7UF/6.3V
2

C8802
1UF/25V
MLCC/+/-10%

1%
AD_IINP

17015_DCIN

2
2.2Ohm

R8815
10KOhm
0.5%

5
6
7
8

2
R8820
1

09/07/01

D8800
1N4148W

4.7UF/25V_0805
2
1

AC_BAT_SYS
C

T8816

2.0188V

0.055V
0.865V

TPC28T

1024
VFB=2.1;T=0.4%

CHG_CURRENT

0.157A
2.472A(0.52C)

R8813

PRECHG

<30> VSET_EC

2
66.5KOhm
0.1%

Quick CHG

0.1%
2

R8828
66.5KOhm
0.1%
1

Ichg=(240m/RS2)*(VISET/VAA)
Ichg=(240m/20m)*(0.055/4.2)=0.157A
Ichg=(240m/20m)*(0.865/4.2)=2.4714A

R8819
249KOhm
1

0.1294V

ISET(Voltage)

<30> AC_IN_OC#

ISET_EC

MAX17015 VBAT setting:


VCTL connect to GND,VFB=2.1V
VBAT=2.1*(R8819+R8828)/R8828
Fix R8828 to 10K, adjust R8819

VSET_EC

BAT

VCTL connect to GND,VFB=2.1V

1.4106V

12.545V

ON

R8819=30K,VBAT=8.4V(2cell)

VBAT=2.1*(R8819+R8828)/R8828

3.2871V

5.519V

OFF

R8819=49.9K,VBAT=12.579V(3cell)

12.641V(min)<VBAT-12.515(Typ)<12.768V(Max)

R8819=69.8K,VBAT=16.758V(4cell)

<Variant Name>

Title : CHARGER_201
Engineer:
Size

Rev

G50J

C
Date:

Benson_Lin

Project Name
Friday, July 31, 2009

0.3
Sheet

88

of

99

<Variant Name>
A

Title : POWER_N/A
Engineer: Jeff_Du
Size

Project Name

G50J

Date: Friday, July 31, 2009


5

Rev

0.3
Sheet

89
1

of

99

BATTERY IN DETECT
+5VAO

TPC26T
T9002

Master Battery: BAT1_IN_OC#


Second Battery: BAT2_IN_OC#

+5VO

ADAPTER IN DETECT

<30>

BAT1_IN_OC#

3
Q9000B
UM6K1N

Second Battery: TS2#

R9001
100KOhm_0402

Master Battery: TS1#

Use MAX17015 IC function to Cost down component

R9002
100KOhm_0402

Q9000A
UM6K1N

2
1

<60> TS1#

2.Cost down : mount R9004.R9003.Q9002.C9003


3.Cost down : mount R9008.C9003

+3VA

090113(Cost down to Check)


R9003
100KOhm_0402
@

+3VO

1.Original : mount R9001.R9002.C9003.Q9000A.Q9000B


C9003
1000PF/50V_0402

R9004
100KOhm_0402
@

Q9002 @
2N7002

1
G
3
D

2 S

R9008 5% @
0Ohm_0402

090703(Cost down to Check)

POWER LIMIT CIRCUIT


@---09.07.01(Cost Down)

VAA

<88> AD_IINP
C9008
100PF/50V
@

TPC26T
T9004

+5VO
@

PW RLIMIT#

PW RLIMIT# <30>

VAA=4.2V;T=0.47%

R9007 @
2

100KOhm 1%

2 S

Q9001
2N7002
@

C9006
0.1UF/25V
@

C9005
0.1UF/25V
@

C9004 @
47UF/6.3V_1206

C9007
0.1UF/25V
@

V-

3
@

R9005
365KOHM
@

1%

090113(Check)

3
U9001
LMV321IDBVR
@

Viinp=3.326V(Max);
3.297V(Typ);
3.267V(Min)

D9000
1SS355
V+

1%

+2.5Vref delete

R9006
100KOhm
@

090113(Check)

Pinput=111.8625W----->Iinput=5.8875A

4pcs

RS1=20mohm,Glinp=2.8uA/mV,Riinp=10K
Iinput=Viinp/(RS1*Giinp*Riinp)=Viinp/(20m*2.8uA/mV*10K)=5.8875A----->Viinp=3.297V

<Variant Name>

Title : POWER_DETECT
Engineer: Benson_Lin
Size

Project Name

Custom
Date:
5

Rev

G50J

0.3

Friday, July 31, 2009

Sheet
1

90

of

99

SUSC#_PWR POWER

C9109
0.033UF/16V

1 1
1

1
2

C9113
0.1UF/25V
@

+12V

+5V

1
B

10K

47K

R9103
100KOhm
1%

Q9107

+5VS

C9107
0.1UF/25V
@

(Max:2.21A)

SI4134DY-T1-GE3

1 1

47KOHM
1

+3V

TPC26T
T9112

R9107
2

8
7
6
5

+5VO

(Max:3.28A)

TPC26T TPC26T
T9101
T9127

Q9106
D
S
1
2
3
4
G

C9105
0.033UF/16V

47K

TPC26T
T9119
SUSC#_PWR

2009/06/05

22KOhm
1

UMC4N
+12VSUS

SI4134DY-T1-GE3

+3VS

C9102
0.1UF/25V
@

C9104
0.1UF/25V

SI4134DY-T1-GE3

(Max:1.25A)

C9106
0.1UF/25V
@

TPC26T TPC26T
T9124
T9113

R9110
2

47K

47KOHM
1

R9108
2

Q9108
D
S
1
2
3
4
G

8
7
6
5

+3VO

+1.8VS=1.395A
(Max:6.825A)

TPC26T TPC26T
T9109
T9114

2009/06/05

Q9101
S
1
2
3
4
G

+5VO

Thermal &Voltage drop Issue

8
7
6
5

TPC26T
T9108

2009/06/05
D

C9110
0.033UF/16V

SI4134DY-T1-GE3

22KOhm
1

R9109
2

+3VO

Q9115
S
1
2
3
4
G

8
7
6
5

TPC26T
T9126

2009/06/05

SUSB#_PWR POWER

1 1
1

+1.05VM

+12VM

47K

No circuit connect to E.E circuit

10K

R9122
100KOhm
1% @

47K

2
1

09.04.09

C9116
0.1UF/25V
@

(Max:2.342A)

TPC26T
T9116
@

09.04.09

+5VSUS
R9133 @
100KOhm
2

2009/01/10(unmount)
Q9112B
UM6K1N
@

+3VM

Q9111

10K

47K

47K

0Ohm
1

47K

+12VS

R9129
2

R9134
100KOhm
@

SLP_M#_PWR

TPC26T
T9120
@

0Ohm
1

C
4

(Max:0.02A)

R9130
2
@

R9102
100KOhm
1%

22KOhm
1
@

47K

TPC26T
T9102

TPC26T
T9129

C9118
0.033UF/16V
@

UMC4N

UMC4N

TPC26T TPC26T
T9125
T9115
@
@
R9120
2

SI4134DY-T1-GE3

(Max:1.3A)

C9115
0.1UF/25V
@

+1.05VS

C9114
0.1UF/25V
@

Q9102 @
S
1
2
3
4
G

+12VSUS

SUSB#_PWR

8
7
6
5

1%

SLP_LAN#_PWR

+12VSUS

R9123 @
10mOhm_1508
2

C9112
0.033UF/16V

SI4134DY-T1-GE3

+1.05VO

1 1

47KOHM
1

R9118
2

TPC26T TPC26T
T9104
T9130

+1.05VS=+VTT_PCH
(Max:5.172A)

22KOhm
1

2
8
7
6
5

C9117
0.033UF/16V
@

2009/06/05

2009/06/05
+1.05VO

R9125
2

SI4134DY-T1-GE3

Thermal &Voltage drop Issue


Q9110
D
S
1
2
3
4
G

Q9116 @
S
1
2
3
4
G

8
7
6
5

TPC26T
T9110
@

+3VO

+1.5VS

C9108
0.1UF/25V
@

C9111
0.033UF/16V

SI4134DY-T1-GE3

TPC26T
T9132
@

2009/06/05

R9124 @
10mOhm_1508
1
2
1%

(Max:2.9A)

47KOHM
1

R9117
2

Q9109
S
1
2
3
4
G

8
7
6
5

+1.5VO

@Cost down---PR Unmount(combine with SUSB#_PWR)

TPC26T TPC26T
T9103
T9128

2009/06/05

IAMT POWER

Q9105

2009/01/10(add)

Q9112A
UM6K1N
@

2009/07/01_For power +3VA test; If short +3VA JP point to check power;


should be cut off this temp line.
TPC26T
T9122

2009/07/01

<30,36,43,57,92>

ME_PM_SLP_LAN#

R9126 @
1KOhm
1
2

<83,93>

SLP_M#_PWR

ME_SLP_M_EC#

TPC26T
T9136

54pcs
2009/07/01
<Variant Name>

R9128
<30,57>

GFX_VR_ON

R0603(1KOhm)

TPC26T
T9123

IAMT

TPC26T
T9137

<30,57>

1
TPC26T
T9133

2009/07/01

TPC26T
T9138

Title : POWER_LOAD SWITCH

R0603(1KOhm)

R0603(1KOhm)

Engineer: Benson_Lin
<70,82,83,85,93>

<83,93> SUSC#_PWR

R0603(1KOhm)

R9104
TPC26T
T9134

R9127

NON_IAMT

SLP_LAN#_PWR

<83,93>

GFX_VRON_PWR

TPC26T
T9121
<30,57> SUSC_EC#

<30,57> SUSB_EC#

2009/07/01

2009/07/01
R9106

R0603(1KOhm)

SUSB#_PWR

<70,82,83,85,93>

TPC26T
T9135

<30,36,43,57,92> SUSB_EC#

TPC26T
T9139

R9105

TPC26T
T9131

Size

2009/01/13_R9106(mount); R9126(unmount)for Test

Project Name

Custom
Date:
2

Rev

G50J

0.3
Sheet

Friday, July 31, 2009


1

91

of

99

1
2

1
+3VSUS

T9203
TPC26T
2009.07.01

<70> PWR_OK_VGA

T9200
TPC26T

3 GND

Y
NC7SZ08P5X

R0402

H_VTTPWRGD <3>
1
R9213
1KOhm_0402
1%

2
R9204 @
0Ohm_0402

2009.07.01(for CPU Auburndale)


T9210
TPC26T

ME_+VM_PWRGD

ALL_SYSTEM_PWRGD <22,30,67>

R9212
2KOHM_0402
1%

T9206
TPC26T
<86> GFX_PWRGD

Clarkfield
Auburndale

R0402
T9205
TPC26T
2009.07.01
R9203
1
1

X
R9204

2 B

T9207
R0402
TPC26T
2009.07.01
R9208
1
1

<85> +1.8VS_PWRGD

CPU

U9200
1 A
VCC

BOM change
YES/NO

D9201
1SS355
R9202
1
2

<83> DDR_PWRGD

<30,81> SUS_PWRGD

T9204
TPC26T

POWER GOOD DETECTER

+3VS

R9200
100KOhm_0402

+3VSUS

R9205
100KOhm_0402

1006

1
D9203 @
1SS355

2009.07.01(for CPU IAMT POWER)


+3VSUS

VTT_CPU_PWRGD

1
D9202
1SS355

<86>

T9208
TPC26T

R9210
100KOhm_0402

1.05VO_PWRGD

<82>

R9219
100KOhm_0402

T9211
TPC26T
1

2009.07.01(for CPU Auburndale)

+3VS

T9201
TPC26T
1

1
D9204
1SS355

FORCE_OFF#_PWR

<32,81>

090113(D9204 add in power place)

R9201
560KOhm
1%

Q9200B
5

UM6K1N

2 B

<32,81>

1
ALL_SYSTEM_PWRGD

FORCE_OFF#

2
D9200
1SS355

+3VSUS

U9201
1 A
VCC

<30,80> VRM_PWRGD

R9207
100KOhm_0402

T9209
TPC26T

SUSB_EC#

<30,36,43,57,91> SUSB_EC#

+3VS

090113(D9202 move to E.E place)

2
Q9200A

Y
NC7SZ08P5X

UM6K1N
3 GND

C9200
4.7UF/6.3V

1006

2009.07.01(For IAMT)

+3VSUS
1

2009.07.01

R9215
100KOhm_0402
@

+3VSUS

1
G

R9209 @
2
1
0Ohm_0402

R9206
100KOhm_0402
@
2

2009.07.01

1.05VO_PWRGD

<82>

Q9201B
UM6K1N
@

42pcs

Q9201A
UM6K1N
@

100KOhm
R9211
1%
@

R9214 1% @
1
2
270KOhm

T9202
TPC26T
@

+3VSUS

+3VM

<3>

1
2

C9202
0.047UF/16V
@

ME_+VM_PWRGD

2 S

Q9203
PMBS3904
E@
2

R9216
100KOhm
1%
@

ME_+VM_PWRGD

Q9202
2N7002
@

1 B
1

+1.05VM

3
C

R9217 1% @
20KOhm
1
2

R9218
100KOhm_0402
@

C9201
0.047UF/16V
@

<Variant Name>

Title : POWER_PROTECT

2009.07.01

Engineer: Benson Lin


Size

Project Name

Custom
Date:
5

Rev

G50J

0.3

Friday, July 31, 2009

Sheet
1

92

of

99

AC_BAT_SYS

AC_BAT_SYS

<70,80,81,82,83,86,88>

BAT <88>

BAT

BAT_CON <60,88>

BAT_CON

FOR POWER TEST


+3VA

+3VA <20,30,56,57,81>

+5VAO

+5VAO <81,85,90>

+5VA

+5VA <31,56,81>

+3VA

JP9300 @
2 2

TPC26T
T9301
CPU_VRON_PW R

<80>

SGL_JUMP

+0.9VO

+0.9VO

+1.05VO

+1.05VO <80,82>

+1.5VO

+1.5VO <83,91>

+5VSUS

+5VSUS <27,56,81,86>

+3VSUS

+3VSUS <3,21,22,24,25,27,30,33,37,53,70,81,82,92>

+12VSUS

SGL_JUMP

JP9302

JP9303

JP9304
+5V <31,36,44,45,46,52,56,57,65,68,70,85,91>

+3V <24,31,43,45,57,61,64,68,69,91>

+12V

+1.8V

+0.9V

+0.9V

SUSC#_PW R

<83,91>

TPC26T
T9304
VSUS_ON <30,81>

TPC26T
T9305

SLP_M#_PW R

<30,81>

SLP_LAN#_PW R

<30,81>

SGL_JUMP

+12V <37,42,68,91>

+1.8V

TPC26T
T9303

SGL_JUMP

+3V

SGL_JUMP

+12VSUS <28,70,81,91>

+5V

SUSB#_PW R <70,82,83,85,91>

+1.8VO

JP9301 @
2 2

+1.8VO

+3VO <81,91>

+5VO <81,82,83,90,91>

+3VO

JP9305

TPC26T
T9306

+5VO

TPC26T
T9302

SGL_JUMP
+3VS <16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,36,37,40,41,42,43,44,45,46,47,48,50,51,53,56,57,64,65,66,67,70,80,85,91,92>

+5VS

+5VS <27,31,37,45,46,47,48,50,51,56,57,71,80,91>

JP9306
+12VS

+12VS <28,45,70,91>

+1.5VS

+1.5VS <26,43,53,57,64,70,91>

+VCCP

+VCCP

+VCORE

TPC26T
T9307
GFX_VRON_PW R <30,81>

+3VS

SGL_JUMP

+VCORE <6,57,80>

<Variant Name>

Title : POWER_SIGNAL
Engineer: Benson_Lin
Size

Project Name

Custom
Date:
5

Rev

G50J

0.3

Friday, July 31, 2009

Sheet
1

93

of

99

Design rating

SLP_LAN#_PWR

VSUS_ON

SI4134

+3VM

(1.3A)

SI4134

+3VSUS

(0.919A)

SI4134

+3V

(1.25A)

SI4134

+3VS

(6.825A)

+3VA

(0.12A)

(10.414A)

SUSC#_PWR

+3VO

SUSB#_PWR

+5VAO
+3VA
AC_BAT_SYS
+5VO

SUSC#_PWR

AC(adapter)
RT8206A

SUSB#_PWR

VSUS_ON

SI4134

ISET_EC

Charger

VSET_EC

MAX17015B

(3.28A)

+12V

(0A)

SUSC#_PWR

+12VS

SUSB#_PWR

UMC4N
(SWITCH)

+5VO_DL1

+5VAO

(2.21A)

+5VS
+12VSUS

charge pump
FORCE_OFF#_PWR

(0.01A)

+5V

UMC4N
(SWITCH)

SI4134

+5VO

BAT_CON

+5VSUS

(6.915A)

(0.02A)

+5VAO

(0A)

+1.8VS

(1.395A)

SUS_PWRGD

SUSB#_PWR

VIN=+3VS
C

+1.8VO
G966A

Vpp=+5V
SLP_LAN#_PWR

+1.05VO
SLP_LAN#_PWR

RT8204A

+5VO

1.05VO_PWRGD
SUSB#_PWR

SUSB#_PWR

SI4134

+1.05VS

(5.172A)

SI4134

+1.05VM

(2.342A)

+VTT_CPU

(18.062A)

(7.514A)

+VTT_CPU
RT8204A

+1.5VO

SUSC#_PWR

+1.5V

(8A)

+1.5VS

(2.9A)

RT8204A

+5VO

(10.9A)
DDR_PWRGD

SUSB#_PWR

VIN=+1.5VO

(18.062A)

VTT_CPU_PWRGD

+5VO

SUSB#_PWR

SI4134

+0.75VO

+0.75VS

RT9045

(1A)

(1A)

VCNTL=+5VO
GFX_VRON_PWR
B

+5VS

+VGFX_CORE_0

+VGFX_CORE

MAX17028
CPU:
Auburndale

(15A)

(15A)

GFX_PWRGD

CPU_VRON,
CPU_VRON_PWR

+3VS
1.
2.
3.
4.

VR_VID0~VR_VID6;
PM_DPRSLPVR,PM_PSI#;
CLK_EN#;
VCCSENSE,VSSSENSE

MAX17030+
MAX8791
CPU:
Auburndale
Clarkfield

(51A)

NVVDD

(19.6A)

+1.5VS_VGA

(7A)

(51A)

I_MON

AC_BAT_SYS_VGA
SUSB#_PWR_VGA

+VCORE
VRM_PWRGD

NVVDD
ISL6228
Nvdia

+5VS_VGA

+1.5VO_VGA

(19.6A)
(7A)

VCC_GFX_COR_PWRGD

SUSB#_PWR_VGA

VIN=+1.5VS_VGA

+1.05VO_VGA

+1.05VS_VGA

G9731

(2.17A)

(2.17A)

Vpp=+5VS_VGA

<Variant Name>

Title : POWER_FLOWCHART
Engineer: Benson_Lin
Size

Project Name

Rev

G50J

Custom
Date:
5

Friday, July 31, 2009


1

0.3
Sheet

94

of

99

JUMP must be shorted:


---------------------JP1601,JP1801,JP1802,JP2601,JP2602,JP2603,
JP2701,JP2702,JP2703,JP2704,JP8100,JP8101,
JP8102,JP8106,JP8205,JP8301,JP8504.

OPTIONAL selection:
------------------@
-> no-stuff for all
CFD
-> stuff for Clarkfield with MXM
CFD@ -> no-stuff for Clarkfield with MXM
AUB
-> stuff for Auburndale with MXM (switchable GFX)
AUB@ -> no-stuff for Auburndale with MXM (switchable GFX)
IAMT -> stuff for IAMT sku
IAMT@ -> no-stuff for IAMT sku
NON_IAMT -> stuff for non-IAMT sku
NON_IAMT@ -> no stuff for non-IAMT sku
CPU_XDP -> stuff for CPU XDP using
CPU_XDP@ -> no-stuff for CPU XDP using
PCH_XDP -> stuff for PCH XDP using
PCH_XDP@ -> no-stuff for PCH XDP using

R1.1--> R1.2 Changed List:


------------------1.Refer to #413686.
2.For the buffered mode is stable.
3.For Deleting PCH XDP, modify P20,P67.
4.For MXM 2.1a, modify P21, P70.
5.For PCIE CB,modify P40, P24.
6.Refer to DG R1.0.
7.Del the tested 0ohm.
8.For LVDS display on AUB.
9.Change DP port from B to D by Intel recommendation.
10.For reassigning USB Port, modify P24.
11.Repair R1.1 bug.
12.For Lighting Keyboard.
13.For Non-IAMT.
14.Remove PCIE<-->SATA Circuit(P66) for PCH SATA stable.
15.For Project SPEC, Del P68.
16.Add Second Source.

R1.3--> R1.4 Changed List:


------------------1.Intel recommended.
2.For G60J SPEC.
3.Change CK505 from ICS3362 to ICS3197.
4.For PCH GPIO Definition.
5.R1.3 bug fixed.
6.GLAN from RTL8111C to AR8131
7.Add HDMI Switch(PI3HDMI201).
8.NV recommonded.
B

Title : System History


Engineer:

BU2/RD1
Size
C
Date:
5

Gary Tsai

Project Name

Rev

G60J

1.1

Friday, July 31, 2009

Sheet
1

95

of

99

I/O Board
USB Port 0

+5V_USB_IO

IOJ102
IOJ101

+5V_USB_IO

USB_PN0_IO_CON
USB_PP0_IO_CON

IO_C101
0.1UF/16V

GND_IO

1
GND_IO
USB_PP0_IO_CON

IO_CE101
47UF/6.3V

IO_LX101
90Ohm/100Mhz
@

1
2
3
4

1 P_GND4 8
7
2 P_GND3
3 P_GND2 6
5
4 P_GND1
USB_CON_1X4P

GND_IO

GND_IO

IO_D102
IO_D101
@
@
0603-050E101NP-LF 0603-050E101NP-LF

2 0Ohm

0Ohm

IO_R104

USB_PN0_IO_CON

3
IO_RNX101A 2

GND_IO

GND_IO

USB Port 1
IOJ103
USB_PN1_IO

0Ohm

USB_PN1_IO_CON

+5V_USB_IO

IO_R116

2 0Ohm

IO_RNX102A 2

0Ohm

USB_PP1_IO_CON

IO_C102
0.1UF/16V

1
2
3
4

1
2
3
4

P_GND4
P_GND3
P_GND2
P_GND1

8
7
6
5

USB_CON_1X4P

GND_IO

GND_IO

GND_IO
IO_D104
IO_D103
@
@
0603-050E101NP-LF 0603-050E101NP-LF

USB_PP1_IO

IO_CE102
150UF/6.3V

USB_PN1_IO_CON
USB_PP1_IO_CON

R1.2

IO_LX102
90Ohm/100Mhz
@

AGND_IO

AGND_IO

IO_RNX102B 4

HP_JD_IO
SPDIF_JD_IO
LINE1_JD_IO
MIC_JD_IO
SPDIF1_OUT_IO
HP_R_IO
HP_L_IO
LINEIN_R_IO
LINEIN_L_IO
MIC_IO

USB_PP0_IO

USB_PN1_IO
USB_PP1_IO

GND_IO

USB_PN0_IO
USB_PP0_IO

0Ohm

IO_RNX101B 4

20
19 SIDE1 22
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
21
2 SIDE2
1
W TOB_CON_20P

USB_PN0_IO

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS_IO

GND_IO

GND_IO

GND_IO

HP1_IN#_IO
JACK_IN#_IO

Headphone &
S/PDIF Jack

1
2

2 0Ohm
2 0Ohm

1
1

SPDIFOUT_IO

10K

AGND_IO
6

IO_R107
IO_R108

SPDIF1_OUT_IO

HP1_IN#_IO

AGND_IO

AGND_IO

IO_C104
100PF/50V
@

6
1
4
5
7
11
12

+3VS_SPDIF_IO

IO_Q102

JACK_IN#_IO

2 S

2N7002

IO_C103
100PF/50V
@

JACK_IN#_IO

IO_C111
1000PF/50V
@

IO_C105
0.1UF/16V

3
2

47K

HP1_IN#_IO

IO_Q101B
UM6K1N

IO_Q103

47K

2
IO_Q101A
UM6K1N

HP_JD_IO

1
4

IO_R113
100KOhm

47K

IO_R112
100KOhm

UMC4N

HP_R_CON_IO
HP_L_CON_IO

+3VS_SPDIF_IO

2 0Ohm
2 0Ohm

1
1

+3VS_IO

+5V_USB_IO

IO_R105
IO_R106

+5V_USB_IO

IOJ104
HP_R_IO
HP_L_IO

SPDIF_JD_IO

A
B
C

IO_C106
100PF/50V
@

GND
VCC
Vin

MS

9
10

PHONE_JACK_8P

IO_C110
1000PF/50V
@

AGND_IO

Line-in Jack
AGND_IO

AGND_IO
IOJ105
LINE1_JD_IO

2 0.1UF/16V

2 0Ohm

LINEIN_L_IO

IO_R110

2 0Ohm

R1.2

GND_IO

AGND_IO

LINE1_JD_IO

LINEIN_R_CON_IO
LINEIN_L_CON_IO
IO_C107
100PF/50V
@

IO_C115 1

2 0.1UF/16V

IO_R109

IO_C114 1

LINEIN_R_IO

IO_C108
100PF/50V
@

5
4
3
6
2
1

R
L

7
8
9
10

AUDIO JACK
PHONE_JACK_6P

IO_C112
1000PF/50V
@

AGND_IO

MIC In Jack
AGND_IO
IOJ106
MIC_JD_IO

Left Screw Hole


A

Right Screw Hole

IO_H1

IO_R111

2 0Ohm

MIC_CON_IO

MIC_IO

R1.2

IO_H2

GND_IO

NP_NC1GND5
NP_NC2GND4
GND2 GND3

6
5
4

1
2
3

NP_NC1GND5
NP_NC2GND4
GND2 GND3

6
5
4
GND_IO

D110N&DO130X110N

AGND_IO

D110N

MIC_JD_IO

1
2
3

IO_C109
100PF/50V
@

5
4
3
6
2
1

R
L

AUDIO JACK
PHONE_JACK_6P

IO_C113
1000PF/50V
@

AGND_IO

Title : USB & Audio Jack

ASUSTeK COMPUTER INC. NB4


Size
Date:

Engineer:

Kenny Wu

Project Name

Custom
4

AGND_IO
AGND_IO

7
8
9
10

Rev

G60J

1.1

Friday, July 31, 2009

Sheet
1

96

of

99

Title : ****
Engineer:

BU2/RD1
Size
Date:
5

Gary Tsai

Project Name

Custom

Rev

G60J

1.1

Friday, July 31, 2009

Sheet
1

97

of

99

Power On Sequence Diagram

Rev. 0.2

Reset
Logic
(RC)
P.32

P.81

+VGFX_CORE

19 GFX_VR_ON

22

+0.75VS
+1.5VS
+1.8VS
+3VS
+5VS
+12VS

15 SUSB_EC#

18

GFX_PWRGD

PWROK
Logic1
P.92

PWROK
Logic2
P.92

CPU_VRON

VRM_PWRGD

ME_+VM_PWRGD

14 SUSC_EC#

ALL_SYSTEM_PWRGD

23 26 16 24

PLT_RST#
CPU_PWRGD

PCH

15 14

13

29

30

28

VCCPWRGOOD_0
VCCPWRGOOD_1

5 SUS_PWRGD

+1.5V
+3V
+5V
+12V

DRAMPWRGD

PCH_PWROK
SYS_PWROK
SUSB_EC#
SUSC_EC#
ME_SLP_M_EC#

+3VSUS
+5VSUS
+12VSUS

ME_PWROK
AUXPWROK

10
12 To EC
11
12

H_DRAM_PWRGD

3 VSUS_ON

PM_SUSC#
SLP_S4#
PM_SUSB#
SLP_S3#

PWROK
Logic3
P.92

H_VTTPWRGD 21

VDDPWRGD

P.81

ME_PM_SLP_M#
ME_PM_SLP_LAN#

BUF_PLT_RST#

EC
IT8512E
(+IT8301E)

1 +3VA_EC

MAX17020

ME_AC_PRESENT 7
ME_SusPwrDnAck 4
PM_PWRBTN# 9
PM_RSMRST# 6
ME_PWROK 17
PM_PWROK 27

RSTIN#

+3VA
+5VA

AC_BAT_SYS

Power On
Button

H_CPUPWRGD

PWR_SW# 8

EC_RST#

CPU

VTT_PWRGD

SYSTEM_PWRGD

+VTT_CPU

20

+VTT_CPU_PWRGD

12

ME_PM_SLP_LAN#

+1.1VM_LAN

15 SUSB_EC#

13

ME_SLP_M_EC#

+1.1VM

+VM_OK
Logic
P.84

+VTT_PCH

+3VSUS

12

ME_PM_SLP_LAN#

Power On Sequence

+3VM
IMVP6.5
+VCORE

25 CLK_PWRGD

CLK Gen.
CK505

30
A

Title : Power On Sequence


Engineer:

BU2/RD1
Size
C
Date:
5

Gary Tsai

Project Name

Rev

G60J

1.1

Friday, July 31, 2009

Sheet
1

98

of

99

Power-On Sequence
Timing Diagram Rev. 0.2

1 +3VA/+5VA/+3VA_EC
2 EC_RST#
3 VSUS_ON
+3VSUS/+5VSUS
D

(pull up to +3VSUS)

4 ME_SusPwrDnAck
5 SUS_PWRGD

T0=20ms

T1<200ms(check)

6 PM_RSMRST#
7 ME_AC_PRESENT
(falling edge)

8 PWR_SW#

T2=50ms

9 PM_PWRBTN#
10 ME_PM_SLP_M#
11 PM_SUSC#
PM_SUSB#/
12 ME_PM_SLP_LAN#
+1.1VM_LAN
C

13 ME_SLP_M_EC#
+1.1VM/+3VM

14 SUSC_EC#
+1.5V/+3V/+5V

15 SUSB_EC#
+0.75VS/+1.5VS/
/+1.8VS/+3VS/+5VS
16 ME_+VM_PWRGD

T3=2ms

17 ME_PWROK
18 SYSTEM_PWRGD
+VTT_CPU
B

19 GFX_VR_ON

T=TBD

+VGFX_CORE

20 +VTT_CPU_PWRGD

T=1.25ms

21 H_VTTPWRGD

T=60us(typ.)

22 GFX_PWRGD

T=TBD

23 ALL_SYSTEM_PWRGD

T02=110ms

24 CPU_VRON

10~100us

+VCORE

25 CLK_PWRGD

(inversion of CLK_EN#)

3~20ms

26 VRM_PWRGD

27
28

PM_PWROK

T04=10ms

H_DRAM_PWRGD

29

Title : Power On Timing

H_CPUPWRGD
Size

30
5

Engineer:

BU2/RD1

BUF_PLT_RST#

C
Date:
4

Gary Tsai

Project Name

Rev

G60J

1.1

Friday, July 31, 2009

Sheet
1

99

of

99

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