VERILOG CODE FOR ALU:

`timescale 1ns / 1ps

module logic_unit(d_out1,logic_unit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin
if(logic_unit== 1'b1)
begin
if(s0 == 1'b0 & s1 == 1'b0)
begin
d_out1 = ( A & B);
end
else if(s0 == 1'b1 & s1 == 1'b0)
begin
d_out1 = ( A | B);
end
else if(s0 == 1'b0 & s1 == 1'b1)
begin
d_out1 = ( A ^ B);
end
else
begin
d_out1 = ( A ^~ B);
end
end
 else
begin
d_out1 = 4'b0000;
end
end
endmodule
`timescale 1ns / 1ps

module arithmetic(d_out,A,B,cout,arithmetic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;
input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;
wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;
wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always @(s0,s1,c0,arithmetic_unit)
begin
if(arithmetic_unit)
begin
if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin
d_out2 = A;
end
else if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b1)
begin
d_out2 = A + 1'b1;
end
else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b0)
begin
d_out2 = D1;
cout = D0;
end
else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b1)
begin
d_out2 = D1 + 1'b1;
cout = D0;
end
else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b0)
begin
d_out2 = L1;
cout = L0;
end
else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b1)
 begin
d_out2 = L1 + 1'b1;
cout = L0;
end
else if(s1 == 1'b1 & s0 == 1'b1 & c0 == 1'b0)
begin
d_out2 = K1;
cout = K0;
end
else
begin
d_out2 = K1 + 1'b1;
cout = K0;
end
end
else
begin
d_out2 = 4'b0000;
end
end
endmodule

`timescale 1ns / 1ps

module
alu(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,SEL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;
reg arithmetic_unit;
wire [3:0] DATA_OUT1;
wire [3:0] DATA_OUT2;
assign DATA_OUT = (MODE ? DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(DATA_OUT2),
.s0(SEL1),
.s1(SEL2),
.c0(CRY_IN),
.A(DATA_IN1),
.B(DATA_IN2),
.logic_unit(logic_unit)
);
arithmetic arithmetic_ins(.d_out(DATA_OUT1),
.cout(CRY_OUT),
.s0(SEL1),
.s1(SEL2),
.A(DATA_IN1),
.B(DATA_IN2),
.c0(CRY_IN),
.M(MODE),
.arithmetic_unit(arithmetic_unit)
);
always @(SEL1,SEL2,MODE)
begin
if(MODE == 1'b0)
begin
logic_unit = 1'b1;
arithmetic_unit = 1'b0;
 end
else
begin
logic_unit = 1'b0;
arithmetic_unit = 1'b1;
end
end
endmodule

TEST BENCH FOR ALU:

`timescale 1ns / 1ps
module t_alu;
wire CRY_OUT;
wire [3:0] DATA_OUT;
reg CRY_IN;
reg [3:0] DATA_IN1,DATA_IN2;
reg SEL1,SEL2,MODE;
alu
alu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,SEL2,MODE);
initial
begin
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b0;
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
#500 MODE = 1'b0;
 #500 SEL1 = 1'b0; SEL2 = 1'b1;
#500 SEL1 = 1'b1; SEL2 = 1'b1;
#500 SEL1 = 1'b1; SEL2 = 1'b0;
#500 SEL1 = 1'b0; SEL2 = 1'b0;
end
endmodule