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Year/Branch: II-ME-VLSI Design

Course Title & Code: VL9201 Testing of VLSI Circuits


UNIT-1
BASICS OF TESTING AND FAULT MODELLING
PART-A
1. What are the types of fault models?
Stuck-at fault
Bridging fault
Stuck-open fault
2. Define stuck-at fault?
It is a faults in logic gates results in one of its inputs or output being fixed either a logic 0 (stuckat-0) or a
logic 1 (stuck-at-1).
3. Define fault equivalence
Two faults f and g are said to be functionally equivalent, iff Z
f
(x) = Z
g
(x).
4. Define sensitized path?
A path composed of sensitized lines is called a sensitized path.
5. State the lemma rule.
Let G be the gate with inversion i and controlling value c, whose output is sensitized to a fault f(by a test t).
1. All inputs of G sensitized to f have the same value (say a).
2. All inputs of G not sensitized to f (if any have value c).
3. The output of G has value a.
6. What is redundancy?
A combinational circuit that contains an undetectable struck fault is said to be redundant.
7. Define fault dominance.
Let Tg be the set of all tests that detect a fault g. we say that a fault f dominates the fault g iff f and g are
functionally equivalent under To.
8. Give the algorithm for one pass strategy.
for every event (i,v,')pending at the current time t
begin
v(i) = Vi'
for every j on the fanout list of i
begin
update input values of j
Vi'=evaluate (j) if vi *Isvo then begin
schedule (j, vo) for time t+d(j)
lsv(j vo)
end
end
9. What are the proper lies of Single (Rote) stuck-at Bob?
Only one line is faulty
The faulty line is permanently set to 0 or 1.The fault can be at an input or output of a gate
Simple logical model is independent of technology details
It reduces the complexity of fault description Algorithms.
10. Define bridging faults and mention its types?
shorts between two or more signal lines are called as bridging faults. It can be classified into three types.
Input bridging faults
Feedback bridging faults
Not Feedback bridging faults
II. What is the difference between transient and inrynnittent faults?
Trans Wry fault -recurring faults and it is caused by power supply fluctuation. An intermittent Fault is a
recurring (reappear on a regular basis) and it is caused by loose connection, poor design and some environmental
conditions.
PART-B
I. Disciss the types of fault models used in digital circuits at different levels of design.
2. a. Explain how gate level event driven simulation is caned out. (10) b. Explain about die delay modeis.(6)
3. Discuss on the various types of fault simulation techniques used in digital circuits.
4. Discuss on the faults in digital circuit and its modeling at various levels of IC diagram.
5. Explain about Bridging faults, Delay faults and temporary faults.








UNIT-2
TEST GENERATION
PART-A
1. Mention any four methods used in test generation for combinational circuits?
One-Dimensional path sensitization
Boolean Difference
D-Algorithm
PODEM AlgoOthm
2. What is controllability and observability?
Controllability is an ability to apply test patterns to the inputs of a sub circuit via primary of the circuit.
Observability is an ability to observe Me response of a sub circuit via the primary output of the circuit.
3. Define Backtrace
The procedure for obtaining a primary input assignment given an initial objective. It is known as Backtrace.
4. Mention any two methods used M test generation for sequential circuits
State table verification
Testing of sequential circuits as iterative combinational circuits
5. Draw the hardware model for delay fault testing?

6. What Is mean by homing sequence?
To design checking experiment it is necessary to blow the initial state of the network, which is determined by
distinguish or homing sequence.
7. List out the three phases of checking experiment?
1. Initialization phase
2. State identification phase
3. Transition verification phase
8. List out the advantages of LSSD techniques,
The correct operation of the logic network is independent of nc characteristics such as clock edge rise tine and
fall time. News is combinational in name as far as test generation and testing is concerned.
The elimination of all hazards and races greatly simplifies both test generation and fault

PART-B
I. Explain 17-algoritInn and using that algorithm fuld a tem vector for the given BIM in die circuit shown in Fig. I.

2. Explain how test sequence is generated in sequential circuits using checking experiments with example.
3. Explain PODEM algorithm and using PODEM find a test vector for the fault 'X S/O' in the circuit shown in Figure

4. Explain how sequential circuits are tested using time frame expansion method.
5. Problems in Boolean differences (8 Marks) and Properties of Boolean differences (8marks)
6. Explain the following i) Ad-hoc design rules for improving testability and ii) LSSD Design rules.









UNIT-3
DESIGN FOR TESTABILITY
PART-A
1. What are the advantages of using DFT approach for testing?
2. Define Predictability?
It is an ability to obtain known output values in response to given input stimuli.
3. List out the characteristics that influences various cost associative with testing?
Status of a device to be determined and the isolation of faults within the device to be performed quickly to
reduce both test time and cost. The cost effective development of the tests to be determine this status.
4. What are the classifications of test points?
Test points are classified into two types
Control points (CP) - CPs are primary inputs to enhance controllability.
Observation points (OP) - Ops are primary outputs to enhance observability.
5. Define Initialization?
It is a process of bringing a sequential circuit into a known state at some known time, such as when it is
powered on or after an initialization sequence is applied.
6. List out the types of generic scan based design?
Full serial integrated scan
Isolated serial scan
Non serial scan
7. State the LSSD design rules?
All internal storage elements must consist of polarity hold latches. Latches can be controlled by two or more
non overlapping clocks. Clock primary inputs cannot feed the data inputs to latches, either directly or through
combinational logic. They may only feed clock inputs ti latches or primary outputs.
8. List out the uses of scan design?
Flipflops and latches are more complex. Hence scan designs are expensive in terms of board or silicon area.
Some designs are not easily realizable as scan designs. Test generation costs can be significantly reduced. This can
also lead to higher fault coverage.
PART-B
1. Discuss briefly about generic scan based design techniques?
2. How Ad-hoc designs are used to improve testability digital circuits? Explain with examples.
3. Discuss on system level DFT techniques?
4. Explain any four ad-hoc design methods used for improving the testability of digital circuits.
5. Discuss on system level DFT techniques.
6. Explain about the following i) Classical scan based design and ii) LSSD design rules.


























UNIT-4
SELF TEST AND TEST ALGORITHMS
2. List out the categories of test pattern generation approaches for BIST?
Exhaustive/Pseudo exhaustive testing
Pseudo random testing
Deterministic testing
3. Draw the BIST structure

4. What are the methods to derive n input and m output combinational circuit?
Syndrome driver counter
Constant weight counter
Linear feedback shift register/ shift register(LFSR/SR)
Linear feedback shift register/ EX-OR gates(LFSR/EX-OR)
5. List out the BIST architectures?
BILBO
STUMPS
LOCST
6. Mention the test algorithms for RAMs?
GALPAT
WALKING 0s AND 1s
March Test
Checkboard test
7. List the types of coupling faults exist in memories?
Inversion coupling fault
Idem-potent fault OR State coupling fault
8. Mention the advantages of transition counting?
It is not necessary to store either the correct response sequence or the actualresponse sequence at any test
point; only the transition counts are needed.
9. What are the advantages of circular BIST?
It provides high fault coverage.
Low hardware overhead.
10. List out the methods of pseudo exhaustive pattern generation?
Syndrome driver counter
Constant weight counter
LFSR/SR
PART-B
1. Discuss the test pattern generators used in BIST.
2. Discuss the fault models used in memories and explain how test generation is done for embedded RAM
3. Draw the circular BIST architecture and explain how testing is done using this architecture.
4. Explain any two test algorithms used for testing memories.
5. Explain about test generation and Built in self-test for embedded RAM.

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