FPGA IMPLEMENTATION OF DSP

ALGORITHMS

By: NITIN SINGH,

M.S (By Research),
The LNMIIT, Jaipur.

SYSTEM LEVEL IMPLEMENTATION

APPROACH

RF
RECEIVER

ADC

FPGA

DAC

LAPTOP

HARDWARE-IN-LOOP APPROACH

LAPTOP
(SIMULINK)

FPGA
BOARD

BRIEF DESCRIPTION OF WORKFLOW

IMPLEMENTATION
ON FPGA

HDL
CONVERSION
SIMULINK
MODEL

CONSTRAINT
FILE
GENERATION

BRIEF DESCRIPTION OF WORKFLOW

IMPLEMENTATION
ON FPGA
1. SYSTEM GENERATOR
(BY XILINX)
NETLIST
HDL
CONVERSION
SIMULINK
MODEL

FILE
GENERATION

2. HDL CODER
(BY MATHWORKS)

SYSTEM GENERATOR
Adds a separate Xilinx Blockset to Simulink library.
Facilitates Direct comparison of Simulink block
output and Xilinx block output.
Can generate HDL netlist, IP Cores and HDL code.

Supports Hardware-in-loop verification.

Option of adding custom boards is not available in
student version.

SYSTEM GENERATOR

HDL CODER
Can be used with Matlab code, Simulink model and
Flow chart.
Can generate HDL code, Test Bench and supports
co-simulation and Hardware-in-loop verification.
Simulink library blocks can be used for designing.

HDL CODER

HDL CODER

THANK YOU