module SeqDetect(

input b,
input clk,
input reset,
output reg x
);
parameter S0=0, S1=1, S2=2, S3=3, S4=4;
reg [2:0] State, StateNext;
//Comb Block
always @(State, b) begin
case(State)
S0: begin
x<=0;
if(b==0)
StateNext <= S1;
else
StateNext <= S0;
end
S1: begin
x<=0;
if(b==0)
StateNext <= S1;
else
StateNext <= S2;
end
S2: begin
x<=0;
if(b==0)
StateNext <= S1;
else
StateNext <= S3;
end
S3: begin
x<=0;
if(b==0)
StateNext <= S4;
else
StateNext <= S0;
end
S4: begin
x<=1;
if(b==0)
StateNext <= S1;
else
StateNext <= S0;
end
endcase
end
always @(posedge clk)begin
if(reset ==1)
State <= S0;
else
State <= StateNext;
end
endmodule