Documente Academic
Documente Profesional
Documente Cultură
74 / A, Dhanpaleshwar Society,
Near Vinzol Railway Colony,
S. L. M Road, Vatva, Ahmedabad-382445
Contact: +91 9429322575
Email: kashyap.rahul260@gmail.com
CAREER OBJECTIVE
Seeking a challenging and rewarding opportunity with an organization of repute which recognizes and
utilizes my true potential while nurturing my analytical and technical skills
PROFILE
Industrial Automation Engineer: Skills include PLC (AB, Siemens, Mitsubishi and GE Fanuc), SCADA
Systems and Interfaces, HMI, DCS Systems (ABB) and GSM based control.
Accented with the latest trends and techniques of the field; Pursued M.E in VLSI and Embedded
System Design from Gujarat Technological University, Ahmedabad, Gujarat.
Pursued B.Tech in Electronics and Communication Engineering from Rajasthan Technical University
KOTA, Rajasthan.
Interest in Automation based Systems, DCS, Basic Electronics, VLSI and Embedded System,
Communication Systems and Computer Networks.
Conceptually strong with an innovative and analytical approach to the work with an eye for detail.
Enriched with the ability to learn new concepts & technology within a short span of time.
Self motivated, hard working and goal-oriented with a high degree of flexibility, creativity,
resourcefulness, commitment and optimism.
EDUCATIONAL CREDENTIALS
Qualification
Specialization
Institute/University
Year of Passing
%/CPI
M.E
Gujarat Technological
University PG School
2014
8.79 CPI
B.Tech
Rajasthan Technical
University, KOTA
2012
71.21%
XII
Science
2007
83.6%
Science
2005
75.83%
Projects Undertaken
1. M.E. Dissertation
Title: Implementation of Ternary Sequential Elements using CNTFET.
Platform: VLSI with Analog and Mixed Signal Design
Organization: CDAC, PUNE
Duration: 10-12 Months
Abstract: The Aim of this work is to present the Advantages of Ternary Logic over Binary Logic in
terms of Computations and Circuit Designs based on CNTFET, replacing MOSFET reduces the total
power consumption and occupies less area on VLSI Chips.
Other M.E Projects
CAN (Controller Area Network) Protocol Controller Design using Verilog.
ALU (Arithmetic and logical Unit) Physical Design (Frontend and Backend).
Minor Projects on ARM7 Microcontroller.
Papers Published
(1)
(2)
Rahul Kashyap, Implementation of Ternary Logic Gates using CNTFET in International Journal
for Scientific Research and Development (IJSRD), Vol. 2 Issue 3, 2014, ISSN: 2321-0613, Page 352355.
Rahul Kashyap, Radha Tapiawala, Design of Universal Logic Gates based on CNTFET for Binary
and Ternary Logic in IJERT, Vol. 3 Issue 6, June 2014, ISSN: 2278-0181, Page 604-609.
Areas of Interest
AUTOMATION (PLC, SCADA, DCS Systems), Low Power VLSI Design, Digital Electronics, Control
Systems, Physical Electronics and Embedded System Design (Software)
Technical Skills
Achievements
Ethical Hacking Expert from Tech Defense Private Limited, Techfest IIT Bombay.
Served as an Event Manager of National Techfest SAKSHAMA NEW 10 and LAN Gaming.
Participated in Cultural & Technical events, involved as a team member of Colleges Annual Sports.
Seeked workshops on WEB DESIGNING, Communication Skills and Ethical Hacking.
Seminars Delivered
Hobbies
PC Games, Reading, Photography, Computer Learning, Riding Bikes, Outing.
Personal Details
Date of Birth
Gender
Nationality
Marital Status
Languages Known
Declaration:
I hereby declare that the above mentioned Information is Correct and I Bear the Responsibility for the
Correctness of the above mentioned Particulars.
Date:
Place: