Lab 09 : Single Cycle Processor and Control Unit

Name:
Kevin Bradshaw

Sign the following statement:

On my honor, as an Aggie, I have neither given nor received unauthorized
aid on this academic work
Kevin Bradshaw

Objective

The objective of this lab is to implement the main control unit and integrate it with the
data path, to build a complete, single-cycle processor microarchitecture.

Pre-requisite

For this lab you are expected to be familiar with the MIPS single-cycle processor from the
textbook microarchitecture.

Introduction

In this lab, you will complete the control unit for the single-cycle MIPS processor and
assemble all of the datapath components constructed in previous labs using Verilog. You
will also execute some test programs on your single-cycle processor. By the end of this
lab, you should thoroughly understand the internal operation of the MIPS single-cycle
processor.

Computer Architecture and Design, Lab 09

Processor

This version of MIPS implements the single-cycle processor given in Figure 1 and supports
the following instructions: add, sub, and, or, slt, lw, sw, beq, and j as well as many
of their immediate equivalents. The instruction formats are the same as the real MIPS
instruction set.
Our model of the single-cycle MIPS processor divides the machine into two major units:
the control and the data path. You have already built many of the datapath components
such as the ALU, the data memory, the sign extender, etc.
Instruction [250]
26

Jump address [310]

Shift
left 2

28

PC + 4 [3128]

Add
Add

Instruction [3126]

PC

Instruction [2521]

Read
register 1

Instruction [2016]

Read
register 2

Read
address
Instruction
[310]
Instruction
memory

0
M
u
Instruction [1511] x
1

Write
register
Write
data

Instruction [150]

16

M
u
x

M
u
x

Shift
left 2

RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite

Control

ALU
result

Read
data 1
Zero
Read
data 2

Registers

Sign
extend

ALU ALU
result

0
M
u
x
1

Address

Read
data

1
M
u
x
0

Data
Write memory
data

32
ALU
control

Instruction [50]

Fig. 1: MIPS schematic

You have also built the ALU control module that is needed for this version of the
MIPS processor. You are provided with the instruction memory (read only), which is preinitialized with test programs. Your task is to complete the Main Control unit, connect all

Computer Architecture and Design, Lab 09

modules together, and simulate the code.

Control Unit

Complete the control unit Verilog code found in SingleCycleControl.v for the data path
shown in Figure 1 that supports R-type, load/store word, immediate, branch and jump
instructions. All opcodes that you must implement are defined above the module definition.
Your control unit should be implemented based on the truth table that you filled during
the prelab.
RegDst
ALUSrc
MemToReg
RegWrite
OPCODE[5:0]

MemRead
MemWrite
Branch
Jump
ALUOp[3:0]

Fig. 2: Main Control Unit

The Datapath

The provided SingleCycleProc.v module partially implements the single cycle processor.
You will need complete this code and ensure that all connections are properly made. The
comments in the code will provide hints as to what is missing.

Computer Architecture and Design, Lab 09

Diagnostic and Testing

Your code should simulate properly with the test programs provided. Each program tests
different parts of your processor. Ensure proper operation of each test and make any
necessary corrections to your code. Once all tests have successfully completed, demo your
progress to the TA.

Questions
1. In SingleCycleProcTest.v , the clock Period is defined by the macro HalfClockPeriod.
Try changing this value. What is the smallest value for which the processor does not
fail tests?
About 2.01535

2. Considering the delays in your datapath and control unit, what is the maximum clock
speed for your design? List the components which are part of the critical path and
which instructions utilize the critical path.
The lw instruction uses the most hardware, hence creating the critical path through:
ALUSrc, MemReg, RegWr, MemRd, ALUop, and the smaller hardware pieces that accompany
these stages.
Total delays through each verilog file in use:
ALU: 20 ns
ALUControl: 2 ns
DataMemory: 20 ns
NextPClogic: 1 ns
SingleCycleControl: 2 ns
SincleCycleProc: 4 ns
Total delay of 49 ns, which is 20.4 GHz.(1/49 ns).

3. In what ways is this design inefficient? How would you improve it?
Since this is a single cycle processor, in reality it's slow and doesn't have much computing power.
It could be improved tremendously by pipelining. Instead of just sending one instruction at a time
through the processor, pipelining allows multiple instructions through. A basic MIPS processor can
be improved by having a 5 stage pipeline:
1. Instruction Fetch
2. Instruction Decode
3. Execution
4. Memory
5. Write Back

Computer Architecture and Design, Lab 09

4. Briefly describe what each of the test programs do and what instructions they might
be testing.
Test Program 1:
Sums the words in $a0 and stores it at the endo of the array.
Instructions tested: add, addi, lw, sw, and beq.
Test Program 2:
Does arithmetic computations and stores results in memory.
Instructions tested: All arithmetic operations, lw, and sw.
Test Program 3:
Tests Immediate Function
Instructions tested: All I-type instructions including addi, andi, sll, srl, sra, slti, and sltiu.
Test Program 4:
Tests jump and link and jump return
Instructions tested: jr and jal

Deliverables

Test Program 5:
Tests mula using wavelet transform
PleaseInstructions
turn-in the
following:
tested: li, sw, and lw

All
your verilog
modules.
Testof
Program
6:
Tests Overflow Exceptions

Results
of tested:
the testbench.
Instructions
li, add, lw, and mula
Filled out PDF form.