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A B C D E BATTERY CHARGER Hawke Intel Discrete Block Diagram MAX8731A 38 INPUTS
A
B
C
D
E
BATTERY CHARGER
Hawke Intel Discrete Block Diagram
MAX8731A
38
INPUTS
OUTPUTS
AD+
DCBATOUT
BAT+
Project code : 91.4W101.001
SYSTEM DC/DC
TPS51120
39
CLK GEN
Intel Mobile CPU
PCB P/N
1
ICS9LPRS365
4
PCB No.
Merom 4M
FSB:667 or 800 MHz
Revision
: 48.4W101.011
: 07212
: -1
INPUTS
OUTPUTS
1
5V_AUX_S5
DCBATOUT
3D3V_AUX_S5
5V_S5
3D3V_S5
5, 6, 7
SYSTEM DC/DC
VRAM
VRAM
TPS5117
16Mbx32x2
16Mbx32x2
51
52
42, 43
INPUTS
OUTPUTS
Host BUS
RGB CRT
DCBATOUT
1D05V_S0
CRT
17
GDDRIII
GDDRIII
667/800MHz
1D8V_S3
700MHz
700MHz
SYSTEM DC/DC
44
LCD
LVDS
18
nVidia NB8P
DDRII 667 Channel A
DDRII
533/667 Slot 1
TPS51100
Crestline-PM
INPUTS
OUTPUTS
14
(256MB)
AGTL+ CPU I/F
Power SW
1D8V_S3
0D9V_S3
PCIe x 16
27
OR
DDR Memory I/F
DDRII
TI TPS2231
SYSTEM DC/DC
HDMI
HDMI
Slot 2
16
nVidia NB8M
EXTERNAL GRAHPICS
DDR II 667 Channel B
533/667
RT9018
8, 9, 10, 11, 12, 13
15
44
(128MB)
INPUTS
OUTPUTS
2
2
47, 48, 49, 50
1D8V_S3
1D5V_S0
S-Video
SVIDEO
PCIE x 1 & USB 2.0 x 1
1D8V_S3
1D25V_S0
New Card
27
DMI I/F
100MHz
VGA DC/DC
10/100 NIC
PCIE x 1
26
RJ45 CONN
TPS5117
27
53
Marvell 88E8040
1394
25
1394
INPUTS
OUTPUTS
INTEL
Mini-Card x 1
Ricoh
PCIE
PCIE x 1
28
PCI
DCBATOUT VCC_GFX_CORE_S0
802.11a/b/g
R5C833
SD/SDIO/MMC
ICH8-M
PCIE x 2 & USB 2.0 x 2
CardReader
Mini-Card x 2
WWAN&BT&Robson
29
MS/MS Pro/XD
CPU DC/DC
25
24, 25
ISL6262A
40
10 USB 2.0/1.1 ports
USB 2.0
USB 2.0 x 1
Camera
18
6 PCI Express ports
INPUTS
OUTPUTS
High Definition Audio
DCBATOUT
VCC_CORE
ATA 66/100
USB 2.0 x 1
HEADPHONE
Biometic reader
30
AZALIA
HP2
SATA
3
AMP
3
MAX4411
ACPI 1.1
PCB LAYER
32
USB 2.0 x 1
Bluetooth 2.1
30
LPC I/F
L1:TOP
PCI/PCI BRIDGE
LPC Bus
Lift Side: USB x 2
19, 20, 21, 22
37
L2:GND
USB 2.0 x 3
Azalia
MIC IN
Right Side:USB x 1
L3:Signal
34
CODEC
SPI
KBC
L4:Signal
Digital Mic Array
Sigmatel
Winbond WPC8763L
STAC 9228
33
L5:VCC
31
L6:Singal
HP1
L7:GND
Thermal
Capacity
Touch
Int.
S/W
Flash ROM
L8:BOT
& Fan
OP AMP
HDD
ODD
2CH
Button
Pad
KB
CIR
4
2MB
<Core Design>
<Core Design>
<Core Design>
4
23
23
30
36
36
30
35
30
G792
SPEAKER
MAX9789A
32
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
System Block Diagram
System Block Diagram
System Block Diagram
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
1
1
1
of
of
of
57
57
57
A
B
C
D
E
SATA
PATA
A B C D E Adapter TPS51117 1D8V TPS51117 1D05V Input Signal Output Signal Input
A
B
C
D
E
Adapter
TPS51117 1D8V
TPS51117 1D05V
Input Signal
Output Signal
Input Signal
Output Signal
Input Signal
Output Signal
AD_IN#
PM_SLP_S4#
CPUCORE_ON
PM_SLP_S3#
CPUCORE_ON
AD_OFF
(I)
(O)
EN_PSV(I / 5V)
(O)
EN_PSV(I / 5V)
(O)
5V_S5
Input Power
Output Power
5V_S5
Input Power
Output Power
Input Power
Output Power
VCC
VCC
1D8V_S3(19A)
1D05V_S0(5A)
1
1
AD_JK
AD+
DCBATOUT
(O)
DCBATOUT
(O)
VCC(I)
VCC(O)
VIN
VIN
5V_AUX_S5
VCC(I)
TI TPS51100 0.9V/DDR_VREF_S3
Charger MAX8731A
Input Signal
PM_SLP_S4#
Input Signal
Output Signal
S5
CHARGE_OFF
MAX8731_LDO
CLS (I / 3.3V)
LDO (O / 5.4V)
PM_SLP_S4#
S3
ACAV_IN
(O)
BAT+SENSE
AD_IA
Input Power
Output Power
FBSA/B (I/3.3V)
(O)
5V_S5
DDR_VREF_S3
VCC(I)
VCC(O)
BAT_SCL
SCL (IO / 3.3V)
1D8V_S3
DDR_VERF_S0
VIN(I)
VCC(O)
BAT_SDA
ISL6262A
SDA (IO / 3.3V)
2
Output Power
2
CPU_CORE
DCBATOUT
VCC (O)
RT9018A 1D5V
VID Setting
Output Signal
BT+
CPU_VID0
VCC (O)
VID0(I / 3.3V)
VGATE_PWRGD
MAX8731_ACIN
VROK(O)
ACIN
Input Signal
Output Signal
CPU_VID1
PM_SLP_S3#
CPUCORE_ON
VID1(I / 3.3V)
EN(I / 5V)
(O)
CPU_VID2
Input Power
VID2(I / 3.3V)
AD+
DCIN (I)
5V_S5
Input Power
Output Power
CPU_VID3
VCC
VID3(I / 3.3V)
1D5V_S0(2.2A)
Output Power
1D8V_S3
(O)
CPU_VID4
VIN
VID4(I / 3.3V)
CPU_VID5
VID5(I / 3.3V)
VCC_CORE_S0
TI TPS51120 3D3V/5V
CPU_VID6
(Imax=47A)
RT9018A 1D25V
VID6(I / 3.3V)
VCC_CORE_PWR(O)
Input Signal
Output Signal
Input Signal
CPUCORE_ON
3V/5V_EN
FOR
Input Signal
Output Signal
EN (I / 3.3V)
3
3
51120_EN2
CPUCORE_ON
PM_SLP_S3#
CPUCORE_ON
3.3V
PGOUT(OD / 5V)
EN(I / 5V)
(O)
3V/5V_EN
51120_EN1
FOR
Voltage Sense
5.0V
5V_S5
Input Power
Output Power
VCC_SENSE
VCC
VSEN(I / Vcore)
1D25V_S0(2.7A)
Input Power
Output Power
1D8V_S3
(O)
VSS_SENSE
5V_AUX_S5
VIN
RGND(I / Vcore)
DCBATOUT
(O)
VIN
3D3V_AUX_S5
5V_AUX_S5
(O)
Input Power
REG5V_IN(I / 5V)
5V_S5 (6A)
DCBATOUT
5V (O)
TPS51117 VGA_CORE
VIN(I)
3.3V (O)
3D3V_S5 (5A)
5V_S0
Input Signal
Output Signal
VCC(I)
PM_SLP_S3#
CPUCORE_ON
EN_PSV(I / 5V)
(O)
3D3V_S0
VCC(I)
5V_S5
Input Power
Output Power
VCC_GFX_CORE_S0
VCC
(18.4A)
4
<Core Design>
<Core Design>
<Core Design>
4
DCBATOUT
(O)
VIN
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Power Block Diagram
Power Block Diagram
Power Block Diagram
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
2
2
2
of
of
of
57
57
57
A
B
C
D
E
A B C D E 20,22 +RTCVCC +RTCVCC 5,6,7,8,10,11,12,20,22,33,42,46 1D05V_S0 1D05V_S0 INTEL ICH8-M STRAP PIN
A
B
C
D
E
20,22
+RTCVCC
+RTCVCC
5,6,7,8,10,11,12,20,22,33,42,46
1D05V_S0
1D05V_S0
INTEL ICH8-M STRAP PIN
8,11,22,44,47,48,49
1D25V_S0
1D25V_S0
26 1D2V_LAN_S5
1D2V_LAN_S5
27 1D5V_NEW_S0
1D5V_NEW_S0
Signal
Usage/When Sampled
Comment
XOR Chain Entrance Strap
6,11,20,21,22,27,28,29,44
1D5V_S0
1D5V_S0
HDA_SDOUT
XOR Chain Entrance/
Allows entrance to XOR Chain testing when TP3
ICH_RSVD
tp3
AZ_DOUT_ICH
Description
8,11,12,14,15,43,44,45,46
1D8V_S3
1D8V_S3
1
PCIE Port Config 1 bit1,
Rising Edge of PWROK
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
0
0
RSVD
1
0
1
Enter XOR Chain
26,27
2D5V_LAN_S5
2D5V_LAN_S5
1
0
Normal Operation(default)
1
1
Set PCIE port cofig bit1
20,30,33,35,38,39,46
3D3V_AUX_S5
3D3V_AUX_S5
HDA_SYNC
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
26,27
3D3V_LAN_S5
3D3V_LAN_S5
GNT2#
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
4,8,11,14,15,16,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,40,42,45,46,47,49,50,53
3D3V_S0
3D3V_S0
19,21,22,26,27,30,37,39,45,46
3D3V_S5
3D3V_S5
GPIO20
Reserved
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
18,38,39,46
5V_AUX_S5
5V_AUX_S5
16,17,18,22,23,30,32,34,35,36,40,44,45,46
5V_S0
5V_S0
GNT3#
Top-Block Swap Override.
Rising Edge of PWROK.
Sampled low:Top-Block Swap mode(inverts A16 for all
cycles targeting FWH BIOS space).
A16 swap override strap
22,23,29,30,34,36,37,39,42,43,44,45,53
5V_S5
5V_S5
PCI_GNT#3
low = A16 swap override enable
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
high = default
37,38,46
AD+
AD+
BOOT BIOS Strap
18,38,39,40,41,42,43,45,46,53
DCBATOUT
DCBATOUT
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
GNT0#
Boot BIOS Destination
14,15,44,46
DDR_VREF_S0
DDR_VREF_S0
SPI_CS1#
Selection.
Rising Edge of PWROK.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
0 SPI
1
1 PCI
0
8,14,15,44
DDR_VREF_S3
DDR_VREF_S3
1 LPC(Default)
1
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
18 +LCDVDD
+LCDVDD
INTVRMEN
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
integrated VccSus1_05,VccSus1_5,VccCL1_5
6,7,41
VCC_CORE_S0
VCC_CORE_S0
SM_INTVRMEN
High=Enable
Low=Disable
sampled.
2
2
integrated VccLan1_05VccCL1_05
Integrated VccLAN1_05
Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high
PCI ROUTING
LAN100_SLP
LAN100_SLP
VccCL1_05 VRM enable
/Disable. Always sampled.
High=Enable
Low=Disable
IDSEL
INT
REQ
GNT
SATALED#
PCIE LAN REVERSAL.Rising
Edge of PWROK.
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
DEFAULE HIGH
1394/
A
AD25
0
0
No Reboot Strap
MediaCard
D
SPKR
No Reboot.
Rising Edge of PWROK.
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
SPKR
LOW = Defaule
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
USB TABLE
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
USB0
Ext Lift Side (Bottom)
GPIO33/
Flash Descriptor Security
USB1
Ext Lift Side (Top)
HDA_DOCK_EN#
Override Strap
Rising Edge of PWROK.
Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
This should only be used in manufacturing
environments
INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS
8.2K PULL HIGH
USB2
Ext Right Side
SIGNAL
Resistor Type/Value
USB3
N/A
HDA_BIT_CLK
PULL-DOWN 20K
USB4
WWAN
HDA_RST#
NONE
USB5
Bluetooth
3
3
HDA_SDIN[3:0]
PULL-DOWN 20K
USB6
Camera
HDA_SDOUT
PULL-DOWN 20K
USB7
Biometric
HDA_SYNC
PULL-DOWN 20K
USB8
Express Card
GNT[3:0]
PULL-UP 20K
INTEL CRESTLINE STRAP PIN
USB9
3rd mini card
GPIO[20]
PULL-DOWN 20K
CFG Strap
LOW 0
HIGH 1
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
CFG 5
LAN_RXD[2:0]
PULL-UP 20K
PCIE Routing
DMI X 2
DMI X 4
CFG 8
LDRQ[0]
PULL-UP 20K
Low Power PCI Express
Normal
Low Power mode
LANE1
10/100M Bit LOM
CFG 9
LDRQ[1]/GPIO23
PULL-UP 20K
PCI Express Graphics
Lane Reversal
Lane Reversal
Normal Mode(Lanes
number in order)
LANE2
MiniCard WLAN
PME#
PULL-UP 20K
CFG 16
LANE3
MiniCard WWAN
FSB Dynamic ODT
Disabled
Enabled
PWRBTN#
PULL-UP 20K
CFG 19
LANE4
BT/UWB/Robson
DMI Lane Reserved
Normal Operation
Reserved Lane
SATALED#
PULL-UP 20K
CFG 20
Only PCIE or SDVO
PCIE and SDVO are
LANE5
Express Card
Concurrent SDVO/PCIE
is operation
operation simultaneous
SPI_CS1#
PULL-UP 20K
LANE6
N/A
SDVO_CTRL_DATA
NO SDVO Card
SDVO Card Present
SPI_CLK
PULL-UP 20K
Present
SDVO Present
SPI_MOSI
PULL-UP 20K
4
<Core Design>
<Core Design>
<Core Design>
4
CFG 12
XOR/ALL-Z
SPI_MISO
PULL-UP 20K
CFG 13
Wistron Corporation
Wistron Corporation
Wistron Corporation
LL(00)
Reserved
TACH_[3:0]
PULL-UP 20K
LH(01)
XOR Mode Enabled
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HL(10)
All Z Mode Enabled
SPKR
PULL-DOWN 20K
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
HH(11)
Normal Operation
TP[3]
PULL-UP 20K
Title
Title
Title
Table of Content
Table of Content
Table of Content
USB[9:0][P,N]
PULL-DOWN 15K
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
CL_RST#
TBD
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
3
3
3
of
of
of
57
57
57
A
B
C
D
E
A B C D E 3D3V_S0_CK505 3D3V_S0_CK505_IO 3D3V_S0 3D3V_S0_CK505 X4 CL=10pF±0.2pF Freq. Tolerance:±30ppm L15
A
B
C
D
E
3D3V_S0_CK505
3D3V_S0_CK505_IO
3D3V_S0
3D3V_S0_CK505
X4 CL=10pF±0.2pF
Freq. Tolerance:±30ppm
L15
L15
1
2
0R0603-PAD
0R0603-PAD
C439
C439
C436
C436
C824
C824
C429
C429
C437
C437
C383
C383
C396
C396
X4
X4
CLK_XTAL_IN
CLK_XTAL_OUT
1
2
X-14D31818M-37GP
X-14D31818M-37GP
C399
C399
C392
C392
SC12P50V2JN-3GP
SC12P50V2JN-3GP
SC12P50V2JN-3GP
SC12P50V2JN-3GP
1
1
U22
U22
SB
CLK_CPU_BCLK1
RN25
RN25
61
1
4
CLK_CPU_BCLK
5
CPUT0
CLK_CPU_BCLK1#
SRN0J-6-GP
SRN0J-6-GP
60
2
3
CLK_CPU_BCLK#
5
CPUC0
CLK_XTAL_IN
CLK_MCH_BCLK1
RN26
RN26
3
58
1
4
CLK_MCH_BCLK
8
X1
CPUT1_F
3D3V_S0
C837C837
SC4D7P50V2CN-1GPSC4D7P50V2CN-1GP
CLK_XTAL_OUT
CLK_MCH_BCLK1#
SRN0J-6-GP
SRN0J-6-GP
2
57
2
3
CLK_MCH_BCLK#
8
X2
CPUC1_F
3D3V_S0_CK505_IO
CLK_PCIE_MINI3_1
RN27
RN27
1
2
54
1
4
CLK_PCIE_MINI3
29
CPUT2_ITP/SRCT8
L16
L16
R448
R448
CLK_PCIE_MINI3_1#
SRN22-3-GP
SRN22-3-GP
53
2
3
CLK_PCIE_MINI3#
29
CPUC2_ITP/SRCC8
FSA
1
2
1
2
17
21 CLK_48M_ICH
USB_48MHZ/FSLA
0R0603-PAD
0R0603-PAD
SB
33R2J-2-GP
33R2J-2-GP
CLK_PCIE_LAN1
RN28
RN28
51
1
4
CLK_PCIE_LAN
26
SRCT7/CR#_F
C445
C445
C435
C435
C426
C426
C811
C811
C821
C821
C384
C384
C438
C438
CLK_PCIE_LAN1#
SRN22-3-GP
SRN22-3-GP
50
2
3
CLK_PCIE_LAN#
26
SRCC7/CR#_E
DY
DY
45
21
H_STP_PCI#
PCI_STOP#
CLK_PCIE_MINI1_1
RN29
RN29
44
48
1
4
CLK_PCIE_MINI1
28
21
H_STP_CPU#
CPU_STOP#
SRCT6
CLK_PCIE_MINI1_1#
SRN22-3-GP
SRN22-3-GP
47
2
3
CLK_PCIE_MINI1#
28
SRCC6
CLK_PCIE_NEW1
RN30
RN30
41
2
3
CLK_PCIE_NEW
27
SRCT10
CLK_PCIE_NEW1#
SRN0J-6-GP
SRN0J-6-GP
7
42
1
4
CLK_PCIE_NEW#
27
14,15,21,28,29
ICH_SMBCLK
SCLK
SRCC10
6
1
2
14,15,21,28,29
ICH_SMBDATA
3D3V_S0
SDATA
R434R434
10KR2J-3-GP10KR2J-3-GP NEWCARD_CLKREQ#
40
SRCT11/CR#_H
27
R183
R183
63
39
1
2
21
CK_PWRGD
CK_PWRGD/PD#
SRCC11/CR#_G
10KR2J-3-GP
10KR2J-3-GP
DY
DY
CLK_PCIE_MINI2_1
RN31
RN31
37
2
3
CLK_PCIE_MINI2
29
SRCT9
2
CLK_PCIE_MINI2_1#
SRN22-3-GP
SRN22-3-GP
2
38
1
4
CLK_PCIE_MINI2#
29
SRCC9
8
SB
21 CLKSATAREQ#
PCI0/CR#_A
CLK_MCH_3GPLL1
RN32
RN32
10
34
2
3
CLK_MCH_3GPLL
8
8 CLKREQ#_B
PCI1/CR#_B
SRCT4
PCI2_TME
CLK_MCH_3GPLL1#
SRN0J-6-GP
SRN0J-6-GP
11
35
1
4
CLK_MCH_3GPLL#
8
PCI2/TME
SRCC4
R184R184
33R2J-2-GP33R2J-2-GP
PCLK_PCM_R
1 2
12
24
PCLK_PCM
PCI3
R186R186
1 33R2J-2-GP33R2J-2-GP
27_SEL
CLK_PCIE_ICH1
RN34
RN34
31
2
3
33
PCLK_KBC
13
CLK_PCIE_ICH
21
PCI4/27_SELECT
SRCT3/CR#_C
R187R187
1 33R2J-2-GP33R2J-2-GP
ITP_EN
CLK_PCIE_ICH1#
SRN0J-6-GP
SRN0J-6-GP
14
32
1
4
19
CLK_PCI_ICH
CLK_PCIE_ICH#
21
PCI_F5/ITP_EN
SRCC3/CR#_D
CLK_PCIE_SATA1CLK_PCIE_SATA1
RN33
RN33
28
2
3
CLK_PCIE_SATA
20
SRCT2/SATAT
CLK_PCIE_SATA1#CLK_PCIE_SATA1#
SRN0J-6-GP
SRN0J-6-GP
29
1
4
CLK_PCIE_SATA#
20
SRCC2/SATAC
R432
R432
FSB
64
FSLB/TEST_MODE
1 FSC
5
21 CLK_14M_ICH
REF0/FSLC/TEST_SEL
CLK_VGA_27M_NSS1
RN35
RN35
24
2
3
CLK_VGA_27M_NSS
49
27MHZ_NONSS/SRCT1/SE1
33R2J-2-GP
33R2J-2-GP
CLK_VGA_27M_SS1
SRN0J-6-GP
SRN0J-6-GP
55
25
1
4
CLK_VGA_27M_SS
49
NC#55
27MHZ_SS/SRCC1/SE2
CLK_PCIE_VGA1
RN36
RN36
20
2
3
CLK_PCIE_VGA
47
SRCT0/DOTT_96
CLK_PCIE_VGA1#
SRN0J-6-GP
SRN0J-6-GP
21
1
4
CLK_PCIE_VGA#
47
SRCC0/DOTC_96
3D3V_S0_CK505
ICS9LPRS365BKLFT-GP
ICS9LPRS365BKLFT-GP
For Discrete:
R436
R436
Rename for GPU clock.
10KR2J-3-GP
10KR2J-3-GP
-1 SC
PCI2_TME
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0_CK505
Main source : 71.00875.A03 RTM875M-606-LF
CLK_VGA_27M_NSS
3
3
R435
R435
CLK_VGA_27M_SS
10KR2J-3-GP
10KR2J-3-GP
2nd source : 71.28541.A03 SL28541AQCT
3rd source : 71.08513.003 SLG8SP513VTR
4th source : 71.09365.A03 ICS9LPRS365BKLFT
R440
R440
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
10KR2J-3-GP
10KR2J-3-GP
FS_C
FS_B
FS_A
CPU
27_SEL
PCI2_TME
Output
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
0
1
100M
0
Overclocking of CPU and SRC allowed
0
0
1
133M
0
1
0
200M
For Discrete
0
1
1
166M
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
Overclocking of CPU and SRC not allowed
SB
ITP_EN
Output
FSC
1
2
27_SEL strap 0:For 965GM, 1:For 965PM
6,8
CPU_BSEL2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
ITP_EN
R431R431
2K2R2J-2-GP2K2R2J-2-GP
FSB
1
2
27_SEL
PIN 20
PIN 21
PIN 24
PIN 25
0
SRC8
6,8
CPU_BSEL1
R426R426
0R0402-PAD0R0402-PAD
R444
R444
1
CPU_ITP
FSA
1
2
965GM
6,8
CPU_BSEL0
0 DOT96T
DOT96C
SRCT1/LCDT_100
SRCT1/LCDT_100
10KR2J-3-GP
10KR2J-3-GP
R449R449
2K2R2J-2-GP2K2R2J-2-GP
1 SRCT0
SRCC0
27M_NSS
27M_SS
965PM
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
4
<Core Design>
<Core Design>
<Core Design>
4
Design Note:
1. All of Input pin didn't have internal pull up resistor.
Wistron Corporation
Wistron Corporation
Wistron Corporation
2. Clock Request (CR) function are enable by registers.
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3. ICS9LPRS365 integrated serial resistor of differential clock,
so put 0 ohm serial resistor in the schematic.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Clock generator ICS9LPRS365
Clock generator ICS9LPRS365
Clock generator ICS9LPRS365
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
4
4
4
of
of
of
57
57
57
A
B
C
D
E
12
12
12
12
12
12
12
12
12
12
12
12
12
12
C413SC4D7P50V2CN-1GP
C413SC4D7P50V2CN-1GP
12
12
12
C416SC4D7P50V2CN-1GP
C416SC4D7P50V2CN-1GP
12
12
12
C419SC4D7P50V2CN-1GP
C419SC4D7P50V2CN-1GP
12
C822SC4D7P50V2CN-1GP
C822SC4D7P50V2CN-1GP
12
12
18
4
GND48
VDDREF
15
16
GNDPCI
VDD48
1
9
GNDREF
VDDPCI
46
VDDSRC
62
VDDCPU
22
23
GND
VDDPLL3
30
GNDSRC
36
GNDSRC
49
GNDSRC
59
19
GNDCPU
VDD96_IO
26
27
GND
VDDPLL3_IO
43
VDDSRC_IO
52
VDDSRC_IO
33
VDDSRC_IO
65
56
GND
VDDCPU_IO
12
12
C839
C839
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
C840
C840
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
A B C D E 8 H_A#[3 35] U47A U47A 1 1 OF 4 OF
A
B
C
D
E
8 H_A#[3 35]
U47A
U47A
1
1
OF 4
OF 4
H_A#3
H_ADS#
J4
H1
A3#
ADS#
H_ADS#
8
H_A#4
H_BNR#
1
L5
E2
1
A4#
BNR#
H_BNR#
8
1D05V_S0
H_A#5
H_BPRI#
L4
G5
A5#
BPRI#
H_BPRI#
8
H_A#6
K5
A6#
H_A#7
H_DEFER#
M3
H5
A7#
DEFER#
H_DEFER#
8
H_A#8
H_DRDY#
N2
F21
A8#
DRDY#
H_DRDY#
8
H_A#9
H_DBSY#
R272
R272
J1
E1
A9#
DBSY#
H_DBSY#
8
H_A#10
56R2J-4-GP
56R2J-4-GP
N3
A10#
H_A#11
H_BR0#
P5
F1
A11#
BR0#
H_BR0#
8
H_A#12
P2
A12#
H_A#13
H_IERR#
L2
D20
A13#
IERR#
H_A#14
H_INIT#
P4
B3
A14#
INIT#
H_INIT#
20
H_A#15
P1
A15#
H_A#16
H_LOCK#
R1
H4
A16#
LOCK#
H_LOCK#
8
H_ADSTB#0
M1
8
H_ADSTB#0
ADSTB0#
H_RESET#
C1
RESET#
H_RESET#
8
H_REQ#0
H_RS#0
K3
F3
8
H_REQ#0
REQ0#
RS0#
H_RS#0
8
H_REQ#1
H_RS#1
H2
F4
8
H_REQ#1
REQ1#
RS1#
H_RS#1
8
H_REQ#2
H_RS#2
K2
G3
8
H_REQ#2
REQ2#
RS2#
H_RS#2
8
H_REQ#3
H_TRDY#
J3
G2
8
H_REQ#3
REQ3#
TRDY#
H_TRDY#
8
H_REQ#4
L1
8
H_REQ#4
REQ4#
H_HIT#
G6
HIT#
H_HIT#
8
H_A#17
H_HITM#
Y2
E4
A17#
HITM#
H_HITM#
8
H_A#18
U5
A18#
H_A#19
XDP_BPM#0
TP16TP16
R3
AD4
A19#
BPM0#
H_A#20
XDP_BPM#1
TP11TP11
W6
AD3
A20#
BPM1#
H_A#21
XDP_BPM#2
TP4TP4
U4
AD1
A21#
BPM2#
H_A#22
XDP_BPM#3
TP15TP15
Y5
AC4
A22#
BPM3#
H_A#23
XDP_BPM#4
TP9TP9
U1
AC2
A23#
PRDY#
1D05V_S0
H_A#24
XDP_BPM#5
TP1TP1
R4
AC1
A24#
PREQ#
2
H_A#25
XDP_TCK
R39R39
27D4R2F-L1-GP27D4R2F-L1-GP
2
T5
AC5
1 2
A25#
TCK
H_A#26
XDP_TDI
R36R36
150R2J-L1-GP-U150R2J-L1-GP-U
T3
AA6
1 2
A26#
TDI
H_A#27
XDP_TDO
TP13TP13
W2
AB3
A27#
TDO
H_A#28
XDP_TMS
R37R37
39D2R2F-L-GP39D2R2F-L-GP
W5
AB5
1 2
A28#
TMS
H_A#29
XDP_TRST#
R38R38
680R2J-3-GP680R2J-3-GP
Y4
AB6
1 2
A29#
TRST#
H_A#30
XDP_DBRESET#
TP19TP19
U2
C20
A30#
DBR#
H_A#31
R74
R74
V4
A31#
H_A#32
56R2J-4-GP
56R2J-4-GP
W3
A32#
H_A#33
AA4
THERMAL
THERMAL
A33#
H_A#34
AB2
A34#
H_A#35
CPU_PROCHOT
R73
R73
AA3
D21
2
DY
DY
1
A35#
PROCHOT#
CPU_PROCHOT#
40
H_ADSTB#1
H_THERMDA
0R2J-2-GP
0R2J-2-GP
V1
A24
8
H_ADSTB#1
ADSTB1#
THRMDA
H_THERMDA
35
H_THERMDC
B25
THRMDC
H_THERMDC
35
H_A20M#
A6
20
H_A20M#
A20M#
H_FERR#
H_THERMTRIP#
A5
C7
20
H_FERR#
FERR#
THERMTRIP#
H_THERMTRIP#
8,20,33,45
H_IGNNE#
C4
20
H_IGNNE#
IGNNE#
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
D5
20
H_STPCLK#
STPCLK#
HCLK
HCLK
CLK_CPU_BCLK
C6
A22
20
H_INTR
LINT0
BCLK0
CLK_CPU_BCLK
4
CLK_CPU_BCLK#
B4
A21
20
H_NMI
LINT1
BCLK1
CLK_CPU_BCLK#
4
H_SMI#
A3
20
H_SMI#
SMI#
TPAD28TPAD28
TP14TP14
CPU_RSVD01
M4
RSVD#M4
TPAD28TPAD28
TP17TP17
CPU_RSVD02
N5
RSVD#N5
TPAD28TPAD28
TP8TP8
CPU_RSVD03
T2
RSVD#T2
TPAD28TPAD28
TP12TP12
CPU_RSVD04
V3
RSVD#V3
TPAD28TPAD28
TP6TP6
CPU_RSVD05
B2
RSVD#B2
TPAD28TPAD28
TP7TP7
CPU_RSVD06
C3
RSVD#C3
TPAD28TPAD28
TP3TP3
CPU_RSVD07
D2
3
RSVD#D2
TPAD28TPAD28
TP20TP20
CPU_RSVD08
D22
RSVD#D22
TPAD28TPAD28
TP10TP10
CPU_RSVD09
D3
RSVD#D3
TPAD28TPAD28
TP18TP18
CPU_RSVD10
F6
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
3
RSVD#F6
TPAD28TPAD28
TP2TP2
CPU_RSVD11
B1
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
KEY_NC
ICH
ICH
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
Main source : 62.10079.021 Tyco 2-1871873-4
2nd source : 62.10040.221 Foxconn PZ47827-274M-41
4
<Core Design>
<Core Design>
<Core Design>
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
5
5
5
of
of
of
57
57
57
A
B
C
D
E
RESERVED
RESERVED
XDP/ITP SIGNALS
XDP/ITP SIGNALS
CONTROL
CONTROL
12
1
2
A B C D E 8 H_D#[0 63] VCC_CORE_S0 VCC_CORE_S0 U47B U47B 2 2 OF
A
B
C
D
E
8 H_D#[0 63]
VCC_CORE_S0
VCC_CORE_S0
U47B
U47B
2
2
OF 4
OF 4
U47C
U47C
3
3
OF 4
OF 4
H_D#0
H_D#32
E22
Y22
D0#
D32#
H_D#1
H_D#33
F24
AB24
A7
AB20
D1#
D33#
VCC
VCC
H_D#2
H_D#34
E26
V24
A9
AB7
D2#
D34#
VCC
VCC
H_D#3
H_D#35
G22
V26
A10
AC7
D3#
D35#
VCC
VCC
H_D#4
H_D#36
1
F23
V23
A12
AC9
1
D4#
D36#
VCC
VCC
H_D#5
H_D#37
G25
T22
A13
AC12
D5#
D37#
VCC
VCC
H_D#6
H_D#38
E25
U25
A15
AC13
D6#
D38#
VCC
VCC
H_D#7
H_D#39
E23
U23
A17
AC15
D7#
D39#
VCC
VCC
H_D#8
H_D#40
K24
Y25
A18
AC17
D8#
D40#
VCC
VCC
H_D#9
H_D#41
G24
W22
A20
AC18
D9#
D41#
VCC
VCC
H_D#10
H_D#42
J24
Y23
B7
AD7
D10#
D42#
VCC
VCC
H_D#11
H_D#43
J23
W24
B9
AD9
D11#
D43#
VCC
VCC
H_D#12
H_D#44
H22
W25
B10
AD10
D12#
D44#
VCC
VCC
H_D#13
H_D#45
F26
AA23
B12
AD12
D13#
D45#
VCC
VCC
H_D#14
H_D#46
K22
AA24
B14
AD14
D14#
D46#
VCC
VCC
H_D#15
H_D#47
H23
AB25
B15
AD15
D15#
D47#
VCC
VCC
H_DSTBN#0
H_DSTBN#2
J26
Y26
B17
AD17
8
H_DSTBN#0
DSTBN0#
DSTBN2#
H_DSTBN#2
8
VCC
VCC
H_DSTBP#0
H_DSTBP#2
H26
AA26
B18
AD18
8
H_DSTBP#0
DSTBP0#
DSTBP2#
H_DSTBP#2
8
VCC
VCC
H_DINV#0
H_DINV#2
H25
U22
B20
AE9
8
H_DINV#0
DINV0#
DINV2#
H_DINV#2
8
VCC
VCC
C9
AE10
VCC
VCC
C10
AE12
VCC
VCC
H_D#16
H_D#48
N22
AE24
C12
AE13
D16#
D48#
VCC
VCC
H_D#17
H_D#49
K25
AD24
C13
AE15
D17#
D49#
VCC
VCC
Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .
H_D#18
H_D#50
P26
AA21
C15
AE17
D18#
D50#
VCC
VCC
H_D#19
H_D#51
R23
AB22
C17
AE18
D19#
D51#
VCC
VCC
H_D#20
H_D#52
L23
AB21
C18
AE20
D20#
D52#
VCC
VCC
H_D#21
H_D#53
M24
AC26
D9
AF9
D21#
D53#
VCC
VCC
H_D#22
H_D#54
L22
AD20
D10
AF10
D22#
D54#
VCC
VCC
H_D#23
H_D#55
M23
AE22
D12
AF12
D23#
D55#
VCC
VCC
H_D#24
H_D#56
P25
AF23
D14
AF14
D24#
D56#
VCC
VCC
H_D#25
H_D#57
P23
AC25
D15
AF15
D25#
D57#
VCC
VCC
H_D#26
H_D#58
P22
AE21
D17
AF17
D26#
D58#
VCC
VCC
H_D#27
H_D#59
T24
AD21
D18
AF18
D27#
D59#
VCC
VCC
1D05V_S0
1D05V_S0
2
H_D#28
H_D#60
2
R24
AC22
E7
AF20
D28#
D60#
VCC
VCC
H_D#29
H_D#61
L25
AD23
E9
D29#
D61#
VCC
H_D#30
H_D#62
T25
AF22
E10
G21
D30#
D62#
VCC
VCCP
H_D#31
H_D#63
N25
AC23
E12
V6
D31#
D63#
VCC
VCCP
R309
R309
H_DSTBN#1
H_DSTBN#3
L26
AE25
E13
J6
8
H_DSTBN#1
DSTBN1#
DSTBN3#
H_DSTBN#3
8
VCC
VCCP
1KR2F-3-GP
1KR2F-3-GP
H_DSTBP#1
H_DSTBP#3
C24
C24
M26
AF24
E15
K6
8
H_DSTBP#1
DSTBP1#
DSTBP3#
H_DSTBP#3
8
VCC
VCCP
H_DINV#1
H_DINV#3
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
N24
AC20
E17
M6
8
H_DINV#1
DINV1#
DINV3#
H_DINV#3
8
VCC
VCCP
E18
J21
VCC
VCCP
V_CPU_GTLREF
COMP0
R311R311
1 27D4R2F-L1-GP27D4R2F-L1-GP
AD26
R26
2
E20
K21
GTLREF
COMP0
VCC
VCCP
TPAD28TPAD28
TP21TP21
TEST1
C23
MISC
MISC
COMP1
R310R310
1 54D9R2F-L1-GP54D9R2F-L1-GP
U26
2
F7
M21
TEST1
COMP1
VCC
VCCP
TPAD28TPAD28
TP23TP23
TEST2
COMP2
R42R42
1 27D4R2F-L1-GP27D4R2F-L1-GP
D25
AA1
2
F9
N21
TEST2
COMP2
VCC
VCCP
R308
R308
C617
C617
TPAD28TPAD28
TP22TP22
TEST3
COMP3
R41R41
1 54D9R2F-L1-GP54D9R2F-L1-GP
C24
Y1
2
F10
N6
TEST3
COMP3
VCC
VCCP
2KR2F-3-GP
2KR2F-3-GP
TEST4
1
2
AF26
F12
R21
TEST4
VCC
VCCP
TPAD28TPAD28
TP5TP5
TEST5
H_DPRSTP#
AF1
E5
F14
R6
TEST5
DPRSTP#
H_DPRSTP#
8,20,40
VCC
VCCP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TPAD28TPAD28
TP24TP24
TEST6
H_DPSLP#
A26
B5
F15
T21
layout note:
TEST6
DPSLP#
H_DPSLP#
20
VCC
VCCP
DY
DY
H_DPWR#
D24
F17
T6
DPWR#
H_DPWR#
8
VCC
VCCP
CPU_BSEL0
H_PWRGOOD
B22
D6
F18
V21
4,8
CPU_BSEL0
BSEL0
PWRGOOD
H_PWRGOOD
20,45
VCC
VCCP
1D5V_S0
CPU_BSEL1
H_CPUSLP#
B23
D7
F20
W21
place C618 near
PIN B26
4,8
CPU_BSEL1
BSEL1
SLP#
H_CPUSLP#
8
VCC
VCCP
CPU_BSEL2
PSI#
C21
AE6
AA7
4,8
CPU_BSEL2
BSEL2
PSI#
PSI#
40
VCC
AA9
B26
VCC
VCCA
AA10
C26
VCC
VCCA
C618
C618
AA12
VCC
CPU_VID[0
6]
40
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
CPU_VID0
C620
C620
AA13
AD6
VCC
VID0
CPU_VID1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AA15
AF5
VCC
VID1
CPU_VID2
DATA GRP0
DATA GRP0
DATA GRP1
DATA GRP1
PLACE C617 close to the TEST4 PIN,
make sure TEST3,TEST4,TEST5 trace
routing is reference to GND and
AA17
AE5
VCC
VID2
CPU_VID3
AA18
AF4
VCC
VID3
CPU_VID4
AA20
AE3
VCC
VID4
CPU_VID5
AB9
AF3
VCC
VID5
CPU_VID6
AC10
AE2
away other noisy signals
3
VCC
VID6
3
AB10
VCC
AB12
VCC
Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
VCC_SENSE
AB14
AF7
VCC
VCCSENSE
VCC_SENSE
40
Length match within
25 mils . The trace
width/space/other is
20/7/25 .
AB15
VCC
AB17
VCC
VSS_SENSE
AB18
AE7
VCC
VSSSENSE
VSS_SENSE
40
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
166
0
1 1
toggling signal .
COMP[0,2] trace
VCC_SENSE
1
2
VCC_CORE_S0
R47R47
100R2F-L1-GP-U100R2F-L1-GP-U
200
0
1 0
width is 18 mils.
COMP[1,3] trace
width is 4 mils .
VSS_SENSE
1
2
R48R48
100R2F-L1-GP-U100R2F-L1-GP-U
Close to CPU pin
within 500mils
4
<Core Design>
<Core Design>
<Core Design>
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
6
6
6
of
of
of
57
57
57
A
B
C
D
E
12
1
2
DATA GRP2DATA
DATA GRP2DATA
GRP3
GRP3
12
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP A B C D E SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
A
B
C
D
E
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_CORE_S0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C64
C64
C43
C43
C53
C53
C54
C54
C45
C45
C62
C62
C50
C50
C47
C47
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
U47D
U47D
4
4
OF 4
OF 4
Place these capacitors on L1
(North side ,Secondary Layer)
1 A4
P6
1
VSS
VSS
A8
P21
DY
DY
DY
DY
VSS
VSS
A11
P24
VSS
VSS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
A14
R2
VSS
VSS
A16
R5
VSS
VSS
A19
R22
VSS
VSS
A23
R25
VSS
VSS
AF2
T1
VSS
VSS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_CORE_S0
B6
T4
VSS
VSS
B8
T23
VSS
VSS
B11
T26
VSS
VSS
B13
U3
VSS
VSS
B16
U6
VSS
VSS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C49
C49
C42
C42
C63
C63
C65
C65
C44
C44
C52
C52
C59
C59
C58
C58
B19
U21
VSS
VSS
B21
U24
VSS
VSS
B24
V2
VSS
VSS
C5
V5
VSS
VSS
Place these capacitors on L1
(North side ,Secondary Layer)
C8
V22
VSS
VSS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C11
V25
DY
DY
DY
DY
VSS
VSS
C14
W1
VSS
VSS
C16
W4
VSS
VSS
C19
W23
VSS
VSS
C2
W26
VSS
VSS
C22
Y3
VSS
VSS
C25
Y6
VSS
VSS
D1
Y21
VSS
VSS
D4
Y24
VSS
VSS
D8
AA2
VSS
VSS
D11
AA5
VSS
VSS
2
2 D13
AA8
VSS
VSS
D16
AA11
VSS
VSS
D19
AA14
VSS
VSS
D23
AA16
VSS
VSS
D26
AA19
VSS
VSS
E3
AA22
Mid Frequencd
Decoupling
VSS
VSS
E6
AA25
VSS
VSS
E8
AB1
VSS
VSS
E11
AB4
VSS
VSS
E14
AB8
VSS
VSS
E16
AB11
VSS
VSS
E19
AB13
VSS
VSS
E21
AB16
VSS
VSS
E24
AB19
VSS
VSS
F5
AB23
VSS
VSS
F8
AB26
VSS
VSS
F11
AC3
VSS
VSS
F13
AC6
VSS
VSS
F16
AC8
VSS
VSS
F19
AC11
VSS
VSS
F2
AC14
VSS
VSS
F22
AC16
VSS
VSS
F25
AC19
VSS
VSS
G4
AC21
VSS
VSS
G1
AC24
VSS
VSS
G23
AD2
VSS
VSS
G26
AD5
VSS
VSS
H3
AD8
VSS
VSS
H6
AD11
3
VSS
VSS
3
H21
AD13
VSS
VSS
H24
AD16
VSS
VSS
J2
AD19
VSS
VSS
1D05V_S0
J5
AD22
VSS
VSS
J22
AD25
VSS
VSS
J25
AE1
VSS
VSS
K1
AE4
VSS
VSS
K4
AE8
VSS
VSS
K23
AE11
VSS
VSS
K26
AE14
VSS
VSS
C588
C588
C586
C586
C581
C581
C587
C587
C580
C580
C579
C579
L3
AE16
VSS
VSS
Place these
inside socket
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L6
AE19
VSS
VSS
L21
AE23
cavity on L1
VSS
VSS
L24
AE26
VSS
VSS
M2
A2
VSS
VSS
M5
AF6
(North side
Secondary)
VSS
VSS
M22
AF8
VSS
VSS
M25
AF11
VSS
VSS
N1
AF13
VSS
VSS
N4
AF16
VSS
VSS
N23
AF19
VSS
VSS
N26
AF21
VSS
VSS
P3
A25
VSS
VSS
AF25
VSS
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
4
<Core Design>
<Core Design>
<Core Design>
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
7
7
7
of
of
of
57
57
57
A
B
C
D
E
1
2
1
2
1
2
12
12
1
2
12
12
12
12
12
12
1
2
12
12
12
12
1
2
12
12
12
12
A B C D E U57A U57A 1 OF 10 1 OF 10 6 H_D#[0
A
B
C
D
E
U57A
U57A
1 OF 10
1 OF 10
6 H_D#[0 63]
H_A#[3
35]
5
H_D#0
H_A#3
E2
J13
H_D#0
H_A#3
H_D#1
H_A#4
G2
B11
H_D#1
H_A#4
H_D#2
H_A#5
G7
C11
H_D#2
H_A#5
H_D#3
H_A#6
U57B
U57B
2 OF 10
2 OF 10
M6
M11
H_D#3
H_A#6
1D8V_S3
H_D#4
H_A#7
H7
C15
H_D#4
H_A#7
H_D#5
H_A#8
M_CLK_DDR0
H3
F16
P36
AV29
H_D#5
H_A#8
RSVD#P36
SM_CK0
M_CLK_DDR0
14
H_D#6
H_A#9
M_CLK_DDR1
G4
L13
P37
BB23
RSVD
RSVD
CFG
CFG
PM
PM
NC
NC
H_D#6
H_A#9
RSVD#P37
SM_CK1
M_CLK_DDR1
14
H_D#7
H_A#10
C668
C668
M_CLK_DDR2
F3
G17
R35
BA25
H_D#7
H_A#10
RSVD#R35
SM_CK3
M_CLK_DDR2
15
H_D#8
H_A#11
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
R329
R329
M_CLK_DDR3
N8
C14
N35
AV23
H_D#8
H_A#11
RSVD#N35
SM_CK4
M_CLK_DDR3
15
H_D#9
H_A#12
1KR2F-3-GP
1KR2F-3-GP
H2
K16
AR12
H_D#9
H_A#12
RSVD#AR12
H_D#10
H_A#13
M_CLK_DDR#0
M10
B13
AR13
AW30
H_D#10
H_A#13
RSVD#AR13
SM_CK#0
M_CLK_DDR#0
14
H_D#11
H_A#14
M_CLK_DDR#1
N12
L16
AM12
BA23
H_D#11
H_A#14
RSVD#AM12
SM_CK#1
M_CLK_DDR#1
14
H_D#12
H_A#15
SM_RCOMP_VOH
M_CLK_DDR#2
N9
J17
AN13
AW25
H_D#12
H_A#15
RSVD#AN13
SM_CK#3
M_CLK_DDR#2
15
H_D#13
H_A#16
M_CLK_DDR#3
H5
B14
J12
AW23
H_D#13
H_A#16
RSVD#J12
SM_CK#4
M_CLK_DDR#3
15
1
H_D#14
H_A#17
1
P13
K19
AR37
H_D#14
H_A#17
RSVD#AR37
H_D#15
H_A#18
R330
R330
DDR_CKE0_DIMMA
K9
P15
AM36
BE29
H_D#15
H_A#18
RSVD#AM36
SM_CKE0
DDR_CKE0_DIMMA
14
H_D#16
H_A#19
3K01R2F-3-GP
3K01R2F-3-GP
DDR_CKE1_DIMMA
M2
R17
AL36
AY32
H_D#16
H_A#19
RSVD#AL36
SM_CKE1
DDR_CKE1_DIMMA
14
H_D#17
H_A#20
DDR_CKE2_DIMMB
W10
B16
AM37
BD39
H_D#17
H_A#20
RSVD#AM37
SM_CKE3
DDR_CKE2_DIMMB
15
H_D#18
H_A#21
DDR_CKE3_DIMMB
Y8
H20
D20
BG37
H_D#18
H_A#21
RSVD#D20
SM_CKE4
DDR_CKE3_DIMMB
15
H_D#19
H_A#22
SM_RCOMP_VOL
V4
L19
H_D#19
H_A#22
H_D#20
H_A#23
DDR_CS0_DIMMA#
M3
D17
BG20
H_D#20
H_A#23
SM_CS#0
DDR_CS0_DIMMA#
14
H_D#21
H_A#24
DDR_CS1_DIMMA#
J1
M17
BK16
H_D#21
H_A#24
SM_CS#1
DDR_CS1_DIMMA#
14
H_D#22
H_A#25
R332
R332
DDR_CS2_DIMMB#
N5
N16
BG16
H_D#22
H_A#25
SM_CS#2
DDR_CS2_DIMMB#
15
H_D#23
H_A#26
C680
C680
1KR2F-3-GP
1KR2F-3-GP
DDR_CS3_DIMMB#
N3
J19
H10
BE13
H_D#23
H_A#26
RSVD#H10
SM_CS#3
DDR_CS3_DIMMB#
15
H_D#24
H_A#27
W6
B18
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
B51
H_D#24
H_A#27
RSVD#B51
H_D#25
H_A#28
M_ODT0
W9
E19
BJ20
BH18
H_D#25
H_A#28
RSVD#BJ20
SM_ODT0
M_ODT0
14
H_D#26
H_A#29
M_ODT1
N2
B17
BK22
BJ15
H_D#26
H_A#29
RSVD#BK22
SM_ODT1
M_ODT1
14
H_D#27
H_A#30
M_ODT2
Y7
B15
BF19
BJ14
H_D#27
H_A#30
RSVD#BF19
SM_ODT2
M_ODT2
15
H_D#28
H_A#31
M_ODT3
Y9
E17
BH20
BE16
H_D#28
H_A#31
RSVD#BH20
SM_ODT3
M_ODT3
15
H_D#29
H_A#32
P4
C18
BK18
H_D#29
H_A#32
RSVD#BK18
H_D#30
H_A#33
SM_RCOMP_VOH
W3
A19
BJ18
BK31
H_D#30
H_A#33
RSVD#BJ18
SM_RCOMP_VOH
1D8V_S3
H_D#31
H_A#34
SM_RCOMP_VOL
N1
B19
BF23
BL31
H_D#31
H_A#34
RSVD#BF23
SM_RCOMP_VOL
H_D#32
H_A#35
AD12
N19
BG23
H_D#32
H_A#35
RSVD#BG23
H_D#33
SM_RCOMP
AE3
BC23
BL15
1
2
H_D#33
RSVD#BC23
SM_RCOMP
H_D#34
H_ADS#
SM_RCOMP#
AD9
G12
BD24
BK14
R328
R328
1
2
20R2F-GP
20R2F-GP
H_D#34
H_ADS#
H_ADS#
5
RSVD#BD24
SM_RCOMP#
H_D#35
H_ADSTB#0
R327
R327
20R2F-GP
20R2F-GP
AC9
H17
H_D#35
H_ADSTB#0
H_ADSTB#0
5
H_D#36
H_ADSTB#1
AC7
G20
AR49
DDR_VREF_S3
H_D#36
H_ADSTB#1
H_ADSTB#1
5
SM_VREF#AR49
H_D#37
H_BNR#
DDR_VREF_S3
AC14
C8
BH39
AW4
H_D#37
H_BNR#
H_BNR#
5
RSVD#BH39
SM_VREF#AW4
H_D#38
H_BPRI#
AD11
E8
AW20
H_D#38
H_BPRI#
H_BPRI#
5
RSVD#AW20
H_D#39
H_BR0#
AC11
F12
BK20
H_D#39
H_BREQ#
H_BR0#
5
RSVD#BK20
H_D#40
H_DEFER#
AB2
D6
H_D#40
H_DEFER#
H_DEFER#
5
H_D#41
H_DBSY#
AD7
C10
B42
For Discrete:
H_D#41
H_DBSY#
H_DBSY#
5
DPLL_REF_CLK
H_D#42
CLK_MCH_BCLK
AB1
AM5
B44
C42
CLK_MCH_BCLK
4
Short to GND.
H_D#42
HPLL_CLK
RSVD#B44
DPLL_REF_CLK#
H_D#43
CLK_MCH_BCLK#
Y3
AM7
C44
H48
H_D#43
HPLL_CLK#
CLK_MCH_BCLK#
4
RSVD#C44
DPLL_REF_SSCLK
H_D#44
H_DPWR#
AC6
H8
A35
H47
H_D#44
H_DPWR#
H_DPWR#
6
RSVD#A35
DPLL_REF_SSCLK#
H_D#45
H_DRDY#
AE2
K7
B37
H_D#45
H_DRDY#
H_DRDY#
5
2
RSVD#B37
2
H_D#46
H_HIT#
CLK_MCH_3GPLL
AC5
E4
B36
K44
H_D#46
H_HIT#
H_HIT#
5
RSVD#B36
PEG_CLK
CLK_MCH_3GPLL
4
H_D#47
H_HITM#
CLK_MCH_3GPLL#
AG3
C6
B34
K45
H_D#47
H_HITM#
H_HITM#
5
RSVD#B34
PEG_CLK#
CLK_MCH_3GPLL#
4
H_D#48
H_LOCK#
AJ9
G10
C34
H_D#48
H_LOCK#
H_LOCK#
5
RSVD#C34
H_D#49
H_TRDY#
AH8
B7
H_D#49
H_TRDY#
H_TRDY#
5
H_D#50
AJ14
H_D#50
1D05V_S0
H_D#51
AE9
H_D#51
H_D#52
DMI_TXN0
AE11
AN47
H_D#52
DMI_RXN0
DMI_TXN0 21
H_D#53
DMI_TXN1
AH12
AJ38
H_D#53
DMI_RXN1
DMI_TXN1 21
H_D#54
H_DINV#0
CPU_BSEL0
DMI_TXN2
AJ5
K5
P27
AN42
H_D#54
H_DINV#0
H_DINV#0
6
4,6
CPU_BSEL0
CFG0
DMI_RXN2
DMI_TXN2 21
H_D#55
H_DINV#1
CPU_BSEL1
DMI_TXN3
AH5
L2
N27
AN46
H_D#55
H_DINV#1
H_DINV#1
6
4,6
CPU_BSEL1
CFG1
DMI_RXN3
DMI_TXN3 21
H_D#56
H_DINV#2
CPU_BSEL2
AJ6
AD13
N24
H_D#56
H_DINV#2
H_DINV#2
6
4,6
CPU_BSEL2
CFG2
R313
R313
R312
R312
H_D#57
H_DINV#3
DMI_TXP0
AE7
AE13
C21
AM47
H_D#57
H_DINV#3
H_DINV#3
6
CFG3
DMI_RXP0
DMI_TXP0 21
H_D#58
DMI_TXP1
AJ7
C23
AJ39
H_D#58
CFG4
DMI_RXP1
DMI_TXP1 21
H_D#59
H_DSTBN#0
CFG5
DMI_TXP2
AJ2
M7
F23
AN41
H_D#59
H_DSTBN#0
H_DSTBN#0
6
TP58TP58
CFG5
DMI_RXP2
DMI_TXP2 21
H_D#60
H_DSTBN#1
CFG6
DMI_TXP3
AE5
K3
N23
AN45
H_D#60
H_DSTBN#1
H_DSTBN#1
6
TP62TP62
CFG6
DMI_RXP3
DMI_TXP3 21
H_D#61
H_DSTBN#2
CFG7
AJ3
AD2
G23
H_DSTBN#2
H_DSTBN#2
TP59TP59
H_D#61
6
CFG7
H_D#62
H_DSTBN#3
CFG8
DMI_RXN0
AH2
AH11
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
J20
AJ46
H_D#62
H_DSTBN#3
H_DSTBN#3
6
TP52TP52
CFG8
DMI_TXN0
DMI_RXN0
21
H_D#63
CFG9
DMI_RXN1
AH13
C20
AJ41
TP53TP53
H_D#63
CFG9
DMI_TXN1
DMI_RXN1
21
H_DSTBP#0
CFG10
DMI_RXN2
L7
R24
AM40
H_DSTBP#0
H_DSTBP#0
6
TP63TP63
CFG10
DMI_TXN2
DMI_RXN2
21
H_DSTBP#1
CFG11
DMI_RXN3
K2
L23
AM44
H_DSTBP#1
H_DSTBP#1
6
TP61TP61
CFG11
DMI_TXN3
DMI_RXN3
21
H_SWNG
H_DSTBP#2
CFG12
B3
AC2
J23
H_SWING
H_DSTBP#2
H_DSTBP#2
6
TP60TP60
CFG12
H_RCOMP
H_DSTBP#3
CFG13
DMI_RXP0
C2
AJ10
E23
AJ47
TP57TP57
H_RCOMP
H_DSTBP#3
H_DSTBP#3
6
CFG13
DMI_TXP0
DMI_RXP0 21
DMI_RXP1
E20
AJ42
CFG14
DMI_TXP1
DMI_RXP1 21
H_SCOMP
H_REQ#0
DMI_RXP2
W1
M14
K23
AM39
H_SCOMP
H_REQ#0
H_REQ#0
5
CFG15
DMI_TXP2
DMI_RXP2 21
H_SCOMP#
H_REQ#1
CFG16
DMI_RXP3
W2
E13
M20
AM43
H_SCOMP#
H_REQ#1
H_REQ#1
5
TP54TP54
CFG16
DMI_TXP3
DMI_RXP3 21
H_REQ#2
A11
M24
H_REQ#2
H_REQ#2
5
CFG17
H_RESET#
H_REQ#3
CFG18
B6
H13
L32
5 H_RESET#
H_CPURST#
H_REQ#3
H_REQ#3
5
TP67TP67
CFG18
H_CPUSLP#
H_REQ#4
CFG19
E5
B12
N33
TP69TP69
6 H_CPUSLP#
H_CPUSLP#
H_REQ#4
H_REQ#4
5
CFG19
CFG20
L35
TP70TP70
CFG20
H_RS#0
E12
H_RS#0
H_RS#0
5
H_VREF
H_RS#1
DFGT_VID0
B9
D7
E35
H_AVREF
H_RS#1
H_RS#1
5
GFX_VID0
TP72TP72
H_RS#2
DFGT_VID1
A9
D8
A39
3
H_DVREF
H_RS#2
H_RS#2
5
GFX_VID1
TP113TP113
3
PM_BMBUSY#
DFGT_VID2
G41
C38
21 PM_BMBUSY#
PM_BM_BUSY#
GFX_VID2
TP112TP112
H_DPRSTP#
DFGT_VID3
L39
B39
6,20,40
H_DPRSTP#
PM_DPRSTP#
GFX_VID3
TP114TP114
PM_EXTTS#0
DFGT_VR_EN
L36
E36
14
PM_EXTTS#0
PM_EXT_TS#0
GFX_VR_EN
TP71TP71
PM_EXTTS#1
J36
15
PM_EXTTS#1
PM_EXT_TS#1
layout note :
PM_POK_R
AW49
PWROK
R103
R103
100R2J-2-GP
100R2J-2-GP
PLT_RST_R#
2
1
AV20
Route H_SCOMP and H_SCOMP# with trace width, spacing
and impedance (55 ohm) same as FSB data traces
19,23,27,28,29,33,47
PLT_RST1#
RSTIN#
1D25V_S0
H_THERMTRIP#
N20
5,20,33,45
H_THERMTRIP#
THERMTRIP#
DPRSLPVR
G36
21,40
DPRSLPVR
DPRSLPVR
CL_CLK0
21
CL_DATA0
21
Layout Note :
R366
R366
AM49
CL_CLK
1KR2F-3-GP
1KR2F-3-GP
BJ51
AK50
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
NC#BJ51
CL_DATA
R128
R128
0R2J-2-GP
PM_POK_R
CLPWROK_MCH
R122
R122
PM_POK_R
1
DY
DY
21,35
PM_PWROK
0R2J-2-GP
BK51
AT43
1
2
NC#BK51
CL_PWROK
BK50
AN49
0R0402-PAD
0R0402-PAD
NC#BK50
CL_RST#
CL_RST#
21
1D05V_S0
CL_VREF
1
BL50
AM50
21,40
VGATE_PWRGD
NC#BL50
CL_VREF
R129
R129
0R2J-2-GP
0R2J-2-GP
BL49
NC#BL49
1D05V_S0
BL3
For Discrete:
NC#BL3
R365
R365
BL2
Short to GND.
NC#BL2
BK1
C749
C749
392R2F-GP
392R2F-GP
NC#BK1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BJ1
H35
NC#BJ1
SDVO_CTRL_CLK
R325
R325
R321
R321
E1
K36
NC#E1
SDVO_CTRL_DATA
1KR2F-3-GP
1KR2F-3-GP
221R2F-2-GP
221R2F-2-GP
A5
G39
NC#A5
CLKREQ#
CLKREQ#_B
4
MCH_ICH_SYNC#
C51
G40
NC#C51
ICH_SYNC#
MCH_ICH_SYNC#
21
B50
NC#B50
H_VREF
H_RCOMP
H_SWNG
A50
NC#A50
TEST1_GMCH
R338
R338
A49
A37
1
2
NC#A49
TEST1
TEST2_GMCH
BK2
R32
1
2
0R0402-PAD
0R0402-PAD
NC#BK2
TEST2
R324
R324
C643
C643
R314
R314
C634
C634
R108
R108
2KR2F-3-GP
2KR2F-3-GP
24D9R2F-L-GP
24D9R2F-L-GP
R320
R320
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
20KR2J-L2-GP
20KR2J-L2-GP
100R2F-L1-GP-U
100R2F-L1-GP-U
3D3V_S0
4
4
Layout Note :
RN21
RN21
PM_EXTTS#0
1
4
<Core Design>
<Core Design>
<Core Design>
Layout Note :
Place C634 near
pin B3 of NB
PM_EXTTS#1
2
3
0921 P/N CHANGE TO 71.CREST.M02
Place C643 within 100 mils of NB
SRN10KJ-5-GP
SRN10KJ-5-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CLKREQ#_B
1
2
R113
R113
10KR2J-3-GP
10KR2J-3-GP
Title
Title
Title
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Hawke-Intel
Hawke-Intel
Hawke-Intel
-1
-1
-1
Date:
Date:
Date:
Sunday, September 09, 2007
Sunday, September 09, 2007
Sunday, September 09, 2007
Sheet
Sheet
Sheet
8
8
8
of
of
of
57
57
57
A
B
C
D
E
54D9R2F-L1-GP
54D9R2F-L1-GP
12
12
12
12
12
54D9R2F-L1-GP
54D9R2F-L1-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
HOST
HOST
12
12
12
12
12
12
12
C683
C683
C672
C672
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
12
12
CLK
CLK
MISC
MISC
ME
ME
GRAPHICS VID
GRAPHICS VID
DMI
DMI
DDR MUXING
DDR MUXING
12
12
1
2
 

A

B

C

D

E

 
 

DDR_A_D[0

63]

14

       
         

DDR_B_D[0

63]

15

 

DDR_A_BS[0

2]

14

 
 

DDR_B_BS[0

2]

15

1

1 DDR_A_DM[0 7] 14     1

DDR_A_DM[0

7]

14

   

1

DDR_B_DM[0

7]

15

DDR_A_DQS[0

7]

14

 
 

DDR_B_DQS[0

7]

15

DDR_A_DQS#[0

7]

14

   
 

DDR_B_DQS#[0

7]

15

 

DDR_A_MA[0

14]

14

 
 

DDR_B_MA[0

14]

15

 

U57D

U57D

4

4

OF 10

OF 10

U57E

U57E

5

5

OF 10

OF 10

 

DDR_A_D0

AR43

   

BB19

DDR_A_BS0

 

DDR_B_D0

AP49

     

AY17

DDR_B_BS0

 

DDR_A_D1

AW44

SA_DQ0

SA_DQ1

 

SA_BS0

SA_BS1

BK19

DDR_A_BS1

DDR_B_D1

AR51

SB_DQ0

SB_DQ1

 

SB_BS0

SB_BS1

 

BG18

DDR_B_BS1

 

DDR_A_D2

BA45

BF29

DDR_A_BS2

DDR_B_D2

AW50

 

BG36

DDR_B_BS2

   

DDR_A_D3

AY46

SA_DQ2

SA_DQ3

SA_DQ4

SA_DQ5

SA_DQ6

SA_DQ7

SA_DQ8

SA_BS2

 

DDR_B_D3

AW51

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5

SB_DQ6

SB_DQ7

SB_DQ8

SB_BS2

     

DDR_A_D4

AR41

SA_CAS#

DDR_A_CAS# BL17
DDR_A_CAS#
BL17

DDR_A_CAS#

14

 

DDR_B_D4

AN51

SB_CAS#

DDR_B_CAS# BE17
DDR_B_CAS#
BE17

DDR_B_CAS#

15

 

DDR_A_D5

AR45

DDR_B_D5

AN50

DDR_A_D6

AT42

SA_DM0

SA_DM1

SA_DM2

SA_DM3

SA_DM4

SA_DM5

SA_DM6

SA_DM7

AT45

DDR_A_DM0

 

DDR_B_D6

AV50

SB_DM0

SB_DM1

SB_DM2

SB_DM3

SB_DM4

SB_DM5

SB_DM6

SB_DM7

AR50

DDR_B_DM0

 

DDR_A_D7

AW47

BD44

DDR_A_DM1

DDR_B_D7

AV49

 

BD49

DDR_B_DM1

 

DDR_A_D8

BB45

BD42

DDR_A_DM2

DDR_B_D8

BA50

 

BK45

DDR_B_DM2

 

DDR_A_D9

BF48

AW38

DDR_A_DM3

DDR_B_D9

BB50

 

BL39

DDR_B_DM3

 

DDR_A_D10

BG47

SA_DQ9

SA_DQ10

SA_DQ11

SA_DQ12

SA_DQ13

SA_DQ14

SA_DQ15

SA_DQ16

 

AW13

DDR_A_DM4

DDR_B_D10

BA49

SB_DQ9

SB_DQ10

SB_DQ11

SB_DQ12

SB_DQ13

SB_DQ14

SB_DQ15

SB_DQ16

   

BH12

DDR_B_DM4

 

DDR_A_D11

BJ45

BG8

DDR_A_DM5

DDR_B_D11

BE50

 

BJ7

DDR_B_DM5

 

DDR_A_D12

BB47

AY5

DDR_A_DM6

DDR_B_D12

BA51

 

BF3

DDR_B_DM6

 

DDR_A_D13

BG50

AN6

DDR_A_DM7

DDR_B_D13

AY49

 

AW2

DDR_B_DM7

 

DDR_A_D14

BH49

 

DDR_B_D14

BF50

   

DDR_A_D15

BE45

SA_DQS0

SA_DQS1

AT46

DDR_A_DQS0

 

DDR_B_D15

BF49

SB_DQS0

SB_DQS1

AT50

DDR_B_DQS0

 

DDR_A_D16

AW43

BE48

DDR_A_DQS1

DDR_B_D16

BJ50

 

BD50

DDR_B_DQS1

2

DDR_A_D17

BE44

BB43

DDR_A_DQS2

DDR_B_D17

BJ44

 

BK46

DDR_B_DQS2

2

DDR_A_D18

BG42

SA_DQ17

SA_DQ18

SA_DQ19

SA_DQ20

SA_DQ21

SA_DQ22

SA_DQ23

SA_DQ24

SA_DQ25

SA_DQ26

SA_DQ27

SA_DQ28

SA_DQ29

SA_DQ30

SA_DQ31

SA_DQS2

SA_DQS3

SA_DQS4

SA_DQS5

SA_DQS6

SA_DQS7

SA_DQS#0

SA_DQS#1

SA_DQS#2

SA_DQS#3

SA_DQS#4

SA_DQS#5

SA_DQS#6

SA_DQS#7

BC37

DDR_A_DQS3

DDR_B_D18

BJ43

SB_DQ17

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ25

SB_DQ26

SB_DQ27

SB_DQ28

SB_DQ29

SB_DQ30

SB_DQ31

SB_DQS2

SB_DQS3

SB_DQS4

SB_DQS5

SB_DQS6

SB_DQS7

SB_DQS#0

SB_DQS#1

SB_DQS#2

SB_DQS#3

SB_DQS#4

SB_DQS#5

SB_DQS#6

SB_DQS#7

 

BK39

DDR_B_DQS3

DDR_A_D19

BE40

BB16

DDR_A_DQS4

DDR_B_D19

BL43

 

BJ12

DDR_B_DQS4

DDR_A_D20

BF44

BH6

DDR_A_DQS5

DDR_B_D20

BK47

 

BL7

DDR_B_DQS5

DDR_A_D21

BH45

BB2

DDR_A_DQS6

DDR_B_D21

BK49

 

BE2

DDR_B_DQS6

DDR_A_D22

BG40

AP3

DDR_A_DQS7

DDR_B_D22

BK43

 

AV2

DDR_B_DQS7

DDR_A_D23

BF40

DDR SYSTEM MEMORRY A

DDR SYSTEM MEMORRY A

AT47

DDR_A_DQS#0

DDR_B_D23

BK42

 

AU50

DDR_B_DQS#0

DDR_A_D24

AR40

DDR_A_DQS#1 BD47 DDR_A_DQS#2 BC41 DDR_A_DQS#3 BA37 DDR_A_DQS#4 BA16 DDR_A_DQS#5 BH7 DDR_A_DQS#6 BC1
DDR_A_DQS#1
BD47
DDR_A_DQS#2
BC41
DDR_A_DQS#3
BA37
DDR_A_DQS#4
BA16
DDR_A_DQS#5
BH7
DDR_A_DQS#6
BC1
DDR_A_DQS#7
AP2

DDR_B_D24

BJ41

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

DDR_B_DQS#1 BC50 DDR_B_DQS#2 BL45 DDR_B_DQS#3 BK38 DDR_B_DQS#4 BK12 DDR_B_DQS#5 BK7 DDR_B_DQS#6 BF2
DDR_B_DQS#1
BC50
DDR_B_DQS#2
BL45
DDR_B_DQS#3
BK38
DDR_B_DQS#4
BK12
DDR_B_DQS#5
BK7
DDR_B_DQS#6
BF2
DDR_B_DQS#7
AV3

DDR_A_D25

AW40

DDR_B_D25

BL41

DDR_A_D26

AT39

DDR_B_D26

BJ37

DDR_A_D27

AW36

DDR_B_D27

BJ36

DDR_A_D28

AW41

DDR_B_D28

BK41

DDR_A_D29

AY41

DDR_B_D29

BJ40

DDR_A_D30 AV38 DDR_B_D30 BL35  

DDR_A_D30

AV38

DDR_B_D30

BL35

 
DDR_A_D30 AV38 DDR_B_D30 BL35  

DDR_A_D31

DDR_A_D32

AT38

AV13

BJ19

DDR_A_MA0

DDR_B_D31

DDR_B_D32

BK37

BK13

BC18

DDR_B_MA0

   

DDR_A_D33

AT13

SA_DQ32

SA_DQ33

SA_DQ34

SA_DQ35

SA_DQ36

SA_DQ37

SA_DQ38

SA_DQ39

SA_DQ40

SA_DQ41