Giao Trinh Verilog HDL Full 3053

I HC QUC GIA THNH PH H CH MINH
TRNG I HC CNG NGH THNG TIN

--------------oOo--------------
Gio trnh
NGN NG M T PHN CNG
VERILOG
Bin son: TS. V c Lung
ThS. Lm c Khi
Ks. Phan nh Duy
2012
Gio trnh ngn ng Verilog HDL
Li ni u
Ngy nay, khi mch thit k vi hng triu cng logic c tch hp trong mt con Chip th
vic thit k mch v i dy kt ni bng tay tr nn bt kh thi, chnh t l do mt khi nim
ngn ng c mc tru tng cao dng m t thit k phn cng c ra i, chnh
l Verilog. Cng vi s ra i ca ngn ng m t phn cng Verilog l hng lot cc cng c
EDA (Electronic Design Automation) v CAD (Computer Aided Design) gip cho nhng
k s thit k phn cng to nn nhng con Chip c tch hp rt cao, tc siu vit v
chc nng a dng.
Gio trnh Ngn ng m t phn cng Verilog nhm gip sinh vin trang b kin thc
v thit k vi mch. Gio trnh tp trung vo mng thit k cc mch s vi mch t hp v
mch tun t. Gio trnh cng gii thiu v cc bc cn thc hin trong qu trnh thit k vi
mch t vic m t thit k, kim tra, phn tch cho n tng hp phn cng ca thit k.
Gio trnh Ngn ng m t phn cng Verilog dng cho sinh vin chuyn ngnh K thut
my tnh v sinh vin cc khi in t. tip nhn kin thc d dng, sinh vin cn trang b
trc kin thc v thit k s v h thng s.
Gio trnh ny c bin dch v tng hp t kinh nghim nghin cu ging dy ca tc gi
v ba ngun ti liu chnh:
IEEE Standard for Verilog Hardware Description Language, 2006;
Verilog Digital System Design, Second Edition, McGraw-Hill;
The Complete Verilog Book, Vivek Sagdeo, Sun Micro System, Inc.
Nhm cung cp mt lung kin thc mch lc, gio trnh c chia ra lm 9 chng:
Chng 1: Dn nhp thit k h thng s vi Verilog. Chng ny s gii thiu lch

s pht trin ca ngn ng m t phn cng Verilog, bn cnh mt qui trnh thit
k vi mch s dng ngn ng m t phn cng Verilog cng c trnh by c th
y.
Chng 2: Trnh by cc t kha c s dng trong mi trng m t thit k bi

Verilog.
Chng 3: Trnh by cc loi d liu c s dng trong thit k mch bi Verilog,

gm hai loi d liu chnh l loi d liu net v loi d liu bin.
Chng 4: Trnh by cc ton t cng nh cc dng biu thc c h tr bi Verilog.
Chng 5: Gii thiu cu trc ca mt thit k, phng thc s dng thit k con.
Chng 6: Trnh by phng php thit k s dng m hnh cu trc, trong phng
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thc ny, module thit k c xy dng bng cch gi cc module thit k nh hn v
kt ni chng li.
Chng 7: Trnh by phng thc thit k s dng m hnh RTL bi php gn ni tip
v m hnh hnh vi s dng ngn ng c tnh tru tng cao tng t nh ngn ng lp
trnh. Phn thit k my trng thi s dng m hnh hnh vi cng c nu ra trong
chng ny.
Chng 8: Trnh by phng php thit k v s dng tc v v hm.
Chng 9: Gii thiu cc phng php kim tra chc nng ca thit k.
Do thi gian cng nh khi lng trnh by gio trnh khng cho php tc gi i su hn
v mi kha cnh ca thit k vi mch nh phn tch nh thi, tng hp phn cng, ... c
c nhng kin thc ny, c gi c th tham kho trong cc ti liu tham kho m gio trnh
ny cung cp.
Mc d nhm tc gi c gng bin son k lng tuy nhin cng kh trnh khi
nhng thiu st. Nhm tc gi mong nhn c nhng ng gp mang tnh xy dng t qu
c gi nhm chnh sa gio trnh hon thin hn.
Nhm tc gi
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Contents
Li ni u.......................................................................................................................................2
1 Chng 1. Dn nhp thit k h thng s vi Verilog..........................................................10
1.1
Qui trnh thit k s.........................................................................................................10
1.1.1
Dn nhp thit k.....................................................................................................12
1.1.2
Testbench trong Verilog...........................................................................................13
1.1.3
nh gi thit k......................................................................................................13
1.1.3.1
1.1.3.2
1.1.3.3
1.1.4
1.1.4.1
1.1.4.2
1.1.4.3
1.1.4.4
1.1.4.5
M phng.......................................................................................................................13
K thut chn kim tra (assertion)..................................................................................15
Kim tra thng thng...................................................................................................16
Bin dch v tng hp thit k.................................................................................16

Phn tch........................................................................................................................17
To phn cng................................................................................................................17
Ti u logic....................................................................................................................17
Binding..........................................................................................................................18
Sp xp cell v i dy kt ni.........................................................................................18
1.1.5
M phng sau khi tng hp thit k........................................................................19
1.1.6
Phn tch thi gian...................................................................................................20
1.1.7
To linh kin phn cng..........................................................................................20
1.2
Ngn ng m t phn cng Verilog (VerilogHDL)................................................................20
1.2.1
Qu trnh pht trin Verilog.....................................................................................20
1.2.2
Nhng c tnh ca Verilog.....................................................................................21
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.5
1.2.2.6
1.2.2.7
Mc chuyn mch.....................................................................................................21
Mc cng..................................................................................................................21
tr hon gia pin n pin...........................................................................................22
M t Bus.......................................................................................................................22
Mc hnh vi..............................................................................................................22
Nhng tin ch h thng.................................................................................................22
PLI.................................................................................................................................22
1.2.3
S lc v Verilog...................................................................................................22
1.3
Tng kt..........................................................................................................................23
1.4
Bi tp.............................................................................................................................23
2 Chng 2. Qui c v t kha...........................................................................................25
2.1
Khong trng...................................................................................................................25
2.2
Ch thch.........................................................................................................................25
2.3
Ton t............................................................................................................................25
2.4
S hc..............................................................................................................................25
2.4.1
Hng s nguyn.......................................................................................................26
2.4.2
Hng s thc............................................................................................................29
2.4.3
S o......................................................................................................................30
2.5
Chui...............................................................................................................................30
2.5.1.1
2.5.1.2
2.5.1.3
Khai bo bin chui.......................................................................................................30

X l chui.....................................................................................................................30
Nhng k t c bit trong chui....................................................................................31
2.6
nh danh, t kha v tn h thng................................................................................31
2.6.1
nh danh vi k t .............................................................................................32
2.6.2
Tc v h thng v hm h thng............................................................................32
2.7
Bi tp.............................................................................................................................33
3 Chng 3. Loi d liu trong Verilog...................................................................................70
3.1
Khi qut.........................................................................................................................70
3.2
Nhng h thng gi tr....................................................................................................70
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3.3
Khai bo loi d liu.......................................................................................................71
3.3.1
Gii thiu.................................................................................................................71
3.4
Khai bo loi d liu net.................................................................................................72
3.4.1
Gii thiu.................................................................................................................72
3.4.2
Wire v Tri...............................................................................................................73
3.4.3
Wired net..................................................................................................................75
3.4.3.1
3.4.3.2
Wand v triand Nets......................................................................................................75

Wor v Tri or.................................................................................................................76
3.4.4
Tri reg net.................................................................................................................76
3.4.5
Tri 0 v Tri 1 Nets....................................................................................................77
3.4.6
Supply0 v Supply1 Nets.........................................................................................77
3.4.7
Thi gian tr hon trn net.......................................................................................78
3.5
Khai bo loi d liu bin - reg.......................................................................................79
3.6
Khai bo port...................................................................................................................79
3.6.1
Gii thiu.................................................................................................................79
3.6.2
input.........................................................................................................................79
3.6.3
output.......................................................................................................................80
3.6.4
inout.........................................................................................................................80
3.7
Khai bo mng v phn t nh mt v hai chiu............................................................80
3.7.1
Gii thiu.................................................................................................................80
3.7.2
Mng net..................................................................................................................81
3.7.3
Mng thanh ghi........................................................................................................81
3.7.4
Mng phn t nh....................................................................................................82
3.8
Khai bo loi d liu bin...............................................................................................83
3.8.1
Gii thiu.................................................................................................................83
3.8.2
Integer......................................................................................................................83
3.8.3
Time.........................................................................................................................83
3.8.4
S thc (real) v thi gian thc (realtime)..............................................................84
3.9
Khai bo tham s............................................................................................................85
3.9.1
Gii thiu.................................................................................................................85
3.9.2
Tham s module (module parameter).......................................................................85
3.9.2.1 Parameter.......................................................................................................................85
3.9.2.1.1 Gii thiu.................................................................................................................85
3.9.2.1.2 Thay i gi tr ca tham s khai bo parameter......................................................86
3.9.2.1.2.1 Pht biu defparam............................................................................................86
3.9.2.1.2.2 Php gn gi tr tham s khi gi instance ca module.......................................87
3.9.2.1.3 S ph thuc tham s...............................................................................................92
3.9.2.2 Tham s cc b (local parameter).................................................................................92
3.9.3
Tham s c t (specify parameter)........................................................................92
3.10 Bi tp.............................................................................................................................94
4 Chng 4. Ton t, Ton hng v Biu thc.....................................................................95
4.1
Biu thc gi tr hng s.................................................................................................95
4.2
Ton t............................................................................................................................96
4.2.1
Ton t vi ton hng s thc.................................................................................96
4.2.2
Ton t u tin.........................................................................................................97
4.2.3
S dng s nguyn trong biu thc.........................................................................98
4.2.4
Th t tnh ton trong biu thc..............................................................................99
4.2.5
Ton t s hc (+, -, *, /, %, **, +, -)......................................................................99
4.2.6
Biu thc s hc vi tp thanh ghi (regs) v s nguyn (integer)........................101
4.2.7
Ton t quan h (>, <, >=, <=)..............................................................................102
4.2.8
Ton t so snh bng (==, !=, ===, !==)...............................................................103
4.2.9
Ton t logic (&&, ||, !).........................................................................................104
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4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
Ton t thao tc trn bit (&, |, ^, ~, ~^, ^~)...........................................................104

Ton t gim..........................................................................................................106
Ton t dch (>>, <<, >>>, <<<)...........................................................................107
Ton t iu kin (?:)............................................................................................108
Ton t ghp ni ({}) v Ton t lp ({{}}).........................................................109
4.2.14.1
4.2.14.2
Ton t ghp ni {}.................................................................................................109

Ton t lp {{}}.......................................................................................................110
4.3
Ton hng......................................................................................................................111
4.3.1
Vector bit-select v part-select addressing.............................................................111
4.3.2
a ch mng v phn t nh.................................................................................112
4.3.3
Chui......................................................................................................................114
4.3.3.1
4.3.3.2
4.3.3.3
Ton t chui................................................................................................................114
Gi tr chui m v vn tim n.............................................................................114
Chui rng...................................................................................................................115
4.4
Biu thc tr hon thi gian ti thiu, trung bnh, v ti a..........................................115
4.5
Biu thc di bit.......................................................................................................117
4.5.1
Qui lut cho biu thc di bit...........................................................................117
4.5.2
V d minh ha vn v biu thc di bit......................................................118
4.5.3
V d minh ha v biu thc t xc nh...............................................................119
4.6
Biu thc c du...........................................................................................................120
4.6.1
Qui nh cho nhng loi biu thc........................................................................120
4.6.2
Nhng bc nh gi mt biu thc......................................................................121
4.6.3
Nhng bc nh gi mt php gn......................................................................122
4.6.4
Tnh ton nhng biu thc ca hai s c du X v Z............................................122
4.7
Nhng php gn v php rt gn..................................................................................122
4.8
Bi tp...........................................................................................................................123
5 Chng 5. Cu trc phn cp v module.............................................................................124
5.1
Cu trc phn cp..........................................................................................................124
5.2
Module..........................................................................................................................124
5.2.1
Khai bo module....................................................................................................124
5.2.2
Module mc cao nht............................................................................................126
5.2.3
Gi v gn c tnh mt module (instantiate)........................................................126
5.2.4
Khai bo port.........................................................................................................129
5.2.4.1
5.2.4.2
5.2.4.3
5.2.4.4
5.2.4.5
5.2.4.6
5.2.4.7
5.2.4.8
5.2.4.9
5.2.4.10
5.2.4.11
nh ngha port............................................................................................................129
Lit k port...................................................................................................................130
Khai bo port trong thn module..................................................................................130
Khai bo port u module............................................................................................131
Kt ni cc port ca module c gi bng danh sch th t.......................................132
Kt ni cc port ca module c gi bng tn............................................................133
S thc trong kt ni port.............................................................................................134
Kt ni nhng port khng tng t nhau.....................................................................135
Nhng qui nh khi kt ni port...................................................................................135
Loi net to ra t vic kt ni port khng tng t nhau..........................................136
Kt ni nhng gi tr c du thng qua (port)..........................................................137
5.3
Bi tp...........................................................................................................................137
Chng 6. M hnh thit k cu trc (Structural model).....................................................138
6.1
Gii thiu......................................................................................................................138
6.2
Nhng linh kin c bn.................................................................................................138
6.2.1
Cng and, nand, or, nor, xor, xnor.........................................................................138
6.2.2
Cng buf v not.....................................................................................................139
6.2.3
Cng ba trng thi bufif1, bufif0, notif1, v notif0...............................................140
6.2.4
Cng tc MOS.......................................................................................................141
6.2.5
Cng tc truyn hai chiu......................................................................................142
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6.2.6
6.2.7
6.2.8
6.2.9
Cng tc CMOS.....................................................................................................143
Ngun pullup v pulldown....................................................................................144
M hnh mnh logic..........................................................................................145
mnh v gi tr ca nhng tn hiu kt hp.....................................................147
6.2.9.1
6.2.9.2
6.2.9.3
6.2.10
6.2.11
6.2.12
S kt hp gia nhng tn hiu c mnh r rng.....................................................147

mnh khng r rng: ngun v s kt hp..............................................................147
Tn hiu c mnh khng r rng v tn hiu c mnh r rng.............................153
S suy gim mnh bng nhng linh kin khng tr.........................................158

S suy gim mnh bng nhng linh kin tr....................................................158
mnh ca loi net.............................................................................................159
6.2.12.1
6.2.12.2
6.2.12.3
6.2.13
6.2.14
6.2.15
mnh ca net tri0, tri1........................................................................................159

mnh ca trireg..................................................................................................159
mnh ca net supply0, supply1...........................................................................159
tr hon cng (gate) v net...............................................................................159

tr hon min:typ:max........................................................................................161
phn r in tch ca net trireg........................................................................162
6.2.15.1
6.2.15.2
Qu trnh phn r in tch.......................................................................................162

c t tr hon ca thi gian phn r in tch.........................................................163
6.3
Nhng phn t c bn ngi dng t nh ngha (UDP).............................................164
6.3.1
nh ngha phn t c bn UDP............................................................................164
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
Tiu UDP................................................................................................................166
Khai bo cng (port) UDP...........................................................................................167
Khai bo khi to UDP tun t....................................................................................167
Bng khai bo UDP......................................................................................................167
Gi tr Z trong UDP.....................................................................................................168
Tng hp cc k hiu...................................................................................................168
6.3.2
UDP t hp............................................................................................................169
6.3.3
UDP tun t tch cc mc.....................................................................................170
6.3.4
UDP tun t tch cc cnh.....................................................................................171
6.3.5
Mch hn hp gia UDP mch tch cc mc v UDP tch cc cnh...................172
6.3.6
Gi s dng UDP...................................................................................................173
6.4
M t mch t hp v mch tun t s dng m hnh cu trc....................................174
6.4.1
M t mch t hp.................................................................................................174
6.4.2
M t mch tun t................................................................................................177
6.5
Bi tp...........................................................................................................................179
7 Chng 7. M hnh thit k hnh vi (Behavioral model)....................................................220
7.1
Khi qut.......................................................................................................................220
7.2
Php gn ni tip hay php gn lin tc - m hnh thit k RTL (continuous assignment)
220
7.2.1
Gii thiu...............................................................................................................220
7.2.2
Php gn ni tip khi khai bo net.........................................................................220
7.2.3
Pht biu php gn ni tip tng minh assign.....................................................221
7.2.4
To tr hon (delay) cho php gn....................................................................222
7.2.5
mnh php gn.................................................................................................223
7.3
Php gn qui trnh - m hnh thit k mc thut ton (procedural assignment)...224
7.3.1
Php gn khai bo bin..........................................................................................227
7.3.2
Php gn qui trnh kn (blocking assignment) '='..................................................228
7.3.2.1
7.3.3
7.3.3.1
Mch t hp vi php gn qui trnh kn.......................................................................228
Php gn qui trnh h (non-blocking assignment).................................................229

Mch tun t vi php gn qui trnh h.......................................................................233
7.4
Pht biu c iu kin...................................................................................................234
7.4.1
Cu trc if-else-if...................................................................................................235
7.5
Pht biu Case...............................................................................................................237
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7.5.1
Pht biu Case vi dont care............................................................................239
7.5.2
Pht biu case vi biu thc hng s.....................................................................240
7.6
Pht biu vng lp.........................................................................................................241
7.6.1
Cc pht biu lp...................................................................................................241
7.6.2
C php..................................................................................................................242
7.7
iu khin nh thi (procedural timing controls).......................................................244
7.7.1
iu khin tr hon (delay control)........................................................................244
7.7.2
iu khin s kin (event control)........................................................................245
7.7.3
Pht biu wait.....................................................................................................246
7.8
Pht biu khi................................................................................................................248
7.8.1
Khi tun t...........................................................................................................248
7.8.2
Khi song song (fork-join)....................................................................................249
7.8.3
Tn khi.................................................................................................................250
7.9
Cu trc qui trnh..........................................................................................................250
7.9.1
Cu trc initial.......................................................................................................251
7.9.2
Cu trc always......................................................................................................251
7.10 My trng thi (state machine).....................................................................................252
7.10.1 My trng thi Moore............................................................................................252
7.10.2 My trng thi Mealy.............................................................................................255
7.11 Bi tp...........................................................................................................................258
8 Chng 8. Tc v (task) v hm (function).....................................................................263
8.1
Phn bit gia tc v (task) v hm (function).............................................................263
8.2
Tc v v kch hot tc v............................................................................................264
8.2.1
nh ngha task......................................................................................................264
8.2.2
Khai bo task.........................................................................................................265
8.2.3
Kch hot tc v v truyn i s..........................................................................266
8.2.4
S dng b nh tc v v s kch hot ng thi.................................................270
8.3
Hm v vic gi hm....................................................................................................270
8.3.1
Khai bo hm.........................................................................................................270
8.3.2
Tr v mt gi tr t hm.......................................................................................273
8.3.3
Vic gi hm..........................................................................................................273
8.3.4
Nhng qui tc v hm............................................................................................273
8.3.5
S dng nhng hm hng s.................................................................................275
8.4
Bi tp...........................................................................................................................276
9 Chng 9. Kim tra thit k.............................................................................................277
9.1
Testbench......................................................................................................................277
9.1.1
Kim tra mch t hp............................................................................................278
9.1.2
Kim tra mch tun t...........................................................................................280
9.2
K thut to testbench....................................................................................................281
9.2.1
D liu kim tra.....................................................................................................282
9.2.2
iu khin m phng............................................................................................282
9.2.3
Thit lp gii hn d liu.......................................................................................283
9.2.4
Cung cp d liu ng b......................................................................................284
9.2.5
Tng tc testbench...............................................................................................285
9.2.6
To nhng khong thi gian ngu nhin...............................................................287
9.2.6.1.1
end.........................................................................................................................287
9.3
Kim tra thit k............................................................................................................288
9.4
K thut chn (assertion) dng kim tra thit k......................................................289
9.4.1
Li ch ca k thut chn kim tra........................................................................289
9.4.2
Th vin thit k m (OVL)..................................................................................290
9.4.3
S dng k thut chn gim st.............................................................................291
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9.5
Bi tp...........................................................................................................................293
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1 Chng 1. Dn nhp thit k h thng s vi Verilog

Khi kch thc v phc tp ca h thng thit k ngy cng tng, nhiu cng c h tr
thit k trn my tnh (CAD) c s dng vo qu trnh thit k phn cng. Thi k u, nhng
cng c m phng v to ra phn cng a ra phng php thit k, kim tra, phn tch, tng
hp v t ng to ra phn cng mt cch phc tp. S pht trin khng ngng ca nhng
cng c thit k mt cch t ng l do s pht trin ca nhng ngn ng m t phn cng
(HDLs) v nhng phng php thit k da trn nhng ngn ng ny. Da trn nhng ngn ng
m t phn cng (HDLs), nhng cng c CAD trong thit k h thng s c pht trin v
c nhng k s thit k phn cng s dng rng ri. Hin ti, ngi ta vn ang tip tc
nghin cu tm ra nhng ngn ng m t phn cng tt hn. Mt trong nhng ngn ng
m t phn cng c s dng rng ri nht l ngn ng Verilog HDL. Do c chp nhn
rng ri trong ngnh cng nghip thit k s, Verilog tr thnh mt kin thc c i hi
phi bit i vi nhng k s cng nh sinh vin lm vic v hc tp trong lnh vc phn cng
my tnh.
Chng ny s trnh by nhng cng c v mi trng lm vic c sn tng thch vi
ngn ng Verilog m mt k s thit k c th s dng trong qui trnh thit k t ng ca mnh
gip y nhanh tin thit k. u tin s trnh by tng bc v thit k phn cp, thit k
mc cao t vic m t thit k bng ngn ng Verilog n vic to ra phn cng ca thit k .
Nhng qui trnh v nhng t kha chuyn mn cng s c minh ha phn ny. K tip s
tho lun nhng cng c CAD hin c tng thch vi Verilog v chc nng ca n trong mi
trng thit k t ng. Phn cui cng ca chng ny s ni v mt s c tnh ca
Verilog khin n tr thnh mt ngn ng c nhiu k s thit k phn cng la chn.
1.1 Qui trnh thit k s

Trong thit k mt h thng s s dng mi trng thit k t ng, qui trnh thit k bt
u bng vic m t thit k ti nhiu mc tru tng khc nhau v kt thc bng vic to ra
danh sch cc linh kin cng nh cc ng kt ni gia cc linh kin vi nhau (netlist) cho
mt mch tch hp vi ng dng c th (ASIC), mch in (layout) cho mt mch tch hp theo
yu cu khch hng (custom IC), hoc mt chng trnh cho mt thit b logic c kh nng lp
trnh c (PLD). Hnh 1.1 m t tng bc trong qui trnh thit k ny.
Bc u ca thit k, mt thit k s c m t bi s hn hp gia m t mc
hnh vi (behavioural) Verilog, s dng nhng gi (module) thit k Verilog c thit k
sn, v vic gn h thng cc bus v wire lin kt cc gi thit k ny thnh mt h thng
hon chnh.
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K s thit k cng phi c trch nhim to ra d liu kim tra (testbench) xem thit k
ng chc nng hay cha cng nh dng kim tra thit k sau khi tng hp. Vic kim tra
thit k c th thc hin c bng vic m phng, chn nhng k thut kim tra, kim tra
thng thng hoc kt hp c ba phng php trn.
Sau bc kim tra nh gi thit k (bc ny c gi l kim tra tin tng hp
(presynthesis verification)), thit k s c tip tc bng vic tng hp to ra phn cng
thc s cho h thng thit k cui cng (ASIC, custom IC hay FPLD,). Nu h thng thit k
l ASIC, thit k s s c sn xut bi nh sn xut khc; nu l custom IC, thit k s c
sn xut trc tip; nu l FPLD, thit k s c np ln thit b lp trnh c.
Hnh 1.1 Lung thit k ASIC

Sau bc tng hp v trc khi phn cng thc s c to ra, mt qu trnh m phng
khc (hu tng hp (postsynthesis)) phi c thc hin. Vic m phng ny, ta c th s dng
testbench tng t testbench s dng trong m phng tin tng hp (presynthesis).
Bng phng php ny, m hnh thit k mc hnh vi v m hnh phn cng ca thit
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k c kim tra vi cng d liu ng vo. S khc nhau gia m phng tin tng hp v hu
tng hp l mc chi tit c th t c t mi loi m phng.
Nhng phn tip theo s m t t m v mi khi trong Hnh 1.1.
1.1.1
Dn nhp thit k
Bc u tin trong thit k h thng s l bc dn nhp thit k. Trong bc ny, thit k

c m t bng Verilog theo phong cch phn cp t cao xung thp (top-down). Mt thit
k hon chnh c th bao gm nhng linh kin mc cng hoc mc transistor, nhng khi
(module) phn cng c chc nng phc tp hn c m t mc hnh vi, hoc nhng linh
kin c lit k bi cu trc bus.
Do nhng thit k Verilog mc cao thng c m t mc m ti , n m t h
thng nhng thanh ghi v s truyn d liu gia nhng thanh ghi ny thng qua h thng bus, v
vy, vic m t h thng thit k mc ny c xem nh l mc truyn d liu gia cc
thanh ghi (RTL - Register Transfer Level). Mt thit k hon chnh c m t nh vy s to ra
c phn cng tng ng thc s r rng. Nhng cu trc thit k Verilog mc RTL s
dng nhng pht biu qui trnh (producedural statements), php gn lin tc (continuous
assignments), v nhng pht biu gi s dng cc khi (module) xy dng sn.
Nhng pht biu qui trnh Verilog (procedural statements) c dng m t mc hnh
vi mc cao. Mt h thng hoc mt linh kin c m t mc hnh vi th tng t vi
vic m t trong ngn ng phn mm. V d, chng ta c th m t mt linh kin bng vic
kim tra iu kin ng vo ca n, bt c hiu, ch cho n khi c s kin no xy ra,
quan st nhng tn hiu bt tay v to ra ng ra. M t h thng mt cch qui trnh nh vy, cu
trc if-else, case ca Verilog cng nh nhng ngn ng phn mm khc u s dng nh nhau.
Nhng php gn lin tc (continuous assignment) trong Verilog l nhng php gn cho vic
th hin chc nng nhng khi logic, nhng php gn bus, hoc m t vic kt ni gia h
thng bus v cc chn ng vo, ng ra. Kt hp vi nhng hm Boolean v nhng biu thc c
iu kin, nhng cu trc ngn ng ny c th c dng m t nhng linh kin v h thng
theo nhng php gn thanh ghi v bus ca chng.
Nhng pht biu gi s dng khi Verilog c thit k sn (instantiantion statements)
c dng cho nhng linh kin mc thp trong mt thit k mc cao hn. Thay v m
t mc hnh vi, chc nng, hoc bus ca mt h thng, chng ta c th m t mt h
thng bng Verilog bng cch kt ni nhng linh kin mc thp hn. Nhng linh kin ny
c th nh nh l mc cng hay transistor, hoc c th ln nh l mt b vi x l hon chnh.
1.1.2
Testbench trong Verilog
Mt h thng c thit k dng Verilog phi c m phng v kim tra xem thit k
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ng chc nng hay cha trc khi to ra phn cng. Trong qu trnh ny, nhng li thit k v
s khng tng thch gia nhng linh kin dng trong thit k c th c pht hin. Vic chy
m phng v kim tra mt thit k i hi phi to ra mt d liu ng vo kim tra v qu
trnh quan st kt qu sau khi chy m phng, d liu dng kim tra ny c gi l
testbench. Mt testbench s dng cu trc mc cao ca Verilog to ra d liu kim tra,
quan st p ng ng ra, v c vic kt ni gia nhng tn hiu trong thit k. Bn trong
testbench, h thng thit k cn chy m phng s c gi ra (instantiate) trong testbench. D
liu testbench cng vi h thng thit k s to ra mt m hnh m phng m s c s dng
bi mt cng c m phng Verilog.
1.1.3
nh gi thit k
Mt nhim v quan trng trong bt k thit k s no cng cn l nh gi thit k. nh

gi thit k l qu trnh m ngi thit k s kim tra thit k ca h c sai st no c th xy
ra trong sut qu trnh thit k hay khng. Mt sai st thit k c th xy ra do s m t thit k
m h, do sai st ca ngi thit k, hoc s dng khng ng nhng khi trong thit k. nh
gi thit k c th thc hin bng m phng, bng vic chn nhng k thut kim tra, hoc
kim tra thng thng.
1.1.3.1 M phng
Chy m phng dng trong vic nh gi thit k, c thc hin trc khi thit k c
tng hp. Bc chy m phng ny c hiu nh m phng mc hnh vi, mc RTL
hay tin tng hp. mc RTL, mt thit k bao gm xung thi gian clock nhng khng bao
gm tr hon thi gian trn cng v dy kt ni (wire). Chy m phng mc ny s chnh
xc theo xung clock. Thi gian ca vic chy m phng mc RTL l theo tn hiu xung
clock, khng quan tm n nhng vn nh: nguy him tim n c th khin thit k b li
(hazards, glitch), hin tng chy ua khng kim sot gia nhng tn hiu (race conditions),
nhng vi phm v thi gian setup v hold ca tn hiu ng vo, v nhng vn lin quan n
nh thi khc. u im ca vic m phng ny l tc chy m phng nhanh so vi chy m
phng mc cng hoc mc transistor.
Chy m phng cho mt thit k i hi d liu kim tra. Thng thng trong mi trng
m phng Verilog s cung cp nhiu phng php khc nhau a d liu kim tra ny
vo thit k kim tra. D liu kim tra c th c to ra bng ha, s dng nhng
cng c son tho dng sng, hoc bng testbench. Hnh 1.2 m t hai cch khc nhau nh
ngha d liu kim tra ng vo ca mt cng c m phng. Nhng ng ra ca cng c m
phng l nhng dng sng ng ra (c th quan st trc quan).
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Hnh 1.2. Hai cch khc nhau nh ngha d liu kim tra ng vo
chy m phng vi Verilog testbench, trong testbench s gi h thng thit k ra
kim tra, lc ny h thng thit k c xem nh l mt phn ca testbench, testbench s
cung cp d liu kim tra n ng vo ca h thng thit k. Hnh 1.3 m t mt on code ca
mt mch m, testbench ca n, cng nh kt qu chy m phng ca n di dng sng ng
ra. Quan st hnh ta thy vic chy m phng s nh gi chc nng ca mch m. Vi mi
xung clock th ng ra b m s tng ln 1. Ch rng, theo biu thi gian th ng ra b
m thay i ti cnh ln xung clock v khng c thi gian tr hon do cng cng nh tr hon
trn ng truyn. Kt qu chy m phng cho thy chc nng ca mch m l chnh xc m
khng cn quan tm n tn s xung clock.
Hin nhin, nhng linh kin phn cng thc s s c p ng khc nhau. Da trn nh
thi v thi gian tr hon ca nhng khi c s dng, thi gian t cnh ln xung clock
n ng ra ca b m s c tr hon khc khng. Hn na, nu tn s xung clock c cp
vo mch thc s qu nhanh so vi tc truyn tn hiu bn trong cc cng v transistor ca
thit k th ng ra ca thit k s khng th bit c.
Vic m phng ny khng cung cp chi tit v cc vn nh thi ca h thng thit k
c m phng. Do , nhng vn tim n v nh thi ca phn cng do tr hon trn cng
s khng th pht hin c. y l vn in hnh ca qu trnh m phng tin tng hp
hoc m phng mc hnh vi. iu bit c trong Hnh 1.3 l b m ca ta m s
nh phn. Thit k hot ng nhanh chm th no, hot ng c tn s no ch c th bit
c bng vic kim tra thit k sau tng hp.
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Hnh 1.3. M t mt on code ca mt mch flip-flop
1.1.3.2 K thut chn kim tra (assertion)

Thay v phi d theo kt qu m phng bng mt hay to nhng d liu kim tra testbench
phc tp, k thut chn thit b gim st c th c s dng kim tra tun t nhng c tnh
ca thit k trong sut qu trnh m phng. Thit b gim st c t bn trong h thng thit
k, c m phng bi ngi thit k. Ngi thit k s quyt nh xem chc nng ca thit k
ng hay sai, nhng iu kin no thit k cn phi tha mn. Nhng iu kin ny phi tun
theo nhng c tnh thit k, v thit b gim st c chn vo h thng thit k m bo
nhng c tnh ny khng b vi phm. Chui thit b gim st ny s sai nu mt c tnh no
c t vo bi ngi thit k b vi phm. N s cnh bo cho ngi thit k rng thit k
khng ng chc nng nh mong i. Th vin OVL (Open Verification Library) cung cp
mt chui nhng thit b gim st chn vo h thng thit k gim st nhng c tnh
thng thng ca thit k. Ngi thit k c th dng nhng k thut gim st ca ring mnh
chn vo thit k v dng chng kt hp vi testbench trong vic kim tra nh gi thit
k.
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1.1.3.3 Kim tra thng thng
Kim tra thng thng l qu trnh kim tra nhng c tnh bt k ca thit k. Khi mt
thit k hon thnh, ngi thit k s xy dng mt chui nhng c tnh tng ng vi hnh vi
ca thit k. Cng c kim tra thng thng s kim tra thit k m bo rng nhng c tnh
c m t p ng c tt c nhng iu kin. Nu c mt c tnh c pht hin l
khng p ng ng, c tnh c xem nh vi phm. c tnh bao ph (coverage) ch
ra bao nhiu phn trm c tnh ca thit k c kim tra.
1.1.4
Bin dch v tng hp thit k
Tng hp l qu trnh to ra phn cng t ng t mt m t thit k phn cng tng ng

r rng. Mt m t phn cng Verilog dng tng hp khng th bao gm tn hiu v m t
nh thi mc cng, hoc nhng cu trc ngn ng khc m khng dch sang nhng phng
trnh logic tun t hoc t hp. Hn th na, nhng m t phn cng Verilog dng cho
tng hp phi tun theo nhng phong cch vit code mt cch nht nh cho mch t hp
cng nh mch tun t. Nhng phong cch ny v cu trc Verilog tng ng ca chng
c nh ngha trong vic tng hp RTL.
Trong qui trnh thit k, sau khi mt thit k c m t hon thnh v kt qu m phng
tin tng hp ca n c kim tra bi ngi thit k, n phi c bin dch tin gn hn
n vic to thnh phn cng thc s trn silicon. Bc thit k ny i hi vic m t phn
cng ca thit k phi c ch ra, ngha l chng ta phi ch n mt ASIC c th, hoc mt
FPGA c th nh l thit b phn cng mc ch ca thit k. Khi thit b mc ch c ch
ra, nhng tp tin m t v cng ngh (technology files) ca phn cng (ASIC, FPGA, hoc
custom IC) s cung cp chi tit nhng thng tin v nh thi v m t chc nng cho qu
trnh bin dch. Qu trnh bin dch s chuyn i nhng phn khc nhau ca thit k ra
mt nh dng trung gian (bc phn tch), kt ni tt c cc phn li vi nhau, to ra mc logic
tng ng (bc tng hp), sp xp v kt ni (place and route) nhng linh kin trong thit b
phn cng mc ch li vi nhau thc hin chc nng nh thit k mong mun v to ra
thng tin chi tit v nh thi trong thit k.
Hnh 1.4 m t qu trnh bin dch v m t hnh nh kt qu ng ra ca mi bc bin dch.
Nh trn hnh, ng vo ca bc ny l mt m t phn cng bao gm nhng mc m t
khc nhau ca Verilog, v kt qu ng ra ca n l mt phn cng chi tit cho thit b phn
cng mc ch nh FPLD hay sn xut chip ASIC.
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Hnh 1.4. M t qu trnh bin dch v m t hnh nh kt qu ng ra
1.1.4.1 Phn tch

Mt thit k hon chnh c m t dng Verilog c th bao gm m t nhiu mc
khc nhau nh mc hnh vi, h thng bus v dy kt ni vi nhng linh kin Verilog khc.
Trc khi mt thit k hon chnh to ra phn cng, thit k phi c phn tch v to ra mt
nh dng ng nht cho tt c cc phn trong thit k. Bc ny cng kim tra c php v ng
ngha ca m ng vo Verilog.
1.1.4.2 To phn cng

Sau khi to c mt d liu thit k c nh dng ng nht cho tt c cc linh kin trong
thit k, bc tng hp s bt u bng chuyn i d liu thit k trn sang nhng nh
dng phn cng thng thng nh mt chui nhng biu thc Boolean hay mt netlist nhng
cng c bn.
1.1.4.3 Ti u logic
Bc k tip ca qu trnh tng hp, sau khi mt thit k c chuyn i sang mt
chui nhng biu thc Boolean, bc ti u logic c thc hin. Bc ny nhm mc ch
lm gim nhng biu thc vi ng vo khng i, loi b nhng biu thc lp li, ti thiu hai
mc, ti thiu nhiu mc. y l qu trnh tnh ton rt hao tn thi gian v cng sc, mt s
cng c cho php ngi thit k quyt nh mc ti u. Kt qu ng ra ca bc ny cng
di dng nhng biu thc Boolean, m t logic di dng bng, hoc netlist gm nhng cng
c bn.
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1.1.4.4 Binding
Sau bc ti u logic, qu trnh tng hp s dng thng tin t thit b phn cng mc ch
quyt nh chnh xc linh kin logic no v thit b no cn hin thc mch thit k. Qu
trnh ny c gi l binding v kt qu ng ra ca n c ch nh c th s dng cho FPLD,
ASIC, hay custom IC.
1.1.4.5 Sp xp cell v i dy kt ni
Bc sp xp v i dy kt ni s quyt nh vic t v tr ca cc linh kin trn thit b
phn cng mc ch. Vic kt ni cc ng vo v ng ra ca nhng linh kin ny dng h
thng dy lin kt v vng chuyn mch trn thit b phn cng mc ch, c quyt nh
bi bc sp xp cell v i dy kt ni ny. Kt qu ng ra ca bc ny c a ti thit b
phn cng mc ch, nh np ln FPLD, hay dng sn xut ASIC.
Mt v d minh ha v qu trnh tng hp c ch ra trn Hnh 1.5. Trong hnh ny, mch
m c dng chy m phng trong Hnh 1 . 3 c tng hp. Ngoi vic m t phn
cng thit k dng Verilog, cng c tng hp i hi nhng thng tin m t thit b phn cng
mc ch tin hnh qu trnh tng hp ca mnh. Kt qu ng ra ca cng c tng hp l
danh sch cc cng, cc flip-flop c sn trong thit b phn cng ch v h thng dy kt ni
gia chng. Hnh 1.5 cng ch ra mt kt qu ng ra mang tnh trc quan c to ra t ng
bng cng c tng hp ca Altera Quartus II.
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Hnh 1.5. Minh ha v qu trnh tng hp
1.1.5
M phng sau khi tng hp thit k
Sau khi qu trnh tng hp hon thnh, cng c tng hp s to ra mt netlist hon chnh
cha nhng linh kin ca thit b phn cng ch v cc gi tr nh thi ca n. Nhng thng
tin chi tit v cc cng c dng hin thc thit k cng c m t trong netlist ny.
Netlist ny cng bao gm nhng thng tin v tr hon trn ng dy v nhng tc ng ca
ti ln cc cng dng trong qu trnh hu tng hp. C nhiu nh dng netlist ng ra c th
c to ra bao gm c nh dng Verilog. Mt netlist nh vy c th c dng m phng,
v m phng ny c gi l m phng hu tng hp. Nhng vn v nh thi, v tn s
xung clock, v hin tng chy ua khng kim sot, nhng nguy him tim n ca thit k ch
c th kim tra bng m phng hu tng hp thc hin sau khi thit k c tng hp. Nh trn
Hnh 1.1, ta c th s dng d liu kim tra m dng cho qu trnh m phng tin tng hp
dng cho qu trnh m phng hu tng hp.
Do tr hon trn ng dy v cc cng, p ng ca thit k sau khi chy m phng
hu tng hp s khc vi p ng ca thit k m ngi thit k mong mun. Trong
trng hp ny, ngi thit k phi sa li thit k v c gng trnh nhng sai st v nh thi
v hin tng chy ua gia nhng tn hiu khng th kim sot.
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1.1.6
Phn tch thi gian
Quan st trn Hnh 1.1, bc phn tch thi gian l mt phn trong qu trnh bin dch, hoc
trong mt s cng c th bc phn tch thi gian ny c thc hin sau qu trnh bin dch.
Bc ny s to ra kh nng xu nht v tr hon, tc xung clock, tr hon t
cng ny n cng khc, cng nh thi gian cho vic thit lp v gi tn hiu.
Kt qu ca bc phn tch thi gian c th hin di dng bng hoc biu . Ngi
thit k s dng nhng thng tin ny xc nh tc xung clock, hay ni cch khc l xc
nh tc hot ng ca mch thit k.
1.1.7
To linh kin phn cng
Bc cui cng trong qui trnh thit k t ng da trn Verilog l to ra phn cng
thc s cho thit k. Bc ny c th to ra mt netlist dng sn xut ASIC, mt chng
trnh np vo FPLD, hay mt mch in cho mch IC.
1.2 Ngn ng m t phn cng Verilog (Verilog HDL)

Trong phn trc, ta trnh by tng bc thit k mc RTL t mt m t thit k
Verilog cho n vic hin thc ra mt phn cng thc s. Qui trnh thit k ny ch c th thc
hin c khi ngn ng Verilog c th hiu c bi ngi thit k h thng, ngi thit k
mc RTL, ngi kim tra, cng c m phng, cng c tng hp, v cc my mc lin quan.
Bi v tm quan trng ca n trong qui trnh thit k, Verilog tr thnh mt chun quc t
IEEE. Chun ny c s dng bi ngi thit k cng nh ngi xy dng cng c thit k.
1.2.1
Qu trnh pht trin Verilog
Verilog c ra i vo u nm 1984 bi Gateway Design Automation. Khi u, ngn

ng u tin c dng nh l mt cng c m phng v kim tra. Sau thi gian u, ngn
ng ny c chp nhn bi ngnh cng nghip in t, bi cc cng c m phng v cng c
phn tch thi gian, sau ny vo nm 1987, cng c tng hp c xy dng v pht trin
da vo ngn ng ny. Gateway Design Automation v nhng cng c da trn Verilog ca
hng sau ny c mua bi Cadence Design System. T sau , Cadence ng vai tr ht sc
quan trng trong vic pht trin cng nh ph bin ngn ng m t phn cng Verilog.
Vo nm 1987, mt ngn ng m t phn cng khc l VHDL tr thnh mt chun ngn
ng m t phn cng ca IEEE. Bi do s h tr ca B quc phng (DoD), VHDL c s
dng nhiu trong nhng d n ln ca chnh ph M. Trong n lc ph bin Verilog, vo nm
1990, OVI (Open Verilog International) c thnh lp v nh , Verilog chim u th trong
lnh vc cng nghip. iu ny to ra mt s quan tm kh ln t ngi dng v cc nh
cung cp EDA (Electronic Design Automation) ti Verilog.
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Vo nm 1993, nhng n lc nhm chun ha ngn ng Verilog c bt u.
Verilog tr thnh chun IEEE, IEEE Std 1364-1995 vo nm 1995. Vi nhng cng c m
phng, cng c tng hp, cng c phn tch thi gian, v nhng cng c thit k da trn
Verilog c sn, chun Verilog IEEE ny nhanh chng c chp nhn su rng trong cng
ng thit k in t.
Mt phin bn mi ca Verilog c chp nhn bi IEEE vo nm 2001. Phin bn mi
ny c xem nh chun Verilog-2001 v c dng bi hu ht ngi s dng cng nh
ngi pht trin cng c. Nhng c im mi trong phin bn mi l n cho php bn
ngoi c kh nng c v ghi d liu, qun l th vin, xy dng cu hnh thit k, h tr nhng
cu trc c mc tru tng cao hn, nhng cu trc m t s lp li, cng nh thm mt s
c tnh vo phin bn ny. Qu trnh ci tin chun ny vn ang c tip tc vi s ti tr
ca IEEE.
1.2.2
Nhng c tnh ca Verilog
Verilog l mt ngn ng m t phn cng dng c t phn cng t mc transistor n

mc hnh vi. Ngn ng ny h tr nhng cu trc nh thi cho vic m phng nh thi
mc chuyn mch v tc thi, n cng c kh nng m t phn cng ti mc thut
ton tru tng. Mt m t thit k Verilog c th bao gm s trn ln gia nhng khi
(module) c mc tru tng khc nhau vi s khc nhau v mc chi tit.
1.2.2.1 Mc chuyn mch

Nhng c im ca ngn ng ny khin n tr nn l tng trong vic m hnh ha v m
phng mc chuyn mch, bao gm kh nng chuyn mch mt chiu cng nh hai chiu,
vi nhng thng s v tr hon v lu tr in tch. Nhng tr hon mch in c th c
m hnh ha nh l tr hon ng truyn, tr hon t thp ln cao hay t cao xung thp. c
im lu tr in tch mc tru tng trong Verilog khin n c kh nng m t nhng
mch in vi linh kin ng nh l CMOS hay MOS.
1.2.2.2 Mc cng
Nhng cng c bn vi nhng thng s c nh ngha trc s cung cp mt kh nng
thun tin trong vic th hin netlist v m phng mc cng. i vi vic m phng mc
cng vi mc ch chi tit v c bit, nhng linh kin cng c th c nh ngha
mc hnh vi. Verilog cng cung cp nhng cng c cho vic nh ngha nhng phn t
c bn vi nhng chc nng c bit. Mt h thng s logic 4 gi tr n gin (0,1,x,z) c s
dng trong Verilog th hin gi tr cho tn hiu. Tuy nhin, m hnh mc logic chnh xc
hn, nhng tn hiu Verilog gm 16 mc gi tr v mnh c thm vo 4 gi tr n gin
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trn.
1.2.2.3 tr hon gia pin n pin

Mt tin ch trong vic m t nh thi cho cc linh kin ti ng vo v ng ra cng c
cung cp trong Verilog. Tin ch ny c th c dng truy vn li thng tin v nh thi
trong m t tin thit k ban u. Hn na, tin ch ny cng cho php ngi vit m hnh ha
tinh chnh hnh vi nh thi ca m hnh da trn hin thc phn cng.
1.2.2.4 M t Bus
Nhng tin ch v m hnh bus v thanh ghi cng c cung cp bi Verilog. i vi nhiu
cu trc bus khc nhau, Verilog h tr chc nng phn gii bus v wire vi h thng logic 4 gi
tr (0,1,x,z). Vi s kt hp gia chc nng bus logic v chc nng phn gii, n cho php m
hnh ha c hu ht cc loi bus. i vi vic m hnh ha thanh ghi, vic m t xung clock
mc cao v nhng cu trc iu khin nh thi, c th c s dng m t thanh ghi vi
nhng tn hiu xung clock v tn hiu reset khc nhau.
1.2.2.5 Mc hnh vi
Nhng khi qui trnh (procedural blocks) ca Verilog cho php m t thut ton ca
nhng cu trc phn cng. Nhng cu trc ny tng t vi ngn ng lp trnh phn mm
nhng c kh nng m t phn cng.
1.2.2.6 Nhng tin ch h thng

Nhng tc v h thng trong Verilog cung cp cho ngi thit k nhng cng c trong vic
to ra d liu kim tra testbench, tp tin truy xut c, ghi, x l d liu, to d liu, v m
hnh ha nhng phn cng chuyn dng. Nhng tin ch h thng dng cho b nh c
v thit b logic lp trnh c (PLA) cung cp nhng phng php thun tin cho vic m
hnh ha nhng thit b ny. Nhng tc v hin th v I/O c th c s dng kim sot tt
c nhng ng vo v ng ra d liu ca ng dng v m phng. Verilog cho php vic truy
xut c v ghi ngu nhin n cc tp tin.
1.2.2.7 PLI
Cng c tng tc ngn ng lp trnh (PLI) ca Verilog cung cp mt mi trng cho
vic truy xut cu trc d liu Verilog, s dng mt th vin cha cc hm ca ngn ng C.
1.2.3
S lc v Verilog
Ngn ng Verilog HDL p ng tt c nhng yu cu cho vic thit k v tng hp nhng

h thng s. Ngn ng ny h tr vic m t cu trc phn cp ca phn cng t mc h
thng n mc cng hoc n c mc cng tc chuyn mch. Verilog cng h tr mnh tt
c cc mc m t vic nh thi v pht hin li. Vic nh thi v ng b m c i
[Type text]
Page 22

hi bi phn cng s c ch trng mt cch c bit.
Trong Verilog, mt linh kin phn cng c m t bi mt cu trc ngn ng gi l
module. S m t mt module s m t danh sch nhng ng vo v ng ra ca linh kin cng
nh nhng thanh ghi v h thng bus bn trong linh kin. Bn trong mt module, nhng
php gn ng thi, gi s dng linh kin v nhng khi qui trnh c th c dng m t
mt linh kin phn cng.
Nhiu module c th c gi mt cch phn cp hnh thnh nhng cu trc phn cng
khc nhau. Nhng phn t con ca vic m t thit k phn cp c th l nhng module, nhng
linh kin c bn hoc nhng linh kin do ngi dng t nh ngha. m phng cho thit k,
nhng phn t con trong cu trc phn cp ny nn c tng hp mt cch ring l.
Hin nay c rt nhiu cng c v mi trng da trn Verilog cung cp kh nng chy m
phng, kim tra thit k v tng hp thit k. Mi trng m phng cung cp nhng chng
trnh giao din ha cho bc thit k trc layout (front-end), nhng cng c to dng sng
v cng c hin th. Nhng cng c tng hp da trn nn tng ca Verilog v khi tng hp mt
thit k th thit b phn cng ch nh FPGA hoc ASIC cn phi c xc nh trc.
1.3 Tng kt
Phn ny cung cp mt ci nhn tng quan v nhng c ch, nhng cng c v
nhng qui trnh dng trong vic m t mt thit k t bc thit k n qu trnh hin thc phn
cng. Phn ny cng ni s lc v thng tin kin thc m ta s i su trong cc phn sau. Bn
cnh , n cng cung cp n ngi c lch s pht trin ca Verilog. Cng vi vic pht
trin chun Verilog HDL ny l s pht trin khng ngng ca cc cng ty nghin cu, xy
dng v hon thin cc cng c h tr i km, kt qu l to ra nhng cng c tt hn v nhng
mi trng thit k ng b hn.
1.4 Bi tp
1. Verilog l g ? Ti sao ta phi s dng ngn ng m t phn cng Verilog trong thit k
Chip?
2. Tm hiu mi trng thit k trn FPGA l QuartusII ca Altera v tm hiu mi trng
m phng, mi trng tng hp ca n. Hy lin tng, so snh mi trng thit k ny vi
mi trng m phng v tng hp c trnh by trong phn ny.
3. Nu s khc bit gia ngn ng m t phn cng ni chung (ngn ng Verilog HDL ni
ring) v ngn ng lp trnh ni chung (ngn ng C ni ring)?
4. Tm hiu s khc bit gia hai loi ngn ng m t phn cng Verilog HDL v
VHDL?
5. Qu trnh tng hp (synthesis) l g?
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Page 23

6. Verilog HDL c th c s dng m t mch tng t (analog) trong phn cng
khng ?
7. Tm kim 3 cng c m phng Verilog HDL h tr min ph.
8. Tm kim 3 ti liu h tr vic hc v nghin cu Verilog HDL.
9. Tm kim 3 website h tr vic hc v nghin cu Verilog HDL.
10. Tm kim cc cng ty thit k chip Vit Nam ang s dng Verilog HDL trong vic thit
k?
11. Tm hiu v s dng thnh tho hai cng c m phng QuartusII v ModelSim?
[Type text]
Page 24
2 Chng 2.
Qui c v t kha
2.1 Khong trng

Khong trng trong Verilog l nhng k t c bit gm c: k t du cch (Space), k t tab
(Tab) v k t xung dng (Enter). Nhng k t ny c th c b qua tr khi n c s dng
tch bit vi nhng k t c bit mang ngha khc. Tuy nhin, k t khong trng v
k t tab l nhng k t bnh thng trong xu v khng b b qua (xem trong Mc 2.5).
2.2 Ch thch
Ngn ng Verilog HDL c hai cch to ch thch:
Ch thch mt dng: bt u bng hai k t // cho n cui dng.
Ch thch mt khi: bt u bng hai k t /* v kt thc bng hai k t */.
Ch thch mt khi khng nn qu ri rm, khng c c s lng nhau gia nhng ch
thch khi, nhng c php lng ch thch 1 dng trong ch thch khi (trong ch thch khi th
hai k t // khng mang ngha g c bit c).
V d:
x = y && y; // y l ch thch mt dng
/* y l ch thch
nhiu dng */
/* y l /* ch thch */ khng hp l */
/* y l //ch thch hp l */
2.3 Ton t
Nhng ton t nh chui k t n, kp hay gm ba k t c dng trong nhng biu thc.
Trong phn tho lun v biu thc (Chng 4) ta s trnh by v cch s dng cc ton t trong
biu thc nh th no.
Nhng ton t n thng xut hin bn tri ca ton hng ca chng (--i). Nhng
ton t kp thng xut hin gia nhng ton hng ca chng (a & b). Ton t c iu kin
thng c hai ton t k t c phn bit bi ba ton hng ( (m>n) ? m : n ).
2.4 S hc
Hng s c m t nh l hng s nguyn hoc hng s thc.
V d 2.1
[Type text] Page 25

243
// s thp phn 243
1.4E9
// s thc 1.4x10
-5d18
// s thp phn -18 lu trong 5 bit
4b1011
// s nh phn 1011 lu trong 4 bit
8hEF
// s thp lc phn EF lu trong 8 bit
16o56
// s bt phn 56 lu trong 16 bit
4bxxxx
// s nh phn ty nh lu trong 4 bit
4bzzzz
// s nh phn 4 bit c gi tr tng tr cao
2.4.1
Hng s nguyn
Hng s nguyn c th c m t theo nh dng s thp phn, thp lc phn, bt phn v

nh phn. C hai dng biu din hng s nguyn:
Dng th nht l mt s thp phn n gin, n c th l mt chui k t t 0 n 9 v
c th bt u vi ton t n cng ( + ) hoc tr (-).
V d:
374
// s thp phn khng du 374
+374
// s thp phn c du +374
-374
// s thp phn c du -374
Dng th hai c m t di dng hng c s, n gm ba thnh phn:
Thnh phn u tin: rng hng s, m t rng l s bit cha hng s. N
c m t nh l mt s thp phn khng du khc khng. V d, rng ca hai s

hexadecimal l 8 bit bi v mi mt s hexadecimal cn 4 bit cha, thnh phn ny c th
c hoc khng. V d:
20h 473FF // s thp lc phn c rng 20 bit
o7439
// s bt phn
Thnh phn th hai: nh dng c s, bao gm mt k t (c th l k t thng hoc
k t hoa) m t c s ca s , ta c th thm vo hoc khng thm vo pha trc n

k t s (hoc S) ch rng n l mt s c du, tip tc pha trc n l mt k t mc
n. Nhng k t m t c s c dng c th l:
d, D : H thp phn
h, H : H lc phn
o, O : H bt phn
b, B : H nh phn
[Type text] Page 26

K t mc n l bt buc phi c khi s dng k t m t c s, gia k t v k t nh
dng c s khng c cch nhau bi bt k khong trng no. V d:
5EB
// khng hp l (s thp lc phn i hi h), ng l 5hEB
10o567
// khng hp l (thiu du ), ng l 10o567
8 b 1001
// khng hp l (gia v b c khong trng), ng l 4b1001
Thnh phn th ba, l mt s khng du, bao gm nhng k t ph hp vi c s
c m t trong thnh phn th hai. Thnh phn s khng du ny c th theo sau ngay
thnh phn c s hoc c th theo sau thnh phn c s bi mt khong trng. Nhng k t
t a n f ca s thp lc phn c th l k t thng hoc k t hoa.
V d 2.3 Hng s c rng bit
4b1011
// s nh phn 4 bit
5 D 5
// s thp phn 5 bit
3B10x
// s nh phn 3 bit vi bit c trng s thp nht c gi tr khng xc nh
12hx
// s thp lc phn 12 bit c gi tr khng xc nh
16Hz
// s thp lc phn 16 bit c gi tr tng tr cao.
Nhng s thp phn n gin khng km theo rng bit v nh dng c s c xem nh
l nhng s nguyn c du.
Nhng s c m t bi nh dng c s c xem nh nhng s nguyn c du khi thnh
phn ch nh s (hoc S) c km thm vo, hoc n s c xem nh nhng s nguyn
khng du khi ch c thnh phn nh dng c s c s dng. Thnh phn ch nh s
c du s (hoc S) khng nh hng n mu bit c m t m n ch nh hng trong qu
trnh bin dch.
Ton t cng hay tr ng trc hng s rng l mt ton t n cng (+) hay tr (-), hai
ton t ny nu c t nm gia thnh phn nh dng c s v s l khng ng c php.
Nhng s m c biu din di dng b hai.
V d 2.4 S dng du vi hng s
6 d -7
// c php khng ng
-6 d 7
// s b 2 ca 7, tng ng vi (6d 7)
4 shf
// s c du (s b 2) 4 bit 1111, bng -1, tng ng vi 4h1
-4 sd15
// tng ng vi (4sd15), hay (-1) = 1 = 0001
8sd?
// tng ng 8sbz
Cc gi tr s c bit x v z:
Mt s x dng biu din mt gi tr khng xc nh trong nhng hng s thp lc
[Type text] Page 27

phn, hng s bt phn v hng s nh phn.
Mt s z dng biu din mt s c gi tr tng tr cao.
Mt s x c th c thit lp trn 4 bit biu din mt s thp lc phn, trn 3 bit biu
din mt s bt phn, trn 1 bit biu din mt s nh phn c gi tr khng xc nh.
Tng t, mt s z c th c thit lp trn 4 bit biu din mt s thp lc phn, trn 3
bit biu din mt s bt phn, trn 1 bit biu din mt s nh phn c gi tr tng tr cao.
V d 2.5 T ng thm vo bn tri
reg [11:0] m, n, p, q; // m, n, p, q u c 12 bit
initial begin
m = h x;
// to ra xxx
n = h 4x;
// to ra 04x
p = h z5;
// to ra zz5
q = h 0z8;
// to ra 0z8
end
reg [15:0] e, f, g;
// e, f, g u c 16 bit
e = h4;
// to ra {13{1b0}, 3b100}
f = hx
// to ra {16{1hx}}
g = hz;
// to ra {16{1hz}}
Nu rng bit ca s khng du nh hn rng c m t trong phn m t hng s th

s khng du s c thm vo bn tri n l cc s 0. Nu bt ngoi cng bn tri trong s
khng du l x hoc z th mt x hoc mt z s c dng thm vo bn tri mt cch
tng ng. Nu rng ca s khng du ln hn rng c m t trong phn m t hng
s th s khng du s b ct xn i t bn tri.
S bit dng to nn mt s khng c rng (c th l mt s thp phn n gin hoc
mt s khng m t rng bit) nn t nht l 32 bit. Nhng hng s khng du, khng rng
m bit c trng s cao l khng xc nh (x) hoc tng tr cao (z) th n s c m rng ra n
rng ca biu thc cha hng s. Gi tr x v z m t gi tr ca mt s c th l ch hoa
hoc ch thng.
Khi c s dng m t mt s trong Verilog, th k t du chm hi (?) c ngha thay
th cho k t z. N cng thit lp 4 bit ln gi tr tng tr cao cho s thp lc phn, 3 bit cho
s bt phn v 1 bit cho s nh phn. Du chm hi c th c dng gip vic c code d
hiu hn trong trng hp gi tr tng tr cao l mt iu kin khng quan tm (dont
care). Ta s tho lun r hn v vn ny khi trnh by v casez v casex. K t du chm hi
[Type text] Page 28

cng c dng trong nhng bng trng thi do ngi dng t nh ngha.
Trong mt hng s thp phn, s khng du khng bao gm nhng k t x, z hoc ? tr
trng hp ch c ng mt k t ch ra rng mi bit trong hng s thp phn l x hoc
z.
K t gch di ( _ ) c th dng bt k ni u trong mt s, ngoi tr k t u tin. K
t gch di s c b qua. c tnh ny c th c dng tch mt s qu di gip vic
c code d dng hn.
V d 2.6 S dng du gch di trong m t s
27_195_000
16b0011_0101_0001_1111
32 h 12ab_f001
Nhng hng s m c rng bit v nhng hng s c du c rng bit l nhng s c
du m rng khi n c gn n mt loi d liu l reg bt chp bn thn reg ny c du hay
khng.
di mc nh ca x v z ging nh di mc nh ca mt s nguyn.
2.4.2
Hng s thc
Nhng s hng s thc c th c biu din nh c m t bi chun IEEE 754-1985,

mt chun IEEE cho nhng s du chm ng c chnh xc kp.
Nhng s thc c th c m t bng mt trong hai cch, mt l theo dng thp phn
6
(v d, 25.13), hai l theo cch vit hn lm (v d, 45e6, c ngha l 45 nhn vi 10 ).
Nhng s thc c biu din vi du chm thp phn s c t nht mt k s mi bn
ca du chm thp phn.
V d 2.7
2.5
1543.34592
3.2E23 or 3.2e23
5.6e-3
0.9e-0
45E13
43E-6
354.156_972_e-19 (du gch di c b qua)
Nhng dng s sau khng ng l s thc v chng khng c t nht mt k s mi bn ca
du chm thp phn.
[Type text] Page 29

.43
8.
7.E4
.6e-9
2.4.3
S o
S thc c th bin i sang s nguyn bng cch lm trn s thc n s nguyn gn nht
thay v ct xn s bit ca n. Bin i khng tng minh c th thc hin khi mt s thc c
gn n mt s nguyn. Nhng ci ui nn c lm trn khc 0.
V d:
Hai s thc 48.8 v 48.5 u tr thnh 49 khi c bin i sang s nguyn, v s 48.3
s tr thnh 48.
Bin i s thc -5.5 sang s nguyn s c -6, bin i s 5.5 sang s nguyn s c
6.
2.5 Chui
Mt chui l mt dy cc k t c nm trong hai du nhy kp() v c ghi trn mt
dng n. Nhng chui c dng nh l nhng ton hng trong biu thc v trong nhng
php gn c xem nh l nhng hng s nguyn khng du v c biu din bi mt
dy k t 8 bit ASCII. Mt k t ASCII biu din bng 8 bit.
2.5.1.1 Khai bo bin chui

Bin chui l bin c loi d liu l reg vi rng bng vi s k t trong chui nhn vi
8.
V d 2.8
/* lu tr mt chui 12 k t Verilog HDL! i hi mt reg c rng 8*12, hoc 96
bit */
reg [8*12:1] stringvar;
initial begin
stringvar = Verilog HDL!;
end
2.5.1.2 X l chui
Chui c th c x l bng vic s dng cc ton t Verilog HDL. Gi tr m c x l
bi ton t l mt dy gi tr 8 bit ASCII. Cc ton t x l chui c th hin chi tit hn
trong phn 4.3.3.
[Type text] Page 30

2.5.1.3 Nhng k t c bit trong chui
Mt s k t ch c s dng trong chui khi ng trc n l mt k t m u, gi l k
t escape \. Bng bn di lit k nhng k t ny v ngha ca n.
Bng 2.1 K t c bit trong chui
Chui escape
K t to bi chui escape
\n
K t xung dng
\t
K t tab
\\
K t \
K t
\ddd
Mt k t c m t trong 1-3 k s bt phn (0 d 7)

Nu t hn ba k t c s dng, k t theo sau khng th l mt k s
bt phn. Vic thc thi c th dn n li nu k t c biu din ln
hn 377
2.6 nh danh, t kha v tn h thng

nh danh (indentifier) c dng gn cho mt i tng (object) mt tn duy nht n
c th c gi ti khi cn. nh danh c th l mt nh danh n gin hoc mt nh danh
escaped. Mt nh danh n gin c th l mt dy bt k gm cc k t, k s, du dollar ($),
v k t gch di (_).
K t u tin ca mt nh danh khng th l mt k s hay $; n c th l mt k t ch
ci hoc mt du gch di. nh danh s l khc nhau gia ch thng v ch hoa nh trong
ngn ng lp trnh C.
V d 2.9
kiemtra_e
net _m
fault_result
string_ab
_wire1
n$983
y c s gii hn v di ca nh danh, nhng gii hn ny t nht l 1024 k t. Nu
mt nh danh vt ra khi gii hn v chiu di c xc nh th li c th c thng bo
ra.
2.6.1
nh danh vi k t \
Tn nh danh escaped c bt u vi k t gch cho (\) v kt thc bi khong trng (k

t khong trng, k t tab, k t xung dng). Chng cung cp cch thc chn thm nhng k
[Type text] Page 31

t ASCII c th in c vo trong cc k t c code t 33 n 126, hoc gi tr thp lc phn t
21 n 7E).
C hai k t gch cho (\) v k t khong trng kt thc u khng c xem nh l thnh
phn ca tn nhn dng. Do , mt nh danh \abc s c x l ging nh nh danh abc.
V d 2.10
\net c+num
\-signal
\***fault-result***
\wirea/\wireb
\{m,n}
\i*(k+l)
Mt t kha trong Verilog HDL m ng trc n l mt k t escape s khng c
bin dch nh l mt t kha.
2.6.2
Tc v h thng v hm h thng
Du dollar ($) m u mt cu trc ngn ng s cho php pht trin nhng tc v h thng
v hm h thng do ngi dng nh ngha. Nhng cu trc h thng khng phi l ngn ng
thit k, m n mun ni n chc nng m phng. Mt tn theo sau du $ c bin dch
nh l mt tc v h thng hoc hm h thng.
Tc v h thng/hm h thng c th c nh ngha trong ba vi tr:
Mt tp hp chun nhng tc v h thng v hm h thng.
Nhng tc v h thng v hm h thng thm vo c nh ngha dng cho PLI
(Programming Language Interface).
Nhng tc v h thng v hm h thng thm vo c nh ngha bi phn mm thc
thi.
V d 2.11
$time
tr v thi gian chy m phng hin ti
$display
tng t nh hm printf trong C
$stop
ngng chy m phng
$finish
hon thnh chy m phng
$monitor
gim st chy m phng
2.7 Bi tp
1. Nu tc dng v s khc bit gia hai hm h thng $monitor v $display khi s
dng hai hm h thng ny trong qu trnh m phng?
[Type text] Page 32

2.
Lm sao c th c v ghi mt file d liu trong m t phn cng Verilog HDL (gi s
file cha ni dung b nh khi to)?
3. Hy tm thm 10 tc v h thng v nu ngha ca chng?
[Type text] Page 33
3 Chng 3.
Loi d liu trong Verilog
3.1 Khi qut

Verilog ch h tr nhng loi d liu c nh ngha trc. Nhng loi d liu ny
bao gm d liu bit, mng bit, vng nh, s nguyn, s thc, s kin, v mnh ca
d liu. Nhng loi ny nh ngha trong phn ln m t ca Verilog.
Verilog ch yu x l trn bit v byte khi m t mch in t. Loi s thc th hu dng
trong vic m t tr hon v nh thi, n cng rt hu dng trong vic m hnh ha
mc cao nh l phn tch xc sut kt ni mch trong h thng v nhng gii thut x l tn
hiu s.
Loi d liu phn cng bao gm net v reg. Thng thng nhng loi ny c th c xem
nh l dy kt ni v thanh ghi. D liu net c th c khai bo chi tit hn to ra nhng
loi d liu khc nh tri-stated hay non-tri-stated v ph thuc vo cc x l nhiu kt ni s to
ra nhng php and, or hoc dng gi tr trc .
Phn tip theo s trnh by chi tit v nhng vn ny.
3.2 Nhng h thng gi tr

Mi loi d liu c nhng mc ch c th ca n trong vic m t. Nhng h thng gi tr
nh ngha nhng loi gi tr khc nhau c nh ngha trong ngn ng v bao gm c
nhng thao tc gip h tr nhng h thng gi tr ny. Chng cng c nhng nh ngha hng s
tng ng. Trong Verilog c nhiu gi tr khc nhau nh:
bits and integers(32 bits), time (64 bits): bit-vectors v integers c th phi hp mt cch
t do. Integers c nh ngha c 32 bit. Gi tr time c 64 bit. Thc s bit c hai loi
sau:
4 gi tr trng thi (0,1,x,z); c bit nh l gi tr logic.
128 loi trng thi: gm 4 trng thi v 64 mnh (8 cho mnh 0 v 8 cho
mnh 1) .
Loi floating point (s thc)

Chui k t
Gi tr tr hon Nhng gi tr ny c th l single, double, triplet hay n-tuple ch
tr hon cnh ln, cnh xung hoc s chuyn i khc ca tn hiu.
Gi tr chuyn trng thi - (01) chuyn trng thi t 0 sang 1. Gi tr ny c th c
trong nhng linh kin c bn do ngi dng nh ngha hoc trong nhng khi m t
(specify blocks)
[Type text] Page 70

Nhng gi tr c iu kin/Boole true/false hoc 0/1
units (ch dng cho timescale) femtoseconds (fs) n seconds (s)
3.3 Khai bo loi d liu

3.3.1
Gii thiu
Nhng loi d liu khc nhau trong Verilog c khai bo bng pht biu khai bo d liu.
Nhng pht biu ny xut hin trong nhng nh ngha module trc khi s dng v mt s
trong chng c th c khai bo bn trong nhng khi tun t c t tn. Thm vo ,
nhng loi gi tr c th phn bit vi nhng loi ca d liu khc, nhng c tnh phn
cng ca wires so vi registers cng c phn bit nh l nhng khai bo net so vi khai
bo reg trong Verilog.
T driving ngha l iu khin c dng trong nhng m t phn cng m t cch thc
mt gi tr c gn n mt phn t. Nets v regs l hai phn t d liu chnh trong
Verilog. Nets c iu khin mt cch ni tip t nhng php gn ni tip (continuous
assignments) hoc t nhng phn t cu trc nh module ports, gates, transistors hoc nhng
phn t c bn do ngi dng t nh ngha. Regs c iu khin mt cch cht ch t nhng
khi hnh vi (behavioural blocks). Nets thng thng c thc thi nh l wires trong phn
cng v regs th c th l wires hoc phn t tm hoc flip-flops (registers).
Nhng loi d liu khc nhau trong Verilog c khai bo gm nhng loi sau:
parameter: Loi ny l nhng biu thc gi tr hng s c phn tch sau qu trnh
bin dch v cho php modules c gn tham s.
input, output, inout: Nhng loi d liu ny nh ngha chiu v rng ca mt port.
net : y l loi d liu dng cho vic kt ni hoc wire (dy ni) trong phn cng vi s
phn tch khc nhau.
reg: y l loi d liu tru tng ging nh l mt thanh ghi (register) v c iu khin
theo hnh vi.
time: y l loi d liu lu tr khong thi gian nh tr hon v thi gian m phng.
integer: y l loi d liu s nguyn.
real: y l loi d liu floating point hay s thc
event: y l d liu ch ra rng mt c hiu c bt tch cc.
Tt c hng loi d liu ny c th c khai bo mc module. Nhng m t khc

trong Verilog vi nhng kh nng to lp mc ch bao gm nhng tc v, nhng hm v
nhng khi begin-end c t tn. Nets c iu khin khng theo hnh vi (non[Type text] Page 71

behaviorally) nn do n khng th c khai bo cho nhng mc ch khc, tt c nhng
loi d liu khc c th c th hin trong nhng tc v v trong nhng khi begin- end.
V d 3.1
input a, b;
reg [15:0] c;
time tg;
Dng u tin trong v d trn l mt dng khai bo input, dng th hai l mt khai bo d
liu reg 16 bit. Dng cui cng l khai bo cho mt bin c t tn l tg.
3.4 Khai bo loi d liu net

3.4.1
Gii thiu
Net l mt trong nhiu loi d liu trong ngn ng m t Verilog dng m t dy kt

ni vt l trong mch in. Net s kt ni nhng linh kin mc cng c gi ra, nhng
module c gi ra v nhng php gn ni tip. Ngn ng Verilog cho php c gi tr t mt
net t bn trong nhng m t hnh vi, nhng ta khng th gn mt gi tr cho mt net bn trong
nhng m t hnh vi.
Mt net s khng lu gi gi tr ca n. N phi c iu khin bi mt trong hai cch
sau:
Bng vic kt ni net n ng ra ca mt cng hay mt module.
Bng vic gn mt gi tr n net trong mt php gn ni tip.
Nhng loi net khc nhau c nh ngha trong Verilog c m t bn di v trong

Bng 3.1 s tm tt s phn gii logic ca chng. S phn gii logic l mt qui nh gii
quyt xung t xy ra khi c nhiu mc logic iu khin mt net.
wire: mt net vi gi tr 0, 1, x v s phn gii logic c da trn s tng ng.
wand: mt net vi gi tr 0, 1, x v s phn gii logic c da trn nguyn tc ca php
wired and.
wor: mt net vi gi tr 0, 1, x v s phn gii logic c da trn wired or.
tri: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca bus
tri-state.
tri0: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca bus
tri-state v mt gi tr mc nh l 0 khi khng c iu khin.
tri1: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca bus
tri-state v mt gi tr mc nh l 1 khi khng c iu khin.
[Type text] Page 72

trior: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca
tri-state cho gi tr z-non-z s dng hm or ca gi tr non-z.
triand: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca
tri-state cho gi tr z-non-z s dng hm and ca gi tr non-z.
trireg: mt net vi gi tr 0, 1, x, z v s phn gii logic c da trn nguyn tc ca
tri-state cng vi gi tr lu tr in tch (gi tr trc c dng phn gii gi tr
mi).
supply0, supply1: tng ng l gnd v vdd.
Bng 3.1 S phn gii ca cc loi net
3.4.2
tri/wire
triand/wand
trior/wor
tri0
trireg
tri1
Wire v Tri
Loi d liu wire l mt loi n gin kt ni gia hai linh kin. D liu wire dng cho
nhng net c iu khin bi mt cng linh kin n hay trong php gn ni tip (continuous
assignments). Trong V d 3.2 nhng khai bo 2-wire c to ra. Khai bo u tin m t wire
n (scalar wire) a1. Khai bo th hai m t mt mng (vector) b2 vi 3 bits. Bit trng s
[Type text] Page 73

cao nht (MSB) ca n c trng s l 2 v bit trng s thp nht (ISB) c trng s l 0.
V d 3.2
wire a1;
wire [2:0] b2;
tri abc
D liu tri th hon ton ging vi d liu wire v c php s dng v chc nng tuy
nhin n khc vi d liu wire ch, d liu tri c dng cho nhng net c iu khin
bi nhiu cng linh kin ng ra. Loi d liu tri (tri-state) l loi d liu c bit ca wire, trong
, s phn gii gi tr ca net c iu khin bi nhiu linh kin iu khin, c thc
hin bng vic s dng nhng qui lut ca bus tri-state. Tt c cc bin m iu khin net tri
phi c gi tr Z (tng tr cao), ngoi tr mt bin ln bin n xc nh gi tr ca net tri.
Trong V d 3.3, ba bin iu khin bin out. Chng c thit lp trong module khc ch
mt linh kin iu khin tch cc trong mt thi im.
V d 3.3
module tri_kiemtra (out, m, n,p);
input [1:0] select ,m ,n, p;
output out;
tri out;
assign out = m; // to kt ni cho net tri
assign out = n;
assign out = p;
endmodule
module mnp (m, n, p, select)
output m, n, p;
input [1:0] select;
always @(select) begin
m = 1bz; // thit lp tt c cc bin c gi tr Z
n = 1bz;
p = 1bz;
case (select)
// ch thit lp mt bin non-Z
2b00: m = 1b1;
2b01: n = 1b0;
2b10: p = 1b1;
endcase
[Type text] Page 74

end
endmodule
module top_tri_test ( out, m, n, p, select);
input [1:0] select;
input m, n, p;
output out;
tri out;
mnp (m, n, p, select);
tri_test (out, m, n, p);
endmodule
3.4.3
Wired net
Wired Nets bao gm nhng loi d liu wor, wand, trior v triand. Chng c dng m
hnh gi tr logic ca net. Nhng wired net trn c bng s tht khc nhau phn gii nhng
xung t nu xy ra khi c nhiu cng linh kin cng iu khin mt net.
3.4.3.1 Wand v triand Nets

Wand v triand l loi d liu c bit ca wire dng hm and tm gi tr kt qu khi
nhiu linh kin iu khin mt net, hay ni cch khc nu c bt k ng ra linh kin iu
khin no c gi tr 0 th gi tr ca net c iu khin s l 0.
Trong V d 3.4, hai bin iu khin bin out. Gi tr ca out c xc nh bng hm logic
and gia b1 v b2.
V d 3.4
module wand_test (out, b1,b2);
input b1, b2;
output out;
wand out;
//out = b1 and b2
assign out = b1; //b1 iu khin out

assign out = b2; //b2 iu khin out
endmodule
Ta c th gn mt gi tr tr hon trong khai bo wand, v ta c th s dng nhng t
kha n (scalar) v mng (vector) cho vic m phng.
3.4.3.2 Wor v Tri or

Loi d liu wor v trior l loi d liu c bit ca wire dng hm or tm gi tr kt qu
khi nhiu linh kin iu khin mt net, hay ni cch khc nu c bt k ng ra linh kin iu
[Type text] Page 75

khin no c gi tr 1 th gi tr ca net c iu khin s l 1.
Trong V d 3.5, hai bin iu khin bin out. Gi tr ca out c xc nh bng hm logic
OR gia a1 v a2.
V d 3.5
module wor_test(a1,a2);
input a1, a2;
ouput out;
wor out;
// out = a1 or a2
assign out = a1; // a1 iu khin out
assign out = a2; // a2 iu khin out
endmodule
3.4.4
Tri reg net
Net trireg c dng m hnh gi tr in dung lu gi trn net ca mch in, n c

kh nng lu gi gi tr in tch. Mt trireg c th l mt trong hai trng thi sau:
Trng thi c iu khin (driven state): Khi c t nht mt ng ra ca linh kin iu
khin net trireg c gi tr 1, 0 hoc x th gi tr ny s c truyn n net trireg, v gi tr ny
iu khin gi tr ca net trireg.
Trng thi lu gi in dung: Khi tt c cc ng ra ca linh kin iu khin net trireg u
c gi tr tng tr cao (z), th net trireg s lu gi gi tr cui cng m n trng thi c iu
khin. Gi tr tng tr cao z ca cc ng ra linh kin iu khin s khng c truyn n net
trireg. Do , net trireg s lun c gi tr 0 hay 1 hoc x v khng c gi tr z. mnh gi
tr trn net trireg trong trng thi lu gi in dung c m t bi rng, c th l ln
(large), va (medium) hay nh (small) vi gi tr mc nh l medium nu n khng c m
t. Trong trng thi c iu khin, mnh ca net trireg s ph thuc vo mnh ca linh
kin iu khin nh supply, strong, pull, weak m ta s tho lun sau.
Nh mt m hnh Verilog nh pha di, ta s ly c gi tr kt qu ca wire trireg khi
transistor iu khin n b tt.
V d 3.6
module kiemtra;
reg c0, c1, i1, i2;
tri d0, d1, d2;
trireg d;
and(d0, il, i2);
nmos nl (d1, d0, c0);
nmos n2(d, d1, c1);
initial begin
$monitor(time = %d d =%d c =%d c1=%d d0=%d d1=%d i1=%d i2=%d,
[Type text] Page 76

$time, d, c0, c1, d0, d1, i1, i2);
#1
i1 = 1;
i2 = l;
c0 = l;
c1 = 1;
#5
c0 = 0;
end
endmodule
Simulation result:
time = 0 d= x c0=x c1=x d0=x d1=x i1=x i2=x
time = 1 d= 1 c1=1 c1=1 d0=1 d1=1 i1=1 i2=1
time = 6 d= 1 c0=0 c1=1 d0=1 d1=0 i1=1 i2=1
3.4.5
Tri 0 v Tri 1 Nets
Net tri0 v tri1 dng m hnh nhng net vi linh kin in tr ko ln hoc ko xung.
Mt net tri0 s tng ng vi mt net c iu khin lin tc bi gi tr 0 vi mnh
pull. Mt net tri1 s tng ng vi mt net c iu khin lin tc bi gi tr 1 vi mnh
pull.
Khi khng c linh kin iu khin net tri0, gi tr ca n vn l 0 vi mnh pull. Khi
khng c linh kin iu khin net tri1, gi tr ca n vn l 1 vi mnh pull. Khi c nhiu
linh kin iu khin net tri0 hoc tri1, th s phn gii mnh ca cc linh kin iu khin vi
mnh pull ca net tri0 hoc tri1, s xc nh gi tr ca net.
3.4.6
Supply0 v Supply1 Nets
Loi d liu supply0 v supply1 nh ngha nhng net wire c mc c nh n mc

logic 0 (ni t, vss) v logic 1 (ngun cung cp, vdd). Vic s dng supply0 v supply1 tng
t nh khai bo mt wire v sau gn gi tr 0 hoc 1 ln n.
Trong V d 3.7, power c ni ln ngun cung cp (lun l logic 1 c mnh ln
nht) v gnd c ni n t (ground) (un l logic 0 c mnh nht).
V d 3.7
supply0 gnd;
supply1 power;
3.4.7
Thi gian tr hon trn net
Trong thc t bt k net no trong mch in t cng to ra tr hon trn net. Trong
Verilog, tr hon c th c khai bo kt hp trong pht biu khai bo net. Nhng gi
[Type text] Page 77

tr tr hon ny l thi gian tr hon, c tnh t khi tn hiu ti ng ra ca linh kin iu
khin thay i, cho n khi tn hiu trn net thc s thay i. tr hon c m t bi s
hoc biu thc theo sau biu tng #. Nhng gi tr ny l hng s, tham s, biu thc ca
chng hay c th l nhng biu thc ng dng nhng bin s khc.
tr hon c th l rise, fall, hay hold, mi loi tr hon ny c th c ba gi tr minimum, typical v maximum. S m t tr hon rise, fall, hold c phn bit bi du
phy (,) v s m t min:typ:max c phn bit bi du hai chm (:):
tr hon rise (cao ln) bao gm thi gian tr hon khi gi tr tn hiu thay i t 0 ln
1, 0 n x v t x n 1.
tr hon fall (thp xung) bao gm thi gian tr hon khi gi tr tn hiu thay i t
1 xung 0, 1 n x v t x n 0.
tr hon hold (thi gian thay i n z) bao gm thi gian tr hon khi gi tr tn hiu
thay i t 0 ln z, 1 n z v t x n z.
Khi nim tr hon ny cng c dng cho vic nh ngha tr hon ca cng,
transistor, linh kin c bn do ngi dng t nh ngha v nhng m t hnh vi.
V d 3.8:
tri #9 t1, t2;
wire #(10,9,8) a1, a2;
wand #(10:8:6, 9:8:6) a3;
Trong V d 3.8, dng u tin m t t1, t2 c thi gian tr hon rise, fall, hold u l 9
n v thi gian. Dng th hai, wire a1 v a2 nh ngha ba gi tr khc nhau cho ba s thay i
10 cho rise, 9 cho fall v 8 cho hold. Dng cui cng, wand a3 nh ngha gi tr min, type
cho c ba s thay i rise, fall, hold.
V d 3.9:
wire a1, a2;
tri[7:0] t1, t2;
trireg large trg1, trg2;
triand [31:0] #(10:5) gate1;
Trong v d trn, dng u tin vi t kha wire khai bo a1 v a2 l wire n (scalar wire
hay single bit). Dng th hai khai bo hai vector wire 8 bit t1 v t2 c loi d liu l tri. Dng
k tip khai bo net c kh nng lu gi in dung trg1 v trg2 vi ln in dung l
large. Dng cui cng khai bo mt net c rng 32 bit c loi d liu l triand vi tr
hon l ti thiu (minimum) v trung bnh (typical).
[Type text] Page 78

3.5 Khai bo loi d liu bin - reg
Khai bo reg c thc hin cho tt c nhng tn hiu m c iu khin t nhng m t
hnh vi. Loi d liu reg lu gi mt gi tr c cho n khi n c gn mt gi tr mi trong
mt m t tun t (khi initial hoc always).
Loi d liu reg th c mc tru tng hn so vi loi d liu net nhng n c quan h
mt thit vi khi nim thanh ghi (register), vi kh nng lu gi gi tr v c th c xem
nh l mt register trong phn cng. Tuy nhin, chng cng c th c xem nh l wire hoc
phn t nh tm thi m khng phi l phn t thc trong phn cng, iu ny ph thuc vo
vic s dng chng bn trong khi m t hnh vi.
V d 3.10
reg reg1, reg2;
reg [63:0] data1, data2, data3;
3.6 Khai bo port

3.6.1
Gii thiu
Ta phi khai bo tht tng minh v chiu (input, output hay bidirectional) ca mi port
xut hin trong danh sch khai bo port. Trong Verilog nh ngha ba loi port khc nhau, l
input, output v inout. Loi d liu ca port c th l net hoc reg. Loai d liu reg ch c th
xut hin port output. Hng s v biu thc lun nm pha di khai bo port.
3.6.2
input
Tt c port input ca mt module c khai bo vi mt pht biu input. Loi d liu mc

nh ca input port l wire v c iu khin bi c php ca wire. Ta c th khai bo rng
ca mt input nh mt mng (vector) ca nhng tn hiu. Nhng pht biu input c th xut
hin bt c v tr no trong m t thit k nhng chng phi c khai bo trc khi chng
c s dng.
V d 3.11
input m;
input [2:0] n;
3.6.3
output
Tt c port output ca mt module c khai bo vi mt pht biu output. Nu

khng c mt loi d liu khc nh l reg, wand, wor, hoc tri c khai bo, th output port
s c loi d liu mc nh l wire v n cng c iu khin bi c php ca wire. Mt
pht biu output c th xut hin bt c v tr no trong m t thit k, nhng n phi
c khai bo trc khi c s dng. Ta c th khai bo rng ca mt output nh mt
[Type text] Page 79

mng (vector) ca nhng tn hiu. Nu ta s dng loi d liu reg khai bo cho output th reg
phi c cng rng vi rng ca mng (vector) ca tn hiu.
V d 3.12
output abc;
// khai bo output abc kiu wire
output [2:0] bcd;

reg [2:0] bcd;
3.6.4
//reg bcd phi c cng kch thc trn khai bo output
inout
Ta c th khai bo port hai chiu (bidirectional) vi pht biu inout. Mt port inout c loi d
liu l wire v c iu khin bi c php ca wire. Ta phi khai bo port inout trc khi n
c s dng.
V d 3.13
inout a:
inout [2:0] b;
V d 3.14
module fulladder(cout, sum, in1, in2, in3);
input in1, in2, in3;
// khai bo 3 ng vo
output cout, sum;
//khai bo 2 ng ra
wire in1, in2, in3;
//khai bo kiu d liu
reg cout, sum;
//khai bo kiu d liu
endmodule
3.7 Khai bo mng v phn t nh mt v hai chiu.

3.7.1
Gii thiu
Verilog ch h tr khai bo mng mt v hai chiu. Nhng mng mt chiu c gi l

bit-vectors v n c th l loi d liu net hoc reg. Nhng mng hai chiu c gi l nhng
phn t nh v l loi d liu reg. Ta c th nh ngha rng cho tt c cc loi d liu
c trnh by trong chng ny. Vic nh ngha rng cung cp mt cch to ra mt
bit-vector. C php ca mt m t rng l [msb:lsb]. Nhng biu thc ca msb (bit c trng
s ln nht) v lsb (bit c trng s nh nht) phi l nhng biu thc c gi tr hng khc 0.
Nhng biu thc c gi tr hng ch c th to nn bi nhng hng s, nhng tham s ca
Verilog v cc ton t. Khng c gii hn trong vic nh ngha rng ti a ca mt bitvector trong Verilog, tuy nhin vic gii hn ny c th s ph thuc vo cng c m phng,
tng hp, hoc nhng cng c khc.
[Type text] Page 80

3.7.2
Mng net
V d 3.15
wire [63:0] bus;
V d 3.15 m t vic khai bo mt mng wire c rng 64 bits.
V d 3.16
wire vectored [31:0] bus1;
wire scalared [31:0] bus2;
V d 3.16, ta s dng hai t kha ch dn vectored v scalared, chng u c dng
khai bo multi-bit Nets, tuy nhin chng khc nhau ch c cho php m t tng bit hay
tng phn ca net hay khng, vi vectored net, vic chn tng bit l khng c php, cn vi
scalared net th c php:
assign bus1 [1] = 1b1;
// sai c php v s dng vic chn bit ca mt vectored net.
assign bus2 [1] = 1b1;
// ng v vic chn bit ca mt scalared net l c php.
Trnh bin dch chp nhn c php ca nhng cu trc m t Verilog ny, tuy nhin chng
s b b qua khi mch c tng hp ra phn cng.
3.7.3
Mng thanh ghi
V d 3.17: Khai bo mng thanh ghi

reg [7:0] Areg
3.7.4
// thanh ghi 8 bit
Mng phn t nh
V d 3.18 : Khai bo mng phn t nh

reg Amem [7:0];
// mng 8 thanh ghi, mi thanh ghi c rng mc nh
reg Bmem [7:0][0:3];
//
reg [7:0] Cmem [0:3];
// mng 4 thanh ghi, mi thanh ghi 8 bit
reg[2:0] Dmem [0:3][0:4];
[Type text] Page 81
3.8
Khai bo loi d liu bin

(s nguyn, thi gian, s thc, v thi gian thc)
[Type text] Page 82

3.8.1
Gii thiu
Thm vo kh nng m hnh ha cho phn cng trong Verilog, ta c th s dng thm mt
s loi d liu bin khc ngoi d liu bin reg. Mc d bin d liu reg c th c dng cho
nhng chc nng tng qut nh m thi gian, lu gi s thay i gi tr ca net, bin d
liu integer v time th cung cp s thun li v d c hiu hn trong vic m t thit k.
3.8.2
Integer
Loi d liu integer l bin c chc nng tng qut c dng tnh ton s lng.
N khng c xem nh l thanh ghi trong phn cng thit k. Loi d liu integer c rng
32 bit, n c th c gn v s dng hon ton ging nh loi bin d liu reg. Php gn qui
trnh (procedural assignment) c dng kch s thay i gi tr ca loi d liu integer.
Nhng php tnh trn bin d liu integer s to ra nhng kt qu di dng b 2.
V d 3.19: Khai bo bin integer
integer i1, i2;
3.8.3
Time
Bin d liu time c rng 64 bit, bin ny thng c dng lu gi gi tr output ca

hm h thng $time, hoc tnh ton thi gian chy m phng trong nhng trng hp m
vic kim tra nh thi l bt buc, hoc cho nhng mc ch d tm v pht hin li ca
thit k trong qu trnh m phng.
Loi d liu time c th c gn v s dng hon ton ging nh loi bin d liu reg.
Php gn qui trnh (procedural assignment) c dng kch s thay i gi tr ca loi d liu
time.
V d 3.20: Khai bo kiu d liu time
time t1, t2;
3.8.4
S thc (real) v thi gian thc (realtime)
Bn cnh bin d liu integer v time, Verilog cn c h tr vic s dng hng s thc v
bin d liu thc (real). Ngoi tr 3 ngoi l nh trnh by pha di y th bin d liu real c
th c s dng tng t nh integer v time:
1. Khng phi tt c cc php ton trong Verilog c th c s dng vi nhng s thc.
Cc bng 3.2 v 3.3 cho bit cc ton t v php ton khng c php dng vi s thc
v ton t s thc (xem thm Mc 4.2.1).
Bng 3.2 Danh sch cc ton t khng c php s dng i vi s thc
unary + unary -
Ton t mt ngi (Unary operation)
+ - *
Ton t s hc (Arithmetic)
/ **
[Type text] Page 83

>, >=, <, <=
Ton t quan h (Relational)
! && ||
Ton t logic (Logical)
== !=
Ton t bng (Logical equality)
?:
Ton t iu kin (Conditional)
Bng 3.3 Danh sch cc ton t khng c php s dng i vi ton t s thc
{} {{}}
Ton t ghp ni, thay th (concatenate replicate)
Ton t chia ly phn d (modulus)
=== !==
Ton t bng case (equality)
~ , &, |, ^, ^~, ~^
Ton t bitwise (bitwise)
^, ^~, ~^, &, ~&, |, ~|
Ton t gim (reduction)
<< >> <<< >>>
Ton t dch (shift)
2. Bin d liu khng c khai bo rng ca bin, vic tnh ton c thc hin dng
chun nh dng IEEE floating point.
3. Bin d liu c gi tr mc nh l 0.
Thi gian thc (realtime) c khai bo v s dng tng t nh s thc (real), chng c
th hon i cho nhau.
V d 3.21
real float;
realtime rtime;
3.9
Khai bo tham s
3.9.1
Gii thiu
Trong Verilog HDL, loi d liu tham s (parameter) khng thuc loi d liu bin (reg,
integer, time, real, realtime) cng nh loi d liu net (wire, tri, wand, wor,...). D liu tham
s khng phi l bin m chng l hng s. C hai loi tham s trong Verilog l:
Tham s module (module parameter): parameter v localparam.
Tham s c t (specify parameter): specparam.
C hai loi tham s trn u c php khai bo rng. Mc nh, parameter v
specparam s c rng cha gi tr ca hng s, ngoi tr khi tham s c khai bo
rng. Vic khai bo trng tn gia net, bin hay tham s l khng c php.
[Type text] Page 84

3.9.2
Tham s module (module parameter)
Tham s module c hai loi khai bo: parameter v localparam (local parameter).
3.9.2.1 Parameter
3.9.2.1.1
Gii thiu
Gi tr ca khai bo parameter trong mt module c th c thay i t bn ngoi

module bng pht biu defparam hoc pht biu gi th hin (instance) ca module .
Thng thng khai bo parameter c dng m t nh thi hoc rng ca bin.
V d 3.22
parameter msb = 1;
// nh ngha tham s msb c gi tr hng s l 1
parameter e = 43, f =789;
// nh ngha hai hng s
parameter r = 46.7;
// khai bo r l mt hng s thc
parameter
byte_size = 9,
byte_mask = byte_size - 6;
parameter average_delay = (r + f) / 2;
parameter signed [3:0] mux_selector = 0;
parameter real r1 = 3.6e19;
parameter p1 = 13'h7e;
parameter [31:0] dec_const = 1'b1;
// gi tr c i sang 32 bit
parameter newconst = 3'h4;
// ng l tham s ny c rng [2:0]
parameter newconst = 4;
3.9.2.1.2
// ng l tham s ny c rng ti thiu l 32 bit.
Thay i gi tr ca tham s khai bo parameter
Mt tham s module c th c m t loi d liu v m t rng. S tc ng ca gi

tr tham s mi khi n ln gi tr ca tham s c khai bo ban u trong module,
vi m t loi d liu v m t rng s tun theo nhng qui lut sau:
Mt khai bo tham s m khng m t loi d liu v rng, s c loi d liu v
rng mc nh ca gi tr cui cng c gn vo tham s .
Mt khai bo tham s m khng m t loi d liu m ch m t rng, th rng
ca tham s s khng i, cn loi d liu s l unsigned khi gi tr mi c ln.
Mt khai bo tham s m ch m t loi d liu m khng m t rng, th loi d
liu ca tham s s khng i, cn rng s c gi tr cha gi tr mi c
ln.
Mt khai bo tham s va m t loi d liu l c du, va m t c rng, th loi d
liu v rng ca tham s cng s khng i khi gi tr mi c ln.
Trong Verilog c hai cch thay i gi tr ca tham s c khai bo bi parameter:
[Type text] Page 85

Mt l pht biu defparam, vi pht biu ny n s cho php gn gi tr mi vo tham
s trong module bng cch dng tn gi mt cch phn cp.
Hai l php gn gi tr tham s khi gi instance ca module , bng cch ny s cho
php thay i gi tr tham s trong cng mt dng vi vic gi instance ca module .
3.9.2.1.2.1
Pht biu defparam
S dng pht biu defparam, gi tr tham s c th c thay i bn trong instance ca

module thng qua vic s dng tn phn cp ca tham s. Tuy nhin, pht biu defparam
c m t trong mt instance hoc mt dy cc instance th s khng lm thay i gi tr
tham s trong nhng instance khc ca cng mt module.
Biu thc bn phi ca php gn defparam l biu thc hng s ch bao gm s v nhng
tham s tham chiu c khai bo trc trong cng module vi pht biu defparam.
Pht biu defparam c bit hu dng v ta c th nhm tt c cc php gn thay i gi tr
cc tham s ca cc module khc nhau ch trong mt module.
Trong trng hp c nhiu pht biu defparam cho mt tham s duy nht th gi tr tham s
s ly gi tr ca pht biu defparam sau cng. Nu pht biu defparam ca mt tham s
c khai bo trong nhiu file khc nhau th gi tr ca tham s s khng c xc nh.
V d 3.23
module top;
reg clk;
reg [0:4] in1;
reg [0:9] in2;
wire [0:4] o1;
wire [0:9] o2;
vdff m1 (o1, in1, clk);
vdff m2 (o2, in2, clk);
endmodule
module vdff (out, in, clk);
parameter size = 1, delay = 1; // hai tham s theo th t
input [0:size-1] in;
input clk;
output [0:size-1] out;
reg [0:size-1] out;
always @(posedge clk)
# delay out = in;
[Type text] Page 86

endmodule
module annotate;
defparam
top.m1.size = 5,
// thay i tham s size ca m1
top.m1.delay = 10,
// thay i tham s delay ca m1
top.m2.size = 10,
top.m2.delay = 20;
// thay i tham s size ca m2

// thay i tham s delay ca m2
endmodule
Trong V d 3.22, module annotate c pht biu defparam, gi tr t pht biu ny s ln
nhng gi tr tham s size v delay trong instance m1 v m2 trong module top. Hai module
top v annotate u c xem nh module top-level.
3.9.2.1.2.2 Php gn gi tr tham s khi gi instance ca module
Trong Verilog c mt phng php khc dng gn gi tr n mt tham s bn trong
instance ca mt module, l s dng mt trong hai dng ca php gn gi tr tham s trong
instance ca module. Mt l php gn theo th t danh sch tham s, hai l php gn bi tn.
Hai dng php gn ny khng th t ln ln vi nhau m chng ch c th l mt trong hai
dng cho ton b instance ca module.
Vic gn gi tr tham s instance ca module theo th t danh sch tham s, tng t nh
vic gn gi tr tr hon cho nhng cng ca instance; cn vic gn gi tr tham s instance ca
module theo tn tham s, th tng t nh vic kt ni port ca module bi tn. N gn nhng
gi tr tham s cho nhng instance c th m trong module ca nhng instance ny nh
ngha nhng tham s trn.
Mt tham s m c khai bo trong mt block, mt tc v hay mt hm ch c th khai
bo li mt cch trc tip dng pht biu defparam. Tuy nhin, nu gi tr tham s ny ph
thuc vo mt tham s th hai, th vic nh ngha li gi tr tham s th hai cng s cp
nht gi tr ca tham s th nht.
Sau y ta xt chi tit hai php gn tham s ny.
1. Php gn gi tr tham s theo th t danh sch tham s
Th t ca nhng php gn trong php gn gi tr tham s theo th t danh sch tham s
instance ca module, s theo th t tham s lc khai bo bn trong module. N khng cn thit
phi gn gi tr cho tt c cc tham s c bn trong module khi dng phng php ny. Tuy
nhin, ta khng th nhy qua mt tham s, do gn nhng gi tr cho mt phn nhng tham
s trong tt c cc tham s khai bo trong module, th nhng php gn thay th gi tr ca
[Type text] Page 87

mt phn nhng tham s , s ng trc nhng khai bo ca nhng tham s cn li. Mt
phng php khc l phi gn gi tr cho tt c cc tham s nhng dng gi tr mc nh
(cng c gi tr nh c gn trong khai bo tham s trong nh ngha module) cho cc tham
s m khng cn c gi tr mi.
Xt V d 3.24, trong v d ny nhng tham s bn trong instance ca nhng module
mod_a, mod_c, v mod_d c thay i trong khi gi instance.
V d 3.24
module tb1;
wire [9:0] out_a, out_d;
wire [4:0] out_b, out_c;
reg [9:0] in_a, in_d;
reg [4:0] in_b, in_c;
reg clk;
/* Bn instance ca module vdff vi php gn gi tr tham s theo th t danh sch
tham s*/
// mod_a c hai gi tr tham s mi size=10 v delay=15
vdff #(10,15) mod_a (.out(out_a), .in(in_a), .clk(clk));
// mod_b c gi tr tham s mc nh l (size=5, delay=1)
vdff mod_b (.out(out_b), .in(in_b), .clk(clk));
// mod_c c mt gi tr tham s mc nh l size=5 v mt gi tr mi l
delay=12
vdff #( 5,12) mod_c (.out(out_c), .in(in_c), .clk(clk));
*/ thay i gi tr ca tham s delay, ta cng cn phi m t gi tr mc nh
ca tham s size*/
/* mod_d c mt gi tr tham s mi l size=10, v gi tr tham s delay vn gi
gi tr mc nh ca n./*
vdff #(10) mod_d (.out(out_d), .in(in_d), .clk(clk));
endmodule
parameter size=5, delay=1; // tham s vi gi tr mc nh
output [size-1:0] out;
input [size-1:0] in;
[Type text] Page 88

input clk;
reg [size-1:0] out;
#delay out = in;
endmodule
Nhng gi tr ca tham s cc b (localparam) khng th b ln, do chng khng c
xem nh l mt phn th t ca danh sch cho php gn gi tr tham s. Trong V d 3.25,
addr_width s c gn gi tr 12, v data_width s c gn gi tr 16, mem_size s khng
c gn gi tr mt cch tng minh do th t danh sch, nhng n s c gi tr 4096 do biu
thc khai bo ca n.
V d 3.25
module my_mem (addr, data);
parameter addr_width = 16; //th t tham s th nht
localparam mem_size = 1 << addr_width;
parameter data_width = 8;
//th t tham s th hai
...
endmodule
module top;
...
my_mem #(12, 16) m(addr,data);
//khng xt tham s localparram
endmodule
2. Php gn gi tr tham s bi tn
Php gn gi tr tham s bi tn bao gm tn tng minh ca tham s v gi tr mi ca n.
Tn ca tham s s l tn c m t trong instance ca module. Ta khng cn thit gn nhng
gi tr n tt c cc tham s bn trong module khi s dng phng php ny. Ch nhng
tham s no m c gn gi tr mi th mi cn c ch ra.
Biu thc tham s c th l mt la chn vic gi instance ca module c th ghi li vic
hin din ca mt tham s, m khng cn bt k mt php gn n n. Nhng du ng m
ngoc c i hi, v trong trng hp ny tham s s gi gi tr mc nh ca n. Khi mt
tham s c gn mt gi tr, th mt php gn khc n tn tham s ny l khng c php.
Xt V d 3.26, trong v d ny c nhng tham s ca mod_a v ch mt tham s ca mod_c
v mod_d b thay i trong khi gi instance ca module.
V d 3.26
[Type text] Page 89

module tb2;
wire [9:0] out_a, out_d;
wire [4:0] out_b, out_c;
reg [9:0] in_a, in_d;
reg [4:0] in_b, in_c;
reg clk;
// Bn instance ca moduel vdff vi gi tr tham s c gn bi tn
// mod_a c gi tr tham s mi l size=10 v delay=15
vdff #(.size(10),.delay(15)) mod_a (.out(out_a),.in(in_a),.clk(clk));
// mod_b c gi tr tham s mc nh l (size=5, delay=1)
vdff mod_b (.out(out_b),.in(in_b),.clk(clk));
/* mod_c c mt gi tr tham s mc nh l size=5 v c mt gi tr tham s mi l
delay=12*/
vdff #(.delay(12)) mod_c (.out(out_c),.in(in_c),.clk(clk));
/* mod_d c mt gi tr tham s mi l size=10, cn tham s delay vn gi gi tr mc
nh*/
vdff #(.delay( ),.size(10)) mod_d (.out(out_d),.in(in_d),.clk(clk));
endmodule
parameter size=5, delay=1;
output [size-1:0] out;
input [size-1:0] in;
input clk;
reg [size-1:0] out;
#delay out = in;
endmodule
Vic gi nhng instance ca module, dng nhng loi nh ngha li tham s trong cng
module top-level th hp l. Xt trong v d sau, nhng tham s ca mod_a b thay i bng
cch dng vic nh ngha li tham s theo th t danh sch; tham s th hai ca mod_c c
thay i bng cch dng vic nh ngha li tham s bng tn, trong khi gi instance ca
[Type text] Page 90

module.
V d 3.27
module tb3;
/* s pha trn gia instance c khai bo tham s theo th t v instance c khai
bo tham s theo tn th hp l*/
vdff #(10, 15) mod_a (.out(out_a), .in(in_a), .clk(clk));
vdff mod_b (.out(out_b), .in(in_b), .clk(clk));
vdff #(.delay(12)) mod_c (.out(out_c), .in(in_c), .clk(clk));
endmodule
S khng hp l khi gi instace ca bt k module no, dng ln ln nhng php gn li
gi tr tham s bng th t danh sch tham s v tn, ging nh trong php gi instance ca
module mod_a di y:
V d 3.28
// instance mod_a khng hp l do c s pha trn gia cc php gn tham s
vdff #(10, .delay(15)) mod_a (.out(out_a), .in(in_a), .clk(clk));
3.9.2.1.3
S ph thuc tham s
Mt tham s (v d, memory_size) c th c nh ngha vi mt biu thc cha nhng

tham s khc (v d, word_size). Tuy nhin, vic gn gi tr tham s, c th l bng pht biu
defparam hoc trong pht biu gi instance ca module, s thay th mt cch hiu qu vic
nh ngha tham s vi mt biu thc mi. Bi v memory_size ph thuc vo gi tr ca
word_size, bt k c s thay i no ca word_size s lm thay i gi tr ca memory_size. V
d, trong khai bo tham s sau, mt gi tr mi cp nht ca word_size, c th l bi pht biu
defparam hoc pht biu gi instance ca module m trong module ny nh ngha nhng
tham s trn, th gi tr ca memory_size s c t ng cp nht. Nu memory_size c cp
nht bi pht biu defparam hay mt pht biu gi instance th n s ly gi tr m khng cn
quan tm n gi tr ca word_size.
V d 3.29
parameter
word_size = 32,
memory_size = word_size * 4096;
3.9.2.2 Tham s cc b (local parameter)

Trong Verilog, tham s cc b (localparam) ging tng t vi tham s (parameter)
ngoi tr n khng th c gn li gi tr bi pht biu defparam, hoc php gn gi tr tham
s khi gi instance ca module. Nhng tham s cc b (localparam) c th c gn bi nhng
[Type text] Page 91

biu thc hng s cha nhng tham s (parameter), m nhng tham s (parameter) ny c
th c gn li gi tr bi pht biu defparam, hoc php gn gi tr tham s khi gi instance
ca module.
Vic chn bit hay mt phn ca tham s cc b m loi d liu ca n khng phi l real
th c php.
V d 3.30
localparam thamso1;
localparam signed [3:0] thamso2;
localparam time t1;
localparam integer int2;
localparam var = 5*6;
3.9.3
Tham s c t (specify parameter)
T kha specparam khai bo n l mt loi c bit ca tham s (parameter) ch dng cho

mc ch cung cp gi tr nh thi (timing) v gi tr tr hon (delay), nhng n c th xut
hin trong bt k biu thc no, vi iu kin biu thc khng c gn n mt tham s
(parameter) v biu thc cng khng phi l phn m t rng trong mt khai bo.
Nhng tham s c t (specparams) c php khai bo bn trong khi c t (specify block
- l cc khi bt u bng t kha specify...endspecify) hoc bn trong mt module chnh. Mt
tham s c t (specify parameter) khai bo bn ngoi mt khi c t (specify block) th cn
c khai bo trc khi n c s dng. Gi tr m c gn n mt tham s c t, c th l
mt biu thc hng s bt k. Mt tham s c t c th c dng nh l phn ca mt
biu thc hng s cho mt khai bo tham s c t k tip.
Khng ging nh mt tham s module (module parameter), mt tham s c t khng th
c gn li gi tr t bn trong ngn ng Verilog, nhng n c th c gn li gi tr thng
qua tp tin d liu SDF (Standard Delay Format).
Nhng tham s c t (specify parameter) v tham s module (module parameter) khng th
thay th cho nhau. Ngoi ra, tham s module (module parameter) khng th c gn bi mt
biu thc hng s m c cha tham s c t (specify parameter). Bng 3.4 tm tt s khc nhau
gia hai loi khai bo tham s.
Bng 3.4 S khc nhau gia hai loi khai bo tham s
Specparams (tham s c t)
Parameters (tham s module)
S dng t kha specparam
S dng t kha parameter
Cn c khai bo bn trong mt module Cn c khai bo bn ngoi nhng khi

hoc mt khi c t (specify block)
[Type text] Page 92
c t (specify block)

C th c dng bn trong mt module hoc Khng th c dng bn trong nhng
mt khi c t (specify block)
khi c t (specify block).
C th c gn bi tham s c t Khng th c gn bi specparams.

(specparam) v tham s module (parameter).
S dng tp tin d liu SDF gn gi tr Dng pht biu defparam hoc php gn
cho tham s c t.
gi tr tham s cho instance ca module

gn gi tr cho tham s.
Mt tham s c t (specify parameter) c th c m t rng. rng ca nhng

tham s c t cn tun theo nhng qui lut sau:
Mt khai bo tham s c t m khng c m t rng th mc nh s l rng
ca gi tr cui cng c gn n n, sau khi c bt k gi tr no gn ln n.
Mt khai bo tham s c t m c m t rng th rng ca n s theo rng
khai bo. rng s khng b nh hng bi bt k gi tr no c gn ln n.
Vic chn bit hay mt phn ca tham s c t m loi d liu ca n khng phi l real
th c php.
V d 3.31
specify
specparam trise_clk_q = 150, tFall_clk_q = 200;
specparam trise_control = 40, tFall_control = 50;
endspecify
Trong v d ny, nhng dng gia nhng t kha specify v endspecify l khai bo bn
tham s c t. Dng u tin khai bo hai tham s c t trise_clk_q v tFall_clk_q vi gi tr
tng ng l 150 v 200. Dng th hai khai bo hai tham s c t trise_control v
tFall_control vi gi tr tng ng l 40 v 50.
V d 3.32
module RAM16GEN (output [7:0] DOUT, input [7:0] DIN,
input [5:0] ADR, input WE, CE);
specparam dhold = 1.0;
specparam ddly = 1.0;
parameter width = 1;
parameter reg size = dhold + 1.0; /* Khng hp l - khng th gn tham s c t
(specparam) n mt tham s (parameter)*/
endmodule
[Type text] Page 93

3.10Bi tp
1. Trong ngn ng m t phn cng Verilog HDL, c my loi d liu c bn? Nu chc
nng s dng ca mi loi?
2. Trong kiu d liu net c nhng loi khai bo d liu no? Nu s khc nhau gia cc
loi khai bo d liu net ?
3. Trong kiu d liu bin c nhng loi khai bo d liu no? Nu s khc nhau gia cc
loi khai bo d liu bin?
4. Trong ngn ng m t phn cng Verilog HDL, c nhng loi tham s no? Nu s khc
bit gia tham s module v tham s c t?
5. Khi no ta s dng khai bo defparam?
6. C my loi tham s module? Nu s khc bit gia hai khai bo parameter v
localparam trong tham s module ?
[Type text] Page 94
4 Chng 4.
Ton t, Ton hng v Biu thc
Biu thc l mnh m t cc ton t v cc gi tr ca cc ton hng trong Verilog HDL

v cch s dng chng.
Mt biu thc l mt cu trc t hp ca cc ton hng vi ton t, to nn mt kt qu
l mt hm ca cc gi tr ton hng v ng ngha ca ton t. Bt k mt ton hng hp l nh
l mt net bit-select, bt chp ton t u c xem nh l mt biu thc. Bt k ni no cn
mt cu lnh trong Verilog, biu thc c th c s dng.
4.1 Biu thc gi tr hng s

Mt vi cu trc cu lnh yu cu mt biu thc l mt biu thc gi tr hng s. Ton hng
ca biu thc gi tr hng s bao gm cc hng s, chui, tham bin, bit-select hng, part-select
hng ca tham bin, cc hm gi hng, v cc hm gi h thng, nhng chng c th s dng
bt k ton t no c nh ngha trong Bng 4.1.
Cc hm gi h thng hng, gi cc hm c xy dng trong h thng, ni m cc i s l
cc biu thc hng. Khi s dng trong biu thc hng s, cc hm gi s nh gi tr trong thi
gian thit lp. Cc hm h thng s dng trong hm gi h thng hng s, gi l cc hm
thun ty, gi tr ca n ch ph thuc vo cc i s u vo v khng nh hng n
xung quanh. C th, cc hm h thng cho php trong biu thc hng s c chuyn i t
danh sch cc hm h thng trong phn 17.8 v danh sch cc hm h thng ton hc trong
17.11.
Cc loi d liu reg, integer, time, real v realtime l cc loi d liu cho bin. M t lin
qua ti bin p dng cho tt c cc loi d liu ny.
Mt ton hng c th l mt trong:
Hng s (bao gm c s thc) hoc chui.
Tham bin (bao gm c tham bin ni v tham bin ch nh).
Bit-select v part-select ca tham bin (khng bao gm s thc).
Net.
Bit-select v part-select ca net.
Bin reg, integer, hoc time.
Bit-select v part-select ca bin reg, integer, hoc time.
Bin real hoc realtime.
Mng cc phn t.
Bit-select v part-select ca mng cc phn t.
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Mt hm gi do ngi dng nh ngha hoc hm gi h thng m n tr v bt k gi tr
no bn trn.
4.2 Ton t
K hiu cho ton t trong ngn ng m t phn cng Verilog tng t nh trong ngn ng
lp trnh C. Bng 4.1 l danh sch cc ton t ny.
Bng 4.1 Danh sch cc ton t
{} {{}}
++ - * / **
%
> >= < <=
!
&&
||
==
!=
===
!==
~
&
|
^
^~ hoc ~^
<<
>>
<<<
>>>
?:
4.2.1
Ton t kt ni, ton t lp

Ton t mt ngi
Ton t s hc
Ton t chia ly phn d
Ton t quan h
Ton t nghch o logic
Ton t logic and
Ton t logic or
Ton t bng
Ton t khng bng
Ton t bng case
Ton t khng bng case
Ton t ph nh bitwise
Ton t and bitwise
Ton t or ton b bitwise
Ton t or loi tr bitwise
Ton t tng ng
Ton t dch tri logic
Ton t dch phi logic
Ton t dch tri ton hc
Ton t dch phi ton hc
Ton t iu kin
Ton t vi ton hng s thc
Cc ton t trong Bng 4.2 l hp l khi p dng i vi ton hng s thc. Tt c cc

ton t khc s xem nh l bt hp l khi s dng vi ton hng s thc. Kt qu khi s dng
ton t logic v ton t quan h trn s thc l mt gi tr bit n v hng .
Bng 4.2 Danh sch cc ton t khng c php s dng i vi s thc
unary + unary -
Ton t mt ngi (Unary operation)
+ - *
Ton t s hc (Arithmetic)
/ **
>, >=, <, <=

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Ton t quan h (Relational)

Page 96

! && ||
Ton t logic (Logical)
== !=
Ton t bng (Logical equality)
?:
Ton t iu kin (Conditional)
Bng 4.3 Danh sch cc ton t khng c php s dng i vi ton t s thc
{} {{}}
Ton t ghp ni, thay th (concatenate replicate)
Ton t chia ly phn d (modulus)
=== !==
Ton t bng case (equality)
~ , &, |, ^, ^~, ~^
Ton t bitwise (bitwise)
^, ^~, ~^, &, ~&, |, ~|
Ton t gim (reduction)
<< >> <<< >>>
Ton t dch (shift)
4.2.2
Ton t u tin
Th t u tin ca cc ton t trong Verilog c m t trong Bng 4.4

Bng 4.4 Th t u tin ca ton t
+ - ! ~ & ~& | ~| ^ ~^ ^~(ton t mt ngi)
u tin cao nht
**
u tin cao nh
* / %
<< >> <<< >>>
< <= > >=
== != === !==
&(ton t 2 ngi)
u tin gim dn t cao xung

thp
^ ^~ ~^(ton t 2 ngi)
|(ton t 2 ngi)
&&
||
?:
u tin thp nh
{} {{}}
u tin thp nht
Cc ton t trong cng mt dng trong Bng 4.4 c th t u tin nh nhau. Cc dng c
sp xp theo th t tng dn u tin. V d cc ton t *, /, v % c cng u tin v u
tin ca n cao hn ton t + v -.
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Tt c cc ton t s c thc hin t tri sang phi, ngoi tr ton t iu kin ( ? : ) , n
c thc hin t phi sang tri. S kt hp ton t theo th t i vi cc ton t c cng
u tin. V vy, trong v d ny B s cng vi A v sau ly tng A+B tr cho C:
A+B-C
Khi ton t c u tin khc nhau, th ton t c u tin cao s thc hin trc. Trong
v d tip theo, B s chia cho C (ton t chia c u tin cao hn), v sau kt qu s c
cng thm A:
A+B/C
Du ngoc c th s dng thay i u tin ca ton t, v d sau A s cng vi B ri
sau ly tng chia cho C:
(A+B)/C // khng ging vi A+B/C
4.2.3
S dng s nguyn trong biu thc
S nguyn c th s dng nh mt ton hng trong biu thc. Mt s nguyn c th biu

din nh l:
Mt s nguyn khng du, khng c s (v d: 12,).
Mt s nguyn khng du, c c s (v d: d12, sd12,).
Mt s nguyn c du, c c s (v d: 16d12,16sd12,).
S nguyn c hiu l c du nu gia du nhy n ' v k t m t c s c thm k t s

hoc S.
Mt gi tr ph nh (c du tr trc) ca mt s nguyn khng ch r c s (v d: -12),
s c nh gi khc vi mt s nguyn ch r c s (v d: -'d12) nh sau:
Mt gi tr ph nh ca s nguyn, khng ch r c s, s c nh gi nh l mt s
khng du gm hai phn: du v gi tr. V d:
integer IntA = -12;
// phn du l '-', phn gi tr l 12 => l s m 12

// biu din trong Verilog l: 100 ...000 1100 (32bit)
Mt gi tr ph nh ca s nguyn khng du, c c s (v d: -4'd12) s c nh gi

nh l mt gi tr khng du. V d:
integer IntA = -'d 12; // l s khng du, c gi tr -12=>l s b 2 (32bit) ca 12
= 111111 0100(32bit)=2 31+230+..+25+24+ 4 = 232-12 =4294967284
V d 4.1 ch ra 4 cch vit biu thc "-12 chia 3". Ch rng c hai gi tr "-12" v
"-'d12" c nh gi l ging nhau v 2 thnh phn bit, nhng trong biu thc "-'d12"
khng cn c nh danh nh l mt s ph nh c du.
V d 4.1
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integer IntA;
IntA = -12 / 3;
// kt qu l -4.
IntA = -'d 12 / 3;
// kt qu l 1431655761.
IntA = -'sd 12 / 3;
// s c du m 12 (1000000 1100-32bit)=>kt qu l
-4.
IntA = -4'sd 12 / 3;
// 4'sd12 l mt s c du 4-bit bng 1100 = -4,

// vy (-4'sd12)= -(-4) = 4 => kt qu l 1.
4.2.4
Th t tnh ton trong biu thc
Ton t phi thc hin theo cc quy tc kt hp trong khi nh gi mt biu thc nh c
miu t trong Mc 4.2.2. Tuy nhin, nu kt qu cui cng ca biu thc c th c pht hin
sm hn, th ton b biu thc khng cn c nh gi ht. iu ny gi l ngn mch (shortcircuiting) mt nh gi biu thc, vic ngn mch nh gi mt biu thc xy ra khi trong biu
thc dng cc ton t n (&, |, ) thay v ton t i (&&, ||).
V d 4.2
Reg regA, regB, regC, result;
Result = regA&(regB|regC)
Nu gi tr ca regA l 0 th kt qu ca biu thc c pht hin l 0 m khng cn tnh
ton gi tr ca biu thc con (regB|regC).
4.2.5
Ton t s hc (+, -, *, /, %, **, +, -)
Ton t hai ngi c a ra trong Bng 4.5

Bng 4.5 Ton t hai ngi
a+b
a cng b
a-b
a tr b
a*b
a nhn b
a/b
a chia b
a%b
a chia b ly d
a**b
a ly tha b
Php chia: Trong php chia s nguyn, cn phn tch phn s khi mu s l s 0. i
vi php chia v php chia ly phn nguyn (/), nu ton hng th 2 l 0 th kt qu ca ton b
biu thc phi l x. Trong php chia ly phn d (%), v d y%z, cho ra kt qu l phn d
khi ly y chia cho z, v vy khi z = 0 th kt qu chnh l y, khi kt qu ca php chia ly d
c gn bng ton hng u tin.
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Bng 4.6 Ton t chia
Biu thc
Kt qu
Ch thch
10%3
10 chia 3 d 1
12%3
12 chia 3 khng d
-10%3
-1
Du ca kt qu l du ca ton hng u tin
11%-3
Du ca kt qu l du ca ton hng u tin
Php ly tha: Nu mt trong hai ton hng i vi ton t ly tha l s thc, th kt
qu cng l s thc. Kt qu ca ton t ly tha l khng xc nh nu ton hng th nht l 0

v ton hng th hai khng dng, hoc nu ton hng th nht l s m v ton hng th hai
khng l mt s nguyn. Nu c hai ton hng ca ton t ly tha l s thc th cc loi kt qu
c th hin trong phn 4.5.1v 4.6.1. Kt qu l bx nu ton hng th nht l 0 v ton
hng th hai l mt s m. Kt qu l 1 nu ton hng th 2 l 0. Trong tt c cc trng hp,
ton hng th hai ca ton t ly tha phi c xem l na xc thc.
Nhng iu ny s c minh ha trong Bng 4.7. v v d trong Bng 4.8.
Bng 4.7 Ton t ly tha
Ton hng 1(op1) m <-1
Ton hng 2 (op2)
dng
op1**op2
0
-1
dng > 1
op2 l chn ->-1

op2 l l ->1
1
op1**op2
op2 l chn ->-1

op2 l l ->1
bx
Bng 4.8 Ton t chia ly d v ly tha

-4d12%3
-4d12 c gi tr l 1
3**2
3*3
2**3
2*2*2
2**0
Bt k s no ly tha 0 cng bng 1
2.0**-3sb1
0.5
2.0 l s thc, nn kt qu cng l s thc
2**-3sb1
2**-1=1/2, c phn nguyn l s 0
0**-1
bx
0 ly tha s m l mt s khng xc nh
9**0.5
3.0
Kt qu l mt s thc
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9.0**(1/2)
1.0
kt qu l 0
-3.0**2.0
9.0
Kt qu l mt s thc
Ton t s hc mt ngi: Ton t ny c quyn u tin cao hn i vi ton t nh
phn, ton t mt ngi c a ra trong Bng 4.7

Bng 4.7 Ton t s hc mt ngi
+m
Ton t mt ngi cng m
-m
Ton t mt ngi tr m
i vi ton t s hc, nu bt k ton hng no c gi tr bit l khng xc nh X v tr

khng cao Z th kt qu chung ca biu thc phi l X.
4.2.6
Biu thc s hc vi tp thanh ghi (regs) v s nguyn (integer)
Mt gi tr c gn cho mt bin reg hoc net c xem nh l mt gi tr khng du, nu

khng, bin reg hoc net phi c khai bo r rng l c du. Mt gi tr c gn cho mt
bin integer, real hoc realtime, c xem nh l mt gi tr c du. Mt gi tr c gn
cho bin time c xem nh l mt gi tr khng du. Gi tr c du s s dng mt biu din
hai thnh phn, ngoi tr khi chng c gn cho bin real v realtime th gi tr s s dng
biu din du chm ng. S chuyn i gia gi tr c du v khng du s gi nguyn s biu
din, ch thay i s th hin.
Bng 4.9 a ra cch gii thch mi loi d liu trong ton t s hc:
Bng 4.9 Loi d liu trong ton t s hc
Loi d liu
Gii thch
net khng du
Khng du
net c du
C du, b 2
reg khng du
Khng du
reg c du
C du, b 2
integer
C du, b 2
time
Khng du
real, realtime
C du, du chm ng
Theo V d 4.3 s cho thy nhiu cch khc nhau chia tr 12 chia 3- s dng d
liu loi integer v reg trong biu thc.
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V d 4.3
integer intA;
reg [15:0] regA;
reg signed [15:0] regS;
intA = -4'd12;
// kt qu ca biu thc l -4,
regA = intA / 3; // intA l d liu loi integer, regA bng 65532

regA = -4'd12;
// regA bng 65524
intA = regA / 3; // Kt qu ca biu thc 21841,

// regA l d liu loi reg
intA = -4'd12 / 3; // kt qu ca biu thc l 1431655761.
// -4'd12 thc t l mt d liu loi reg 32-bit
regA = -12 / 3;
// kt qu ca biu thc l -4,

//-12 thc t l mt d liu loi integer.
regS = -12 / 3;
// kt qu ca biu thc l -4, regS l mt reg c du
regS = -4'sd12 / 3;
// kt qu ca biu thc l 1. -4'sd12 l 4.

// Theo lut chia s nguyn ly phn d 4/3==1.
4.2.7
Ton t quan h (>, <, >=, <=)
Bng 4.10 lit k v nh ngha ton t quan h

Bng 4.10 Ton t quan h
a<b
a nh hn b
a>b
a ln hn b
a<=b
a nh hn hoc bng b
a>=b
a ln hn hoc bng b
Mt biu thc s dng nhng ton t quan h ny s c trng gi tr l 0 nu quan h l

sai, hoc c gi tr l 1 nu n l ng. Nu mi ton hng trong mt ton t quan h cha gi
tr khng xc nh (x) hoc gi tr tr khng cao (z), th kt qu s l mt bit c gi tr khng xc
nh (x).
Khi mt hoc c hai ton hng ca mt ton t quan h l khng du, biu thc c hiu
nh l so snh gia hai gi tr khng du. Nu ton hng khng bng nhau v chiu di bit,
th ton hng c s bit nh hn s thm bit 0, c di bng ton hng c s bit ln hn.
Khi c hai ton hng l c du, th hiu thc s c hiu nh l so snh gia hai gi tr c
du. Nu ton hng khng bng nhau v chiu di bit, th ton hng c s bit nh hn s thm
bit du, c di bng ton hng c s bit ln hn.
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Nu mt ton hng l s thc th ton hng khc s c chuyn i v dng s thc v
biu thc c hiu nh l mt so snh gia hai gi tr s thc.
Tt c cc ton t quan h s c u tin ging nhau. Ton t quan h s c u tin
thp hn so vi ton t s hc.
V d 4.4
V d sau s minh ha vic thc thi cc lut v u tin:
a<foo 1
// biu thc ny ging vi biu thc a<(foo - 1)
Nhng . . .
foo-(1<a)
// biu thc ny khng ging vi biu thc foo-1<a
Khi foo-(1<a) c tnh ton, biu thc quan h s c tnh ton u tin, v sau hoc
l 0, hoc l 1 s c tr bi foo. Cn khi foo-1<a c tnh ton th gi tr ca ton hng foo
s tr i 1 sau em so snh vi a.
4.2.8
Ton t so snh bng (==, !=, ===, !==)
Ton t so snh bng c u tin thp hn so vi ton t quan h. Bng 4.11 lit k v
nh ngha ton t so snh bng
Bng 4.11 Ton t so snh bng
a===b
a bng b, bao gm c x v z
a!==b
a khng bng b, bao gm c x v z
a==b
a bng b, kt qu l khng xc nh nu gp bin x hoc z
a!=b
a khng bng b, kt qu l khng xc nh nu gp bin x hoc z
C bn ton t so snh bng s c u tin ging nhau. Bn ton t ny so snh tng bit
ca cc ton hng. Ging nh ton t quan h, kt qu s l 0 nu so snh sai v 1 nu so snh
ng.
Nu ton hng khng bng nhau v chiu di bit v nu mt hoc c hai ton hng l khng
du, th ton hng c s bit nh hn s thm bit 0 vo trc, cho bng kch thc ca ton
hng ln hn. Nu c hai l c du th ton hng c s bit nh hn s thm bit du vo trc,
cho bng kch thc ca ton hng c s bit ln hn.
Nu mt ton hng l mt s thc, th ton hng cn li s chuyn v kiu s thc v biu
thc c xem nh l php so snh gia hai s thc.
Trong ton t == v !=, nu ton hng l khng xc nh (x) hoc tr khng cao (z) th quan
h l khng xc nh, v kt qu s l mt bit c gi tr khng xc nh (x).
Trong ton t === v !==, s so snh s hon thnh nh l mt cu lnh case. Bit x hoc z
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trong ton hng s c so snh v s cho kt qu l bng nu ging nhau. Kt qu ca ton
t s l mt gi tr xc nh 0 hoc 1.
4.2.9
Ton t logic (&&, ||, !)
Ton t logic and (&&) v or (||) l ton t logic lin kt. Kt qu ca s tnh ton so
snh logic s l 1, 0 hoc x nu kt qu khng r rng. u tin ca && ln hn || v c hai
c u tin thp hn ton t quan h v ton t so snh bng. Khi s dng hai ton t ny th
tt c cc biu thc con trong biu thc u c tnh ton (khng c s ngn mch nh gi
mt biu thc).
Ton t logic th 3 l ton t nghch o logic 1 ngi (!). Ton t nghch o chuyn i
ton hng khng phi s 0 hoc 1 thnh s 0 v chuyn s 0 hoc sai thnh 1. Kt qu gi tr
ng khng r rng s l x.
V d 4.5
V d 1: Nu reg alpha gi gi tr integer 237 v beta gi gi tr l 0, th v d cho php
thc thi nh m t:
regA=alpha && beta
//regA c ci t l 0
regB =alpha || beta
//regB c ci t l 1
V d 2: Biu thc cho php thc thi mt ton t logic v ba biu thc con m khng
cn bt k du ngoc n no
a < size -1 && b != c && index != lastone
Tuy nhin, khuyn khch s dng du ngoc n lm cho biu r rng hn v u
tin, nh cch vit trong v d di y:
(a < size -1) && (b != c) && (index != lastone)
V d 3: Thng thng s dng ton t ! trong mt cu trc nh:
if(!inword)
// kim tra nu inword == 0
Trong mt vi trng hp, cu trc trn lm cho ngi c chng trnh kh hiu hn
cu trc: if (inword ==0).
4.2.10
Ton t thao tc trn bit (&, |, ^, ~, ~^, ^~)
Ton t thao tc trn bit s thc thi thao tc trn tng bit ca ton hng, y l ton t kt
hp tng bit trn mi ton hng, vi bit tng ng trn ton hng kia, tnh ton ra 1 bit kt
qu. Cc bng t 4-12 n 14-16 s cho thy kt qu mi php ton c th trn bit.
Bng 4.12 Ton t &
&
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1
Bng 4.13 Ton t |

|
^~, ~^
Bng 4.14 Ton t ^
Bng 4.15 Ton t ^~,~^
Bng 4.16 Ton t ~

~
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z
Khi cc ton hng khng bng nhau v chiu di, th ton hng ngn hn s thm bit 0 vo
v tr bit c ngha nht (MSB).
4.2.11 Ton t gim

Ton t gim mt ngi s thc hin mt ton t trn bit, trn mt ton hng n
c kt qu l mt bit n.
Cc ton t gim gm c: & (and), ~& (nand), | (or), ~| (nor), ^ (xor), ~^ (xnor).
thc hin ton t gim and, or, xor :
Bc th nht, ton t s p dng ton t gia bit u tin vi bit th hai ca ton hng,
s dng cc bng logic t 4-17 n 4-19.
Bc th hai v cc bc con tun t tip theo, s p dng ton t gia 1 bit kt qu
ca bc pha trc vi bit tip theo ca ton hng, s dng cc bng logic trn.
Vi cc ton t gim nand, nor, xnor, kt qu s tnh ton bng cch o kt qu ca
ton t gim and, or, xor tng ng.
Bng 4.17 Ton t gim &
&
Bng 4.18 Ton t gim |
Bng 4.19 Ton t gim ^

^
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1
Bng 4.20 cho thy kt qu ca vic p dng ton t gim trn cc ton hng khc nhau.
Bng 4.20 Ton t gim trn cc ton hng khc nhau.
Ton hng
&
~&
~|
~^
Ch thch
4b0000
Tt c cc bit l 0
4b1111
Tt c cc bit l 1
4b0110
S chn l 1
4b1000
S l l 1
4.2.12 Ton t dch (>>, <<, >>>, <<<)

y l hai loi ton t dch, ton t dch logic (<< v >>), v ton t dch s hc (<<< v
>>>). Quy tc hot ng ca cc loi ton t ny nh sau:
Ton t dch tri: << v <<<, s dch ton hng bn tri ca chng sang tri mt s v tr
bit c a ra trong ton hng bn phi. Trong c hai trng hp, bit v tr trng s
c in vo bng s 0.
Ton t dch phi: >> v >>>, s dch ton hng bn tri ca chng sang phi mt s
v tr bit c a ra trong ton hng bn phi.
Trong ton t dch phi logic >>: s in vo v tr bit trng l bit 0.
Trong ton t dch phi ton hc >>>: s in vo v tr bit trng s 0 nu kt qu

l loi khng du, ngc li, nu kt qu l loi c du, n s in vo v tr bit trng,
gi tr bit c ngha nht ca ton hng bn tri.
Nu ton hng bn phi c dng gi tr x hoc z, th kt qu s khng xc nh (x). Ton

hng bn phi lun lun c xem nh l mt s khng du v khng c nh hng n
du ca kt qu. Du ca kt qu c xc nh bng ton hng bn tri v s d ca
biu thc nh m t trong Mc 4.6.1.
V d 4.6
V d 1: Trong v d ny, thanh ghi result c gn gi tr nh phn 0100, do dch gi tr
nh phn 0001 sang tri hai v tr v in s 0 vo v tr trng:
module shift;
reg [3:0] start, result;
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initial begin
start = 1;
result = (start << 2);
end
endmodule
V d 2: Trong v d ny, thanh ghi result c gn gi tr nh phn 1110, l do dch
gi tr nh phn 1000 sang phi hai v tr v in bit du vo v tr trng:
module ashift;
reg signed [3:0] start, result; // khai bo s c du
initial begin
start = 4'b1000;
result = (start >>> 2);
end
endmodule
4.2.13
Ton t iu kin (?:)
Ton t iu kin, cn gi l ton t tam phn, s c quyn lin kt v xy dng s dng

ba ton hng ngn cch bi hai ton t trong dng c a ra trong c php 4-1:
C php 4-1
conditional_expression ::= expression1 ? { attribute_instance } expression2 : expression3
expression1 ::= expression
Vic nh gi ton t iu kin s bt u bng vic so snh gi tr logic ca biu thc
1(expression1) vi s 0, c cc trng hp nh sau:
Nu iu kin nh gi l sai (0), th biu thc 3 (expression3) s c tnh ton v s
dng kt qu cho kt qu ca biu thc iu kin (conditional_expression).
Nu iu kin nh gi l ng (1), th biu thc 2 (expression2) s c tnh ton v s
dng kt qu cho kt qu ca biu thc iu kin.
Nu iu kin nh gi l gi tr khng xc nh (x hoc z), th c biu thc 2 v biu
thc 3 s c tnh ton, v kt qu s c kt hp, bit ti bit s dng Bng 4.21
tnh ton kt qu cui cng.
Ngoi ra:
Nu biu thc 2 v biu thc 3 khng phi l s thc, trong trng hp ny kt qu l 0.
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Nu kch thc ca biu thc 2 v biu thc 3 khc nhau, ton hng ngn hn s tng
chiu di cho bng ton hng di v thm s 0 vo bn tri (th t cao hn).
Bng 4.21 Ton t iu kin
?:
V d 4.7
Theo v d ny s c 3 trng thi bus u ra minh ho vic s dng ton t iu kin
thng thng.
wire [15:0]busa=drive_busa?data:16'bz;
Bus data s c li vo busa khi bit drive_busa l 1, cn khi bit drive_busa l 0 th
data s nhn 16'bz . Nu bit drive_busa khng xc nh, th mt gi tr khng xc nh s
c li vo busa, ni cch khc busa khng xc nh.
4.2.14
Ton t ghp ni ({}) v Ton t lp ({{}})
4.2.14.1
Ton t ghp ni {}
L kt qu ca vic ni cc bit t mt hay nhiu biu thc li vi nhau. Ton t ghp ni s

dng k hiu ngoc nhn ({}) v dng du phy (,) ngn cch cc biu thc.
Mt s hng s khng xc nh kch thc, s khng c php s dng trong ton t ghp
ni. l v kch thc ca mi ton hng trong ton t ghp ni, cn phi tnh ton cho ph
hp vi kch thc ca kt qu ton t ghp ni.
V d 4.8
V d ny s ghp ni bn biu thc:
{a, b[3:0], w, 3b101}
N c c lng cho php trong v d:
{a, b[3], b[2], b[1], b[0], w, 1b1, 1b0, 1b1}
4.2.14.2
Ton t lp {{}}
Ton t lp c th ng dng kt ni nh l mt ton t nhn bn (khi nim lp v nhn

bn l tng ng), mt biu thc nhn bn (hay lp) gm 2 thnh phn: mt l biu thc s
lng nhn bn v hai l biu thc c nhn bn, v d:
{5{v}}
// ton hng v c lp vi s lng 5 ln, kt qu l {v,v,v,v,v}
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Vi biu thc s lng nhn bn l mt biu thc khng m, khng z, v khng x th ton
t c gi l ton t nhn bn hng. Cc du ngoc nhn c lng vo nhau v n biu
th mt kt ni nhiu gi tr nhn bn vi nhau trong php ton kt ni. Khng ging nh
ton t kt ni, biu thc bao gm ton t lp khng c nm bn tri php gn v khng
c kt ni vi cng output hoc inout.
V d:
y l v d cho ton t nhn bn bn ln gi tr w:
{4{w}}
// tp cc gi tr ging nhau {w, w, w, w} (lp 4 ln)
y l mt v d cho ton t nhn bn hp l :

{1bx{1b0}}
V d sau minh ha ton t nhn bn lng vo ton t kt ni:
{b, {3{a, b}}}
// tp cc gi tr {b, a, b, a, b, a, b}
Ton t nhn bn c th c hng s nhn bn l s 0. iu ny c dng lm tham bin

cho chng trnh. Mt php nhn bn vi hng s nhn bn l s 0, c tnh l c 1 s 0
hoc b qua, v d:
B={ 5{ 0{w} } };// tng ng vi: B={ 5{0}} = {0,0,0,0,0} => hp l
C={{0{w}}};
// tng ng vi: C={ {0} } => khng hp l v s 0 xut hin 1 mnh

// trong ton t kt ni
Ton t nhn bn s tip cn ch vi kt ni, m ton hng c kt ni vi kch thc dng.

V d 4.9
parameter P = 32;
assign b[31:0]={ { 32-P{1b1}}, a[P-1:0] };
// Hp l cho tt c P t 1 ti 32
assign c[31:0] = { {{32-P{1b1}}}, a[P-1:0] }; /*Khng hp l cho P=32 bi v s 0

nhn bn xut hin mt mnh trong ton t kt ni*/
initial
$displayb({32-P{1b1}}, a[P-1:0]); // Khng hp l cho P=32
Khi mt biu thc nhn bn c tnh ton, ton hng s tnh ton mt cch chnh xc
thm ch nu ton t nhn bn l s 0.
V d:
Result = {4{func(w)}}
S tnh ton nh l :
y = func(w)
Result = {y, y, y, y}
4.3 Ton hng

C mt s loi ton hng c th c ch r trong cc biu thc. Loi n gin l mt tham
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chiu n mt net, bin, hoc tham s, dng hon chnh ca n, ch l tn ca net, bin,
hoc tham s c a ra. Trong trng hp ny, tt c cc bit to thnh gi tr ca net, bin
hoc tham s c s dng nh ton hng.
Nu mt bit duy nht ca mt bin vector net, vector reg, integer, hoc time, hoc tham s
c yu cu, th bit c gi l ton hng bit- select. Ton hng part-select s c s dng
tham chiu ti mt nhm cc bit gn nhau trong bin vector net, vector reg, integer hoc time
hoc tham s.
Mt mng cc yu t hoc bit-select hoc part-select hoc bt k mng cc phn t c th
c tham chiu nh l mt ton hng. Mt ton t kt ni ca mt ton hng khc (bao gm
c kt ni lng nhau) c th c xem nh l mt ton hng. Mt hm cng l mt ton hng.
4.3.1
Vector bit-select v part-select addressing
Bit-select: Trch ra mt bit ring bit t bin vector net, vector reg, integer, hoc time, hoc
parameter. Cc bit c th c nh a ch bng mt biu thc. Nu mt bit-select nm ngoi
gii hn hoc bit-select l x hoc z, th gi tr tr v c tham chiu s l x. Mt bit-select
hoc part-select ca mt gi tr v hng, hoc ca mt bin, hoc tham s thuc loi real hoc
realtime, s khng hp l.
Part-select: Mt s bit lin k nhau trong mt bin vector net, vector reg, integer, hoc time,
hoc tham s c th nh a ch, c gi l mt part-select. C hai loi part-select, part-select
hng s v part-select ch s. Part-select hng s ca mt vector net hoc reg c a ra theo
c php bn di:
Vect [msb_expr: lsb_expr]
C msb_expr v lsb_expr s l biu thc s nguyn khng i, gia hai biu thc ny c
du : ngn cch, biu thc u c a ch c ngha hn biu thc th hai.
Part-select ch s ca mt bin vector net, vector reg, integer hoc time, hoc tham s c
a ra theo c php bn di:
// khai bo hai vector reg
reg [15:0] big_vect;
reg [0:15] little_vect;
// cc c php part-select:
(a) big_vect[lsb_base_expr +: width_expr]
(b) little_vect[msb_base_expr +: width_expr]
(c) big_vect[msb_base_expr -: width_expr]
(d) little_vect[lsb_base_expr -: width_expr]
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Trong msb_base_expr v lsb_base_expr l hai biu thc s nguyn, v width_expr l
mt biu thc s nguyn dng khng i, msb_base_expr v lsb_base_expr c th thay i
trong thi gian chy, msb_base_expr v lsb_base_expr xc nh a ch bit bt u, width_expr
l s lng bit tham chiu ca part-select. Trong hai c php (a) v (b), s dng du +: phn
cch, bit c chn bt u t base v tng dn n bit th (width-1). Hai c php (c) v (d), s
dng du -: phn cch, bit c chn bt u t v tr base v gim dn n bit (width+1).
Mt part-select ca bt k loi no c phm vi a ch nm ngoi vng a ch ca net,
bin reg, integer, time hoc parameter, hoc part- select m c gi tr x hoc z, th chng s
c gi tr x khi c v s khng nh hng n d liu lu tr khi ghi. Part-select nm ngoi
phm vi cc b ny, s tr v gi tr x cho cc bit nm ngoi phm vi khi c v ch nh hng
n cc bit trong phm vi khi ghi.
V d 4.10
reg [31: 0] big_vect;
reg [0 :31] little_vect;
reg [63: 0] dword;
integer sel;
big_vect[ 0 +: 8]
// == big_vect[ 7 : 0]
little_vect[ 0 +: 8]
// == little_vect[0 : 7]
big_vect[15 -: 8]
// == big_vect[15 : 8]
// c php (c)
little_vect[15 -: 8]
// == little_vect[8 :15]
// c php (d)
dword[8*sel +: 8]
// bin part-select vi rng c nh
4.3.2
// c php (a)
// c php (b)
a ch mng v phn t nh
Vic khai bo mng v b nh (mng thanh ghi mt chiu) c tho lun Mc 3.7.
Trong phn ny s i vo vn nh a ch mng.
V d 4.11
Khai bo mt b nh 1024 t 8 bit:
reg [7:0] mem_name[0:1023];
C php cho a ch b nh s bao gm tn vng nh v biu thc a ch, theo nh dng
sau:
mem_name[addr_expr];
Trong addr_expr l mt biu thc nguyn bt k; v vy mt b nh gin tip c th
ch ra nh l mt biu thc n.V d sau minh ha cho b nh gin tip:
mem_name[mem_name[3]];
y, t nh a ch mem_name[3] s dng lm biu thc cho vic truy cp b nh
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ti a ch mem_name[mem_name[3]].
Cng ging nh ton t bit-select, a ch trong vng khai bo b nh, mi l biu thc a
ch c nh hng. Nu ch s nm bn ngoi vng gin hn a ch b nh, hoc nu bt k bit
no trong a ch l z hoc x, th gi tr tham chiu s l x.
V d 4.12
V d khai bo mt mng hai chiu [256:256] phn t 8 bit v mt mng ba chiu
[256:256:8] cc phn t mt bit:
reg [7:0] twod_array[0:255][0:255];
wire threed_ array[0:255][0:255][0:7];
C php sau truy xut n mng, bao gm tn ca b nh hoc mng, v biu thc s
nguyn cho mi chiu ca mng:
twod_array[addr_expr][addr_expr]
threed_array[addr_expr][addr_expr][addr_expr]
Nh cc v d trc, addr_expr l mt biu thc s nguyn bt k. Trong mng hai chiu
twod_array, truy cp n vector 8 bit, trong khi mng ba chiu threed_array truy xut n
cc bit n.
biu din bit-select hoc part-seclect ca phn t mng, t mong mun s c chn
u tin, bng cch cung cp a ch cho mi chiu. Mt la chn bit-select v part-select s
nh a ch ging nh l bit-select v part-select net v reg.
V d 4.13
twod_array[14][1][3:0]
// Truy xut 4 bit thp ca t c truy cp
twod_array[1][3][6]
// Truy xut bit th 6 ca t c truy cp
twod_array[1][3][sel]
// S dng bin bit-select
threed_array[14][1][3:0]
// Khng hp l
4.3.3
Chui
Ton hng chui s c xem nh hng s, bao gm mt chui tun t cc k t ASCII 8

bit. Bt k ton t Verilog HDL no cng c th thao tc trn ton hng chui. Ton t s
xem bn trong chui nh l mt gi tr s ring l.
Khi mt bin ln hn yu cu gi gi tr cho vic gn, ni dung sau khi gn s c
b sung s 0 vo bn tri. iu ny th hp vi vic b sung xy ra trong php gn nhng
gi tr khng phi chui.
V d 4.14 Theo v d ny, ta khai bo mt bin chui c ln cha 14 k t v gn
cho n mt gi tr. V d s thao tc trn chui s dng ton t ghp ni.
module string_test;
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reg [8*14:1]stringvar;
initial begin
stringvar="Hello world";
$display("%s is stored as %h", stringvar, stringvar);
stringvar={stringvar,"!!!"};
$display("%s is stored as %h", stringvar, stringvar);
end
endmodule
Kt qu m phng cho on chng trnh trn:
Hello world is stored as 00000048656c6c6f20776f726c64
Hello world!!! is stored as 48656c6c6f20776f726c64212121
4.3.3.1 Ton t chui

Cc ton t x l chui thng dng nh sao chp, ni chui, so snh,... c h tr bi
ton t Verilog HDL. Ton t sao chp cung cp bng mt php gn. Ton t ni chui
cung cp bng ton t ghp ni. Ton t so snh c cung cp bng ton t so snh bng.
Khi thao tc trn cc gi tr trong cc vector reg, cc reg phi c t nht 8*n bit (vi n l s
k t ASCII) trong th t ph hp vi m 8 bit ASCII.
4.3.3.2 Gi tr chui m v vn tim n

Khi chui c gn cho mt bin, gi tr lu tr s thm vo bn tri gi tr s 0. S thm
vo ny c th nh hng n kt qu ca ton t so snh v ton t ni chui. Ton t so snh
v ni chui s khng phn bit c gia s 0 do kt qu ca vic thm vo v s 0 trong chui
chnh thc (\0, ASCII NUL). V d 4.15 s minh ha vn xy ra:
V d 4.15
reg [8*10:1]s1,s2;
// hai chui s1 v s2 c th cha c 10 k t
initial begin
s1="Hello";
// ton t gn s thm vo trc 10 s 0
s2=" world!";
// ton t gn s thm vo trc 6 s 0
if ({s1,s2}=="Hello world!")
$display("strings are equal");
end
Vic so snh trong V d 4.15 khng cho kt qu nh mong mun, bi v trong qu trnh
gn vo bin chui, gi tr thm vo cc bin s1, s2 c lu vo nh sau:
s1 = 000000000048656c6c6f
s2 = 00000020776f726c6421
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Ton t ghp ni s1 v s2 bao gm c cc gi tr s 0 thm vo, kt qu cho ta gi tr:
{s1,s2} = 000000000048656c6c6f00000020776f726c6421
Bi v chui Hello world! khng bao gm s 0 thm vo, php so snh s theo m t sau:
4.3.3.3 Chui rng

Chui rng ("") s c xem nh l gi tr ASCII NUL (\0), c gi tr l 0 v n khc
vi chui (0).
4.4
Biu thc tr hon thi gian ti thiu, trung bnh, v ti a
Biu thc tr hon trong ngn ng Verilog HDL thng thng c ba gi tr, c m t bi
ba biu thc ngn cch nhau bi du hai chm (:) v gp li vi nhau bng du ngoc n (()).
iu theo th t th hin cc gi tr i din cho thi gian ti thiu, trung bnh v ti a
(min:typ:max). Ba gi tr ny cho php thit k cc chng trnh kim tra vi gi tr tr hon ti
thiu, trung bnh v ti a.
Cc gi tr th hin trong nh dng (min:typ:max) c th c s dng trong cc biu thc.
nh dng (min:typ:max) c th s dng bt k biu thc no.
C php min:typ:max c a ra theo c C php 4-2.
C php 4-2
constant_expression ::= constant_primary
| unary_operator { attribute_instance } constant_primary
| constant_expression binary_operator { attribute_instance }constant_expression
|
constant_expression
attribute_instance
constant_expression
constant_expression
constant_mintypmax_expression ::= constant_expression
| constant_expression : constant_expression : constant_expression
expression ::= primary
| unary_operator { attribute_instance } primary
| expression binary_operator { attribute_instance } expression
| conditional_expression
mintypmax_expression ::= expression
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| expression : expression : expression
constant_primary ::= (From A.8.4) number
| parameter_identifier [ [ constant_range_expression ] ]
| specparam_identifier [ [ constant_range_expression ] ]
| constant_concatenation
| constant_multiple_concatenation
| constant_function_call
| constant_system_function_call
| ( constant_mintypmax_expression )
| string
primary ::= number
| hierarchical_identifier [ { [ expression ] } [ range_expression ] ]
| concatenation
| multiple_concatenation
| function_call
| system_function_call
| ( mintypmax_expression )
| string
V d 4.16
V d 1: Cho thy biu thc nh ngha b ba duy nht ca gi tr tr hon. Trong biu
thc:
(a:b:c)+(d:e:f)
Gi tr nh nht l tng ca a+d, gi tr trung bnh l tng ca b+e, gi tr ln nht l
tng ca c+f.
V d 2: Th hin mt biu thc in hnh s dng gi tr theo nh dng min:typ:max:
val-(32'd50:32'd75:32'd100)
4.5
Biu thc di bit
Kim sot s lng bit c s dng trong vic tnh ton cc biu thc l rt quan trng nu
ph hp vi kt qu t c. Mt vi tnh hung c gii php n gin; v d, nu mt bit v
ton t c quy nh trn hai thanh ghi 16 bit, th kt qu s l mt gi tr 16 bit. Tuy nhin,
trong mt vi tnh hung, khng bit r rng l c bao nhiu bit c s dng trong vic tnh
ton biu thc, hoc kch c ca kt qu l bao nhiu.
V d, thc hin tnh ton php cng s hc ca hai thanh ghi 16 bit, cn s dng 16 bit,
hoc cn s dng 17 bit c th cha c bit trn? Cu tr li ph thuc vo loi thit b
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c m hnh v cch m thit b iu khin nh bit trn. Verilog HDL s dng di bit ca
ton hng, pht hin c bao nhiu bit c s dng trong qu trnh tnh ton biu thc. Cc
lut v di bit c a ra Mc 4.5.1. Trong trng hp ton t cng, di bit ca ton
hng ln hn s c s dng cho bin bn tri php gn.
V d 4.17
reg [15:0] a, b;
// thanh ghi 16 bit
reg [15:0] sumA;
// thanh ghi 16 bit
reg [16:0] sumB;
// thanh ghi 17 bit
sumA = a + b;
// biu thc tnh ton s dng 16 bit
sumB = a + b;
// biu thc tnh ton s dng 17 bit
4.5.1
Qui lut cho biu thc di bit
Cc lut qun l biu thc di bit c trnh bi r rng cc tnh hung thc t c
mt gii php t nhin.
S lng bit ca mt biu thc (cn gi l kch c ca biu thc) s c xc nh bng
ton hng c gi trong biu thc v ni dung ca biu thc a ra.
Mt biu thc t xc nh, l biu thc m di bit ca n c xc nh duy nht bi t
biu thc , v d, biu thc th hin gi tr tr hon.
Mt biu thc xc nh ton b, l biu thc m di bit ca n c xc nh bng
di bit ca biu thc v mt phn ca biu thc c lin quan khc. V d, kch c bit ca
biu thc bn phi php gn ph thuc vo t n v kch c ca biu thc bn tri.
Bng 4.22 th hin cch cc biu thc thng thng xc nh di bit ca kt qu biu
thc. Trong Bng 4.22, i, j v k l cc ton hng ca biu thc, v L(i) th hin di bit ca
ton hng i.
Ton hng nhn c th thc hin m khng mt bt k bit trn no bng cch gn kt qu
rng cha n.
Bng 4.22 Biu thc xc nh di bit ca kt qu biu thc
Biu thc l:
di bit
Ch thch
Hng s khng xc nh kch Bng di bit ca

thc
s integer (32 bit)
Hng s c kch thc xc nh Kch thc ca hng
i op j, vi op l:
+ - * / %
& | ^ ^~ ~^
i op j, vi op l : + - ~
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s
max (L(i),L(j))
L(i)
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i op j, vi op l:
===
!== 1bit
Ton hng c kch thc l max
== != > >= < <=

i op j, vi op l: && ||
1bit
(L(i),L(j))
Tt c cc ton hng t xc nh
i op j, vi op l:
1bit
& ~& | ~| ^ ~^ ^~ !
i op j, vi op l:
L(i)
Ton hng j t xc nh
>> << ** >>> <<<

i?j:k
// ton t iu kin
max(L(j),L(k)
Ton hng i t xc nh
{i,...,j}
L(i)+..+L(j)
i *(L(j)+..+L(k))
// ton t ghp ni
{i{j,..,k}} // ton t lp
4.5.2
V d minh ha vn v biu thc di bit
Trong sut qu trnh tnh ton mt biu thc, kt qu tm thi s ly kch c ca ton hng
ln hn (trong trng hp ton t gn, n cn bao gm c bn tri php gn). S thn trng
s ngn chn vic mt bit du trong qu trnh tnh ton. V d sau y m t cch di bit
ca ton t c th lm cho kt qu mt bit du.
V d 4.18
reg [15:0] a, b, answer;
// thanh ghi 16 bit
answer = (a+b ) >> 1;
// Mc ch tnh ton biu thc ny s khng thc thi ng
Mc ch y l ly a cng vi b, kt qu c th xy ra trn (bit nh bng 1) hoc khng

trn (bit nh bng 0), sau kim tra php cng c trn hay khng, dch phi tng thu c 1
bit lu li bit nh trong thanh ghi answer 16 bit.
Vn xy ra l, bi v tt c cc ton hng trong biu thc (a+b) u c rng 16
bit, nn biu thc (a+b) cho ra mt kt qu tm thi l mt gi tr 16 bit, v vy bit nh b
mt trc khi thc thi vic tnh ton ton t dch phi mt bit, do khng lu c bit nh.
Gii php l p buc biu thc (a+b) thc hin tnh ton s dng t nht 17 bit. V d thm
vo ton t cng mt s integer c gi tr 0, biu thc s tnh ton ng v n thc thi s
dng kch c bit l 32 bit ca bin integer. V d sau y s cho kt qu ng vi mc ch:
Answer = (a + b + 0) >> 1;
// s thc thi ng
Xt v d tip theo:
V d 4.19
module bitlength();
reg [3:0] a,b,c; // a, b, c l 4 bit
reg [6:0] d;
// d l 7 bit
initial begin
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a = 9; b = 8; c = 1;
$display("answer = %b", c ? (a&b) : d);
// v c=1 nn (a&b) c chn
end
endmodule
Cu lnh $display s hin th:
answer = 0001000
// 7 bit
Bng cch t n, biu thc a&b c chiu di l 4 bit, nhng bi v trong ni dung ca biu
thc iu kin, n s s dng di bit ln nht (Bng 4.2.2), vy nn biu thc a&b s c
di l 7, l di ca d.
4.5.3
V d minh ha v biu thc t xc nh
V d 4.20
reg [3:0] a;
reg [5:0] b;
reg [15:0] c;
initial begin
a = 4'hF;
b = 6'hA;
$display("a*b=%h", a*b);
c = {a**b};
// Kch thc ca biu thc t xc nh => bng 6
// biu thc a**b l t xc nh trong ton t kt ni {}
$display("a**b=%h", c);
c = a**b;
// Kch thc ca biu thc xc nh bi c
$display("c=%h", c);
end
Kt qu m phng ca v d ny:
a*b=16 // 'h96 b ct b cn 'h16 v kch thc ca biu thc l 6
a**b=1 // kch thc ca biu thc 4 bit (kch thc ca a)
c=ac61 // kch thc ca biu thc 16 bit (kch thc ca c)
4.6 Biu thc c du

iu khin du ca mt biu l rt quan trng to ra mt kt qu ph hp. Thm vo ,
tun theo cc lut trong cc mc t Mc 4.6.1 ti Mc 4.6.4, hai chc nng h thng s s
dng iu khin theo cc loi khun kh trong biu thc: $signed() v $usnigned(). Cc
hm ny s tnh ton cc biu thc u vo v tr v mt gi tr c cng kch c. Gi tr
ca biu thc u vo v c nh ngha bi cc hm:
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$signed
tr v mt gi tr c du
$unsigned
tr v mt gi tr khng du
V d 4.21
reg [7:0] regA, regB;
reg signed [7:0] regS;
regA = $unsigned(-4);
// regA = 8'b11111100
regB = $unsigned(-4'sd4);
// regB = 8'b00001100
regS = $signed (4'b1100);
// regS = -4
4.6.1
Qui nh cho nhng loi biu thc
Cc lut cho vic xc nh kt qu loi cho mt biu thc:

Loi biu thc ch ph thuc vo ton hng. N khng ph thuc vo v bn tri.
S thp phn l c du.
S c s l khng c du, ngoi tr trng hp c thm k hiu s c s dng trong c
s ch nh (nh l 4sd12).
Kt qu ca bit-select l khng du, bt chp ton hng.
Kt qu ca part-select l khng du, bt chp ton hng, thm ch nu part-select ch nh
ton b vector. V d:
reg [15:0] a;
reg signed [7:0] b;
initial
a = b[7:0];
// b[7:0] l khng du
Ku qu ca ton t kt ni l khng du, bt chp ton hng.

Kt qu ca ton t so snh (1,0) l khng du, bt chp ton hng.
Chuyn i t s thc sang s nguyn bng loi cng bc l c u.
Du v kch c ca ton hng t xc nh, c xc nh bi t ton hng v c lp vi yu
cu ca biu thc.
i vi ton hng khng t xc nh, p dng cc lut sau:
Nu bt k ton hng no l s thc, kt qu l s thc.
Nu bt k ton hng no l khng du, kt qu l khng du, bt chp ton t.
Nu tt c ton hng no l c du, kt qu l c du, bt chp ton t, ngoi tr
trng hp c ch r theo cch khc.
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4.6.2
Nhng bc nh gi mt biu thc
Cc bc tnh ton mt biu thc:

Xc nh kch c ca biu thc da trn cc chun v lut xc nh kch c ca biu thc
bn trn.
Xc nh du ca biu thc s dng cc lut Mc 4.6
Truyn li cc loi v kch thc ca biu thc (hoc t xc nh biu thc con tr xung
ton hng) xc nh theo ng cnh ca biu thc. Ni chung, ton hng xc nh theo
ng cnh ca mt ton t s ging loi v kch thc ca kt qu ton t. Tuy nhin, c 2
ngoi l:
Nu kt qu ca ton t l s thc v nu n c ton hng xc nh theo ng cnh m
khng phi s thc, th ton hng s i x nh th nu n l t xc nh, th n s
chuyn i sang s thc trc khi ton t c p dng.
Ton t quan h v ton t bng c ton hng, m khng hon ton l t xc nh
hoc khng hon ton l xc nh theo ng cnh. Ton hng s nh hng ln nhau nh
l nu chng l ton hng xc nh theo ng cnh, vi loi v kch thc ca kt qu
(kch thc ln nht ca 2 ton hng) xc nh theo chng. Tuy nhin, loi kt qu
thc s s lun l 1 bit khng du. Loi v kch thc ca ton hng s c lp vi phn
cn li ca biu thc v ngc li.
Khi truyn t ti mt ton hng n gin nh c nh ngha Mc 5.2 th ton
hng s chuyn i truyn t loi v kch thc. Nu mt ton hng c m rng th
n s ch m rng du nu loi truyn t l c du.
4.6.3
Nhng bc nh gi mt php gn
Cc bc tnh ton mt php gn:

Xc nh kch thc ca phn bn phi bng chun v lut xc nh kch thc ca php
gn.
Nu cn, m rng kch thc ca ton t bn phi, thc hin m rng bit du nu v
ch nu phn bn phi ca ton t l c du.
4.6.4
Tnh ton nhng biu thc ca hai s c du X v Z
Nu mt ton hng c du b thay i kch thc ti mt kch thc c du ln hn v gi

tr ca bit du l x, th gi tr ca kt qu s in thm Xs. Nu bit du l c gi tr l z, th
gi tr ca kt qu s in thm Zs. Nu gi tr du ca bt k bit no l x hoc z, th ton t
khng hp logic bt k, s c gi gi tr ca kt qu s l z v loi ph hp vi loi ca biu
thc.
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4.7 Nhng php gn v php rt gn
Nu chiu rng ca biu thc bn phi ln hn chiu rng ca biu thc bn tri trong php
gn, th MSBs ca biu thc bn phi s lun lun b loi b ph hp vi kch thc ca biu
thc bn tri. Qu trnh thc hin khng yu cu cnh bo hoc bo co bt k li no lin
quan n kch thc ca php gn khng ph hp hoc b ct ngn. Ct ngn bit du ca biu
thc c du s thay i du ca kt qu.
V d 4.22
V d 1:
reg
[5:0] a;
reg signed [4:0] b;

initial begin
a = 8'hff;
// sau khi gn, a = 6'h3f
b = 8'hff;
// sau khi gn, b = 5'h1f
end
V d 2:
reg
[0:5] a;
reg signed [0:4] b, c;

initial begin
a = 8'sh8f; // sau khi gn, a = 6'h0f
b = 8'sh8f; // sau khi gn, b = 5'h0f
c = -113;
// sau khi gn, c = 15
// 1000_1111 = (-'h71 = -113) b ct ngn cn ('h0F = 15)

end
V d 3:
reg
[7:0] a;
reg signed [7:0] b;

reg signed [5:0] c, d;
initial begin
a = 8'hff;
c = a;
// sau khi gn, c = 6'h3f b = -113;
d = b;
// sau khi gn, d = 6'h0f
end
4.8 Bi tp
1. Nu cc ton t thng dng v u tin ca chng?
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2. Nu th t tnh ton trong mt biu thc logic?
3. Cch s dng s nguyn trong biu thc?
4. C bao nhiu loi ton hng trong Verilog? M t c th tng loi?
5. Cc lut xc nh du cho kt qu ca mt biu thc?
6. Cc bc nh gi tr ca mt biu thc?
7. Cho a, b, c, d, e c khai bo nh sau:
reg [7:0] a, b; reg [8:0]c; reg [15:0] d;
nh gi tr ca cc biu thc sau:
a = 255; b = 255; c = a + b;
c = 9'b0 + a + b;
d={a,b};
c = &b;
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5 Chng 5. Cu trc phn cp v module

5.1
Cu trc phn cp
Ngn ng m t phn cng Verilog h tr cu trc phn cp bng cch cho php module
c nhng trong module khc, module cp cao hn to th hin ca module cp thp
hn v giao tip vi chng thng qua cc u vo, u ra v u vo-ra 2 chiu. Cc cng vo ra
c th l v hng hoc l vector.
Cu trc phn cp gip ngi thit k chia mt h thng thit k ra thnh cc module nh
hn d thit k v kim sot lung d liu trong qu trnh thit k.
Nh mt v d cho h thng module phn cp, hy xem xt mt h thng bao gm cc
bng mch in (PCBs).
5.2
Module
5.2.1
Khai bo module
Trong mc ny cung cp c php thng thng cho mt nh ngha module v c php cho
vic ci t module, cng vi mt v d v nh ngha module v ci t module.
Mt nh ngha module c bao gia bi hai t kha module v endmodule. Cc nh
danh km theo sau t kha module s l tn nh ngha ca module; danh sch cc ty chn
ca tham s c nh ngha, s ch r mt danh sch theo th t cc tham s ca module;
danh sch cc ty chn ca cng hoc khai bo cng c nh ngha, s ch r mt danh sch
theo th t cc cng ca module. Th t c s dng trong nh ngha danh sch cc
tham s v trong danh sch cng, c th c ngha trong vic ci t cc module. Cc nh
danh trong danh sch ny s khai bo li trong cc cu lnh input, output, v inout trong nh
ngha module. Khai bo cng trong danh sch khai bo cng s khng khai bo li trong thn
module. Cc mc ca module nh ngha ci to thnh module, v chng bao gm nhiu loi
khai bo v nh ngha khc nhau, nhiu trong s c gii thiu.
T kha macromodule c th dng thay th t kha module nh ngha mt module.
Mt qu trnh thc thi c th chn gii quyt module c nh ngha bt u vi th kha
macromodule khc nhau. C php khai bo module c cho trong c php 5-1:
C php 5-1
module_declaration ::=
{attribute_instance} module_keyword
module_identifier [module_parameter_port_list ]
list_of_ports ; { module_item }
endmodule
|{ attribute_instance } module_keyword
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module_identifier [module_parameter_port_list ]
[ list_of_port_declarations ] ; { non_port_module_item }
endmodule
module_keyword ::= module | macromodule
module_parameter_port_list ::= (From A.1.3
# ( parameter_declaration { , parameter_declaration } )
list_of_ports ::= ( port { , port } )
list_of_port_declarations ::= ( port_declaration { , port_declaration } ) | ( )
port ::= [ port_expression ] | . port_identifier ( [ port_expression ] )
port_expression ::= port_reference | { port_reference { , port_reference } }
port_reference ::= port_identifier [ [ constant_range_expression ] ]
port_declaration ::= {attribute_instance} inout_declaration
| {attribute_instance} input_declaration
| {attribute_instance} output_declaration
module_item ::= (From A.1.4)
port_declaration ;
| non_port_module_item
module_or_generate_item ::={ attribute_instance } module_or_generate_item_declaration
| { attribute_instance } local_parameter_declaration ;
| { attribute_instance } parameter_override
| { attribute_instance } continuous_assign
| { attribute_instance } gate_instantiation
| { attribute_instance } udp_instantiation
| { attribute_instance } module_instantiation
| { attribute_instance } initial_construct
| { attribute_instance } always_construct
| { attribute_instance } loop_generate_construct
| { attribute_instance } conditional_generate_construct
module_or_generate_item_declaration ::= net _declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| genvar_declaration
| task_declaration
| function_declaration
non_port_module_item ::=module_or_generate_item
|generate_region
| specify_block
| { attribute_instance } parameter_declaration ;
| { attribute_instance } specparam_declaration
parameter_override ::= defparam list_of_defparam_assignments ;
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V d 5.1 nh dng ca mt module chun
module tn_module (danh sch cc cng, nu c);
Khai bo port: input, output, inout;
Khai bo tham s: parameter
Khai bo cc loi d liu (d liu net, d liu bin, v d: wire, reg, integer)
Gi v gn c tnh (instantiate) module con (sub-module)
Pht biu gn s dng m hnh RTL (assign)
Pht biu gn qui trnh (always, initial)
Khai bo hm v tc v
endmodule (Khai bo kt thc module)
5.2.2
Module mc cao nht
Module mc cao nht (top-module) l module bao gm trong vn bn gc, nhng n hu

nh khng c mt cu lnh ci t no trong bt k mt module no khc. iu ny p dng
c khi module ci t to ra trong khi to m khng phi t n ci t. Mt m hnh phi
c t nht mt module mc cao nht.
5.2.3
Gi v gn c tnh mt module (instantiate)
Vic gi v gn c tnh module cho php mt module gi v gn c tnh mt module

khc ra s dng. Cc module khng c nh ngha lng nhau. Ni cch khc, mt
module c nh ngha s khng cha m t thit k ca mt module khc trong cp t kha
module-endmodule. Mt module c nh ngha lng trong mt module khc bng cch
gi v gn c tnh ca module ra s dng. Mt cu lnh gi v gn c tnh module s to
ra mt hoc nhiu bn sao ca module c nh ngha.
V d, mt module b m phi ci t module D_flip_flop to ra nhiu th hin ca Dflip-flop. C php 5-2 a ra c php chi tit cho vic gi v gn c tnh module.
C php 5-2
module_instantiation ::= (From A.4.1)
module_identifier [ parameter_value_assignment ]
module_instance { , module_instance } ;
parameter_value_assignment ::=
# ( list_of_parameter_assignments )
list_of_parameter_assignments ::=
ordered_parameter_assignment { , ordered_parameter_assignment }
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| named_parameter_assignment { , named_parameter_assignment }
ordered_parameter_assignment ::=
expression
named_parameter_assignment ::=
. parameter_identifier ( [ mintypmax_expression ] )
module_instance ::=
name_of_module_instance ( [ list_of_port_connections ] )
name_of_module_instance ::=
module_instance_identifier [ range ]
list_of_port_connections ::=
ordered_port_connection { , ordered_port_connection }
| named_port_connection { , named_port_connection }
ordered_port_connection ::=
{ attribute_instance } [ expression ]
named_port_connection ::=
{ attribute_instance } . port_identifier ( [ expression ] )
Vic gi v gn c tnh module c th cha mt lot cc c im k thut. N cho php
mt mng cc th hin c to ra. C php v ng ngha ca cc mng, th hin nh ngha
cho cc cng v cc cng c bn p dng tt cho cc module. Mt hoc nhiu th hin ca
module (bn sao nguyn bn ca module) c th a ra trong mt cu lnh gi v gn c tnh
module ring l.
Danh sch cc cng kt ni s cung cp ch cho module c nh ngha vi cng. Cc du
ngoc n lun lun cn thit. Khi mt danh sch cc cng kt ni, c a ra s dng theo
thc t phng thc cc cng kt ni, phn t u tin trong danh sch s kt ni vi cng u
tin trong khai bo cng trong module, phn t th 2 kt ni vi cng th 2 v c nh th. Mc
5.2.4.9 s tho lun r hn v cc lut kt ni cng vi cng.
Mt kt ni c th tham kho n gin ti mt bin hoc mt nh danh net, mt biu
thc, hoc mt khong trng. Mt biu thc c th s dng cung cp mt gi tr, ti mt
cng vo ca module. Mt cng kt ni trng s trnh by tnh hung ni m cng khng
kt ni.
Khi kt ni mt cng bng tn, mt cng cha c kt ni s ch ra bng cch b n ra
trong danh sch, hoc khng cung cp biu thc bn trong u ngoc (v d portname()).
V d 5.2
V d 1: V d ny minh ha mt mch (module cp thp) c iu khin bi mt
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dng sng n gin (module cp cao hn) ni m mch c ci t bn trong module
dng sng:
//module cp thp: module m t mt mch flip-flop nand
module ffnand (q, qbar, preset, clear);
output q, qbar;
//khai bo 2 net u ra cho mch
input preset, clear;
// khai bo 2 net u vo cho mch
// khai bo cng nand 2 u vo v cc kt ni vi chng

nand g1 (q, qbar, preset), g2 (qbar, q, clear);
endmodule
// module cp cao: dng sng m t cho flip-flop nand
module ffnand_wave;
wire out1, out2; //u ra t mch
reg in1, in2;
//bin iu khin mch
parameter d = 10;
// th hin ca mch ffnand, tn l "ff", v c t u ra ca cc kt ni IO bn trong
ffnand ff(out1, out2, in1, in2);
// nh ngh dng sng m phng mch
initial begin
#d in1 = 0; in2 = 1;
#d in1 = 1;
#d in2 = 0;
#d in2 = 1;
end
endmodule
V d 2: V d ny to ra 2 th hin ca module flip-flop ffnand c nh ngha trong v
d 1. N kt ni ch vi u ra q vo mt th hin v ch mt u ra qbar vo mt th
hin khc.
// dng sng m t kim tra nand flip-flop, khng c cng u ra
module ffnand_wave;
reg in1,in2;//bin iu khin mch
parameter d=10;
// to hai bn sao ca mch ff nand
// ff1 c qbar khng kt ni, ff2 c q khng kt ni
ffnand ff1(out1,,in1,in2),
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ff2(.qbar(out2), .clear(in2), .preset(in1), .q());
// nh ngh dng sng m phng mch
initial begin
#din1=0;in2=1;
#din1=1;
#din2=0;
#din2=1;
end
endmodule
5.2.4
Khai bo port
Cng cung cp mt phng tin kt ni cc m t phn cng bao gm module v cc

phn cng nguyn thy. V d, module A c th khi to module B, s dng cc cng kt ni
ph hp ti module A. Tn cc cng ny c th khc vi tn ca cc dy ni ni v cc bin
c ch ra trong nh ngha module B.
5.2.4.1 nh ngha port

C php cho cc cng v danh sch cng c a ra trong C php 5-3
C php 5-3
list_of_ports ::= (From A.1.3)
( port { , port } )
list_of_port_declarations ::=
( port_declaration { , port_declaration } )
|()
port ::=
[ port_expression ]
| . port_identifier ( [ port_expression ] )
port_expression ::=
port_reference
| { port_reference { , port_reference } }
port_reference ::=
port_identifier [ [ constant_range_expression ] ]
port_declaration ::=
{attribute_instance} inout_declaration
| {attribute_instance} input_declaration
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| {attribute_instance} output_declaration
5.2.4.2 Lit k port

Cng tham kho cho mi cng, trong danh sch cc cng bn trn ca mi khai bo
module c th l 1 trong s:
Mt nh danh n gin hoc nh danh b b qua (khai bo nhng khng dng).
Mt bit-select ca mt vector khai bo trong module
Mt part- select ca mt vector khai bo trong module
Mt ton t kt ni ca bt k phn no trong 3 loi trn.
Biu thc cng l ty chn bi v cng c th c nh ngha m khng cn bt k kt ni
no trong module. Khi mt cng c nh ngha, th khng c cng no khc c nh
ngha cng tn.
C hai loi cng module, loi u tin ch l cng biu thc, l loi cng ngm; loi th hai
l loi cng trc tip. Cng biu thc bao gm khai bo cc nh danh bn trong thn module
nh miu t trong Mc 5.2.4.3, v cng trc tip s dng kt ni vi cng ca module th hin
bng tn nh trong Mc 5.2.4.4. Tn cng kt ni s khng s dng cho cng ngm nh m s
s dng tn cng biu thc, nu cng biu thc khng l mt nh danh n gin hoc l nh
danh b b qua.
5.2.4.3 Khai bo port trong thn module

Mi cng nh danh trong mt cng biu thc, trong danh sch ca cc cng trong khai bo
module, cng s khai bo trong thn ca module nh mt trong cc khai bo: input, output hoc
inout (cng hai chiu). c th thm vo khai bo cc loi d liu khc cho cc cng t
th v d reg hoc wire.
C php cho vic khai bo cng a ra trong C php 5-4:
C php 5-4
inout_declaration ::=
inout [ net _type ] [ signed ] [ range ] list_of_port_identifiers
input_declaration ::=
input [ net _type ] [ signed ] [ range ] list_of_port_identifiers
output_declaration ::=
output [ net _type ] [ signed ] [ range ]
list_of_port_identifiers
| output reg [ signed ] [ range ]
list_of_variable_port_identifiers
| output output_variable_type
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list_of_variable_port_identifiers
list_of_port_identifiers ::= (From A.2.3)
port_identifier { , port_identifier }
V d:
module test (a, b, c, d, e, f, g, h);
input [7:0] a;
// du ng ngoc v chm phy

// ngn cch nhau bi du chm phy
input signed [7:0] b, c, d; // nhiu cng cng chia s mt thuc tnh khai bo
output [7:0] e;
// mi thuc tnh phi c 1 khai bo.
output reg signed [7:0] f, g;

output signed [7:0] h;
endmodule
Nu khai bo mt cng bao gm mt net hoc loi bin khc, th cng c th khai bo
li trong khai bo net hoc bin. Nu mt net hoc bin khai bo nh l mt vector, th c t
phm vi gia hai khai bo cng phi ging ht nhau.
5.2.4.4 Khai bo port u module

y l mt c php ch ra cc cng trong module thay th c php Mc 5.2.4.3, nhm
gim ti t nht vic sao chp d liu.
Mi khai bo cng cung cp thng tin y v cng, hng cng, rng, net, hoc cc
loi bin v nhng m t y khc v port nh c du hoc khng du. C php tng t cho
khai bo u vo, u vo-ra v u ra cng c s dng phn u ca module, theo cch
khai bo cng, ngoi ra danh sch khai bo port l bao gm phn u ca module ch khng
phi tch bit (ngay sau du ; cui phn u module).
V d 5.3: Trong v d sau, module tn test c a ra trong v d trc c khai bo li nh
sau:
module test (
input [7:0] a,
// ngn cch nhau bi du phy
input signed [7:0] b, c, d,
//nhiu cng cng chia s mt thuc tnh khai bo
output [7:0] e,
// mi thuc tnh phi c 1 khai bo.
output reg signed [7:0] f, g,

output signed [7:0] h
) ; //Du ng ngoc v chm phy
// Khng hp l nu c bt k khai bo cng no trong phn thn module

endmodule
Cc loi cng tham chiu ca khai bo cng module, s khng hon thnh s dng cch thc
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danh sch khai bo cng ca khai bo module. Cng nh khai bo cng s dng trong danh sch
khai bo cng s ch nh danh n gin hoc nh danh trng. Chng s khng c bit-select,
part-select hoc ton t kt ni, hoc khng c cc cng phn chia, hoc khng c tn cng.
Thit k t do c th s dng ln ln cc c php khai bo cng trong khai bo module.
5.2.4.5 Kt ni cc port ca module c gi bng danh sch th t

Mt phng php lm cho cc kt ni gia cc biu thc cng, c lit k trong th hin
ca module, v cng khai bo bn trong th hin module, l theo th t danh sch. Ngha l biu
thc cng lit k trong th hin ca module, s kt ni ti cng v tr cng trong danh sch cng
khi khai bo module con.
V d 5.4 minh ha mt module mc cao nht (topmod) ci t module th 2 (mobB).
Module mobB c cng kt ni theo th t danh sch. Kt ni thc hin nh l:
Cng wa trong modB nh ngha kt ni ti bit-select v[0] trong module topmod.
Cng wb kt ni ti v[3].
Cng c kt ni ti w.
Cng d kt ni ti v[4].
Trong nh ngha mobB, cng wa v wb c khai bo l cng vo ra trong khi cng c v

d c khai bo l cng vo.
V d 5.4
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (v[0], v[3], w, v[4]);
endmodule
module modB (wa, wb, c, d);
inout wa, wb;
input c, d;
tranif1 g1 (wa, wb, cinvert);
not #(2, 6)n1 (cinvert, int);
and #(6, 5)g2 (int, c, d);
endmodule
Trong sut qu trnh m phng ca th hin b1 ca modB, cng and g2 hot ng u tin
cung cp mt gi tr int. Gi tr ba trng thi qua cng not n1 cung cp u ra cinvert, sau
cho hot ng cng tranif g1.
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5.2.4.6 Kt ni cc port ca module c gi bng tn
Cch th 2 kt ni cc cng ca module bao gm lin kt r rng hai tn ca mi bn
trong kt ni: khai bo tn cng t khai bo module ti biu thc, tc l tn s dng trong khai
bo module, theo sau bng tn s dng trong th hin ca module. Tn ghp ny sau c
t trong danh sch kt ni ca module. Tn cng s l tn ch ra trong khai bo module. Tn
cng khng th l bit-select, part-select hoc ton t kt ni ca cc cng. Nu khai bo cng
ca module l ngm nh, biu thc cng phi l biu thc n gin hoc l biu thc trng, m
s c s dng nh tn cng. Nu khai bo cng ca module l r rng, tn r rng s
c s dng nh tn cng.
Biu thc cng c th l mt biu thc hp l bt k. Biu thc cng l ty chn v vy
trong ci t module c th bo co s tn ti ca cng m khng kt ni vi bt k ci g.
Cc du ngoc n vn phi yu cu c.
Hai loi kt ni cng ca module khng c ln ln, kt ni ti cng c th ca th
hin module s hoc tt c theo th t hoc tt c theo tn.
V d 5.5
V d 1: Trong v d ny, ci t module kt ni ti tn hiu topA v topB ti cng In1 v
Out, nh ngha trong module ALPHA. C mt cng cung cp bi module ALPHA khng
c s dng, tn l In2. C th c cc cng khng c s dng c cp trong ci t
ny.
ALPHA instance1 (.Out(topB),.In1(topA),.In2());
V d 2: V d ny nh ngha module modB v topmod, v sau topmod ci t modB
s dng kt ni cng theo tn.
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (.wb(v[3]),.wa(v[0]),.d(v[4]),.c(w)); // khng cn thep th t
endmodule
module modB(wa, wb, c, d);
inout wa, wb;
input c, d;
tranif1 g1(wa, wb, cinvert);
not #(6, 2)n1(cinvert, int);
and #(5, 6)g2(int, c, d);
endmodule
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Bi v kt ni l theo tn nn th t ca cc cng khai bo c th o v tr.
Nhiu kt ni cng ca th hin module l khng cho php, v d bn di l khng hp l
V d 3: v d cho thy kt ni cng khng hp l:
module test (a, b, c, d, e, f, g);
input [7:0] a;
input signed [7:0] b, c, d;
output [7:0] e;
output reg signed [7:0] f, g;
endmodule
module demo(input i, output o, inout e);
test false (.i (a), .i (b), // khng hp l khi kt ni u vo 2 ln.
.o (c), .o (d), // khng hp l khi kt ni u ra 2 ln.
.e (e), .e (f)); // khng hp l khi kt ni u vo-ra 2 ln.
endmodule
5.2.4.7 S thc trong kt ni port

Loi d liu s thc khng kt ni trc tip vi cng. N s kt ni gin tip, nh v d bn
di. Hm h thng $realtobits v $bitstoreal s c s dng kt ni qua cc bit trn m
hnh cng ca module.
V d 5.6
// kt ni s thc vi cng s dng hm h thng $realtobits
module driver (net _r);
output net _r;
real r;
wire [64:1] net _r = $realtobits(r);
endmodule
// kt ni s thc vi cng s dng hm h thng $bitstoreal
module receiver (net _r);
input net _r;
wire [64:1] net _r;
real r;
initial
assign r = $bitstoreal(net _r);
endmodule
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5.2.4.8 Kt ni nhng port khng tng t nhau
Mt cng ca mt module c th c xem nh l cung cp mt lin kt hoc mt kt
ni gia hai biu tng (dy ni, thanh ghi, biu thc, ), mt biu tng ci t bn trong
module v mt ci t bn ngoi module.
Kim tra kt ni cng theo lut m t trong Mc 5.2.4.9 s thy rng, biu tng nhn
gi tr t mt cng (biu tng input ca module ni v output ca module ngoi) s c cu trc
biu thc net. Cc biu tng khc cung cp gi tr c th l mt biu thc bt k.
Mt cng c khai bo l mt u vo (u ra) nhng s dng nh l u ra (u vo)
hoc u vo-ra c th c cng ch vo ra. Nu khng cng ch s c cnh bo xut
hin.
5.2.4.9 Nhng qui nh khi kt ni port

Cc lut kt ni cng trong phn ny s chi phi cch khai bo cng ca module v cch
chng kt ni vi nhau:
Lut 1: Mt cng vo hoc cng vo ra phi l mt net.
Lut 2: Mi cng kt ni s l php gn lin tc ca ngun ti cui cng, ni m mt biu
tng kt ni l tn hiu ngun v nhng ci khc l tn hiu chm. Mt php gn l php
gn lin tc t ngun ti cui cng cho u vo hoc u ra. Php gn l khng mnh
gim kt ni bn dn cho cng inout. Ch dy ni hoc biu thc c cu trc dy ni s n
trong php gn.
Mt biu thc cu trc dy dn l mt biu thc cng trong ton hng l:
Mt net v hng.
Mt vector net.
Mt hng s bit-select ca mt vector net.
Mt part-select ca mt vector net.
Mt ton t kt ni ca biu thc cu trc net.
Theo cc biu tng bn ngoi s khng kt ni ti u ra hoc u vo ra ca

module:
Cloud
Bin.
Biu thc khc vi nhng iu sau:

1.
Mt net v hng
2.
Mt vector net.
3.
Mt hng s bit-select ca mt vector net.
4.
Mt part-select ca mt vector net.

Page 135

5.
Mt ton t kt ni ca biu thc trong danh sch trn.
Lut 3: Nu net hai bn ca cng l loi net wire, mt cnh bo s xy ra n net khng gp
li vo trong mt net n nh m t trong Mc 5.2.4.10.
5.2.4.10
Loi net to ra t vic kt ni port khng tng t nhau
Khi cc loi net khc nhau kt ni vi nhau thng qua mt module, th cc net ca tt c
cc cng phi a v cho ging loi vi nhau. Kt qu loi net c xc nh theo bng 5-1.
Trong bng ny, net ngoi ngha l net ch ra trong th hin ca module, net ni ngha l
net ch ra trong module nh ngha. Net m loi ca n c s dng gi l dominating net. Net
m loi ca n b thay i gi l dominated net. N c quyn hp cc dominating v dominatr
net vo trong mt net n, loi ny c loi nh l mt dominating net. Kt qu ca net gi l
simulated net v dominated net gi l collapsed net.
Loi simulated net s thc hin delay ch ra dominating net. Nu dominating net l loi
trireg, bt k gi tr mnh no ch ra cho trireg s p dng cho simulated net.
Bng 5.1 T hp gia net ni v net ngoi
Net ni
Net ngoi
wire, tri
ext
ext
ext
ext
ext
ext
ext
ext
ext
wand,
int
ext
ext
ext
ext
ext
ext
ext
ext
warn
ext
warn
ext
warn
ext
warn
ext
ext
ext
warn
ext
warn
ext
warn
ext
warn
ext
ext
ext
ext
ext
warn
ext
ext
ext
int
ext
warn
ext
warn
ext
ext
ext
int
warn
ext
ext
ext
warn
int
int
ext
ext
ext
warn
ext
triand
wor,
int
ext
warn
ext
trior
trireg
int
warn
ext
ext
int
warn
ext
warn
ext
int
warn
ext
warn
ext
int
warn
int
warn
int
int
warn
int
int
warn
int
warn
int
warn
int
warn
int
tri0
tri1
uwire
supply0
supply1
int
int
int
int
int
int
int
int
warn
T kha:
Cloud
ext: s dng net ngoi

Page 136
int: s dng net ni
warn: xut hin cnh bo
Lut gii quyt loi net

Khi 2 net kt ni vi nhau bi cc cng khc loi nhau, kt qu l mt net n c th l
mt trong:
Loi dominating net nu mt trong hai net l dominating net, hoc
Loi ca net ngoi ti module
Khi loi dominatin net khng tn ti, loi net ngoi s c s dng.
Bng loi net
Bng 5.1 ch ra loi net b gi bi loi net theo lut gii quyt net. Simulated net s theo loi
net ch ra trong bng v tr hon k thut ca net. Nu simulated net c chn l trireg, bt
k mnh gi tr no ch ra cho trireg s p dng cho simulated net.
5.2.4.11
Kt ni nhng gi tr c du thng qua (port)
Thuc tnh du khng c thng qua trong cu trc phn cp. Trong th t c
loi c du qua cu trc phn cp, t kha signed phi c s dng trong khai bo i tng
mt cp khc trong cu trc phn cp. Bt k biu thc no trong mt cng s c xem nh
l bt k biu thc no khc trong php gn. N s c loi, k c, nh gi v gi tr kt qu gn
ti i tng bn khc ca cng s dng ging lut nh mt php gn.
5.3
Bi tp
1. M hnh cu trc phn cp trong Verilog l g?

2. Cc cch khai bo, gi v gn c tnh cho mt module?
3. Cc cch khai bo port?
4. Cc cch kt ni port?
5. Nhng quy lut khi kt ni port?
Cloud
Page 137
6 Chng 6. M hnh thit k cu trc (Structural model)

6.1
Gii thiu
M hnh thit k cu trc m t cc h thng di dng cc cng linh kin hay cc khi linh
kin c kt ni li vi nhau thc hin c nhng chc nng mong mun. M hnh thit
k cu trc c m t mt cch trc quan h thng thit k s, do n thc s gn ging
vi m t vt l phn cng ca h thng.
Ngi thit k thng s dng m hnh thit k cu trc cho nhng module nh cn ti u
v timing, din tch, v s dng m hnh ny th phn cng thit k sau khi tng hp ra mch s
ging vi m t thit k trn Verilog. Tuy nhin, i vi mt h thng ln th vic s dng m
hnh cu trc l khng kh thi, bi v s cng knh ca n khi ghp hng ngn hng vn cng c
bn li vi nhau, cng nh tiu tn thi gian rt ln cho vic chy m phng kim tra thit k.
6.2
Nhng linh kin c bn
6.2.1
Cng and, nand, or, nor, xor, xnor
Su cng logic ny c mt u ra v mt hoc nhiu u vo. Tham s u tin trong danh

sch cc tham s s kt ni vi u ra ca cng logic, cc tham s khc kt ni ti u vo.
Khai bo th hin ca mt cng logic c bn nhiu u vo loi ny s bt u vi mt trong
nhng t kha sau:
and
nand
or
nor
xor
xnor
c t tr hon s l 0, 1 hoc 2 tr hon. Nu c t tr hon bao gm 2 tr hon, tr hon u

s xc nh u ra tr hon cnh ln, tr hon th hai s xc nh u ra tr hon cnh
xung, v trong thi gian nh hn 2 tr hon s thit lp u ra l x. Nu ch c mt tr hon
c a ra th s tr hon c cnh ln v cnh xung. Nu khng c c t tr hon th s
khng c tr hon thng qua cng.
Bng s tht ca cc cng ny th hin kt qu ca cng 2 gi tr u vo:
Bng 6.1 Bng s tht ca cc cng logic
and
0
1
x
z
0
0
0
0
0
1
0
1
x
x
x
0
x
x
x
z
0
x
x
x
nand
0
1
x
z
0
1
1
1
1
1
1
0
x
x
x
1
x
x
x
z
1
x
x
x
or
0
0
0
1
1
x
x
z
x
xor
0
0
0
1
1
x
x
z
x
[Type text]
Page 138

1
x
z
1
x
x
1
1
1
1
x
x
1
x
x
1
x
z
1
x
x
0
x
x
x
x
x
x
x
x
nor
0
1
x
z
0
1
0
x
x
1
0
0
0
0
x
x
0
x
x
z
x
0
x
x
xnor
0
1
x
z
0
1
0
x
x
1
0
1
x
x
x
x
x
x
x
z
x
x
x
x
Cc phin bn ca su cng logic ny c nhiu hn 2 u vo s m rng t nhin theo

bng trn, nhng s lng u vo nh hng ti tr hon truyn.
V d 6.1
V d ny khai bo mt cng and 2 u vo:
and a1 (out, in1, in2);
Trong u vo l in1, in2. u ra l out, th hin tn l a1.
6.2.2
Cng buf v not
Hai cng logic ny c mt u vo v mt hoc nhiu u ra. Tham s cui cng trong
danh sch cc tham s s kt ni vi u vo ca cng logic, cc tham s khc kt ni ti u ra.
Khai bo th hin ca mt cng logic nhiu u ra loi ny s bt u vi mt trong nhng t
kha sau:
buf
not
c t tr hon s l 0, 1 hoc 2 tr hon. Nu c t tr hon bao gm 2 tr hon, tr hon u

s xc nh u ra tr hon cnh ln, tr hon th hai s xc nh u ra tr hon cnh xung,
v nh hn 2 tr hon s thit lp u ra l x. Nu ch c mt tr hon c a ra th s tr
hon c cnh ln v cnh xung. Nu khng c c t tr hon th s khng c tr hon thng
qua cng.
Bng s tht ca cc cng ny th hin kt qu ca cng 1 u vo v mt u ra:
Bng 6.2 Bng s tht ca cng buffer v cng not
buf
u vo
0
1
x
z
not
u ra
0
1
x
z
u vo
0
1
x
z
u ra
1
0
z
x
V d 6.2
[Type text]
Page 139

V d sau khai bo mt cng buf 2 u ra:
buf b1 (out1, out2, in);
u vo l in, u ra l out1, out2, tn th hin l b1
6.2.3
Cng ba trng thi bufif1, bufif0, notif1, v notif0
y l bn cng logic thuc loi ba trng thi iu khin. Bn cnh cc gi tr logic 0 v 1,

u ra cng ny c th l gi tr z. Bn cng logic ny s c mt u ra v mt u vo d
liu, mt u vo iu khin. Tham s th nht trong danh sch tham s kt ni vi u ra,
tham s th hai kt ni vi u vo, tham s th ba kt ni vi u vo iu khin.
Khai bo th hin ca mt cng logic ba trng thi s bt u vi mt trong cc t kha
sau:
bufif0
bufif1
notif1
notif0
c t tr hon s l 0, 1, 2 hoc 3 tr hon. Nu c t tr hon bao gm 3 tr hon, tr hon

u s xc nh u ra tr hon cnh ln, tr hon th hai s xc nh u ra tr hon cnh
xung, tr hon th ba s xc nh tr hon s chuyn tip ti gi tr z v nh nht trong 3 tr
hon s xc nh tr hon ca chuyn tip ti x. Nu c t tr hon bao gm 2 tr hon, tr hon
xung, v nh hn trong 3 tr hon s xc nh tr hon ca chuyn tip ti x v z. Nu ch c
mt tr hon c a ra th n ch ti tr hon tt c cc chuyn tip u ra. Nu khng c c
t tr hon th s khng c tr hon thng qua cng.
Mt vi t hp ca gi tr d liu u vo v gi tr iu khin u vo c th gy ra
cng c hai gi tr u ra, m khng c tham kho no cho mt trong hai gi tr (xem Mc
7.10.2). Bng logic cho cc cng ny bao gm hai k hiu biu din cho kt qu khng xc
nh. K hiu L s ch ra mt kt qu c gi tr 0 hoc z. Gi tr H ch ra kt qu c gi tr 1
hoc z. Tr hon trn s chuyn tip ti H hoc L s xem nh ging vi tr hon chuyn tip ti
gi tr x.
Bng 6.3 Bng s tht ca cc cng ba trng thi
bufif0
INPUT
notif0
[Type text]
0
0
1
x
z
0
1
x
x
0
CONTROL
1
x
z
z
z
z
L
H
x
x
CONTROL
1
x
z
L
H
x
x
z
bufif1
INPUT
notif1
0
0
1
x
z
z
z
x
x
0
CONTROL
1
x
0
1
z
z
L
H
x
x
CONTROL
1
x
z
L
H
x
x
z
Page 140

0
1
x
z
INPUT
1
0
x
x
z
z
z
z
L
H
x
x
L
H
x
x
INPUT
0
1
x
z
z
z
x
x
1
0
z
z
L
H
x
x
L
H
x
x
V d 6.3
V d sau khai bo mt th hin ca cng bufif1:
bufif1 bf1 (outw, inw, controlw);
Trong u ra l outw, u vo l inw, u vo iu khin l controlw, th hin
tn l bf1
6.2.4
Cng tc MOS
Khai bo th hin ca mt cng tc MOS s bt u vi mt trong cc t kha sau:

cmos
nmos
pmos
rcmos
rnmos
rpmos
Cng tc cmos v rcmos c m t trong Mc 6.2.6.

T kha pmos vit tt cho transistor P-type matal-oxide semiconductor (PMOS) v t kha
nmos l vit tt cho transistor N-type matal-oxide semiconductor (NMOS). Transistor PMOS v
NMOS c tr khng tng i thp gia cc ngun v cc mng khi chng dn. T kha
rpmos l vit tt ca transistor in tr PMOS v t kha rnmos l vit tt ca transistor in
tr NMOS. Transistor in tr PMOS v NMOS c tr khng cao hn nhiu gia cc ngun v
cc mng khi chng dn so vi transistor PMOS v NMOS thng. Thit b ti trong mch
MOS tnh l v d ca transistor rpmos v rnmos. Bn cng tc l knh dn mt chiu cho d
liu tng t nh cng bufif.
xung, tr hon th ba s xc nh tr hon s chuyn tip ti gi tr z v nh nht trong 3 tr
hon s xc nh tr hon ca chuyn tip ti x. Nu c t tr hon bao gm 2 tr hon, tr hon
xung, v nh hn trong 2 tr hon s xc nh tr hon ca chuyn tip ti x v z. Nu ch c
mt tr hon c a ra th n ch ti tr hon tt c cc chuyn tip u ra. Nu khng c c
t tr hon th s khng c tr hon thng qua cng.
Mt vi t hp ca gi tr d liu u vo v gi tr iu khin u vo c th gy ra
cng tc c hai gi tr u ra, m khng c tham kho no cho mt trong hai gi tr. Bng
logic cho cc cng ny bao gm hai k hiu biu din cho kt qu khng st nh. K hiu L s
ch ra mt kt qu c gi tr 0 hoc z. Gi tr H ch ra kt qu c gi tr 1 hoc z. Tr hon trn
[Type text]
Page 141

s chuyn tip ti H hoc L s xem nh ging vi tr hon chuyn tip ti gi tr x.
Bn cng logic ny s c mt u ra v mt u vo d liu, mt u vo iu khin. Tham
s th nht trong danh sch tham s kt ni vi u ra, tham s th hai kt ni vi u vo,
tham s th ba kt ni vi u vo iu khin.
Cng tt nmos v pmos s cho qua tn hiu t u vo v thng ti u ra ca chng vi
mt thay i v mnh tn hin trong mt trng hp, tho lun Mc 7.11. Cng tt
rnmos v rpmos s gim mnh tnh hin truyn qua chng, tho lun trong Mc 7.12.
Bng 6.4 Th hin bng logic ca cng truyn
pmos
CONTROL
rpmos
INPUT
cmos
CONTROL
rcmos
INPUT
V d 6.4
V d ny khai bo mt cng tc pmos:
pmos p1 (out, data, control);
Trong u ra l out, u vo l data, u iu khin l control v tn th hin l p1.
6.2.5
Cng tc truyn hai chiu
Khai bo th hin ca cng tc truyn hai chiu s bt u vi mt trong cc t kha sau:

tran
tranif1
tranif0
rtran
rtranif1
rtranif0
Cng thc truyn hai chiu s khng tr hon tn hiu truyn qua chng. Khi thit b tranif0,
tranif1, rtranif0 hoc rtranif1 l tt, chng s chn tn hiu; v khi chng m th chng s
cho tn hiu i qua. Thit b tran v rtran khng th tt v chng lun lun cho tn hiu qua
chng.
c t tr hon cho cc thit b tranif1, tranif0, rtranif1, v rtranif0 l 0, 1 hoc 2 tr hon.
Nu c t tr hon bao gm 2 tr hon, tr hon u s xc nh u ra tr hon m, tr hon th
hai s xc nh u ra tr hon ng, v nh hn trong 2 tr hon s xc nh tr hon ca chuyn
tip ti x v z. Nu ch c mt tr hon c a ra th n c t cho c tr hon m v ng.
Nu khng c c t tr hon th s khng c tr hon ng v m cho cng tc truyn hai chiu.
Cng tc truyn hai chiu tran v rtran s khng chp nhn c t tr hon.
[Type text]
Page 142

Cc thit b tranif1, tranif0, rtranif1 v rtranif0 c 3 tham s trong danh sch vo ra. Hai
tham s u s l hai thit b u cui hai chiu iu khin tn hiu ti v i t thit b, v u
cui th 3 s kt ni vi u vo iu khin. Thit b tran v rtran s c danh sch cc cng
gm hai cng hai chiu. C hai u cui hai chiu s iu khin truyn v iu kin tn hiu ti
v i t thit b, cho php tn hin qua theo mi hng t thit b. Thit b u cui hai chiu c
tt c 6 thit b ch kt ni vi nhng net v hng hoc bit-select ca nhng vector net.
Thit b tran, tranif0 v tranif1 cho qua tn hiu vi thay i v mnh ch trong trng
hp m t Mc 6.11. Thit b rtran, rtranif1, rtranif0 s lm gim mnh ca tn hiu
qua chng theo lut tho lun trong phn 6.12
V d 6.5
V d sau m t khai bo mt th hin tranif1:
tranif1 t1 (inout1,inout2,control);
Thit b u cui hai chiu l inout1 v inout2, u vo iu khin l control, tn
th hin l t1.
6.2.6
Cng tc CMOS
Khai bo th hin ca mt cng tc CMOS bt u vi mt trong nhng t kha sau:

cmos
rcmos

xung, tr hon th ba s xc nh tr hon s chuyn tip ti gi tr z, v nh nht trong 3 tr
hon s xc nh tr hon ca chuyn tip ti x. Tr hon trong qu trnh chuyn tip ti gi tr
H hoc L ging nh tr hon trong chuyn tip ti x. Nu c t tr hon bao gm 2 tr hon, tr
hon u s xc nh u ra tr hon cnh ln, tr hon th hai s xc nh u ra tr hon
cnh xung, v nh hn trong 2 tr hon s xc nh tr hon ca chuyn tip ti x v z. Nu ch
c mt tr hon c a ra th n ch ti tr hon tt c cc chuyn tip u ra. Nu khng c
c t tr hon th s khng c tr hon thng qua cng.
Cng tc cmos v rcmos c mt u vo d liu, mt u ra d liu v hai u vo iu
khin. Trong danh sch cc cng vo ra, cng vo ra u tin kt ni ti u ra d liu, cng
vo ra th hai kt ni ti u vo d liu, cng vo ra th 3 kt ni ti knh n ca u vo
iu khin, v cng vo ra cui cng kt ni ti knh p ca u vo iu khin.
Cng cmos s cho qua tn hiu vi thay i mnh ch trong mt trng hp, m t Mc
6.2.11. Cng rcmos lm gim mnh ca tn hiu qua n theo lut m t Mc 6.2.12.
Cng tc cmos xem nh l t hp ca cng tc pmos v cng tc nmos. Cng tc rcmos xem
nh l t hp ca cng tc rpmos v cng tc rnmos. Cng tc t hp trong cu hnh ny s
[Type text]
Page 143

chia s d liu u vo v u ra trn cng vo ra nhng chng phn bit nhau v u vo iu
khin.
V d 6.6
S tng ng mt cng cmos ghp i t mt cng nmos v mt cng pmos c a ra
trong v d sau:
cmos (w, datain, ncontrol, pcontrol);
tng ng vi :
nmos (w, datain, ncontrol);
pmos (w, datain, pcontrol);
Hnh 6.1 Cng truyn CMOS
6.2.7
Ngun pullup v pulldown
Khai bo th hin ca mt ngun pullup v pulldown bt u bng mt trong cc t

kha:
pullup
pulldown
Ngun pullup t gi tr logic 1 ln net kt ni ti danh sch cc cng. Ngun

pulldown t gi tr 0 ln net kt ni vi danh sch cc cng.
Tn hin m ngun t ln nhng net c mnh pull trong s thiu c t mnh. Nu c
mt c t mnh 1 trn ngun pullup hoc mnh 0 trn ngun pulldown, tn hiu s c
c t mnh. c t mnh 0 trn ngun pullup v c t mnh 1 trn ngun
pulldown. Khng c c t tr hon cho ngun
V d 6.7
V d khai bo hai th hin ngun pullup:
pullup (strong1) p1 (net a), p2 (net b);
Trong v d ny, th hin p1 iu khin net a v th hin p2 iu khin net b vi
mnh strong
[Type text]
Page 144

6.2.8
M hnh mnh logic
Ngn ng Verilog cung cp cho m hnh chnh xc ca tn hiu tranh chp, cng truyn hai
chiu, thit b MOS in tr, MOS ng, chia s thay i, v nhng cu hnh mng khc ph
thuc k thut bng cch cho php tn hiu net v hng c gi tr khng y v c nhiu
cp mnh khc nhau hoc t hp cc cp mnh. M hnh logic nhiu cp
mnh gii quyt t hp tn hiu trong cc gi tr bit v khng bit biu din cho hnh vi ca
phn cng thc hin chnh xc hn.
Chi tit v mnh s c hai yu t:
mnh phn 0 ca gi tr net, gi l strength0, thit k nh mt trong cc t kha sau:
supply0
strong0
pull0
weak0
highz0
mnh phn 1 ca gi tr net, gi l strength1, thit k nh mt trong cc t kha sau:

supply1
strong1
pull1
weak1
highz1
T hp (highz0, highz1) v (highz1, highz0) l khng hp l.

Mc d phn ny c t mnh, n hu ch xem xt mnh nh mt thuc tnh
nm gi cc vng ca mt chui lin tc trong th t d on kt qu ca tn hiu t hp.
Bng 6.5 chng minh s lin tc ca mnh. Ct bn tri l danh sch cc t kha s dng
trong c t mnh. Ct bn phi l mc mnh tng quan.
Bng 6.5 mnh ca net
Tn mnh
supply0
strong0
pull0
large0
weak0
medium0
small0
highz0
highz1
small1
medium1
weak1
large1
pull1
strong1
[Type text]
Cp mnh
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
Page 145

supply1
Trong Bng 6.5 c bn mnh iu khin

supply
strong
pull
weak
Tn hiu vi mnh iu khin s truyn t u ra cng v u ra ca php gn lin tc.

Trong Bng 6.5 c ba mnh thay i do lu tr
large
medium
small
Tn hiu vi mng thay i do lu tr s hnh thnh trong loi net triregC th ngh rng
mnh ca tn hiu trong Bng 6.5 nh v tr trn thc t l trong Hnh 6.2.
strength0
7
strength1
2
Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 HiZ1 Sm1 Me1 We1 La1 Pu1 St1 Su1
Hnh 6.2 mnh cc mc logic 0 v 1
Tho lun v t hp tn hiu sau phn ny dng hnh v tng t nh Hnh 6.2
Nu gi tr tn hiu ca mt net l bit, tt c mnh ca n s nm trong mt trong hai
phn: phn strength0 ca thc t l trn Hnh 6.2 hoc phn stregth1. Nu gi tr ca mt
net l khng bit, n s c cp mnh cu trong phn strength1 v strength0. Mt net
vi gi tr z c cp mnh trong mt phn con ca thc t l.
6.2.9
mnh v gi tr ca nhng tn hiu kt hp
Thm vo trong gi tr ca tn hiu, mt net c th hoc l c mnh nhiu cp

khng r rng hoc l mnh r rng bao gm mt hay nhiu cp . Khi t hp tn hiu,
mi mnh v gi tr s xc nh mnh v gi tr ca tn hiu kt qu tun theo cc khi
nim trong phn 6.2.9.1ti 6.2.9.4.
6.2.9.1 S kt hp gia nhng tn hiu c mnh r rng

Phn ny gii quyt vi cc tn hiu t hp m mi tn hiu c mt gi tr r rng v c
mt mc mnh.
Nu hai hoc nhiu hn cc tn hiu c mnh khng bng nhau t hp trong mt cu
hnh dy dn net, mnh ca tn hiu s l mnh tri hn trong tt c v xc nh kt
qu. T hp ca hai hoc nhiu hn cc tn tn hiu c gi tr ging nhau s c kt qu ging
vi gi tr c mnh ln nht trong tt c. T hp tn hiu ng nht mnh v gi tr s cho
kt qu ging vi tn hiu .
[Type text]
Page 146

T hp ca cc tn hiu c gi tr khng ging nhau v c mnh ging nhau s c th c
mt trong ba kt qu. Hai kt qu xy ra trn dy dn logic, kt qu th ba xy ra trong trng
hp trng. Dy dn logic s tho lun trong 6.2.9.4. Kt qu trong s vng mt ca dy dn
logic c tho lun trong ch ca Hnh 6.4.
V d: Trong Hnh 6.3, nhng con s trong du ngoc n ch ra quan h v mnh ca tn
hiu. T hp ca mt pull1 v mt strong0 kt qu l mt strong0, v n mnh hn trong 2 tn
hiu.
Hnh 6.3 Kt qu ca vic iu khin net bi hai mch khc nhau
6.2.9.2 mnh khng r rng: ngun v s kt hp

Mt s phn loi tn hiu s l mnh khng r rng:
Tn hiu vi gi tr xc nh v nhiu cp mnh.
Tnh hiu vi mt gi tr x, trong cc cp mnh bao gm c hai phn strength1

v strength0 ca thc mnh trong Hnh 6.2.
Tn hiu vi mt gi tr L, trong cc cp mnh bao gm tr khng cao gia nhp

vi cp mnh trong phn strength0 trong thc o mnh trong Hnh 6.2.
Tn hiu vi mt gi tr H, trong cc cp mnh bao gm tr khng cao gia nhp

vi cp mnh trong phn strength1 trong thc o mnh trong Hnh 6.2.
Nhiu cu hnh c th to ra cc tn hiu vi mnh khng r rng. Khi hai tn hiu bng
nhau v mnh v ngc nhau v gi tr kt hp, kt qu s l gi tr x, cng vi cp
mnh ca c hai tn hiu v cc cp mnh nh hn.
V d: Trong Hnh 6.4 ch ra mt t hp ca tn hiu weak vi gi tr 1 v tn hiu weak
vi gi tr 0 cho ra mt tn hiu c mnh weak v c gi tr l x.
Hnh 6.4 Hai tn hiu c mnh bng nhau cng iu khin mt net
[Type text]
Page 147

u ra ca tn hiu (WeX) c m t trong Hnh 6.5:
strength0
7
strength1
2
Hnh 6.5 u ra ca tn c mnh nm trong mt trong cc gi tr thuc dy trn

Mt tn hiu c mnh khng r rng c th c gi tr l mt dy cc gi tr c th. V
d mnh ca u ra t mt cng iu khin ba trng thi vi u vo iu khin l khng
xc nh nh Hnh 6.6:
Hnh 6.6 Cng ba trng thi vi tn hiu iu khin khng xc nh

u ra ca bufif1 trong Hnh 6.6l mt strong H, dy gi tr u ra c m t trong Hnh
6.7.
strength0
7
strength1
2
Hnh 6.7 Tn hiu ng ra ca bufif1 c mnh nm trong khong nh trn hnh

u ra ca bufif0 trong Hnh 6.6 l mt strong L, dy gi tr u ra c m t trong Hnh
6.8.
strength0
7
strength1
2
Hnh 6.8 Tn hiu ng ra ca bufif0 c mnh nm trong khong nh trn hnh

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T hp ca hai tnh hiu c mnh khng r rng s cho ra kt qu l mt tn hiu c
mnh khng r rng. Kt qu ca tn hiu s c mt dy cc cp mnh m bao gm cc
cp mnh ca cc thnh phn tn hiu. T hp u ra t 2 cng iu khin 3 trng thi vi
u vo iu khin khng xc nh c m t trong Hnh 6.9, l mt v d.
Hnh 6.9 T hp hai ng ra c mnh khng xc nh

Trong Hnh 6.9, t hp tn hiu c mnh khng r rng cho ra mt dy bao gm cc
mc cao nht v thp nht ca tn hiu v tt c cc mnh gia chng, nh m t trong
Hnh 6.10.
strength0
7
strength1
2
Hnh 6.10 mnh ca ng ra trn hnh 6.9

Kt qu l mt gi tr x bi v phm vi ca n gm gi tr 1 v 0. S 3 5, i trc gi tr x,
l t hp ca hai s. S th nht l s 3, tng ng vi mc strength0 cao nht cho kt qu.
S th hai l 5, tng ng vi cp strength1 cao nht cho kt qu.
Mng chuyn mch c th to ra mt phm vi mnh ca cc gi tr ging nhau, nh l
tnh hiu ca mt cu hnh t cao xung thp nh Hnh 6.11.
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Hnh 6.11 Mng chuyn mch

Trong Hnh 6.11, t hp cao ca mt thanh ghi, mt cng iu khin bng mt thanh ghi c
gi tr khng xc nh, v mt pullup to ra mt tn hiu c gi tr 1 v phm vi mnh 651
m t trong Hnh 6.12.
strength0
7
strength1
2
Hnh 6.12 mnh ng ra ca net 651

Trong Hnh 6.11, t hp thp ca mt pulldown, mt cng iu khin bi mt thanh
ghi c gi tr khng xc nh, v mt cng and cho ra mt tn hiu c gi tr 0 v phm vi
mnh 530 m t trong Hnh 6.13.
strength0
7
strength1
2
Hnh 6.13 mnh ng ra ca net 530

Khi tn hiu ca cu hnh t cao xung thp trong Hnh 6.11 t hp, kt qu l mt gi tr
[Type text]
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khng xc nh vi phm vi (56x) xc nh bi gi tr
u v cui l hai tn hiu trong Hnh 6.14.
strength0
7
strength1
Hnh 6.14 mnh ng ra ca net 56x

Trong Hnh 6.11, thay th pulldown trong cu hnh thp bng mt supply0 s thay i
phm vi ca kt qu ti phm vi (StX) m t trong Hnh 6.15.
Phm vi trong Hnh 6.15 l strong x bi v n l khng xc nh v cc cc ca c hai thnh
phn l strong. Cc cc ca u ra ca cu hnh thp l strong bi v pmos thp gim mnh
ca tn hiu supply0. M hnh ha tnh nng ny tho lun trong phn 6.2.10.
strength0
7
strength1
2
Hnh 6.15 mnh ng ra ca net 56x khi thay th pulldown bi supply0

Cng logic to ra kt qu vi mnh khng r rng cng ging nh iu khin ba trng
thi. Nh trong trng hp trong Hnh 6.16. Cng andN1 khai bo vi mnh highz0, v N2
khai bo vi mnh weak0.
Hnh 6.16 Ng ra to bi cc cng logic c tn hiu iu khin khng r rng

Hnh 6.16, thanh ghi b c gi tr khng xc nh; v vy u vo ca cng and pha trn l
strong x, cng and pha trn c c t mnh bao gm highz0. Tn hiu t cng and pha trn
l mt strong H bao gm cc gi tr m t trong Hnh 6.17.
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7
strength0
4
3
2
strength1
2
3
4
Hnh 6.17 mnh ca tn hiu ng ra StH
Hiz0 trong phn ca kt qu bi v c t mnh cho cng trong cu hi xc inh
mnh cho u ra vi gi tr 0. c t mnh khc ngoi tr khng cao cho gi tr 0 kt qu u
ra trong mt u ra cng c gi tr x. u ra ca cng and bn di l weak 0 nh m t
trong Hnh 6.18.
strength0
7
strength1
2
Hnh 6.18 mnh ca tn hiu ng ra We0
Khi tn hiu t hp, kt qu c phm vi (36x) nh m t trong Hnh 6.19
strength0
7
strength1
2
Hnh 6.19 mnh ca tn hiu ng ra 36x

Hnh 6.19 trnh by t hp ca mt tn hiu c mnh khng r rng v mt tn h iu
c mnh r rng. T hp ny l ch ca phn 6.2.9.3.
6.2.9.3 Tn hiu c mnh khng r rng v tn hiu c mnh r rng

T hp ca mt tn hiu c mnh r rng v gi tr xc nh vi mt tn hiu c mnh
khng r rng c trnh bi trong mt vi trng hp c th. hiu mt tp cc lut qun l
loi t hp, n cn thit xem xt cc cp mnh ca tn hiu c mnh khng r rng
rin mi n v quan h vi tn hiu c mnh r rng. Khi tn hiu c gi tr xc nh v c
mnh r rng kt hp vi mt thnh phn tn hiu khng r rng, s theo cc lut sau:
Cc cp mnh ca tn hiu c mnh khng r rng ln hn cp
mnh ca tn hiu c mnh r rng s vn c trong kt qu.
Cc cp mnh ca tn hiu c mnh khng r rng nh hn cp mnh
ca tn hiu c mnh r rng s bin mt khi kt qu, ch ca lut c.
Nu cc hot ng ca cc lut a v lut b cho ra kt qu cc cp mnh gin
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on v tnh hiu ngc nhau v gi tr, tn hiu gin on s l mt phn ca kt qu.
Cc hnh sau m t mt vi ng dng ca cc lut.
Trong Hnh 6.20, cc cp mnh ca tn hiu c mnh khng r rng nh hn hoc
bng cp mnh ca tn hiu c mnh r rng, bin mt khi kt qu, theo lut b.
Trong Hnh 6.21, lut a, lut b v lut c c p dng. Cc cp mnh ca tn hiu c
mnh khng r rng m c gi tr i ngc v mnh thp hn mnh ca tn hiu c
mnh r rng khng xut hin trong kt qu. Cc cp mnh ca tn hiu c mnh
khng r rng thp hn mnh ca tn hiu c mnh r rng, v c gi tr ging nhau
khng xut hin trong kt qu. Cc cp mnh ca tn hiu c mnh r rng c
mnh cao hn cc cc ca tn hiu c mnh khng r rng nh ngha phm vi ca kt
qu.
strength0
7
strength1
2
strength0
7
strength1
2
T hp ca hai tn hiu bn trn cho ra tn hiu kt qu bn di:

strength0
7
strength1
2
Hnh 6.20 mnh ng ra tun theo lut b

strength0
7
strength1
2
strength0
[Type text]
strength1
Page 153

7

strength0
7
strength1
2
Hnh 6.21 mnh ng ra tun theo lut a, b v c

Trong Hnh 6.22, lut a v lut b c p dng. Cc cp mnh ca tn hiu c
mnh khng r rng m c gi tr i ngc v mnh thp hn mnh ca tn hiu c
mnh r rng khng xut hin trong kt qu. Cc cp mnh ca tn hiu c mnh r
rng c mnh cao hn cc cc ca tn hiu c mnh khng r rng nh ngha phm vi
ca kt qu.
strength0
7
strength1
2
strength0
7
strength1
2

strength0
7
strength1
2
Hnh 6.22 mnh ng ra tun theo lut a, b

Trong Hnh 6.23, lut a, lut b v lut c c p dng. Cc cc ln ca mnh ca tn
hiu c mnh khng r rng ln hn cp mnh ca tn hiu c mnh r rng.
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Kt qu l mt phm vi c nh ngha bi mnh ln nht trong phm vi mnh ca
tn hiu c mnh khng r rng v cp mnh ca tn hiu c mnh r rng.
strength0
7
strength1
2
strength0
7
strength1
2

strength0
7
strength1
2
Hnh 6.23 mnh ng ra tun theo lut a, b v c

6.2.9.4 Loi wired logic net
Cc loi net triand, wand, trior v wor s gii quyt xung t khi c nhiu iu khin c
cng mt mnh. Loi net s gii quyt gi tr tn hiu bng cch xem tn hiu nh u vo
ca hm logic.
V d:
Xem xt t hp ca hai tn hiu c mnh r rng trong Hnh 6.24.
strength0
7
strength1
2
strength0
7
strength1
2
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Hnh 6.24 Ng ra t hp bi tn hiu ng vo c mnh r rng
T hp ca tn hiu trong Hnh 6.24, s dng dy dn logic and, cho ra mt kt qu vi gi
tr ging vi k qu to ra bi cng and vi gi tr ca hai tn hiu u vo. T hp ca tn
hiu s dng dy dn logic or to ra kt qu vi gi tr ging vi kt qu c to ra bi
cng or vi gi tr ca hai tn hiu u vo. mnh ca kt qu ging vi mnh ca t
hp tn hiu trong c hai trng hp. Nu gi tr ca tn hiu bn trn thay i c hai tn hiu
trong Hnh 6.24 thnh gi tr 1, th kt qu ca c hai loi logic l 1.
Khi tn hiu c mnh khng r rng t hp trong dy dn logic, n cn phi xem xt
cc kt qu ca tt c cc t hp ca mi cp mnh trong tn hiu u vi mi cp
mnh trong tn hiu th 2, nh
trong Hnh 6.25.
strength0
7
strength1
2
Signal1
strength0
7
strength1
2
Signal2
T hp cc cp mnh cho cng and theo hnh di y:

Signal1
mnh
Signal2
Gi tr
mnh
Kt qu
Gi tr
mnh
Gi tr
Kt qu ca tn hiu:
strength0
7
strength1
2
T hp cc cp mnh cho cng or theo hnh di y:

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Signal1
mnh
Signal2
Gi tr
mnh
Kt qu
Gi tr
mnh
Gi tr
Kt qu ca tn hiu:
strength0
7
strength1
2
Hnh 6.25 T hp cc mc logic c mnh khc nhau
6.2.10 S suy gim mnh bng nhng linh kin khng tr

Cc cng tc nmos, pmos v cmos s cho qua mnh t d liu u vo ti d liu u
ra, ngoi tr mnh ca supply s gim xung mnh strong.
Cc cng tc tran, tranif0, tranif1 s khng nh hng ti mnh tn hiu qua cc cng
u cui hai chiu, ngoi tr mnh supply s gim xung mnh strong.
6.2.11 S suy gim mnh bng nhng linh kin tr

Cc thit b rnmos, rpmos, rtran, rtranif1, rtranif0 s gim mnh ca tn hiu i qua
chng theo Bng 6.6
Bng 6.6 mnh nhng linh kin tr
mnh u vo
mnh gim
Supplydrive
Pulldrive
Strongdrive
Pulldrive
Pulldrive
Weak drive
Largecapacitor
Mediumcapacitor
Weak drive
Mediumcapacitor
Mediumcapacitor
Smallcapacitor
Smallcapacitor
Smallcapacitor
Highimpedance
Highimpedance
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6.2.12 mnh ca loi net
Cc loi net tri0, tri1, supply0 v supply1 s to ra tn hiu vi cc cp mnh c th.
Khai bo mt trireg c th c t mt trong hai cp mnh khc cp mnh mc nh.
6.2.12.1 mnh ca net tri0, tri1

Loi net tri0 m hnh mt mng kt ni ti mt thit b in tr ko xung. Trong s vng
mt ca mt ngun , nh vy tn hiu c gi tr 0 v mnh pull.Loi net tri1 m hnh
mt mng kt ni ti mt thit b in tr ko xung. Trong s vng mt ngun , nh vy
tn hiu c gi tr 1 v mnh pull.
6.2.12.2 mnh ca trireg

Loi net trireg m hnh mt nt lu tr thay i. mnh ca kt qu t mt net trireg
m n thay i trng thi lu tr ( l, mt iu khin thay i net v sau i n tr
khng cao) s l mt trong ba trng mnh: large, medium, hoc small. c t mnh kt
ni vi mt net trireg c th s c t bi ngi dng nh ngha net. Mt nh l medium. C
php ca c t ny c m t trong 3.4.1( thay i mnh).
6.2.12.3 mnh ca net supply0, supply1

Loi net supply0 m hnh mt kt ni vi t. Loi net supply0 m hnh mt kt ni ti
ngun cung cp. Loi net supply0 v supply1 l cc supply iu khin mnh.
6.2.13 tr hon cng (gate) v net

Tr hon cng v net cung cp mt phng tin m t chnh xc hn tr hon thng qua mt
mch. Tr hon cng c t tr hon truyn tn hiu t bt k u vo no ca cng ti u ra
cng. Ti a ba gi tr trn mt u ra trnh din bi tr hon cnh tng, cnh gim, v tt c t
nh thy t 6.2.1 ti 6.2.8.
Tr hon net tham kho thi gian ly c t bt k iu khin no trn net thay i gi tr
theo thi gian khi gi tr ca net cp nht v truyn qua hn na. Ti a c ba gi tr trn net c
th c t.
C cng v net, mt nh tr hon s l 0 khi khng c c t tr hon c a ra. Khi mt
gi tr tr hon c a ra, th gi tr ny s s dng cho tt c cc tr hon truyn chnh xc
cho cng hoc net. Khi hai tr hon c a ra, tr hon th nht s c t cho tr hon cnh
ln, v tr hon th hai c t cho tr hon cnh xung. Tr hon khi tn hiu thay i ti tr
khng cao hoc khng xc nh s thp hn hai gi tr tr hon ny.
Ba c t tr hon :
Tr hon th nht tham kho ti chuyn tip ti gi tr 1 (tr hon cnh ln).
Tr hon th hai tham kho ti chuyn tip ti gi tr 0 (tr hon cnh xung).
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Tr hon th ba tham kho ti chuyn tip ti gi tr tr khng cao.
Khi mt gi tr thay i ti gi tr khng xc nh, tr hon s l nh nht trong ba tr hon.

mnh ca tn hiu u vo s khng nh hng ti tr hon truyn t u vo ti u ra.
Bng 6.7 tng hp tr hon truyn t - ti c la chn c t 2 v 3 tr hon.
Bng 6.7 tr hon trn net
Tr hon nu c
T gi tr:
Ti gi tr:
2 tr hon
3 tr hon
d1
d1
min(d1,d2)
min(d1,d2,d3)
min(d1,d2)
d3
d2
d2
min(d1,d2)
min(d1,d2,d3)
min(d1,d2)
d3
d2
d2
d1
d1
min(d1,d2)
d3
d2
d2
d1
d1
min(d1,d2)
min(d1,d2,d3)
V d 6.8
V d 1: V d ny c t mt, hai v ba tr hon:
and #(10) a1 (out, in1, in2);
and #(10,12) a2 (out, in1, in2);
bufif0 #(10,12,11) b3 (out, in, ctrl);
// ch c mt tr hon
// tr hon cnh ln v cnh xung
// tr hon cnh ln, cnh xung, v tt
V d 2: V d ny c t mt module mch lt n gin vi ba trng thi u ra,

ni tr hon ring c a ra cho tng cng. Tr hon truyn t u vo ti u ra ca
mt module s c tch ly, v n ph thuc vo phn tn hiu i qua mng.
module tri_latch (qout, nqout, clock, data, enable);
output qout, nqout;
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Page 159

input
clock, data, enable;
tri qout, nqout;

not #5
nand
n1 (ndata,data);
#(3,5)
n2 (wa,data,clock),
n3 (wb,ndata,clock);
nand #(12,15)
n4 (q,nq,wa),
n5 (nq,q,wb);
bufif1 #(3,7,13) q_drive(qout,q,enable),

nq_drive(nqout,nq,enable);
endmodule
6.2.14 tr hon min:typ:max

C php cho tr hon trn mt cng nguyn thy (bao gm UPD), net v lnh gn lin tc
s cho php ba gi tr tr hon cho cnh ln, cnh xung v tc. Gi tr ti a, trung bnh v
ti thiu ca mi gi tr tr hon s c t nh l cc biu thc cch nhau bi du hai chm (:).
Chng khng yu cu qua h (v d: min<=typ<=max) gia cc biu thc tr hon ti thiu,
trung bnh v ti a. c th l ba biu thc bt k.
V d 6.9 cho thy gi tr min:typ:max cho tr hon cnh ln, cnh xung v tc.
V d 6.9
module iobuf (io1, io2, dir);
...
bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);
bufif1 #(6:8:10, 5:7:9, 13:17:19) b2 (io2, io1, dir);
...
endmodule
C php tr hon iu khin trong lnh th tc (9.7) cng cho php cc gi tr ti thiu, trung
bnh v ti a. l cc c t bi cc biu thc ngn cch bi du hai chm (:). V d 6.10
minh ho l thuyt ny:
V d 6.10
parameter min_hi = 97, typ_hi = 100, max_hi = 107;
reg clk;
always begin
#(95:100:105) clk = 1;
#(min_hi:typ_hi:max_hi) clk = 0;
[Type text]
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end
6.2.15 phn r in tch ca net trireg

Ging nh vi net, c t tr hon trong trireg net khai bo cng bao gm ba gi tr tr hon.
Hai tr hon u c t tr hon chuyn tip ti trng thi logic 1 v 0 khi net trireg c iu
khin bi mt iu khin. Tr hon th ba c t cho thi gian phn r in tch th hin cho
tr hon chuyn tip ti trng thi logic z. Thi gian phn r in tch c t tr hon gia khi
iu khin trireg net tc v khi n thay i lu tr trong khong khng xc nh.
Mt net trireg khng cn c t tr hon tc v net trireg khng bao gi thc hin chuyn tip
ti trng thi logic z. Khi iu khin ca mt net trireg thc hin chuyn tip t trng thi
logic 1, 0, hoc x ti tc, net trireg s nh li trng thi logic 1, 0 hoc x trc khi m
iu khin cn m. Gi tr z s khng truyn t iu khin ca mt net trireg ti mt trireg. Mt
net trireg c th ch gi mt trng thi logic x khi x l trng thi logic khi u ca net trireg
hoc khi net trireg b p buc sang trng thi z khi s dng cu lnh force ( trong phn 9.3.2).
Mt c t tr hon cho phn r in tch mt hnh mt nt lu tr np khng l l tng,
v d mt nt lu tr np s np dng r ra ngoi thng qua thit b xung quanh v cc kt ni.
Cc qu trnh phn r in tch v c t tr hon cho phn r in tch c m t trong
phn 6.2.15.1 v 6.2.15.2.
6.2.15.1Qu trnh phn r in tch

Phn r in tch l nguyn nhn ca chuyn tip t 1 hoc 0 lu tr trong net trireg ti gi
tr khng xc nh sau c t tr hon. Qu trnh phn r in tch bt u khi iu khin ca
net trireg tc v net net trireg bt u gi in tch. Qu trnh phn r in tch s kt thc theo
hai iu kin bn di:
c t tr hon bi thi gian phn r in tch tri qua v net trireg thc hin chuyn tip
t 1 hoc 0 ti x.
iu khin ca mt net trireg m v truyn 1, 0 hoc x vo net trireg.
6.2.15.2c t tr hon ca thi gian phn r in tch

Gi tr tr hon th 3 trong khai bo mt net trireg c t thi gian phn r in tch. Mt b
ba gi tr tr hon c t trong mt khai bo net trireg c m t:
#(d1,d2,d3)// (tr hon cnh ln, tr hon cnh xung , thi gian phn r in tch).
Thi gian phn r in tch c t trong mt khai bo net trireg s i trc bi mt c t tr
hon cnh tng hoc cnh gim.
V d 6.11
V d 1: V d sau m t mt c t ca thi gian phn r in tch trong mt khai bo
net trireg:
[Type text]
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trireg (large) #(0,0,50) cap1;
V d ny khai bo mt net trireg tn cap1. Net trireg ny lu tr mt in tch large.
c t tr hon cho cnh tng l 0, cho tr hon cnh gim l 0, v thi gian phn r in
tch l 50 n v thi gian.
V d 2: V d tip theo trnh din mt file ngun m t bao gm mt khai bo net
trireg vi mt c t thi gian phn r in tch. Hnh 6-26 th hin thi s mch ca
ngun m t:
module capacitor;
reg data, gate;
// khai bo trireg vi thi gian phn r in tch l 50 n v.
trireg (large) #(0,0,50) cap1;
nmos nmos1 (cap1, data, gate); // nmos iu khin trireg
initial
begin
$monitor("%0d data=%v gate=%v cap1=%v", $time, data, gate, cap1);

data = 1;
// Cht iu khin u vo bng cng tc nmos
gate = 1;
#10 gate = 0;
#30 gate = 1;
#10 gate = 0;
#100 $finish;
end
endmodule
Hnh 6.26 M hnh phn cng ca on m t trong v d trn
6.3 Nhng phn t c bn ngi dng t nh ngha (UDP)

Phn ny m t mt m hnh k thut tng thm vo tp cc cng nguyn thy c nh
ngha trc bng cch thit kt v c t nhng yu t c bn mi gi l UDPs. Th hin ca
[Type text]
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UDPs mi c th s dng ging ht nh l cng nguyn thy biu din cc m hnh
mch in.
C hai loi quan h c th hin trong mt UDP:
Mch t hp - m hnh bi mt UDP t hp.
Mch tun t - m hnh bi mt UDP tun t.
Mt UDP t hp s dng gi tr u vo ca n xc nh gi tr u ra tip theo ca
n. Mt UDP tun t s dng gi tr ca u vo ca n v gi tr ca u ra hin ti xc
nh gi tr u ra tip theo ca n. UDP tun t cung cp mt cch m hnh mch in tun
t l cc flip- flop v mch cht. UDP tun t c c quan h kch hot theo mc v theo cnh.
Mi UDP c chnh xc mt u ra, c th c mt trong ba trng thi 1, 0 hoc x. Gi tr ba
trng thi z khng c h tr. Trong mch UDPs tun t, u ra lun lun c gi tr l trng
thi ni b.
Gi tr z truyn ti u vo ca mt UDP c xem nh l mt gi tr x.
6.3.1
nh ngha phn t c bn UDP
nh ngha UDP l mt module c lp, chng ging nh mt cp nh ngha module

trong c php phn cp. Chng c th nm bt c u trong vn bn ngun, c th c trc
hoc sau th hin ca chng trong module gi chng. Chng khng nm gia cp t kha
module v endmodule.
Thc c th gii hn s nh ngh UDP ti a trong mt m hnh, nhng chng cho php ti
t nht l 256.
C php thng thng ca mt nh ngha UDP nh c C php 6-1:
C php 6-1
udp_declaration ::=
{ attribute_instance } primitive udp_identifier ( udp_port_list ) ;
udp_port_declaration { udp_port_declaration }
udp_body
endprimitive
| { attribute_instance } primitive udp_identifier (
udp_declaration_port_list ) ;
udp_body
endprimitive
udp_port_list ::= (From A.5.2)
output_port_identifier , input_port_identifier{, input_port_identifier}
udp_declaration_port_list ::=
[Type text]
Page 163

udp_output_declaration, udp_input_declaration{, dp_input_declaration }
udp_port_declaration ::=
udp_output_declaration ;
| udp_input_declaration ;
| udp_reg_declaration ;
udp_output_declaration ::=
{ attribute_instance } output port_identifier
| { attribute_instance } output reg port_identifier [ =constant_expression ]
udp_input_declaration ::=
{ attribute_instance } input list_of_port_identifiers
udp_reg_declaration ::=
{ attribute_instance } reg variable_identifier
udp_body ::= (From A.5.3)
combinational_body | sequential_body
combinational_body ::=
table combinational_entry { combinational_entry } endtable
combinational_entry ::=
level_input_list : output_symbol ;
sequential_body ::=
[ udp_initial_statement ] table sequential_entry { sequential_entry }
endtable
udp_initial_statement ::=
initial output_port_identifier = init_val ;
init_val ::= 1'b0 | 1'b1 | 1'bx | 1'bX | 1'B0 | 1'B1 | 1'Bx | 1'BX | 1 | 0
sequential_entry ::=
seq_input_list : current_state : next_state ;
seq_input_list ::=
level_input_list | edge_input_list
level_input_list ::=
level_symbol { level_symbol }
edge_input_list ::=
{ level_symbol } edge_indicator { level_symbol }
edge_indicator ::=
( level_symbol level_symbol ) | edge_symbol
[Type text]
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current_state ::= level_symbol
next_state ::=output_symbol | output_symbol ::= 0 | 1 | x | X
level_symbol ::= 0 | 1 | x | X | ? | b | B
edge_symbol ::= r | R | f | F | p | P | n | N | *
6.3.1.1 Tiu UDP

Mt nh ngha UDP c hai hnh thc xen k nhau. Hnh thc th nht bt u vi t
kha primitive, theo sau l mt nh danh, s l tn ca UDP. N ko theo sau l mt danh sch
cc cng nm trong du ngoc n v c phn cch nhau bi du phy, cui cng l mt du
chm phy. Tiu ca nh ngha UDP s theo sau bi danh sch cc cng v bng trng thi.
nh ngha UDP kt thc bi t kha UDP.
Hnh thc th hai bt u vi t kha primitive, theo sau l mt nh danh, s l tn
ca UDP. N ko theo sau l mt danh sch cc cng nm trong du ngoc n v c phn
cch nhau bi du phy, cui cng l mt du chm phy. Tiu ca nh ngha UDP s theo
sau bi bng trng thi. nh ngha UDP kt thc bi t kha UDP.
UDPs c nhiu cng u vo v c chnh xc mt cng u ra; cng hai chiu vo ra khng
c php dng trong UDPs. Tt c cc cng trong UDP l v hng, cng vector khng c
php dng.
u ra s cng u tin trong danh sch cng.
6.3.1.2 Khai bo cng (port) UDP

UDPs bao gm cc khai bo cng u vo v u ra. Khai bo cng u ra bt u bng t
kha output, theo sau l tn cng u ra.Khai bo cng u vo bt u bng t kha input,
theo sau l tn ca mt hoc nhiu cng u vo.
UDPs tun t bao gm khai bo mt reg cho cng u ra thm vo khai bo u ra, khi khai
bo UDP s dng cch khai bo th nht ca tiu UDP hoc nh phn khai bo u ra.
UDPs t hp khng bao gm khai bo reg. Gi tr ban u ca u ra c th c t bi cu ln
initial trong UDP tun t (6.3.1.3).
Qu trnh thc thi c th gii hn s u vo ca UDP, nh chng cho php t nht 9 u
vo cho UDP tun t v 10 u vo cho UDP t hp.
6.3.1.3 Khai bo khi to UDP tun t

Cu lnh khi to ca mt UDP tun t c t gi tr u ra khi qu trnh m phng bt u.
Cu lnh ny bt u vi t kha initial. Cu ln ny theo sau s l cu lnh gn m mt bit n
nguyn c gn vo cng u ra.
[Type text]
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6.3.1.4 Bng khai bo UDP
Bng trng thi nh ngha quan h ca mt UDP. N bt u vi t kha table v kt thc
vi t kha endtable. Mi dng ca bng kt thc bng mt du chm phy.
Mi dng ca bng c to ra s dng mt lot cc k t (m t trong trong Bng 6.8),
trong cho thy gi tr u vo trng thi u ra. Ba trng thi 1, 0 v x c h tr.
Trng thi z b loi thc thi trong UDPs. Mt s k t t bit c nh ngha biu din
cc trng thi c th ca mch t hp. Chng c m t trong Bng 6.8.
Th t ca cc trng trng thi u vo trong mi dng ca bng theo th t trong danh
sch cng trong nh ngha tiu UDP. N khng quan h vi th t khai bo cng.
UDPs t hp c mt trng trn u vo v mt trng cho u ra. Trng u vo ngn
cch vi u ra bi u hai chm (:). Mi dng nh ngha u ra cho mt t hp t bit cc gi
tr u vo.
UDPs tun t c thm vo mt trng gia trng u vo v u ra. l trng th hin
trng thi hin ti ca UDP v tng ng vi gi tr u ra hin ti. N gii hn bi du hai
chm (:). Mi dng nh ngha u ra da trn trng thi hin ti, t hp chi tit ca cc gi tr
u vo, v mt chuyn tip gi tr hin ti ti u vo. Mt dng nh m t bn di l khng
hp l:
(01) (10) 0 : 0 : 1 ;
Nu tt c cc gi tr u vo l x, th trng thi u ra s l x.
Khng cn thit c t r rng mi t hp u vo c th. Khi tt c t hp cc gi tr u
vo l khng c t r rng kt qu mc nh cho u ra l x.
Khng hp l nu t hp ca u vo ging nhau, bao gm c cnh c t cho u vo
khc.
6.3.1.5 Gi tr Z trong UDP

Gi tr z trong bng trng thi khng c h tr v n xem nh l khng hp l. Gi tr z
qua cng u vo ti UDP c xem nh l gi tr x.
6.3.1.6 Tng hp cc k hiu

tng s r rng v d vit ca bng trng thi, mt vi k hiu t bit c cung cp.
Bng 6.8 tng hp ngha ca tt c cc gi tr k hiu hp l trong phn bng ca nh ngha
UDP.
Bng 6.8 Gi tr k hiu hp l trong phn bng ca nh ngha UDP
K hiu Gii thch
[Type text]
Ghi ch
Page 166

0
Logic 0
Logic 1
Khng xc nh
Cho php trong cc trng u vo v u ra

ca tt c UDPs v trng trng thi hin ti
trong UDPs tun t

Lp li cc gi tr 0,1 v x Khng cho php trong trng u ra
Lp li cc gi tr 0,1
Cho php trong cc trng u vo ca tt c

UDPs v trng trng thi hin ti trong UDPs
tun t. Khng cho php trong trng u ra
Khng thay i
Ch cho php trong trng u ra ca UDPs

tun t.
(vw)
Gi tr thay i t v ti v v w c th l mt gi tr bt k trong 0, 1, x, ?,
w
Nh (??)
b v ch cho php trong trng u vo.

Bt k thay i no trong u vo
Nh (01)
Cnh tng ca u vo
Nh (10)
Cnh gim ca u vo
Lp li cc gi tr (01), Cnh dng ca in th u vo

(0x) v (x1)
Lp li cc gi tr (01), Cnh m ca in th u vo
(0x) v (x0)
6.3.2
UDP t hp
Trong UDPs t hp, trng thi u ra c xc nh ch nh l mt hm ca cc trng thi

u vo hin ti. Bt k thay i no ca trng thi u vo, UDP cng c lng v trng
thi u ra s c thit lp theo gi tr ch nh bi dng trong bng trng thi ph hp vi tt
c cc trng thi u vo. Tt c cc t hp ca u vo khng c t r rng s iu khin trng
thi u ra ti gi tr x.
V d 6.12 nh ngha mt b dn knh vi hai u vo d liu v mt u vo iu
khin:
V d 6.12
primitive multiplexer (mux, control, dataA, dataB);
output mux;
input control, dataA, dataB;
[Type text]
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table
// bng iu khin mux dataA dataB
01 0 : 1 ;
01 1 : 1 ;
01 x : 1 ;
00 0 : 0 ;
00 1 : 0 ;
00 x : 0 ;
10 1 : 1 ;
11 1 : 1 ;
1x 1 : 1 ;
10 0 : 0 ;
11 0 : 0 ;
1x 0 : 0 ;
x0 0 : 0 ;
x1 1 : 1 ;
endtable
endprimitive
Mc nhp u tin trong

V d 6.12 c th c gii thch nh sau: Khi control bng 0, dataA bng 1 v dataB bng
0 th u ra mux bng 1.
T hp u vo 0xx( control =0, dataA=x, dataB=x) l khng r rng. Nu t hp ny
xy ra trong sut qu trnh m phng th gi tr cng u ra s l x.
S dng du hi chm ?, m t mt b dn knh c th c vit tt:
V d 6.13
primitive multiplexer (mux, control, dataA, dataB);
output mux;
input control, dataA, dataB;
table
//bng iu khin mux dataA dataB
01?:1 ; // ? = 0 1 x
00?:0 ;
1?1:1 ;
[Type text]
Page 168

1?0:0 ;
x00:0 ;
x11:1 ;
endtable
endprimitive
6.3.3
UDP tun t tch cc mc
Hnh vi ca mch tun t tch cc mc cng ging vi hnh vi ca mnh t hp, ngoi tr
u ra khai bo l mt loi reg v thm vo mt trng trong mi mc ca bng. Trng mi
ny s biu din trng thi hin ti ca UDP. Trng u ra trong UDP tun t biu din
trng thi tip theo.
Xem xt v d mch cht:
V d 6.14
primitive latch (q, clock, data);
output q; reg q;
input clock, data;
table
// clock data q q+
01 : ? : 1 ;
00 : ? : 0 ;
1? : ? : - ;// - = khng thay i
endtable
endprimitive
M t ny khc vi UDP t hp hai iu. iu th nht, nh danh u ra q c thm khai

bo l reg ch ra l trng thai ni b q. Gi tr u ra ca UDP lun ging vi trng thi
hp b. iu th hai l mt trng cho trng thi hiu ti, c thm vo phn cch vi
u vo v u ra bng du hai chm.
6.3.4
UDP tun t tch cc cnh
Trong hnh vi tch cc mc, gi tr ca u vo v trng thi hin ti l xc nh gi tr

u ra. Hnh vi tch cc cnh khc ch thay i u ra gy nn bi mt chuyn tip ca u
vo. iu ny lm cho bng trng thi thnh bng chuyn tip.
Mi mc ca bng c mt c t chuyn tip t nht mt gi tr u vo. Chuyn tip ny
c t bi mt cp gi tr trong du ngoc n nh l (01) hoc k hiu chuyn tip nh l r.
[Type text]
Page 169

Mc nh th ny l khng hp l:
(01)(01)0:0:1 ;
Tt c cc chuyn tip m khng nh hng n trng thi u ra c quy nh r rng.
Nu khng, qu trnh chuyn i lm cho gi tr u ra chuyn sang z. Tt c cc chuyn tip
khng r rng c mt nh gi tr u ra l x.
Nu hnh vi ca UDP tch cc cnh ca u vo bt k, trng thi u ra mong mun s
c t cho tt c cc cnh ca tt c cc u vo.
V d 6.15 sau m t mt flip-flopD tch cc cnh ln:
V d 6.15
primitive d_edge_ff (q, clock, data);
output q; reg q;
input clock, data;
table
// clock dataqq+
// u ra thu c trn cnh tng ca clock
(01) 0:?:0;
(01) 1:?:1;
(0?) 1:1:1;
(0?) 0:0:0;
// b qua cnh m ca lock
(?0) ?:?:-;
// b qua s thay i d liu khi clock khng thay i
?(??):?:-;
endtable
endprimitive
Thut ng (01) biu din cho qu trnh chuyn tip ca gi tr u vo. C th, (01) biu
din mt chuyn tip t 0 ti 1. Dng u tin trong bng nh ngha UDP trc c hiu nh
sau: khi clock thay i gi tr t 0 ti 1 v d liu bng 0, u ra s l 0 bt k gi tr hin hnh.
Chuyn tip ca clock t 0 ti x vi d liu bng 0 v trng thi hin ti l 1 th kt qu u
ra q s l x.
6.3.5
Mch hn hp gia UDP mch tch cc mc v UDP tch cc cnh
nh ngha UDP cho php trn ln ln gia cu trc tch cc mc v tch cc cnh trong
[Type text]
Page 170

cng mt bng. Khi u vo thay i, trng hp tch cc cnh x l u tin, theo sau l
trng hp tch cc mc. V vy, khi trng hp tch cc cnh v tch cc mc cho ra cc gi tr
u ra khc nhau, th kt qu s quyt nh bi trng hp tch cc mc.
V d 6.16
primitive jk_edge_ff (q, clock, j, k, preset, clear);
output q; reg q;
input clock, j, k, preset, clear;
table
// clockjkpcstate output/next state
???01: ? : 1 ; // preset logic
???*1: 1 : 1 ;
???10: ? : 0 ; // clear logic
???1*: 0 : 0 ;
r0000: 0 : 1 ; // normal clockingcases
r0011: ? : - ;
r0111: ? : 0 ;
r1011: ? : 1 ;
r1111: 0 : 1 ;
r1111: 1 : 0 ;
f????: ? : - ;
b*???: ? : - ; // chuyn tip j v k
b?*??: ? : - ;
endtable
endprimitive
Trong v d ny, bin logic preset v clear l tch cc mc. Bt k khi no t hp preset
v clear l 01, th u ra s l 1. Tng t, khi t hp preser v clear l 10, th gi tr u ra s l
0.
Cc logic cn li l tch cc cnh vi clock. Trong trng hp clock thng thng, flip-flop
tch cc vi cnh ln ca clock, nh ch nh r trong trng clock trong bng bn trn. Trng
hp khng tch cc vi cnh xung ca clock c ch ra bi mt du gch (-) trong trng
u ra ( Bng 6.8) cho mi mu vi f l gi tr ca clock. Nh rng u ra mong mun cho cc
chuyn tip u vo trnh gi tr khng mong mun x u ra. Hai mu cui cng ch ra
chuyn tip trong u vo j v k khng thay i u ra khi ng h n nh mc thp hoc
[Type text]
Page 171

cao.
6.3.6
Gi s dng UDP
C php to mt th hin UDP c m t nh C php 6-2.

C php 6-2
udp_instantiation ::=
udp_identifier [ drive_strength ] [ delay2 ]
udp_instance { , udp_instance } ;
udp_instance ::=
[ name_of_udp_instance ] ( output_terminal , input_terminal
{ , input_terminal } )
name_of_udp_instance ::=
udp_instance_identifier [ range ]
Th hin ca UDPs c c t bn trong module ging nh l mt cng (xem 6.2) Tn th
hin l ty chn ging nh cng. Cc cng kt ni theo th t khai bo trong nh ngha UDP.
Ch c hai tr hon c th c t bi g gi tr z khng c h tr cho UDPs.
Mt lot cc ty chn ch th c ch nh bi mt mng cc th hin UDP. Lut kt ni
cc cng cng yu cu ging nh vi cng trong phn 6.2.
V d 6.17 m t vic to mt th hin ca flip-flop loi D d_edge_ff (nh ngha trong phn
6.3.2)
V d 6.17
module flip;
reg clock, data;
parameter p1 = 10;
parameter p2 = 33;
parameter p3 = 12;
d_edge_ff #p3 d_inst (q, clock, data);
initial
begin
data = 1; clock = 1;
#(20 * p1) $finish;
end
always #p1 clock = ~clock;
always #p2 data = ~data;
endmodule
[Type text]
Page 172

6.4 M t mch t hp v mch tun t s dng m hnh cu trc
6.4.1
M t mch t hp
Ta c th s dng m hnh cu trc m t thit k cho tt c cc loi mch t hp nh

multiplexer, decoder, encoder, adder,
V d 6.18 M t cng XOR
module xor_gate ( out, a, b );
input a, b;
output out;
wire
abar, bbar, t1, t2;
not invA (abar, a);

not invB (bbar, b);
and and1 (t1, a, bbar);
and and2 (t2, b, abar);
or or1 (out, t1, t2);
endmodule
V d 6.19 M t mch MUX2

module mux2 (in0, in1, select, out);
input in0,in1,select;
output out;
wire s0,w0,w1;
not (s0, select);
and (w0, s0, in0),
(w1, select, in1);
or (out, w0, w1);
endmodule // mux2
V d 6.20 M t mch decoder2-4
module decoder2_to_4 ( y0, y1, y2, y3, s1, s0 );
// Inputs and outputs
output y0, y1, y2, y3;
input s1, s0;
// Internal wires
wire s1n, s0n;
[Type text]
Page 173

// Create complements of s1 and s0
not ( s1n, s1 );
not ( s0n, s0 );
and ( y0, s1n, s0n );
and ( y1, s1n, s0 );
and ( y2, s1, s0n );
and ( y3, s1, s0 );
endmodule
V d 6.21 M t mch encoder8-3

module encoder8_3( A , D );
output[2:0] A;
input[7:0] D;
or( A[0], D[1], D[3], D[5], D[7] );
or( A[1], D[2], D[3], D[6], D[7] );
or( A[2], D[4], D[5], D[6], D[7] );
endmodule
V d 6.22 M t mch adder 1 bit

module adder1 (s, cout, a, b, cin);
output s, cout;
input a, b, cin;
xor (t1, a, b);
xor (s, t1, cin);
and (t2, t1, cin),
(t3, a, b);
or (cout, t2, t3);
endmodule
V d 6.23 M t mch adder 4 bit t mch adder 1 bit

module adder4 (sum, carry, inA, inB);
output [3:0] sum;
output carry;
input [3:0] inA, inB;
[Type text]
Page 174

adder1 a0 (sum[0], c0, inA[0], inB[0], 1'b0);
adder1 a1 (sum[1], c1, inA[1], inB[1], c0);
adder1 a2 (sum[2], c2, inA[2], inB[2], c1);
adder1 a3 (sum[3], carry, inA[3], inB[3], c2);
endmodule
6.4.2
M t mch tun t
Ta c th s dng m hnh cu trc m t thit k cho tt c cc loi mch tun t nh

latch, flipflop, register, counter,
V d 6.24 M t mch SR latch
module clockedSR_latch(Q, Qbar, Sbar, Rbar, clk);
//Port declarations
output Q, Qbar;
input Sbar, Rbar, clkbar;
wire X, Y;
// Gate declarations
not a(clkbar, clk);
or r1(X, Sbar, clkbar);
or r2(Y, Rbar, clkbar);
nand n1(Q, X, Qbar);
nand n2(Qbar, Y , Q);
endmodule
V d 6.25 M t mch D latch

module clockedD_latch(Q, Qbar, D, clk);
//Port declarations
output Q, Qbar;
input D, clk;
wire X, Y, clkbar, Dbar;
// Gate declarations
not a1(clkbar, clk);
not a2(Dbar, D);
or r1(X, Dbar, clkbar);
or r2(Y, D, clkbar);
[Type text]
Page 175

nand n1(Q, X, Qbar);
nand n2(Qbar, Y , Q);
endmodule
V d 6.26 M t mch D flipflip

module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar;
not (cbar, clear);
not (clkbar, clk);
// Input latches
nand (sbar, rbar, s);
nand (s, sbar, cbar, clkbar);
nand (r, rbar, clkbar, s);
nand (rbar, r, cbar, d);
// Output latch
nand (q, s, qbar);
nand (qbar, q, r, cbar);
endmodule
V d 6.27 M t D flipflop master-slaver

// Negative edge-triggered D-flipflop with 2 D-latches in master-slave relation
module edge_dff(q, qbar, d, clk, clear);
output q, qbar;
input d, clk, clear;
wire q1;
clockedD_latch master(q1, , d, clk, clear); // master D-latch
not(clkbar, clk);
clockedD_latch slave(q, qbar, q1, clkbar, clear, writeCtr); // slave D-latch
endmodule
V d 6.28 M t b m 4 bit
module counter(Q , clock, clear);
[Type text]
Page 176

output [3:0] Q;
input clock, clear;
// Instantiate the T flipflops
t_ff tff0(Q[0], clock, clear);
t_ff tff1(Q[1], Q[0], clear);
endmodule
V d 6.29 M t thanh ghi 4 bit

// Register module - 4-bit register
module register4bits( dataOut, dataIn, enable, clock, clear );
// Inputs and outputs
output [3:0] dataOut;
input [3:0] dataIn;
input enable, clock, clear;
// 4 D-flipflops
edge_dff ff0( dataOut[0], dataIn[0], enable, clock, clear );
endmodule
6.5 Bi tp
1. Bn hiu th no v m hnh cu trc (structural model)?
2. Nu mt s cng logic c bn m bn bit v cc gi chng trong m hnh cu trc bng
ngn ng Verilog?
3. Cc m hnh mnh logic trong Verilog?
4. S kt hp mnh logic ca nhng tn hiu khng r rng trong Verilog nh th
no?
5. Nu cc t t tr hon cng v net ?
6. UDP l g? Nu cc loi UDP c bn?
7. Cch khai bo v s dng mt UDP c bn?
8. To mt UDP theo cng thc boolean sau: out = (a1 & a2 & a3 ) | (b1 & b2)
[Type text]
Page 177
7 Chng 7. M hnh thit k hnh vi (Behavioral model)

7.1 Khi qut
M hnh thit k mc hnh vi s m t h thng theo cch m n hnh x thay v kt
ni cc linh kin mc thp li vi nhau. Hay ni cch khc, m hnh thit k hnh vi ch m t
mi quan h gia cc tn hiu ng ra vi cc tn hiu ng vo m khng cn quan tm n cu
trc phn cng bn trong n. M hnh hnh vi c hai mc m t khc nhau, mt l m t
mc RTL hay cn gi l php gn ni tip hay cng c th gi l php gn lin tc, hai l
m t mc gii thut (algorithmic).
7.2 Php gn ni tip hay php gn lin tc - m hnh thit k RTL

(continuous assignment)
7.2.1
Gii thiu
Php gn ni tip m hnh thit k RTL, thng thng m t lung d liu bn trong
nhng h thng ging nh lung d liu gia nhng thanh ghi. Php gn ni tip m hnh
thit k RTL a s c s dng trong vic thit k mch t hp.
Php gn ni tip m hnh thit k RTL, dng gn mt gi tr n net, net y c
th l net n hoc mt mng (vector) cc net, do biu thc bn tri php gn ni tip phi
c d liu l net, khng th l loi d liu thanh ghi (register). Php gn ny c thc hin
ngay khi c s thay i gi tr bn phi ca php gn. Php gn ni tip m hnh thit k
RTL, cung cp mt phng php m hnh mch t hp m khng cn m t s kt ni gia
cc cng vi nhau, m thay vo n m t biu thc logic iu khin net. Hay ni cch
khc, php gn ni tip iu khin net theo nh cch m cc cng linh kin iu khin net, trong
biu thc bn phi php gn c th c xem nh l mt mch t hp iu khin net mt
cch lin tc.
V d 7.1
assign m = 1b1;
assign a = b & c;
assign #10 a = 1bz;
7.2.2
Php gn ni tip khi khai bo net
Verilog cho php mt php gn ni tip c t trn cng pht biu khai bo net
V d 7.2
wire (strong1, pull0) mynet = enable ; //khai bo v gn
wire a = b & c; //khai bo v gn
[Type text]
Page 220
Tuy nhin vi cch gn ny, do mt net ch c khai bo mt ln dn n net ny ch

nhn c gi tr t mt php gn duy nht. Nu mun mt net c th nhn gi tr t nhiu
php gn khc nhau th ta phi dng pht biu php gn ni tip tng minh.
7.2.3
Pht biu php gn ni tip tng minh assign
Trong pht biu php gn ni tip tng minh, ta dng mt cch tng minh mt php gn
ni tip vi t kha assign gn gi tr cho net sau khi net c khai bo. Nhng php gn
trn cc net s c thc hin lin tc mt cch t ng. Hay ni cch khc, bt c khi no gi
tr ca mt ton hng bn biu thc pha phi ca php gn thay i th ton b gi tr cc net
bn tri php gn s cp nht ngay li gi tr. Nu gi tr mi khc vi gi tr trc th gi tr
mi s c gn vo net bn tri php gn.
V d 7.3
wire a; //khai bo
parameter Zee = 1'bz;
assign a = Zee; //gn 1
assign a = b & c; //gn 2
Nhng dng hp l ca biu thc bn tri ca php gn ni tip phi l loi d liu net :
Net (c th l net n scalar hoc mt mng cc net net vector)
Bit bt k c chn trong net vector
Mt phn cc bit bt k c chn trong net vector
Mt phn cc bit bt k c ch s (index) c chn trong net vector.
Biu thc ni {} gia cc biu thc hp l trn.
V d 7.4
module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0] sum_out;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
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endmodule
Trong v d trn, php gn ni tip c s dng m hnh mt mch cng 4 bit c nh.
y ta khng th dng php gn ni tip khi khai bo net bi v ta s dng cc net ny
trong php ni {} pha bn tri php gn.
V d 7.5
module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
parameter n = 16; parameter Zee = 16'bz; output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data; // khai bo net
// khai bo net vi php gn ni tip
tri [1:n] busout = enable ? data : Zee;
// pht biu vi 4 php gn ni tip
assign
data = (s == 0) ? bus0 : Zee,

data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule
Trong v d trn ta thy net data c th nhn gi tr t nhiu php gn ni tip khc nhau.
7.2.4
To tr hon (delay) cho php gn
to tr hon tnh t khi gi tr ca mt ton hng bn phi php gn thay i cho n

khi gi tr net bn tay tri c cp nht s thay i gi tr th ta c th m t tr hon
ngay trn php gn. Nu biu thc bn tay tri l mt net n (scalar) th vic m t tr hon
hon ton ging nh m t tr hon cho cc cng linh kin, c th l thi gian ln
(rising), thi gian xung (falling) hay thi gian t trng thi tng tr cao (high
impedance) cho net .
Nu biu thc bn tay tri l mt mng cc net (net vector) th qui lut sau s quyt nh
php gn c tr hon loi no:
Nu biu thc bn phi php gn to ra s thay i t trng thi khc 0 n trng thi
0, th tr hon thi gian xung (falling) s c s dng.
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Nu biu thc bn phi php gn to ra s thay i t trng thi bt k n trng thi

tng tr cao z th thi gian tr hon turn-off s c s dng.
Tt c cc trng hp cn li th tr hon thi gian ln (rising) s c s dng.
Vic m t tr hon trong mt php gn ni tip ngay trn khai bo net s c x l

khc vi vic m t tr hon ca mt net ri sau mi thc hin php gn ni tip. Mt
gi tr tr hon c th c cung cp cho mt net trong khai bao net nh trong v d sau:
wire #10 wireA;
assign wireA = 1bz;
assign wireA = b;
C php ny c gi l m t tr hon ca net, c ngha l bt k s thay i gi tr no
t biu thc bn phi php gn m c cung cp n wireA u s b tr hon trong 10 n
v thi gian trc khi php gn c hiu lc. Nh vy trong v d trn, c hai php gn u
i 10 n v thi gian sau th gi tr bn phi php gn mi c cp nht cho net
wireA.
Cn i vi php gn ni tip c m t ngay trong khai bo net th tr hon l mt
phn ca php gn ni tip ch khng phi l tr hon ca net, do n s khng phi l
tr hon ca cc php gn khc trn net . Hn na, nu bn tri php gn l mt mng cc
net (vector net) th thi gian tr hon ln, thi gian tr hon xung s khng c cung cp n
nhng bit ring l nu php gn nm ngay trong phn khai bo net.
Trong trng hp m mt ton hng bn phi php gn thay i trc khi s thay i
ca gi tr trc c thi gian truyn n net bn tri php gn th nhng bc sau s
din ra:
Gi tr ca biu thc bn phi php gn c tnh.
Nu gi tr c tnh khc vi gi tr ang truyn n net bn tri php gn th gi
tr ang truyn ny s hy.
Nu gi tr c tnh bng vi gi tr ang truyn n net bn tri php gn th gi
tr ang truyn vn c tip tc.
7.2.5
mnh php gn
mnh iu khin ca php gn c th c m t bi ngi s dng. Vic m t

mnh ny ch hp l cho nhng php gn n nhng net n nh sau
wire
tri
trireg
wand
triand
tri0
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wor
trior
tri1
Nhng php gn ni tip c iu khin mnh c th c m t ngay trong khai bo net

hoc ng mt mnh trong php gn ni tip vi t kha assign. Vic m t mnh, nu
c cung cp th phi theo ngay sau t kha (t kha cho loi d liu hay t kha assign) v
ng trc m t tr hon. Bt c khi no m php gn ni tip iu khin net th mnh
ca gi tr s m phng nh l c m t.
Mt m t mnh iu khin s bao gm mt gi tr mnh m t cho mt net
c gn gi tr 1 v mt gi tr mnh m t cho mt net c gn gi tr 0.
Nhng t kha sau s m t mnh ca php gn 1:
supply1 strong1
pull1
weak1
highz1
Nhng t kha sau s m t mnh ca php gn 0:

supply0 strong0
pull0
weak0
highz0
Th t ca s m t hai mnh trn l ty . Hai nguyn tc sau s rng buc vic s dng
s m t mnh iu khin:
Nhng m t mnh (highz1, highz0) v (highz0, highz1) s c xem nh l khng
hp l.
Nu mnh iu khin khng c m t th mnh mc nh s l (strong1,
strong0).
7.3
Php gn qui trnh - m hnh thit k mc thut ton

(procedural assignment)
Php gn qui trnh m hnh thit k mc thut ton s dng mt chui cc lnh c
th ca nhng pht biu nh ngha chui cc php ton trong h thng.
Vic m t ny ging nh vic m t chng trnh s dng ngn ng cp cao khc
chng hn nh C. Php gn qui trnh - m hnh thit k mc thut ton a s c s dng
trong vic thit k mch tun t. Php gn qui trnh s cung cp kh nng tru tng cn thit
m t mt h thng phc tp mc cao chng hn nh h thng vi x l hoc thc thi vic
kim tra nh thi phc tp, m ta kh c th thc hin c chng nu s dng m hnh cu
trc hoc m hnh RTL (php gn ni tip).
Php gn qui trnh c dng cp nht gi tr vo cho loi d liu bin (variable) nh
reg, integer, time, real, realtime v memory. Php gn ny khng mt thi gian, m thay
vo bin s lu gi gi tr ca php gn cho n khi c mt php gn qui trnh k tip cho
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bin xut hin.
Khc vi php gn lin tc (continuous assignment) l iu khin net v cp nht gi tr
cho net bt c khi no gi tr ca mt ton hng trong biu thc bn phi php gn thay i,
cn php gn qui trnh cp nht gi tr cho bin di s iu khin ca lung cu trc qui trnh
xung quanh n.
Bn phi ca php gn qui trnh c th l bt k mt biu thc no, bt k loi d liu no
dng tnh ton ra mt gi tr. Bn tri php gn l mt bin nhn gi tr gn t pha phi php
gn. Bin bn tri php gn ch c th l mt trong nhng dng sau:
Mt bin n hay mt mng bin (variable vector) c loi d liu bin l reg, integer,
real, realtime, hoc time.
Mt bit c chn trong mt mng bin (variable vector) c loi d liu bin l reg,
integer, hoc time. Cc bit cn li s khng b tc ng.
Mt phn cc bit c chn trong mt mng bin (variable vector) c loi d liu
bin l reg, integer, hoc time. Cc bit cn li s khng b tc ng.
Mt t (word) trong b nh.
S kt hp dng php {} ni cc dng trn li vi nhau.
Vic kt hp dng php {} ny khin vic phn chia cc phn kt qu ca gi tr biu thc
bn phi v gn nhng phn ny vo nhng phn khc nhau ca cc bin trong php {} bn tay
tri theo th t r rng.
Ch : Php gn n mt bin c kiu d liu bin l reg s khc so vi php gn n
bin c kiu d liu bin l real, realtime, time, hay integer khi m s bt bn phi php
gn t hn so vi bn tri php gn. Php gn n reg s khng sign-extend.
Php gn qui trnh xut hin bn trong nhng khi qui trnh (procedure) nh l always,
initial, task, function v nhng t kha ny c th c xem nh l s kch khi ca cc php
gn qui trnh.
Cc khi qui trnh always v khi qui trnh initial bt u theo nhng lung hot
ng c lp.
Cc khi qui trnh task v function, ta s xem xt trong chng sau. Ta xt mt v d n
gin hon chnh v m hnh thit k qui trnh procedure.
V d 7.6
module behave;
reg [1:0] a, b;
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initial begin
a = b1; b = b0;
end
always begin
#50 a = ~a;
end
always begin
#100 b = ~b;
end
endmodule
Trong qu trnh chy m phng thit k ny, tt c cc lung d liu c m t bi khi
initial v always s cng thc thi chy m phng ti thi im zero. Lung d liu bn trong
khi initial ch thc thi mt ln, cn lung d liu trong khi always s thc thi lp li khi
lung d liu (php gn) chm n t kha end. Cn ch y l s lp li ca lung d
liu (hay c th ni l s lp li ca cc php gn) bn trong khi always l hon ton khc vi
s lp li ca cc m lnh (instructions) trong ngn ng software. Cc php gn trong khi
always s c synthesize ra mt mch phn cng, mch ny c chc nng hot ng lp li, v
d mt mch m ln chng hn.
Trong m t thit k trn, hai d liu bin thanh ghi a v b c khi to gi tr ln lt l
1 v 0 ngay ti thi im zero. Cc php gn trong khi initial sau khi khi to gi tr cho
cc bin xong th s khng thc thi li bt k ln no na trong sut qu trnh chy m phng.
Khi cu trc initial cha mt block begin-end (y cn c gi l sequential block) ca
pht biu. Trong khi begin-end ny, bin d liu thanh ghi a c khi to trc, sau n
b. Khi cu trc always cng bt u thc thi ti thi im zero, nhng gi tr ca cc bin
d liu thanh ghi khng thay i cho n khi khong thi gian tr hon c m t bi delay
controls (bt u bi #) c tri qua.
Nh vy, theo nh m t thit k, trong qu trnh chy m phng, gi tr bin thanh ghi d
liu a s b o sau khong thi gian l 50 n v thi gian v bin thanh ghi d liu b b o
sau khong thi gian l 100 n v thi gian. Khi cu trc alays cng cha mt block beginend (y cn c gi l sequential block). Bi v, lung d liu (cc php gn) trong khi cu
trc always c lp li khi lung d liu chm end trong khi begin-end nn vi m t thit
k trn th s c hai dng xung tun hon c to ra bi a v b. Mt l xung c chu k l 100
n v thi gian c to ra bi a, mt l xung khc c chu k l 200 n v thi gian c to
ra bi b. Hai khi cu trc always nh trong m t thit k trn s thc thi ng thi trong sut
qu trnh chy m phng, bi v trong thc t sau qu trnh synthesis, th hai khi always ny
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s to ra hai mch phn cng c lp v khi c cung cp ngun in hot ng th c hai s
hot ng ng thi.
7.3.1
Php gn khai bo bin
Php gn khai bo bin l mt trng hp c bit ca php gn qui trnh, dng gn mt

gi tr cho bin. N cho php khi to mt gi tr cho bin trong cng pht biu khai bo bin.
Php gn c th l mt biu thc hng s. Php gn ny khng mt thi gian, m thay vo ,
mt d liu bin gi gi tr cho n khi c mt php gn k tip c gn n n. Nhng php
gn khai bo bin n mt mng l khng c php.
Nhng php gn khai bo bin ch c php mc module. Nu mt bin m c gn
hai gi tr khc nhau, mt l khi initial, mt l trong php gn khai bo bin th th t ca
php gn khng c xc nh.
V d 7.7
V d a: Khai bo mt bin thanh ghi 4 bit v gn gi tr gi tr cho n l 4.
reg[3:0] a = 4h4;
Php gn khai bo bin trn tng ng vi :
reg[3:0] a;
initial a = 4h4;
V d b: Php gn sau l khng c php
reg[3:0] array [3:0] = 0;
V d c: Khai bo hai bin c kiu d liu bin l integer, bin u c gn gi tr 0.
integer i =0, j;
V d d: Khai bo hai bin c kiu d liu bin l s thc real, gn gi tr ln lt l
2.5 v 3,000,000.
real r1 = 2.5, n300k = 3E6;
V d e: Khai bo mt bin c kiu d liu bin l time, mt c kiu d liu bin l
realtime vi gi tr khi to
time t1 = 25;
realtime rt1 = 2.5;
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7.3.2
Php gn qui trnh kn (blocking assignment) '='
Mt php gn c gi l php gn blocking assignment khi m gi tr bn tri ca php gn

ny c gn bi biu thc bn phi (ngha l gi tr ca biu thc bn tri c xc
nh valid) th php gn k tip n trong sequential block (begin-end) mi c thc thi.
Hay ni cch khc, php gn blocking assignment thc thi xong th php gn k tip n trong
sequential block (begin-end) mi c thc thi. Tuy nhin, php gn blocking assignment bn
trong parallel block (fork-join) s khng cn tr vic thc hin cc php gn k tip n.
Theo php gn qui trnh kn, = l ton t gn. iu khin vic nh thi (timing) cho
php gn c th dng mt iu khin tr hon (delay) (v d: #6) hay mt iu khin s kin (v
d: @(posedge clk) ). Gi tr ca biu thc bn phi php gn s c gn vo bn tri php
gn. Nu php gn i hi mt gi tr, gi tr ny s c gn n ngay ti thi im c khai
bo bi mt trong hai iu khin nh thi trn.
Ton t gn = dng trong php gn qui trnh kn cng c dng trong php gn ni
tip (php gn lin tc, continuous assignment).
V d 7.8 M t php gn qui trnh kn:
rega = 0;
rega[3] = 1; // gn ti 1 bit
rega[3:5] = 7; // gn ti mt phn ca mng
mema[address] = 8hff; // php gn n mt phn t nh.
{carry, acc} = rega + regb; // gn n mt php ni (concatenation)
7.3.2.1 Mch t hp vi php gn qui trnh kn

Nhng php gn qui trnh kn thng c s dng trong thit k mch t hp (combination
circuit). Tuy nhin, ta vn c th s dng php gn qui trnh kn m t mch tun t
(sequential circuit) nhng khng ph bin.
Khi dng php gn qui trnh kn thit k mch t hp, ta cn ch nhng yu cu mang
tnh bt buc sau:
Tt c cc tn hiu input phi c t trong danh sch nhy (sensitive list).
Tn hiu ng ra phi c gn trong tt c cc lung iu khin.
V d 7.9 Mch t hp chn knh, m t thit k ny p ng c hai yu cu mang tnh
bt buc trn.
module mux (f, sel, b, c);
output f;
input sel, b, c;
reg f;
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always @(sel or b or c)
if (sel == 1) f= b;
else f = c;
endmodule
iu kin 1: Ba tn hiu input l sel, b, c u nm trong sensitive list l @ (sel or b or

c).
iu kin 2: Tn hiu output f nm trong c hai lung iu khin (sel==1) v (sel ==0).
Ta cn ch y, nu trong m t thit k mch t hp ta khng tun theo hai iu kin
trn th thit k s khng sai v c php nhng chc nng ca thit k s khng nh ta mong
mun, xem v d sau:
V d 7.10
module mux (f, g, a, b, c);
output f, g;
input a, b, c;
reg f, g;
always @ (a or b or c)
if (a == 1)
f= b;
else g = c;
endmodule
Trong V d 7.10, iu kin 1 c p ng tuy nhin iu kin 2 khng c p ng,
trong lung iu khin u tin (a==1) ch c output f c gn, vy output g khng c gi tr
xc nh, tip n lung iu khin k tip (a==0) ch c output g c gn, vy output f khng
c gi tr xc nh. Nh vy y khng th l mt m t thit k cho mch t hp bi v trong
mch t hp khi tn hiu input xc nh th tt c cc gi tr output cng phi xc nh.
7.3.3
Php gn qui trnh h (non-blocking assignment)
Php gn qui trnh h cho php cc tt c cc php gn trong khi sequential block (beginend) c thc thi gn mt cch c lp m khng ph thuc vo qu trnh gn ca php gn
trc chng. Hay c th ni cch khc, tt c cc php gn trong sequential block (begin-end) s
c gn ng thi ngay ti mt thi im m khng cn quan tm n th t cng nh s ph
thuc vo cc php gn trc .
Theo php gn qui trnh h <= l ton t gn ca php gn qui trnh h. iu
khin vic nh thi (timing) cho php gn c th dng mt iu khin tr hon (delay) (v
d: #6) hay mt iu khin s kin (v d: @(posedge clk) ). Nu php gn i hi mt gi
tr t bn phi php gn, gi tr ny s c gn n cng ti thi im biu thc bn phi c
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xc nh. Th t ca vic xc nh gi tr gia php gn v biu thc bn phi s khng c xc
nh nu vic iu khin vic nh thi khng c m t.
Ton t ca php gn h <= ging nh ton t quan h nh hn hoc bng <=. Trnh
bin dch s quyt nh n thuc loi ton t no da vo bi cnh s dng n. Khi <=
c dng trong mt biu thc, n s c xem nh l mt ton t quan h, v khi n c
dng trong php gn qui trnh h th n c xem nh l mt ton t gn.
Php gn qui trnh h c tnh theo hai bc:
Bc 1: Trnh m phng xc nh cc gi tr ca biu thc bn phi ca tt c cc php gn
qui trnh h trong khi sequential block (begin-end) v ch chun b thc thi php gn
gi tr va xc nh khi c mt iu khin nh thi (#delay, @, wait()) hoc sau php gn
cui cng trong sequential block (begin-end) xy ra.
Bc 2: Khi iu khin nh thi (#delay, @, wait()) hoc sau php gn cui cng trong
sequential block (begin-end) xy ra, trnh m phng s gn cc gi tr c xc nh sn
trong bc 1 vo bn tri cc php gn mt cch ng thi.
V d 7.11 M t hai bc trong php gn qui trnh h
module evaluates2 (out);
output out;
reg a, b, c;
initial begin
a = 0;
b = 1;
c = 0;
end
always c = #5 ~c;
always @(posedge c) begin
a <= b; // tnh ton, ch gn
b <= a; // thc hin hai php gn
end
endmodule
Trong V d 7.11:
Bc 1: Trnh m phng xc nh cc gi tr ca biu thc bn phi ca tt c cc php gn

qui trnh h trong khi sequential block (begin-end) v ch chun b thc thi php gn gi tr
va xc nh khi c cnh ln xung clock c. Nh vy ti bc ny a vn mang gi tr 0, b vn
mang gi tr 1.
Bc 2: Ti cnh ln xung clock, trnh m phng s gn cc gi tr c xc nh sn
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trong bc 1 vo bn tri cc php gn mt cch ng thi. Nh vy, sau bc ny, a
c gn gi tr mi t b c sn trc l 1 cn b c gn gi tr mi t a c sn trc
l 0.
V d 7.12 So snh php gn qui trnh kn v qui trnh h trong vic khi to gi tr.
//non_block1.v
module non_block1;
reg a, b, c, d, e, f;
//php gn kn
initial begin
a = #10 1; // a s c gn = 1 ti t = 10
b = #2 0; // b s c gn = 0 ti t = 12
c = #4 1; // c s c gn = 1 ti t = 16
end
//php gn h
initial begin
d <= #10 1; // d s c gn = 1 ti t = 10
e <= #2 0; // e s c gn = 0 ti t = 2
f <= #4 1; // f s c gn = 1 ti t = 4 end
endmodule
Ta thy rng, khi s dng php gn qui trnh h, do tt c php gn ch c thc thi ng
thi ti bc 2 do th t ca cc php gn qui trnh h khng quan trng.
V d 7.13 So snh php gn qui trnh kn v qui trnh h trong m t mch tun t.
Blocking assignments
always @(posedge clk) begin
rega = data ;
regb = rega ;
end
Blocking assignments
regb = rega ;
rega = data ;
end
Trong php gn qui trnh kn, th th t gia cc php gn s nh hng n kt qu
synthesis ca phn cng to ra do trong php gn qui trnh kn, php gn ng sau ch
c thc thi khi gi tr ca php gn trc n c xc nh.
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Non-blocking assignments

rega <= data ;
regb <= rega ;
end
Non-blocking assignments
regb <= rega ;
rega <= data ;
end
Trong php gn qui trnh h, th th t gia cc php gn s khng nh hng n kt
qu synthesis ca phn cng to ra, do trong php gn qui trnh h cc php gn c thc
thi mt cch ng thi.
V d 7.14
//non_block1.v
module non_block1;
reg a, b;
initial begin
a = 0;
b = 1;
a <= b;
b <= a;
end
initial begin
$monitor ($time, ,"a = %b b = %b", a, b);
#100 $finish;
end
endmodule
Gi tr cui cng ca php gn : a = 1; b =0
7.3.3.1 Mch tun t vi php gn qui trnh h

Nhng php gn qui trnh h thng c s dng trong thit k mch tun t
(sequential circuit).
V d 7.15 M t thit k mch ghi dch (shifter)
module shifter (in, A,B,C,clk);
input in, clk;
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input A,B,C;
reg A, B, C;
always @ (posedge clk) begin
B <= A;
A <= in;
C <= B;
end
endmodule
iu ch trong v d trn l, th t ca cc php gn qui trnh h l khng quan trng.
Hnh 7.1 Phn cng thit k ca m t

V d 7.16 M t thit k mt my trng thi
module fsm (Q1, Q2, in, clock);
output Q1, Q2;
input clock, in;
reg Q1, Q2;
always @posedge clock) begin
Q1 <= in & Q0;
Q0 <= in | Q1;
end
endmodule
7.4 Pht biu c iu kin

Pht biu (expression) c iu kin (pht biu if-else) c s dng a ra mt quyt
nh xem mt pht biu (statement), mt php gn c c thc thi hay khng. C php ca
pht biu c iu kin nh sau
C php
conditional_statement ::=
if ( expression ) statement_or_null [ else statement_or_null ]
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statement_or_null ::= statement | ;
Theo C php, nu biu thc (expression) c xc nh l ng (ngha l mt gi tr khc
khng) th pht biu (statement) s c thc thi. Nu biu thc (expression) c xc nh l
sai (ngha l mt gi tr bng 0, x hoc z) th pht biu khng c thc thi. Nu trong pht
biu c iu kin m c thm pht biu else v gi tr ca biu thc (expression) l sai th
pht biu else s c thc thi. Bi v gi tr s hc ca biu thc if s c kim tra xem c
phi l 0 hay khng, biu thc c th c vit ngn gn.
V d 7.17 Ba pht biu s m t cng mt logic
if (expression)
if (expression !=0)
if (expression == 1)
Bi v phn else trong pht biu if-else l ty chn, c th c hoc khng nu khng cn
thit nn c th gy hiu lm khi phn else b b i trong cc pht biu m cc mnh if lin
tip nhau. khng b bi ri trong suy ngh ta cn nh rng phn else lun l mt phn ca
mnh if gn nht vi n. Ta xem xt 3 v d sau:
V d 7.18
if (index > 0)
if (rega > regb)
result = rega;
else
result = regb;
Vi m t thit k nh trn, do ngi vit khng cn thn dn n ngi c d hiu lm
l pht biu else l mt phn ca pht biu if (index > 0). Nhng pht biu else y l mt
phn ca pht biu if (rega > regb) v n gn nht vi else.
V d 7.19
if (index > 0)
if (rega > regb)
result = rega;
else
result = regb;
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Vi cch m t r rng nh trn th s hn ch c nhng hiu lm trong thit k.
kim sot cht ch hn, khi m t ta nn thm begin-end block vo pht biu if-else.
V d 7.20
if (index > 0)
begin
if (rega > regb)
result = rega;
end
else result = regb;
Trong trng hp ny, pht biu else s l mt phn ca pht biu if (index > 0)
7.4.1
Cu trc if-else-if
Cu trc if-else-if rt thng xut hin trong m t thit k. C php ca n nh sau:

C php
if_else_if_statement ::=
if (expression) statement_or_null
{ else if (expression) statement_or_null }
else statement
Chui pht biu if-else-if ny l cch ph bin nht trong vic m t a ra nhiu quyt
nh. Biu thc s c tnh theo th t, nu bt k biu thc no l ng th pht biu i km
vi n s c thc thi v sau n s thot ra khi chui pht biu. Mi pht biu c th
l mt pht biu n hay mt khi cc pht biu nm trong begin-end block.
Phn pht biu else cui cng trong cu trc if-else-if s c thc thi khi m khng c
iu kin no p ng c cc iu kin trn n. Phn else thng c s dng to ra
cc gi tr mc nh, hoc dng trong qu trnh kim tra li.
Trong m t thit k sau s dng pht biu if-else kim tra bin index a ra quyt
nh xem mt trong ba bin thanh ghi modify_segn c phi c cng vo a ch nh hay
khng, v vic tng ny phi c cng vo bin thanh ghi index. Mi dng u tin khai bo
bin thanh ghi v cc tham s.
V d 7.21
// khai bo kiu d liu bin v khai bo tham s
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reg [31:0] instruction, segment_area[255:0];
reg [7:0] index;
reg [5:0] modify_seg1, modify_seg2, modify_seg3;
parameter
segment1 = 0, inc_seg1 = 1, segment2 = 20,

inc_seg2 =2, segment3 = 64, inc_seg3 = 4, data = 128;
// kim tra ch s bin

if (index < segment2) begin
instruction = segment_area [index + modify_seg1];
index = index + inc_seg1;
end
else if (index < segment3) begin
end
else if (index < data) begin
end
else instruction = segment_area [index];
7.5 Pht biu Case

Pht biu case l pht biu to ra nhiu s la chn, n kim tra xem mt biu thc c ph
hp vi mt biu thc khc hay khng. C php ca pht biu case nh sau:
C php
case_statement ::=
| case ( expression ) case_item { case_item } endcase
| casez ( expression ) case_item { case_item } endcase
| casex ( expression ) case_item { case_item } endcase
case_item ::=
expression { , expression } : statement_or_null
| default [ : ] statement_or_null
Pht biu default c th la chn c hoc khng c. S dng nhiu pht biu defaut trong
mt pht biu case l khng hp l.
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Mt v d n gin dng pht biu case gii m bin thanh ghi rega to ra gi tr
cho bin thanh ghi result nh sau:
V d 7.22
reg [15:0] rega;
reg [9:0] result;
case (rega)
16d0: result = 10b0111111111;
16d1: result = 10b1011111111;
16d2: result = 10b1101111111;
16d3: result = 10b1110111111;
16d4: result = 10b1111011111;
16d5: result = 10b1111101111;
16d6: result = 10b1111110111;
16d7: result = 10b1111111011;
16d8: result = 10b1111111101;
16d9: result = 10b1111111110;
default result = bx;
endcase
Nhng biu thc trong case item s c tnh ton v so snh theo th t m chng c
cho. Theo th t t trn xung, nu mt trong cc biu thc trong case item ph hp vi biu
thc trong du ngoc n () ca case th pht biu m kt hp vi case item s c thc thi.
Nu tt c cc so snh u khng ng th pht biu m kt hp vi default item s c thc
thi. Nu default item khng c m t trong pht biu case v tt c cc so snh u khng
ng th khng c bt k pht biu no c thc thi.
Khc c php, pht biu case khc vi cu trc if-else-if hai im quan trng sau:
Biu thc c iu kin trong if-else-if ph bin hn vic so snh biu thc vi nhiu
biu thc khc trong pht biu case.
Pht biu case cung cp mt kt qu r rng khi biu thc c gi tr l x hoc z.
Trong vic so snh biu thc ca pht biu case, vic so snh ch thnh cng khi mi bit
ging nhau chnh xc mt cch tng ng theo cc gi tr 0, 1, x, v z. Kt qu l, s cn trng
khi m t thit k s dng pht biu case l cn thit. di bit ca tt c cc biu thc s phi
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bng nhau vic so snh bit-wise gia cc bit c th c thc hin.
di ca tt c biu thc trong case item cng nh biu thc trong () ca case phi bng
vi di ln nht ca biu thc ca case v case item.
Ch : di mc nh ca x v z bng vi di mc nh ca mt s nguyn (integer).
L do ca vic cung cp kh nng so snh biu thc ca case l gip x l nhng gi tr x
v z, iu ny cung cp mt c ch pht hin ra nhng gi tr ny v c th kim sot c
thit k khi s xut hin ca chng.
V d sau minh ha vic s dng pht biu case x l nhng gi tr x v z mt cch thch
hp.
V d 7.23
case (select[1:2])
2b00: result = 0;
2b01: result = flaga;
2b0x,2b0z: result = flaga ? bx : 0;
2b10: result = flagb;
2bx0,2bz0: result = flagb ? bx : 0;
default result = bx;
endcase
Trong V d 7.23, trong case item th 3, nu select[1] l 0 v flaga l 0 th select[2] c l x
hoc z th result s l 0.
Trong V d 7.24 s minh ha mt cch khc s dng pht biu case pht hin x v
z
V d 7.24
case (sig)
1bz: $display("signal is floating");
1bx: $display("signal is unknown");
default: $display("signal is %b", sig);
endcase
7.5.1
Pht biu Case vi dont care
Hai loi khc ca pht biu case c cung cp cho php x l nhng iu kin dont care
trong vic so snh case. Mt l x l gi tr tng tr cao (z) nh l dont care, hai l x
l nhng gi tr tng tr cao (z) v gi tr khng xc nh (x) nh l dont care.
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Nhng gi tr dont care (gi tr z cho casez, z v x cho casex) trong bt k bit no
ca biu thc trong case hay trong case item s u c xem nh nhng iu kin dont
care trong sut qu trnh so snh, v v tr ca bit s khng c xem xt. Nhng iu kin
dont care trong biu thc case c th c iu khin mt cch linh ng, bit no nn c
so snh ti thi im no.
C php ca s hc cho php s dng du chm hi (?) thay th cho z trong nhng pht
biu case. iu ny cung cp mt nh dng thun tin cho vic m t nhng bit dont care
trong pht biu case.
V d 7.25 dng pht biu casez. N minh ha mt mch gii m lnh, nhng gi
tr c trng s ln nht chn tc v (task) no cn c gi. Nu bit c trng s ln nht
ca ir l 1 th tc v instruction1 c gi m khng cn quan tm n gi tr ca cc bit khc
trong ir.
V d 7.25
reg [7:0] ir;
casez (ir)
8b1???????: instruction1(ir);
8b01??????: instruction2(ir);
8b00010???: instruction3(ir);
8b000001??: instruction4(ir);
endcase
V d 7.26 dng pht biu casex. N minh ha mt case m nhng iu kin dont
care c iu khin mt cch linh hot trong qu trnh m phng. Trong case ny, nu r =
8b01100110, th tc v stat2 s c gi.
V d 7.26
reg [7:0] r, mask; mask = 8bx0x0x0x0;
casex (r ^ mask)
8b001100xx: stat1;
8b1100xx00: stat2;
8b00xx0011: stat3;
8bxx010100: stat4;
endcase
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7.5.2
Pht biu case vi biu thc hng s
Biu thc hng s c th c dng trong biu thc ca case. Gi tr ca biu thc hng s
s c so snh vi biu thc ca case item.
V d 7.27 Minh ha vic s dng mch m ha u tin 3bit
reg [2:0] encode ;
case (1)
encode[2] : $display(Select Line 2) ; encode[1] : $display(Select Line 1) ;
encode[0] : $display(Select Line 0) ;
default $display(Error: One of the bits expected ON);
endcase
Ch rng, biu thc trong case l mt biu thc hng s (1). Cc case item l biu thc
(bit-selects) v s c so snh vi biu thc hng s. Nh vy, ch khi mt trong cc bit ca
encode bng 1 th biu thc i km vi n mi c thc thi.
V d 7.28
reg [2:0] encode ;
case (0)
encode[2] : $display(Select Line 2) ; encode[1] : $display(Select Line 1) ;
encode[0] : $display(Select Line 0) ;
default $display(Error: One of the bits expected ON);
endcase
Vi v d trn, ch khi mt trong cc bit ca encode bng 0 th biu thc i km vi n
mi c thc thi.
7.6
Pht biu vng lp
7.6.1
Cc pht biu lp
Trong Verilog h tr bn loi pht biu lp vng. Nhng pht biu ny cung cp phng
tin kim sot mt pht biu phi cn thc thi bao nhiu ln, c th l mt ln, nhiu ln hoc
c th l khng ln no.
forever: Thc thi mt pht biu lin tc.
repeat: Thc thi mt pht biu vi mt s ln c nh. Nu biu thc s ln lp c gi tr
l khng xc nh (x) hoc tng tr cao (z), n s c xem nh c gi tr zero v khng
c pht biu no c thc thi.
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while: Thc thi mt pht biu cho n khi mt biu thc iu kin tr thnh sai
(false). Nu biu thc iu kin c gi tr bt u l sai (false) th pht biu s khng
c thc thi ln no.
for: iu khin vic thc thi nhng pht biu kt hp vi n bi ba bc sau:
Thc thi mt php gn mt cch bnh thng dng khi to gi tr mt thanh
ghi iu khin s ln cn thc thi lp li.

Xc nh gi tr biu thc iu kin nu kt qu l zero th vng lp for kt thc,
nu kt qu khc khng th vng lp for s thc thi nhng pht biu kt hp vi n,

sau thc hin tip bc c. Nu gi tr biu thc l khng xc nh (x) hay tng
tr cao (z), n s c xem nh zero.
Thc thi mt php gn thng thng dng cp nht gi tr cho thanh ghi iu
khin lp vng, sau lp li bc b.

C php cho nhng pht biu vng lp:
7.6.2
C php
looping_statements ::=
| forever statement
| repeat ( expression ) statement
| while ( expression ) statement
| for ( reg_assignment ; expression ; reg_assignment ) statement
V d 7.29 Pht biu repeat mch nhn s dng ton t add v shift.
parameter size = 8, longsize = 16;
reg [size:1] opa, opb;
reg [longsize:1] result;
initial begin //mult
reg [longsize:1] shift_opa, shift_opb;
shift_opa = opa;
shift_opb = opb;
result = 0;
repeat (size) begin
if (shift_opb[1]) result = result + shift_opa;
shift_opa = shift_opa << 1;
shift_opb = shift_opb >> 1;
end
end
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V d 7.30 Pht biu while m s logic 1 ca mt gi tr trong thanh ghi rega.
begin : count1s
reg [7:0] tempreg;
count = 0;
tempreg = rega;
while (tempreg) begin
if(tempreg[0])
count = count + 1;
tempreg = tempreg >> 1;
end
end
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V d 7.31 M t thit k mch to bit chn l, s dng vng lp while.
`timescale 1ns/100ps
module parity_gen (a, p);
parameter SIZE = 8;
input [SIZE-1:0] a;
output reg p;
reg im_p;
integer indx;
always @( a ) begin
im_p = 0;
indx = 0;
while (indx < SIZE) begin
im_p = im_p ^ a[indx];
indx = indx + 1;
end
p = im_p;
end
endmodule
V d 7.32 Vng lp for: Pht biu for s cho kt qu nh pseudo-code sau m da trn
vng lp while.
begin
initial_assignment;
while (condition) begin statement
step_assignment;
end
end
Vng lp for thc thi cng chc nng trn nhng ch cn hai dng nh pseudo code sau:
for (initial_assignment; condition; step_assignment)
statement
V d 7.33 M t thit k mch t hp priority-encoder dng vng lp for
module priority_encoder (i0, i1, i2, i3, y0, y1, f);
input i0, i1, i2, i3;
output reg y1, y0, f;
wire [3:0] im = { i3, i2, i1, i0 };
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reg [2:0] indx;
always @(im) begin
{ y1, y0 } = 2b00;
f = 1b0;
for (indx=0; indx<4; indx=indx+1) begin if ( im[indx] ) begin
{ y1, y0 } = indx;
f = 1b1;
end
end
end
endmodule
7.7
iu khin nh thi (procedural timing controls)
Verilog HDL h tr ba phng php iu khin nh thi tng minh khi nhng pht
biu qui trnh xut hin. Loi u tin l iu khin tr hon delay control, loi th hai
l iu khin s kin event control. Loi th ba l pht biu wait.
Mt iu khin tr hon, c nhn din bt u vi k hiu #.
Mt iu khin s kin, c nhn din bt du vi k hiu @.
Pht biu wait, hot ng ca n l s kt hp gia iu khin s kin v vng lp while
nhng i lp v chc nng.
V d 7.34
#150 regm = regn;
@(posedge clock) regm = regn;
@(a, b, c) y = (a & b) | (b & c) | (a & c);
Vic m t thi gian tr hon cho cng v net s dng trong m phng c cp
trong cc phn trn, trong phn ny ch tho lun v ba phng php iu khin nh thi trong
cc php gn qui trnh.
7.7.1
iu khin tr hon (delay control)
Mt pht biu qui trnh theo sau mt iu khin tr hon s b tr hon vic thc thi
mt khong thi gian c m t trong iu khin tr hon. Nu biu thc tr hon c gi tr l
khng xc nh hoc tng tr cao, n s c xem nh c tr hon bng 0. Nu biu thc tr
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hon c gi tr m, n s xem nh l khong thi gian c gi tr s nguyn khng du b 2.
V d 7.35
V d 1: Thc thi php gn sau 10 n v thi gian
# 10 rega = regb;
V d 2: Biu thc tr hon
#d rega = regb; // d c nh ngha nh l mt tham s
#((d+e)/2) rega = regb;// tr hon l gi tr trung bnh ca d v e
#regr regr = regr + 1; // tr hon l gi tr trong regr
7.7.2
iu khin s kin (event control)
Vic thc thi mt pht biu qui trnh c th c ng b vi s thay i gi tr trn mt

net hay mt thanh ghi hoc s xut hin ca mt khai bo s kin. Nhng s thay i gi tr
trn net hay trn thanh ghi c th c xem nh mt s kin dng kch hot s thc thi ca
mt pht biu. iu ny ging nh vic d tm mt s kin khng tng minh. S kin c th
c da trn hng ca s thay i l hng ln 1 (posedge) hay hng xung 0 (negedge).
Verilog HDL h tr ba loi iu khin s kin:
S kin c th c d tm khi c bt k s chuyn trng thi no xy ra trn net hoc
thanh ghi. c m t bi @ (net ) hay @ (reg).
S kin negedge c th c d tm khi c s chuyn trng thi t 1 xung x, z, hoc
0, v t x hoc z xung 0. c m t bi @ (negedge net ) hay @ (negedge reg)
S kin posedge c th c d tm khi c s chuyn trng thi t 0 ln x, z, hoc 1, v
t x hoc z ln 1. c m t bi @ (posedge net ) hay @ (posedge reg)
To
From
0
1
x
z
No edge
negedge
negedge
negedge
posedge
No edge
posedge
posedge
posedge
negedge
No edge
No edge
posedge
negedge
No edge
No edge
Nu gi tr ca biu thc nhiu hn 1 bit, s chuyn trng thi cnh s c d tm trn bit
c trng s thp nht ca gi tr . S thay i gi tr trong bt k ton hng no m khng c
s thay i gi tr trn bit c trng s thp nht ca biu thc th s chuyn trng thi cnh
khng th c d thy.
V d 7.36 Minh ha nhng pht biu iu khin s kin
@r rega = regb; // c iu khin bi bt k s thay i gi tr trn thanh ghi r.
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@(a, b, c) rega = regb; // tng ng vi @(a or b or c) rega = regb /* c iu
khin bi bt k s thay i no ca cc tn hiu a, b hoc c.*/
@(posedge clock) rega = regb; // c iu khin bi cnh ln xung clock.
@(posedge clk_a or posedge clk_b or trig) rega = regb;/* c iu khin bi cnh
ln tn hiu clk_a hoc cnh xung tn hiu clk_b hoc c bt k s thay i no xy ra
trn tn hiu trig.*/
forever @(negedge clock) rega = regb; // c iu khin bi cnh xung xung clock
V d 7.37
module maj3 (input a, b, c, output reg y);
always @(a, b, c) begin // tng ng vi @(a or b or c)
y = (a & b) | (b &c) | (a & c);
end
endmodule
Do m t thit k trn ch c mt php gn qui trnh, nn y ta khng cn dng khi
begin-end. V d trn c th c rt gn hn nh sau:
V d 7.38
module maj3 (input a, b, c, output reg y);
always@(a, b, c)
y = (a & b) | (b & c) | (a & c);
// c th vit nh sau: @(a, b, c) y = (a & b) | (b & c) | (a & c);
endmodule
Trong V d 7.38, iu khin s kin c t trc pht biu hnh thnh mt pht
biu qui trnh bng cch b i du chm phy. iu ny c ngha du chm phy sau @(a, b,
c) c th c hoc khng. Khi hai pht biu trn c ghp li th ch mt pht biu c thc
thi.
7.7.3
Pht biu wait
Vic thc thi mt pht biu qui trnh c th c tr hon cho n khi mt iu kin tr
thnh ng (true). iu ny t c bng s dng pht biu wait, y l mt dng c bit ca
iu khin s kin. Mc nh ca pht biu wait l tch cc mc, iu ny tri ngc vi
pht biu iu khin s kin l tch cc cnh.
Pht biu wait s tnh gi tr ca iu kin, nu gi tr sai (false), nhng pht biu qui trnh
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theo sau n s b ng li khng thc thi cho n khi gi tr tr thnh ng (true) th mi
thc thi nhng pht biu qui trnh v thot ra khi pht biu wait tip tc cc pht
biu k tip, iu ny i lp vi hot ng ca pht biu vng lp while, trong pht biu
vng lp while, gi tr ca iu kin nu ng (true) th nhng pht biu qui trnh theo sau
n s thc thi lp li lin tc trong vng lp cho n khi gi tr ca iu kin tr thnh sai (false)
th thot ra khi vng lp while tip tc cc pht biu k tip. C php ca nhng pht
biu wait c m t nh sau:
C php
wait_statement::=
wait (expression) statement_or_null
V d 7.39
begin
wait (!enable) #10 a = b;
#10 c = d;
end
Nu gi tr enable l 1, pht biu wait s tr hon vic thc thi ca pht biu k tip n
(#10 a = b;) cho n khi gi tr ca enable l 0. Nu enable c gi tr sn l 0 khi khi
begin-end bt u th php gn a = b; s c gn sau khong tr hon 10 n v thi gian
v khng c thm tr hon no xut hin.
V d 7.40
always begin
wait (var1 ==1);
a = b; end
V d 7.40 m t mt thit k thc hin chc nng khi var bng 1 th a s lin tc cp nht gi
tr t b.
V d 7.41
always
begin
@var
wait (var1 ==1);
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a = b;
end
V d trn m t mt thit k thc hin chc nng khi var chuyn trng thi ln 1 th
a s cp nht gi tr t b. Tng t nh m t sau:
always @var1
if (var1 ==1)
a = b;
7.8 Pht biu khi

Trong khai bo qui trnh, Verilog HDL c h tr vic pht biu khi. Pht biu khi l
vic nhm hai hay nhiu pht biu cng vi nhau chng c th hot ng theo cng c
php nh l mt pht biu n. C hai loi khi trong Verilog HDL:
Khi tun t, hay cn c gi l khi begin-end
Khi song song, hay cn c gi l khi fork-join
Khi tun t c gii hn bi hai t kha begin v end. Nhng pht biu qui trnh trong
khi tun t s c thc thi mt cch tun t theo th t c cho.
Khi song song c gii hn bi hai t kha fork v join. Nhng pht biu qui trnh trong
khi song song s c thc thi mt cch ng thi
7.8.1
Khi tun t
Mt khi tun t s c nhng c im sau:

Nhng pht biu c thc thi theo th t, ci ny xong n ci kia.
Gi tr tr hon ca mt pht biu l thi gian m phng vic thc thi ca pht biu
ngay trc pht biu hin ti.
iu khin s thot ra khi khi sau khi pht biu cui cng c thc thi.
V d 7.42
begin
areg = breg;
creg = areg; // creg lu trgi trca breg
end
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V d 7.43 iu khin tr hon c th c dng trong khi tun t phn bit hai
php gn theo thi gian
begin
areg = breg;
@(posedge clock) creg = areg; // php gn b tr hon cho n
end
// khi c cnh ln xung clock.
V d 7.44 Kt hp khi tun t v iu khin tr hon c th c s dng m t dng

sng.
parameter d = 50;
reg [7:0] r;
begin // mt dng sng c iu khin bi thi gian tr hon tun t
#d r = h35;
#d r = hE2;
#d r = h00;
#d r = hF7;
#d -> end_wave;//kch hot mt s kin c tn l end_wave
end
7.8.2
Khi song song (fork-join)
Mt khi song song c nhng c im sau:

Nhng pht biu s c thc thi ng thi
Gi tr tr hon ca mi pht biu l thi gian m phng c tnh t khi lung iu
khin bc vo khi fork-join cho n pht biu .
iu khin tr hon c s dng cung cp thi gian tun t cho cc php gn.
iu khin s thot ra khi khi khi pht biu c th t cui cng theo thi gian
(gi tr tr hon ln nht) c thc thi.
Nhng iu khin nh thi trong khi fork-join khng phi theo th t tun t theo thi
gian.
V d 7.45 s m t dng sng ging nh trong v d trn nhng dng khi song song
thay v dng khi tun t. Dng sng c to ra trn mt thanh ghi s ging nhau trong c hai
trng hp.
V d 7.45
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fork
#50 r = h35;
#200 r = hF7; // khng cn theo th t
#100 r = hE2;
#250 -> end_wave; // iu khin thot ra
#150 r = h00;
join
7.8.3
Tn khi
C hai khi tun t v song song u c th c t tn bng cch thm : name_of_block

ngay sau t kha begin hay fork.
Tn ca khi phc v cho cc mc ch sau:
N cho php nhng thanh ghi ni c khai bo cho khi
N cho php khi c tham chiu trong nhng pht biu chng hn nh
pht biu disable.
Tt c cc thanh ghi l tnh, ngha l mt v tr duy nht tn ti trong tt c cc thanh ghi v

ri khi hoc tin vo khi s khng nh hng n gi tr cha trong n.
Tn khi s l tn nh dng duy nht cho tt c cc thanh ghi ti bt k thi im m phng
no.
7.9 Cu trc qui trnh

Tt c qui trnh trong Verilog HDL phi u c m t bn trong mt trong bn cu trc
sau:
Cu trc initial
Cu trc always
Task
Function
Cu trc initial v always c cho php hot ng ti thi im bt u m phng. Cu
trc initial ch thc thi mt ln v hot ng ca n s ngng khi pht biu hon thnh. Tri li,
cu trc always s thc thi lp li, hot ng ca n s ch ngng khi qu trnh m phng b
thot ra. iu ny khng ng n th t ca vic thc thi gia hai cu trc intial v always.
Cu trc initial khng cn ln k hoch trc v cn thc thi trc cu trc always. y cng
khng c s gii hn no v s lng cu trc initial v always c th c m t trong mt
module.
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Tc v (task) v hm (function) s c cho php hot ng t mt hoc nhiu v tr trong
nhng qui trnh khc nhau. Task v function s c tho lun chi tit trong chng sau.
7.9.1
Cu trc initial
C php ca cu trc initial

initial_construct::=
initial statement
V d 7.46 Dng cu trc initial cho vic khi to bin ti thi im bt u m phng.
initial begin
areg = 0; // khi to mt thanh ghi
for (index = 0; index < size; index = index + 1)
memory[index] = 0; //khi to gi tr cho phn t nh
end
Mt cng dng thng gp ca cu trc initial l m t dng sng chy m phng cho
thit k
V d 7.47
initial begin
inputs = b000000; //khi to ti thi im zero
#10 inputs = b011001; // 10 n v thi gian u
#10 inputs = b011011; // 10 n v thi gian th hai
#10 inputs = b011000; // 10 n v thi gian th ba
#10 inputs = b001000; // 10 n v thi gian cui
end
7.9.2
Cu trc always
Cu trc always cho php lp li lin tc trong sut qu trnh m phng.

C php ca cu trc always
always_construct ::=
always statement
Cu trc always do c tnh vng lp t nhin ca n nn ch hu dng khi c dng kt
hp vi mt s dng iu khin nh thi khc. Nu mt cu trc always khng c iu khin
nh thi, n s to ra mt vng lp v hn. V d sau s to ra mt vng lp v hn khng tr
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hon:
always areg = ~areg;
Cung cp mt iu khin nh thi vo on m t trn s to ra mt m t hu dng nh v
d sau:
always #half_period areg = ~areg;
7.10My trng thi (state machine)

My trng thi l my trong tt c cc output c ng b vi xung clock ca h thng.
S dng nhng cu trc m t Verilog HDL m ta tho lun cho n lc ny c th m
t cho bt k loi my trng thi no. Trong phn ny, ta s tho lun c th dng nhng
cu trc Verilog hc m t mt cch tng minh, khoa hc mt my trng thi hu hn. Ta
bt u vi m hnh my trng thi Moore, sau l m hnh my trng thi Mealy.
7.10.1 My trng thi Moore

My trng thi hu hn Moore l my trong ng ra ca h thng ch ph thuc vo trng
thi hin ti ca h thng ch khng ph thuc vo ng vo h thng. H thng my trng thi
hu hn Moore c m t nh hnh di y:
Hnh 7.2 H thng my trng thi hu hn Moore

Vi s khi trn, ta c th m t ngn gn nguyn l my trng thi Moore nh sau:
Next state = F (current state, inputs)
Outputs = G (current state)
Da vo s khi trn, m t mt cch tng minh mt my trng thi hu hn Moore
dng Verilog HDL, ta s m t nh sau:
comb. circuit 1: Khi mch t hp dng cu trc always kim sot s chuyn i
gia cc trng thi to ra trng thi k tip.
memory elements: Khi mch tun t dng to ra trng thi hin ti.
comb. circuit 2: Khi mch t hp khc dng php gn assign to ra gi tr ng ra
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ca h thng.
Hnh 7.3 m t lu my trng thi hu hn Moore c chc nng d tm chui 101 lin
tc dng Verilog HDL. H thng my trng thi d tm chui 101 lin tc t ng vo ca n,
khi chui 101 c pht hin th ng ra s ln 1 v duy tr gi tr ny cho n ht mt chu k
xung clock. Nh c m t trong lu my trng thi, khi my t n trng thi got101 th
ng ra s bt ln 1.
V d 7.48 m t code Verilog cho h thng ny. Chng ta s dng mt khai bo
parameter gn gi tr n cc my trng thi. My trng thi ca ta c bn trng thi do
cn s dng 2 bit khai bo trng thi.
Hnh 7.3 Lu my trng thi hu hn Moore c chc nng d tm chui 101 lin tc.
V d 7.48 M t thit k my trng thi Moore
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module Moore101Detector (dataIn, found, clock, reset);
//Khai bo cng ng vo, ng ra
input
dataIn;
input
clock;
input
reset;
output
found;
//Khai bo bin ni
reg [1:0] state;
reg [1:0] next_state;
//Khai bo trng thi
parameter reset = 2'b00;
parameter got1 = 2'b01;
//Mch t hp ca trng thi k tip
always @(state or dataIn)
case (state)
reset:
if (dataIn)
next_state = got1;
else
next_state = reset;
got1:
if(dataIn)
next_state = got1;
else
next_state = got10;
got10:
if(dataIn)
next_state = got101;
else
next_state = reset;
got101:
if(dataIn)
next_state = got1;
else
next_state = got10;
default:
next_state = reset;
endcase// case(state)
//Mch chuyn trng thi
always@(posedge clock)
if(reset == 1)
state <= reset;
else
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Mch sau khi c tng hp s c nh trn Hnh 7.4. Mch s gm ba phn ng nh

h thng my trng thi Moore: mch t hp trng thi k tip, mch chuyn trng thi v
mch t hp ng ra, trong gi tr ng
ra ch ph thuc vo trng thi hin ti.
Hnh 7.4 Mch pht hin chui 101 sau tng hp s dng FSM Moore
7.10.2 My trng thi Mealy

My trng thi hu hn Mealy l my trong ng ra ca h thng ph thuc vo c trng
thi hin ti ca h thng v ng vo ca h thng. H thng my trng thi hu hn Mealy
c m t nh hnh di:
Hnh 7.5 H thng my trng thi hu hn Mealy

Vi s khi trn, ta c th m t ngn gn nguyn l my trng thi Mealy nh sau:
Next state = F (current state, inputs) Outputs = G (current state, inputs)
Da vo s khi trn, m t mt cch tng minh mt my trng thi hu hn Mealy dng
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Verilog HDL, ta s m t nh sau:
comb. circuit 1Khi mch t hp dng cu trc always kim sot s chuyn i gia
cc trng thi to ra trng thi k tip.
memory elements: Khi mch tun t dng to ra trng thi hin ti.
comb. circuit 2: Khi mch t hp khc dng php gn assign to ra gi tr ng ra
ca h thng.
Hnh 7.6 m t lu my trng thi hu hn Mealy c chc nng d tm chui 101 lin
tc dng Verilog HDL (ging nh minh ha trong my trng thi Moore). H thng my trng
thi d tm chui 101 lin tc t ng vo ca n, khi chui 101 c pht hin th ng ra s
ln 1 v duy tr gi tr ny cho n ht mt chu k xung clock. Nh c m t trong lu my
trng thi, khi my t n trng thi got101 th ng ra s bt ln 1.
V d 7.49 m t code Verilog cho h thng trn. Chng ta s dng mt khai bo
parameter gn gi tr n cc my trng thi. My trng thi ca ta c ba trng thi nn
cn s dng 2 bit khai bo trng thi.
Hnh 7.6 Lu my trng thi hu hn Mealy c chc nng d tm chui 101 lin tc.
V d 7.49
module Mealy101Detector (dataIn, found, clock, reset);
//Khai bo cng ng vo, ng ra
input
dataIn; input
clock; input
reset; output
found;
//Khai bo bin d liu ni

reg [1:0] state;
reg [1:0] next_state;
//Khai bo trng thi parameter reset = 2'b00; parameter got1 = 2'b01; parameter
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got10 = 2'b10;
//Khai bo mch t hp trng thi k tip
always @(state or dataIn)
case (state)
reset:
if (dataIn)
next_state = got1;
else
next_state = reset;
got1:
if(dataIn)
next_state = got1;
else
next_state = got10;
got10:
if(dataIn)
next_state = got1;
else
next_state = reset;
default:
next_state = reset;
endcase// case(state)
//Mch chuyn trng thi
always@(posedge clock)
if(reset == 1)
state <= reset;
else
state <= next_state;
//Mch thp ng ra
assignfound = (state == got10 && dataIn == 1) ? 1: 0;
endmodule// Mealy101
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Hnh 7.7 Mch pht hin chui 101 sau tng hp s dng FSM Mealy
Hnh 7.7. Mch gm ba phn ng nh h thng my trng thi Mealy: mch t hp trng
thi k tip, mch chuyn trng thi v mch t hp ng ra, trong ng ra ph thuc vo gi tr
ng vo v trng thi hin ti.
7.11Bi tp
1. Nu s khc bit gia m hnh cu trc v m hnh hnh vi trong m t phn cng Verilog
HDL. Nu u im v khuyt im ca tng m hnh.
2. Nu s khc bit gia php gn qui trnh kn v php gn qui trnh h.
3. Trong m hnh hnh vi, nu s khc bit gia php gn lin tc (cn gi l continuous
assignment hay php gn RTL) vi php gn qui trnh.
4. Ti sao ta phi s dng hm v tc v trong m t phn cng Verilog HDL?
5. Nu s khc bit gia hm, tc v v module trong m t phn cng Verilog HDL?
6. Nu nhng rng buc khi s dng php gn qui trnh kn trong m t mch t hp?
7. Nu s khc bit gia pht biu case v casex.
8. Nu s khc nhau gia my trng thi Moore v my trng thi Mealy trong m t
phn cng Verilog HDL. Nu u im v khuyt im ca mi loi. Trnh by s tng ng
gia cc phn trong mch phn cng v cc phn trong m t Verilog khi s dng phng
php my trng thi Moore hoc Mealy.
9. Nu nhng phng php iu khin nh thi trong m t phn cng Verilog HDL ?
10. C my loi cu trc qui trnh trong m t phn cng Verilog HDL ?. Nu s khc bit
gia cu trc initial v cu trc always ? Ti sao cu trc initial khng th tng hp ra
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mch phn cng ?
11. C my loi pht biu khi (block assignment) trong m t phn cng Verilog HDL ?
Nu s khc bit gia chng.
12. Vit li on m t thit k s dng php gn h cho on m t thit k sau chc
nng khng i
initial begin
a = #delay1 b;
c = #delay2 d;
end
13. Thay th ba khi initial nh di bi mt khi duy nht
initial
a = #delay1 b;
initial
c = #delay2 d;
initial
begin
e <= #delay3 f;
k <= #delay4 g;
end
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14. on code sau thc hin chc nng g? Vit li on m t li s dng php gn kn
always @(posedge clock) begin
a <= b;
b <= a;
end
15. on code sau thc hin chc nng g? Vit li on m t li s dng php gn kn
always @(posedge clock)
#0 a <= b + c;
always @(posedge clock)
b <= a;
16. V dng sng ca tn hiu d trn ton b thi gian m phng
module test; reg b,c,d; initial begin
b=1b1;
c=1b0;
#10 b=1b0;
end
initial d = #25(b|c);
endmodule
17. V dng sng ca a, b v c trong 100ns u tin ca qu trnh m phng.
module test;
wire a, b;
reg c;
assign #60 a = 1 ;
initial begin
#20 c = b;
#20 c = a;
#20;
end endmodule
18. Kim tra xem on m t sau c thc hin chc nng tm gi tr ln nht c khng?
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reg [3:0] mx;

reg [3:0] lst [0:3];
always @ (lst[0] or lst[1] or lst[2] or lst[3]) begin
mx <= 4b0000;
if ( lst[0] >= mx ) mx <= lst[0]; if ( lst[0] >= mx ) mx <= lst[1]; if ( lst[0] >= mx ) mx
<= lst[2]; if ( lst[0] >= mx ) mx <= lst[3];
end
19. Kim tra xem hai on m t thit k sau c cng chc nng hay khng?
M t 1:
module addr_dcd (addr_in, decoded_addr);
parameter ADDRESS = 8;
parameter RAMSIZE = 256;
input [ADDRESS 1 : 0] addr_in;
output
[RAMSIZE - 1 : 0] decoded_addr;
integer
i;
reg [RAMSIZE 1 : 0] decoded_addr;

always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)
decoded_addr[ i ] = (addr_in == i);
end endmodule
M t 2:
module addr_dcd (addr_in, decoded_addr);
parameter ADDRESS = 8;
parameter RAMSIZE = 256;
input [ADDRESS 1 : 0] addr_in;
output
[RAMSIZE - 1 : 0] decoded_addr;
integer
i;
reg [RAMSIZE 1 : 0] decoded_addr;

always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)
decoded_addr[ i ] <= (addr_in == i);
end endmodule
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8 Chng 8.
Tc v (task) v hm (function)
task v function cung cp kh nng thc thi cc th tc chung t nhiu ni khc nhau trong
mt m t thit k. Chng cung cp mt phng tin chia nh nhng m t thit k ln, phc
tp thnh nhng phn nh hn d dng trong vic c v g ri cc m t thit k ngun.
Nh ta bit, trong m hnh cu trc ta c th gi (instantiate) mt sub-module thc hin
mt chc nng no ra s dng bt k u m khng cn phi m t li thit k ca module
. Tuy nhin, trong m hnh hnh vi (behavioural model), ta khng th gi module ra ging
nh vy c. Do , gii quyt yu cu c th s dng mt m t thit k c chc nng
no nhiu ln trong m hnh hnh vi m khng cn phi m t li th ta s s dng hm
(function) hoc tc v (task).
Phn ny s tho lun s khc nhau gia task v function, m t cch nh ngha v gi task
v function, cc v d m t cho mi phn.
8.1
Phn bit gia tc v (task) v hm (function)
Cc quy tc sau y phn bit task v function:

Mt function s thc hin trong mt n v thi gian m phng, task c th bao
gm cu lnh iu khin thi gian.
Mt function khng th kch hot mt task, mt task c th kch hot cc task v
function khc nhau.
Mt function phi c t nht mt i s u vo v khng c i s u ra hoc u
vo ra, mt task c th khng c hoc c nhiu i s bt k.
Mt function s tr v mt gi tr duy nht, cn task s khng c gi tr tr v.
Mc ch ca mt function l p ng gi tr u vo bng cch tr v mt gi tr n.
Mt task c th h tr nhiu mc ch v c th tnh ton nhiu gi tr kt qu. Tuy nhin,
ch c i s u ra hoc u vo ra thng qua gi tr kt qu t vic gi mt task. Mt function
c s dng nh l mt ton hng ca mt biu thc. Gi tr ca ton hng l gi tr tr v ca
hm.
Gi s task hoc function switch_bytes() c nh ngha chuyn i byte trong mt
t 16 bit. Task c th tr v mt gi tr t chuyn i trong i s u ra; v vy chng
trnh c th gi task switch_bytes nh sau:
switch_bytes (old_word, new_word);
Task switch_bytes s ly cc byte trong old_word, o ngc cc byte v t cc byte
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o ngc trong new_word.

Function o ngc t s tr v t o ngc nh l mt gi tr tr v ca function.
V vy c th gi function switch_bytes nh sau:
new_word = switch_bytes (old_word);
8.2 Tc v v kch hot tc v

Mt task s c kch hot bng mt cu lnh nh ngha cc gi tr i s thng qua
task v cc bin nhn kt qu tr v. Trnh iu khin s truyn li kch hot tin trnh
sau khi task hon thnh. V vy, nu mt task c iu khin thi gian bn trong n, thi gian
kch hot mt task c th khc vi thi gian iu khin qu trnh tr v. Mt task c th kch
hot mt task khc, v trong qu trnh hot ng vn c th kch hot cc task khc na, n
khng gii hn s lng task c kch hot. Bt k c bao nhiu task c kch hot, trnh
iu khin s khng tr v cho n khi tt c cc task kch hot hon thnh.
8.2.1
nh ngha task
C php nh ngha mt task c m t trong C php 8-1.

C php 8-1
task_declaration ::=
task [ automatic ] task_identifier ;
{ task_item_declaration }
statement_or_null endtask
| task [ automatic ] task_identifier ( [ task_port_list ] ) ;
{ block_item_declaration }
statement_or_null endtask
task_item_declaration ::=
block_item_declaration
| { attribute_instance } tf_ input_declaration ;
| { attribute_instance } tf_output_declaration ;
| { attribute_instance } tf_inout_declaration ;
task_port_list ::=
task_port_item { , task_port_item }
task_port_item ::=
{ attribute_instance } tf_input_declaration
| { attribute_instance } tf_output_declaration
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| { attribute_instance } tf_inout_declaration tf_input_declaration ::=

input [ reg ] [ signed ] [ range ] list_of_port_identifiers
| input task_port_type list_of_port_identifiers tf_output_declaration ::=
output [ reg ] [ signed ] [ range ] list_of_port_identifiers
| output task_port_type list_of_port_identifiers tf_inout_declaration ::=
inout [ reg ] [ signed ] [ range ] list_of_port_identifiers
| inout task_port_type list_of_port_identifiers task_port_type ::=
integer | real | realtime | time block_item_declaration ::=
{ attribute_instance } reg [ signed ] [ range ]
list_of_block_variable_identifiers ;
| { attribute_instance } integer list_of_block_variable_identifiers ;
| { attribute_instance } time list_of_block_variable_identifiers ;
| { attribute_instance } real list_of_block_real_identifiers ;
| { attribute_instance } realtime list_of_block_real_identifiers ;
| { attribute_instance } event_declaration
list_of_block_variable_identifiers ::=
block_variable_type { , block_variable_type }
list_of_block_real_identifiers ::=
block_real_type { , block_real_type }
block_variable_type ::=
variable_identifier { dimension }
block_real_type ::=
real_identifier { dimension }
8.2.2
Khai bo task
C hai c php khai bo task:

C php th nht s bt u vi t kha task, theo sau l t kha ty chn automatic, theo
sau l tn task v tip theo l du chm phy (;), v kt thc vi t kha endtask. T kha
automatic khai bo mt task t ng lm vo, vi tt c cc task c khai bo phn b
ng cho mi mc task hin ti. Khai bo cc yu ca task bao gm:
i s u vo
i s u ra.
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i s u vo ra.
Tt c cc kiu d liu c th khai bo trong mt khi th tc.
C php th hai bt u vi t kha task, theo sau l tn ca task v danh sch cc cng
ca task nm trong du ngoc n. Danh sch cc cng ca task c th khng c hoc c
nhiu cc cng ngn cch nhau bi u phy. V c mt du chm phy sau du ngoc n.
Tip theo l phn thn ca task v kt thc bng t kha endtask.
Trong c hai c php, khai bo cc cng ging vi c php c nh ngha bi
tf_input_declaration, tf_output_declaration, tf_inout_declaration c m t trong C php 8-1
bn trn.
Task m khng cha t kha ty chn automatic l mt task tnh, vi tt c cc mc khai
bo s c phn b c nh. Nhng mc ny s c chia s thng qua tt c cc s dng
ca task thc thi hin ti. Task bao gm t kha automatic s l mt task ng. Tt c cc mc
khai bo trong task ng s c phn b ng trong mi ln task c gi. Cc mc ca
task ng khng th truy cp theo cu trc phn cp. Task ng c th c gi s dng thng
qua tn phn cp.
8.2.3
Kch hot tc v v truyn i s
Cu lnh kch hot task s thng qua cc i s nh mt danh sch cc biu thc nm trong
du ngoc n ngn cch vi nhau bi du phy. C php kch hot task c m t trong C
php 8-2.
C php 8-2
task_enable ::=
hierarchical_task_identifier [ ( expression { , expression } ) ] ;
Nu nh ngha mt task khng c i s, danh sch i s s khng c cung cp trong
cu lnh kch hot task. Ngc li, nu nh ngha task c i s, th s c mt danh sch
cc biu thc theo th t tng ng vi kch thc v thc t ca danh sch cc i s trong
nh ngha task. Mt biu thc rng khng c xem l mt i s trong cu lnh kch hot task.
Nu mt i s trong task c khai bo l input, th biu thc tng ng vi i s l
mt biu thc bt k. Trnh t nh gi mt biu thc trong danh sch cc i s l khng c
nh ngha trc. Nu mt i s trong task c khai bo l output hoc inout, th biu thc
tng ng s gii hn l mt biu thc ph hp vi biu thc bn tri trong th tc gn (phn
9.2). Cc mc sau y p ng yu cu ny:
Cc bin reg, integer, real, realtime, v time.
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B nh tham chiu.
Cc bin kt ni ca reg, integer, v time.
Kt ni ca b nh tham chiu
Cc bin bit-selects v part-selects ca reg, integer, v time.
Vic thc thi cu lnh kch hot task s thng qua gi tr input t danh sch cc biu
thc trong cu lnh kch hot ph hp vi i s ca task. Vic thc thi s tr v gi tr t
task thng qua cc gi tr t cc i s loi output hoc inout ca task tng ng vi bin trong
cu lnh kch hot task. Tt c cc i s trong task s thng qua cc gi tr hn l tham chiu
(l mt con tr n gi tr).
V d 8.1 m t cu trc c bn ca nh ngha mt task vi nm i s:
V d 8.1
task my_task;
input a, b;
inout c;
output d, e;
begin
. . . // cc cu lnh thc thi nhim vca task.
...
c = foo1; // gn trng thi ban u cho thanh ghi kt qu.
d = foo2;
e = foo3;
end
endtask
Hoc s dng hnh thc th 2 ca khai bo task, task c th nh
ngha nh sau:
task my_task (inputa, b, inoutc, outputd, e);
begin
. . . // cc cu lnh thc thi nhim vca task.
...
c = foo1; // gn trng thi ban u cho thanh ghi kt qu.
d = foo2;
e = foo3;
end
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endtask
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Cu lnh sau cho php kch hot task:

my_task (v, w, x, y, z);
Cc i s trong cu lnh kch hot task (v, w, x, y, v z) tng ng vi cc i s (a, b, c, d,
v e) trong nh ngha task. Trong thi gian kch hot task, cc i s input v inout (a, b, v
c) nhn cc gi tr thng qua cc i s v, w, v x. Nh vy vic thc thi li gi kch hot task
s tng ng thc hin lnh gn sau:
a = v; b = w; c = x;
Tip theo trong tin trnh ca task, theo nh ngha ca my_task s t gi tr kt qu tnh
ton vo c, d, v e. Khi task hon thnh, lnh gn sau s tr v gi tr tnh ton ti li gi thc
thi task:
x = c;
y = d;
z = e;
V d 8.2 s m t vic s dng task trong chng trnh n giao thng tun t:
V d 8.2
module traffic_lights;
reg clock, red, amber, green;
parameter on = 1, off = 0, red_tics = 350, amber_tics = 30, green_tics = 200;
// trng thi ban u.
initial red = off;
initial amber = off;
initial green = off;
always begin // iu khin n tun t.
red = on; // bt n
light(red, red_tics); // i
green = on; // bt n xanh
light(green, green_tics); // i.
amber = on; // bt n vng
light(amber, amber_tics); // i
end
// task s i 'tics' trong cnh ln ca clock trc khi tc tn hiu n
task light;
output color;
input [31:0] tics;
begin
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repeat(tics) @ (posedge clock);

color = off; // tt n.
end
endtask
always begin// to dng sng cho ng h.
#100 clock = 0;
#100 clock = 1;
end
endmodule
8.2.4
S dng b nh tc v v s kch hot ng thi
Mt task c th kch hot ng thi nhiu ln. Tt c cc bin ca mt task ng c

sao chp trn mi task c gi ng thi lu tr trng thi c th ca vic gi . Tt c cc
bin ca task tnh s c nh trong mi bin n s tng ng vi mt bin ni b trong
module gi th hin, bt k s lng cc task c kch hot ng thi. Tuy nhin, task tnh
trong cc th hin khc nhau trong mt module s lu tr tch bit vi nhng th hin khc.
Khai bo bin trong task tnh bao gm cc loi i s input, output v inout, s gi li
gi tr ca chng gia cc ln gi. Chng c khi to bi gi tr khi to mc nh.
Khai bo bin trong task ng, bao gm i s loi output s khi to bi gi tr khi
to mc nh bt c khi no vic thc thi i vo vng ca n, i s loi input hoc inout
s khi to thng qua gi tr t biu thc tng ng vi danh sch i s trong cu lnh khi
to task.
8.3 Hm v vic gi hm
Mc ch ca mt function l tr v mt gi tr c s dng trong mt biu thc.
Phn tip theo ca chng ny s m t cc nh ngha v s dng function.
8.3.1
Khai bo hm
C php nh ngha mt function c a ra trong C php 8-3.

C php 8-3
function_declaration ::=
function [ automatic ] [ function_range_or_type ]
function_identifier ;
function_item_declaration { function_item_declaration }
function_statement
endfunction
| function [ automatic ] [ function_range_or_type ]
function_identifier ( function_port_list ) ;
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{ block_item_declaration } function_statement endfunction

function_item_declaration ::=
block_item_declaration
| { attribute_instance } tf_input_declaration ;
function_port_list ::=
{ attribute_instance } tf_input_declaration
{ , { attribute_instance }tf_input_declaration }
tf_input_declaration ::=
input [ reg ] [ signed ] [ range ] list_of_port_identifiers
| input task_port_type list_of_port_identifiers function_range_or_type ::=
[ signed ] [ range ]
| integer
| real
| realtime
| time
block_item_declaration ::= (From A.2.8)
{ attribute_instance } reg [ signed ] [ range ]
list_of_block_variable_identifiers ;
| { attribute_instance } integer list_of_block_variable_identifiers ;
| { attribute_instance } time list_of_block_variable_identifiers ;
| { attribute_instance } real list_of_block_real_identifiers ;
| { attribute_instance } realtime list_of_block_real_identifiers ;
| { attribute_instance } event_declaration
list_of_block_variable_identifiers ::=
block_variable_type { , block_variable_type }
list_of_block_real_identifiers ::=
block_real_type { , block_real_type }
block_variable_type ::=
variable_identifier { dimension }
block_real_type ::=
real_identifier { dimension }
Mt function c nh ngha bt u vi t kha function, theo sau bng t kha ty chn
automatic, theo sau l ty chn _range_or_ function type ca gi tr tr v t function, tip theo
l tn ca function, tip theo sau hoc l du chm phy hoc l danh sch cc cng ca
function nm trong du ngoc n, v sau kt thc vi t kha endfunction.
Vic s dng function_range_or_type trong function l ty chn. Mt function khng
c c t function_range_or_type s mc nh tr v mt gi tr v hng. Nu s dng,
function_range_or_type s c t gi tr tr v ca function l real, integer, time, realtime hoc
mt vector (du ty chn) vi dy phm vi [n:m] bit.
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Mt function s c t nht mt khai bo u vo.

T kha automatic khai bo mt function cha n l mt function ng, vi tt c cc khai
bo phn b t ng cho mi hm c gi. Cc mc ca function ng khng th truy cp
bng cu trc phn cp. Function ng c th gi s dng tn phn cp.
u vo ca function c khai bo theo mt trong hai cch. Cch th nht, theo sau tn
hm l mt du chm phy. Sau du chm phy l mt hoc nhiu u vo c khai bo ln
ln vi khai bo cc khi mc km theo. Sau l khai bo cc mc ca function, l cc cu
lnh hnh vi v kt thc bi t kha endfunction.
Cch th hai l theo sau tn hm l mt du m ngoc n, tip theo l mt hoc nhiu khai
bo u vo, ngn cch nhau bi du phy, tip theo l du ng ngoc n v du chm phy.
Sau du chm phy l c hoc khng c khc mc khi khai bo, tip n l cc cu lnh hnh
vi v cui cng kt thc bng t kha endfunction.
V d 8.3 m t mt nh ngha function getbyte, s dng dy ch nh:
V d 8.3
function [7:0] getbyte;
input [15:0] address;
begin
// chng trnh ly byte t word
...
getbyte = result_expression;
end
endfunction
Hoc s dng cch th hai nh ngha function, function getbyte c th c nh
ngha nh sau:
function [7:0] getbyte (input [15:0] address);
begin
// chng trnh ly byte t word
...
end
endfunction
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8.3.2
Tr v mt gi tr t hm
Trong nh ngha function s khai bo mt bin tng minh, bn trong ca hm, vi

tn cng vi tn hm. Bin ny hoc mc nh l mt thanh ghi 1 bit hoc c loi cng vi loi
c c t trong nh ngha function. nh ngha function khi to gi tr tr v t function
bng cch gn kt qu ca function ti mt bin ni c tn ging vi tn ca function.
L khng hp l nu khai bo mt i tng khc c tn ging vi tn function trong
phm vi m function c khai bo. Bn trong function c mt bin ngm nh l tn ca
function, bin ny s dng cho cc biu thc bn trong function. V vy l khng hp l
khi khai bo mt i tng khc c tn ging vi tn ca function trong phm vi bn trong
function.
Dng lnh sau minh ha cho vic gi hm trong v d phn 8.3.1.
8.3.3
Vic gi hm
Mt li gi function l mt ton hng trong mt biu thc. C php ca li gi

function c m t trong C php 8-4.
C php 8-4
function_call ::=
hierarchical_function_identifier{ attribute_instance } (
expression { , expression } )
Trnh t nh gi cc i s gi hm khng c nh ngha.
V d sau to mt t bng cch kt ni kt qu ca hai li gi hm getbyte (nh ngha
trong phn 8.3.1).
word = control ? {getbyte(msbyte), getbyte(lsbyte)}:0;
8.3.4
Nhng qui tc v hm
Function c nhiu hn ch hn so vi task. Cc quy tc sau y chi phi vic s dng

chng:
Mt nh ngha function khng bao gm cc cu lnh iu khin thi gian, l
cc cu lnh c cha #, @ hoc wait.
Function khng th kch hot task.
nh ngha function phi c t nht mt i s u vo.
nh ngha function s khng c bt k khai bo i s u ra hoc u vo ra.
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Function s khng c bt k cu lnh gn non-blocking ( < = ) hoc th tc gn lin

tc (assign).
Function s khng c s kin triggers.
V d 8.4 nh ngha mt hm gi l factorial n tr v mt gi tr integer. Hm factorial s
c gi i gi li v kt qu c in ra.
V d 8.4
// nh ngha hm
function automatic integer factorial;
input [31:0] operand;
integer i;
if (operand >= 2)
factorial = factorial (operand - 1) * operand;
module tryfact;
else
factorial = 1;
endfunction
// kim tra hm integer result; integer n; initial begin
for (n = 0; n <= 7; n = n+1) begin
result = factorial(n);
$display("%0d factorial=%0d", n, result);
end
end
endmodule
Kt qu ca vic m phng:
0 factorial=1
1 factorial=1
2 factorial=2
3 factorial=6
4 factorial=24
5 factorial=120
6 factorial=720
7 factorial=5040
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8.3.5
S dng nhng hm hng s
Li gi hm hng s c s dng h tr vic xy dng cc tnh ton phc tp cu cc

gi tr thi gian xy dng. Mt li gi hm hng s l mt li gi hm ca mt hm hng s
nm trong module gi n ni m cc i s ca hm l cc biu thc hng s. Hm hng s l
mt tp hp con ca cc hm Verilog thng thng, chng phi p ng c cc rng buc
sau:
Chng khng cha cu trc phn cp.
Bt k li gi hm no bn trong hm hng s s lm mt hm hng s trong nm trong
module hin ti.
L hp l gi bt k mt hm h thng no c cho php trong biu thc hng s,
gi cc hm h thng khc l khng hp l.
Tt c cc task h thng trong hm h thng s c b qua.
Tt c cc tham s c s dng bn trong hm phi c nh ngha trc khi s
dng li gi hm hng s.
Tt c cc nh danh khng phi l tham s hoc hm s c khai bo ti hm hin ti.
Nu chng s dng bt k gi tr tham s no nh hng trc tip hoc gin tip n
cu lnh defparam, kt qu khng c nh ngha. iu ny c th to ra mt li hoc
cc hm hng s tr v mt gi tr khng xc nh.
Chng khng c khai bo bn trong mt khi to.
Chng khng t s dng hm hng s trong bt k hon cnh no yu cu mt biu
thc hng s.
Mt li gi hm hng s s c nh gi trong thi gian xy dng. Vic thc thi ca
chng khng nh hng n gi tr khi to ca cc bin s dng hoc trong thi gian
m phng hoc gia nhiu li gi mt hm trong thi gian xy dng. Trong mi trng
hp, bin s c khi to nhng qu trnh m phng thng thng.
V d 8.5 s nh ngha mt hm gi l clogb2 tr v mt s nguyn vi gi tr cao nht ca
log 2.
V d 8.5
module ram_model (address, write, chip_select, data);
parameter data_width = 8;
parameter ram_depth = 256;
localparam addr_width = clogb2(ram_depth);
input [addr_width - 1:0] address;
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input write, chip_select;

inout [data_width - 1:0] data;
//nh ngha hm clogb2 function integer clogb2; input [31:0] value; begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end endfunction
reg [data_width - 1:0] data_store[0:ram_depth - 1];
//phn cn li ca ram_model
Th hin ca ram_model ny vi tham s c gn nh bn di:
ram_model #(32,421) ram_a0(a_addr,a_wr,a_cs,a_data);
8.4 Bi tp
1. Ti sao phi dng task v function trong khi Verilog HDL h tr module?
2. Phn bit task v function?
3. Cch khai bo v s dng task?
4. Cch khai bo v s dng function?
5. S dng function cn tun theo nhng quy tt no?
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GiaotrinhVerilogHDL_v19
9 Chng 9.
Kim tra thit k
Mt h thng c thit k dng Verilog phi c m phng v kim tra xem thit k
ng chc nng cha trc khi to ra phn cng. Trong qu trnh chy m phng ny, nhng li
thit k v s khng tng thch gia nhng linh kin dng trong thit k c th c pht hin.
Chy m phng mt thit k i hi vic to ra mt d liu ng vo kim tra v qu trnh quan
st kt qu sau khi chy m phng, d liu ng vo dng kim tra ny c th c to bng
hai cch, mt l to dng sng (waveform) bng tay s dng trnh waveform editor, tuy nhin
cch ny ch kh thi cho nhng thit k nh vi s lng tn hiu ng vo t, cn i vi mt
thit k h thng ln, phc tp vi nhiu tn hiu ng cn hng ngn chu k kim tra th ta
phi s dng testbench m t d liu ng vo kim tra. Testbench s dng cu trc mc cao
ca Verilog to ra d liu kim tra, quan st p ng ng ra, v c vic bt tay gia nhng
tn hiu trong thit k.
Bn trong testbench, h thng thit k cn chy m phng s c gi ra (instantiate) trong
testbench. D liu testbench cng vi h thng thit k s to ra mt m hnh m phng m s
c s dng bi mt cng c m phng Verilog.
Chng ny s tho lun v vic s dng ngn ng Verilog kim tra vic thit kt
module. Chng ta s thy rng thi gian v th tc hin th s tr nn quan trng hn khi tip
xc vi module testbench. Chng ny cho thy cch cu trc ca ngn ng Verilog c s
dng p dng d liu cho module trong qu trnh kim tra (module under test (MUT)), v
cch module p ng s c hin th v nh du. Trong phn u ca chng ny s tho
lun v d liu ng dng v theo di p ng. Trong phn cui s tho lun v k thut chn
kim tra thit k nhm to gii php tt nht cho vic thit k module.
9.1 Testbench
Mi trng m phng Verilog cung cp mt cng c ha hoc vn bn hin th
hin th cc kt qu m phng. Mt s mi trng m phng i xa hn, n cung cp mt cng
c ha cho vic chnh sa u vo d liu kim tra ti thit k module trong qu trnh kim
tra. Nh cc cng c bin tp dng sng, chng thng ph hp cho nhng thit k nh. i vi
cc thit k ln vi nhiu bus v d liu iu khin th bin tp dng sng tr nn phc
tp. Mt vn trong bin tp dng sng l mi mi trng m phng s dng mt tp cc
th tc khc nhau chnh sa dng sng, v vy khi chuyn sang mt mi trng m phng
mi i hi phi hc li mt tp cc th tc chnh sa dng sng mi.
Vn ny c th c gii quyt bng cch s dng testbenches ca Verilog. Mt
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testbenches Verilog l mt module c cha th hin ca MUT, p dng cc d liu kim tra vo
n v quan st u ra. Bi v testbenches l mt chng trnh Verilog nn n c th chy trn
nhiu mi trng m phng khc nhau. Mt module v testbenches tng ng ca n t mt m
hnh m phng trong MUT c kim tra vi cc d liu u vo ging nhau th s ging
nhau bt chp mi trng m phng.
9.1.1
Kim tra mch t hp
Pht trin mt testbenches cho mt mch t hp l mt bc tin ng k, tuy nhin

vic chn d liu kim tra v cch kim tra ph thuc vo tng MUT v cc chc nng ca
n.
Chng ta s xem xt mt v d minh ha kim tra mch t hp qua module alu_4bit. Phn
u ca module v cc khai bo cc cng c th hin nh sau:
V d 9.1
module alu_4bit (a, b, f, oe, y, p, ov, a_gt_b, a_eq_b, a_lt_b);
input [3:0] a, b;
input [1:0] f;
input oe;
output [3:0] y;
output p, ov, a_gt_b, a_eq_b, a_lt_b;
// . . .
endmodule
Module c cc u vo a, b v u vo chc nng f, u ra y v cc u ra km theo p, ov,
a_gt_b, a_eq_b, a_lt_b.
Mt testbenches cho alu_4bit c nh ngha nh sau:
V d 9.2
module test_alu_4bit;
reg [3:0] a=4b1011, b=4b0110;
reg [1:0] f=2b00;
reg oe=1;
wire [3:0] y;
wire p, ov, a_gt_b, a_eq_b, a_lt_b;
alu_4bit cut( a, b, f, oe, y, p, ov, a_gt_b, a_eq_b, a_lt_b );
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initial begin
#20 b=4b1011;
#20 b=4b1110;
#20 b=4b1110;
#80 oe=1b0;
#20 $finish;
end
always #23 f = f + 1;
endmodule
Cc bin tng ng vi cc u vo v u ra ca MUT c khai bo trong testbench. Cc
bin kt ni ti u vo c khai bo l reg, cc bin kt ni vi u ra c khai bo l wire.
Th hin ca alu_4bit s lin kt vi cc reg v wire cc b ti cc cng ca MUT.
Bin lin kt vi u vo ca module alu_4bit phi c khai bo gi tr ban u. p
dng ca d liu ti u vo d liu b v u ra cho php oe c khai bo trong cu lnh
initial. Trong 60ns u, sau mi 20ns mt gi tr mi c gn cho b. Khi initial sau i
80ns, v hiu ha alu bng cch t oe = 0. V sau i 20ns hon thnh m phng, i
20ns l s thay i u vo cui cng nh hng ti u ra.
p dng d liu ti u vo chc nng f ca alu_4bit trong khi lnh always. Bt u vi
gi tr ban u bng 0, f tng ln 1 sau mi 23ns. Cu lnh $finish trong khi initial kt thc ti
v tr 160ns, ti thi im ny tt c cc khi th tc ang hot ng dng li v qu trnh m
phng chm dt. Hnh 9.1 hin th kt qu qu trnh m phng module alu_4bit
Hnh 9.1 Kt qu qu trnh m phng module alu_4bit
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9.1.2
Kim tra mch tun t
kim tra mt mch tun t cn gi ng b gia mch ng h v cc d liu u vo

khc. Chng ta s dng mch sau v d trong phn ny, mch c mt u vo clock, mt u
vo reset, u vo d liu v u ra:
V d 9.3
module #(parameter [3:0] poly=0) misr (input clk, rst,
input [3:0] d_in, outputreg [3:0] d_out );
always @( posedge clk )
if( rst )
d_out =4b0000;
else
d_out = d_in ^ ({4{d_out[0]}} & poly) ^{1b0,d_out[3:1]};
endmodule
Trong mch ny c tham s poly ch nh k hiu v d liu nn . Vi mi chu k ng
h mt k hiu mi c tnh ton vi d liu mi v nm trong thanh ghi d liu ca misr.
on chng trnh sau y m t mt testbench cho module misr. Cc bin tng ng
vi cc cng ca MUT c khai bo trong testbench. Khi misr c gi th hin, cc bin ny
s kt ni vi cc cng tht s ca n. Th hin ca misr cng bao gm chi tit v cc tham s
poly ca n.
V d 9.4
module test_misr;
reg clk=0, rst=0; reg [3:0] d_in; wire [3:0] d_out;
misr #(4b1100) MUT ( clk, rst, d_in, d_out );
initial begin
#13 rst=1b1;
#19 d_in=4b1000;
#31 rst=0b0;
#330 $finish;
end
always #37 d_in = d_in + 3;
always #11 clk = ~clk;
endmodule
Trong khi initial ca testbench to ra mt pulse ln vo lc rst m bt u ti 13ns v kt
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thc ti 63ns. Thi gian nh vy l s la chn bao gm t nht mt cnh ln ca ng h,
v vy s ng b ca u vo rst c th khi to trong thanh ghi misr. u vo d liu d_in
bt u l x, v trong khi l 4b1000 khi rst l 1.
Ngoi cc khi khi to, module test_misr cn bao gm 2 khi always to d liu
cho d_in v clk. Clock cho ra mt tn hiu tun hon vi chu k 11x2=22ns. u vo misrd_in
gn mt gi tr mi sau mi chu k 37ns. gim trng hp cc u vo thay i cng
mt lc, chng ta s dng s nguyn t cho thi gian ca u vo mch tun t.
Hnh 9.2 m t mt kt qu ca testbench:
Hnh 9.2 Mt kt qu ca testbench
9.2 K thut to testbench

Cc k thut vit chng trnh Verilog khc nhau to d liu kim tra v xem xt p ng
ca mch c tho lun trong phn ny. Chng ta s dng module my trng thi Moore
pht hin chui 101 lm v d cho phn ny. Module ny c nh ngha nh sau:
V d 9.5
module moore_detector (input x, rst, clk, output z );
parameter [1:0] a=0, b=1, c=2, d=3;
reg [1:0] current;
if ( rst ) current = a;
else case ( current )
a : current = x ? b : a ; b : current = x ? b : c ; c : current = x ? d : a ; d : current = x ? b :
c ; default : current = a ;
endcase
assign z = (current==d) ? 1b1 : 1b0;
endmodule
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9.2.1
D liu kim tra
Mt testbench cho module moore_detector c m t nh sau:

V d 9.6
module test_moore_detector; reg x, reset, clock; wire z;
moore_detector MUT ( x, reset, clock, z );
initial begin
clock=1b0; x=1b0; reset=1b1;
end
initial #24 reset=1b0;
always #5 clock=~clock;
always #7 x=~x;
endmodule
Module testbench l mt module khng c cc cng kt ni ra ngoi. Bn trong module, c
4 khi th tc cung cp d liu cho vic kim tra my trng thi. Cc bin kt ni vi MUT
v s dng vo v bn tri ca cc khi th tc phi c khai bo l reg.
Thay v khi to cc bin reg khi chng khai bo, chng ra c th s dng khi initial
khi to cc bin reg. iu quan trng khi khai khi to bin, ging nh clock l gi tr c
ca chng c s dng xc nh gi tr mi ca chng. Nu khng nh vy, clock s bt
u vi gi tr X v cho n khi hon thnh, gi tr ca n cng khng thay i. Khi always
to chu k tn hin vi chu k 10ns trn mt clock.
Theo sau khi th tc always to clock, mt khi always khc s to chu k tn hiu cho x
vi chu k 14ns. Dng sng to ra cho X c th c hoc khng th kim tra my trng thi ca
chng ra ng tun t 101. Tuy nhin, chu k ca clock v X c th thay i iu ny. Vi
thi gian s dng y, u ra ca moore_detector ln 1 sau 55ns v sau mi 70ns tip theo.
9.2.2
iu khin m phng
Mt testbench khc cho mch moore_detector bn trn c m t nh sau:

V d 9.7
module test_moore_detector;
reg x=0, reset=1, clock=0;
wire z;
initial #24 reset=1b0; always #5 clock=~clock; always #7 x=~x;
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initial #189 $stop;
endmodule
Mc d, cu trc Verilog c s dng khc nhau, d liu v clock p dng cho MUT
trong testbench cng ging vi testbench bn trn. Tuy nhin, nu trnh m phng cho testbench
trc khng c ngt, hoc im dng, n s chy mi mi. Trong testbench ny gii quyt vn
ny bng cch thm vo mt khi khc khi initial s dng qu trnh m phng sau 189ns.
Cc task iu khin trnh m phng l $stop v $finish.
Thi gian u tin theo chu trnh ca mt khi th tc c tip cn nh mt task, trnh
m phng s dng li hoc hon thnh. Mt task $stop th c th ni li, nhng mt task
$finish th khng th ni li.
Mt testbench khc c m t nh sau:
V d 9.8
wire z;
initial begin
#24 reset=1b0;
#165 $finish;
end
always #7 x=~x;
endmodule
Trong testbench ny tch hp trong khi initial c tn hiu reset tch cc thp v tn hin iu
khin thi gian trong mt khi initial. Thi gian iu chnh chm dt qu trnh m phng ti
thi gian 189ns ging nh testbench bn trn.
9.2.3
Thit lp gii hn d liu
Thay v ci t gii hn thi gian m phng, mt testbench c th t mt gii hn trn s

d liu t vo u vo ca MUT. iu s cng c th ngn chn vic m phng khng dng
li.
Chng trnh sau m t mt testbench cho module moore_detector MUT.
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V d 9.9
wire z;
initial #24 reset=1b0;
initial repeat(13) #5 clock=~clock;
initial repeat(10) #7 x=$random;
endmodule
Testbench ny s dng $radom to d liu ngu nhin cho u vo x ca mch, cu
lnh repeat trong khi initial to ra tn hin clock 13 ln sau mi 5ns, v x nhn d liu ngu
nhin 13 ln sau mi 7ns. Thay v dng mt b tnh quyt nh d liu m bo tnh quyt
nh cc trng thi, th d liu ngu nhin c s dng y. Chin lt ny lm cho n d
dng hn to d liu, nhng phn tch u ra ca mch s kh khn hn, do u vo khng
on trc. Trong cc mch ln, d liu ngu nhin c s dng nhiu cho u vo d liu
hn tn hiu iu khin. Testbench trong phn ny s dng sau 70ns.
9.2.4
Cung cp d liu ng b
Trong cc v d trc testbench cho MUT s dng thi gian c lp cho clock v d liu.
Trong trng hp nhiu b d liu c p dng, vic ng b ha d liu vi ng h h
thng tr nn kh khn. Hn na, vic thay i tn s clock s yu cu thay i thi gian ca
tt c cc d liu u vo ca module ang kim tra.
Testbench sau c vit cho module moore_detector, s dng mt cu lnh iu khin
s ng b gia d liu p dng vo X vi clock to ra trong testbench. Tn hiu clock ny to
ra trong cu lnh initial s dng cu trc repeat. Mt cu lnh initial khc c s dng to
d liu ngu nhin cho X. Nh ta thy trong cu lnh initial ny, vng lp mi mi s lp i lp
li cu lnh ny s dng y. Vng lp ny i cho ti cnh ln ca clock, v sau khi cnh
ln ca clock 3ns, mt d liu ngu nhin c to ra cho X. Trng thi d liu sau cnh ln ca
clock s s dng bi moore_detector trn u cnh tip theo ca clock. K thut ny ca d
liu m bo rng s thay i d liu v clock khng trng nhau.
V d 9.10
[Type text]
Page 284
wire z;
initial #24 reset=0;
initial repeat(13) #5 clock=~clock;
initial forever @(posedge clock) #3 x=$random;
endmodule
C tr hon 3ns c s dng y lm n c th s dng testbench ging nhau trong m
phng sau khi tng hp thit k tt nh m t hnh vi trong cc phn trn.Trong qu trnh m
phng sau khi tng hp, m hnh cc thnh phn s thc s tr hon nh cc gi tr c s
dng, tr hon trong testbench cho php truyn tn hiu kim tra hon thnh trc khi p dng
tn hiu khim tra mi.
9.2.5
Tng tc testbench
Trong qu trnh to testbench tip theo chng ta s dng mt my trng thi khc. l
my trng thi moore pht hin chui 1101 vi trng thi bt u (start) v reset (rst) iu khin
u vo. Nt start l 0 trong khi tm kim chui 1101, my trng thi s reset v trng thi khi
u. Nh ta thy trong mch sau c 5 trng thi, v u ra ca n ln 1 khi n bt u trng thi
e.
V d 9.11
module moore_detector (input x, start, rst, clk, output z );
parameter a=0, b=1, c=2, d=3, e=4;
reg [2:0] current;
if ( rst ) current <= a;
else if ( ~start ) current <= a;
else case ( current )
a : current <= x ? b : a ;
b: current <= x ? c : a ;
c : current <= x ? c : d ;
d : current <= x ? e : a ;
e : current <= x ? c : a ;
[Type text]
Page 285
default: current <= a;
endcase
assign z = (current==e);
endmodule
Testbench cho my trng thi l mt testbench tng tc mt.
reg x=0, start, reset=1, clock=0;
wire z;
moore_detector MUT ( x, start, reset, clock, z );
initial begin
#24 reset=1b0; start=1b1;
wait(z==1b1);
#11 start=1b0;
#13 start=1b1;
repeat(3) begin
#11 start=1b0;
#13 start=1b1;
wait(z==1b1);
end
#50 $stop;
end
always #7 x=$random;
endmodule
Trong khi initial, testbench giao tip vi MUT. u vo X v clock c to bi 2 khi
always. Mt tn hiu c chu k lin tc c to ra cho clock v mt d liu c chu k ngu
nhin c gn cho x.
u tin, gi tr 0 v 1 c t cho reset v start a my trng thi vo trng thi bt
u. Theo sau , mt cu lnh wait i z ln 1 nh l kt qu p ng ca MUT ti gi tr
x v clock. Sau s kin ny, bin start c gn bng 0 v sau l 1 sau 13ns khi ng
li my. Theo sau vng kch hot u tin ny, mt cu lnh repeat lp li tin trnh bt u my
trng thi v x ln 1 ba ln na. Sau 50ns testbench dng qu trnh m phng bng mt task
[Type text]
Page 286
$stop.
9.2.6
To nhng khong thi gian ngu nhin
Chng ta thy cch hm #random c th s dng to mt d liu ngu nhin. Phn ny

chng ta s tho lun cch dng ngu nhin thi gian i gn gi tr cho x.
Testbench sau dng kim tra module pht hin chui 1101 s dng $random
iu khin tr hon. Nh ta thy, cu lnh initial tn running p dng d gi tr ph hp ln
bin reset v start h thng bt u tm kim chui 1101. Trong khi th tc ny s dng
lnh gn khng chn (nonblocking) to ra cc gi tr tr hon trong cu lnh gn c coi
nh l mt gi tr thi gian tuyt i.
V d 9.12
reg x, start, reset, clock;
wire z;
reg [3:0] t;
initial begin:running
clock <= 1b0;
x <= 1b0;
reset <= 1b1;
reset <= #7 1b0;
start <= 1b0; start <= #17 1b1;
repeat (13) begin
@( posedge clock );
@( negedge clock );
end
start=1b0;
#5;
$finish
moore_detector MUT ( x, start, reset, clock, z );
end
always begin
i = $random;
#(t) x=$random;
9.2.6.1.1
end
endmodule
Sau khi t my trng thi vo trng thi running, testbench i 13ln hon thnh
xung clock trc khi n t li u vo start v hon thnh m phng. Nh ta thy, khi always
ng thi vi khi running lin tc to xung clock 5ns. Cng ng thi vi cc khi ny
[Type text]
Page 287
l mt khi always khc to d liu ngu nhin cho t, v s dng t tr hon lnh gn ngu
nhin cho x. C khi ny to d liu cho u vo x cho n khi cu lnh $finish trong khi
running c thc hin.
9.3 Kim tra thit k

Trong phn trc tho lun cc k thut kim tra kim tra mt thit k Verilog. Trong
phn ny s bn ti mt vi phng thc to d liu kim tra v p dng kim tra, v h
tr mt vi cch xem xt v kim tra kt qu kim tra. To cc kch thch v phn tch p
ng ca mt thit k i hi mt phn n lc ng k ca ngi thit kt phn cng. Tm
hiu cc k thut kim tra ng l tt, nhng thit k t ng lm cc th tc ny s rt hu
dng cho cc k s.
Hnh thc kim tra thit k l mt cch t ng thit k kim tra bng cch loi b
testbenches v cc vn lin quan n vic to d liu v quan st cc p ng ca mch.
Trong hnh thc kim tra thit k, ngi thit k s thit k mt thuc tnh kim tra thit k
ca anh ta. Cng c kim tra thit k hnh thc khng thc hin m phng, nhng a ra cu tr
li c/khng c cho mi thuc tnh ca thit k ang c kim tra. Mc d phng php
kim tra thit k gip tm ra nhiu li thit k nhng hu nh nhiu thit k vn cn pht trin
testbench v m phng xc nhn chng trnh Verilog ca h thc hin ng chc nng
mong i. Ni cch khc, tt c cc cu tr li l c cho tt c cc thuc tnh kim tra bi
cng c kim tra thit k hnh thc l cha .
Thay v b qua vic to d liu v quan st p ng, mt bc theo hng t ng ha thit
k xc nhn l gim hoc b qua cc n lc cn thit cho phn tch kt qu p ng. K
thut chn kim tra thit k c s dng theo hng ny, n s thm gim st thit k
ci thin kh nng quan st p ng. Trong khi thit k ang c m phng vi d liu
testbench, trnh quan st c chn vo i din cho mt s thuc tnh ca thit k lin tc
kim tra c ng vi thit k hnh vi bng cc xc minh nhng thuc tnh . Nu d liu m
phng dn n iu kin ch ra mt trnh gim st chn vo l khng ph hp vi hnh vi
thit k, trnh gim st s cnh bo ti ngi thit k vn .
Nh cp, chng ta vn phi pht trin mt testbench v thit k cn thn cc u
vo kim tra cho thit k cn kim tra l cn thit cho k thut chn kim tra thit k.
Nhng trong nhiu trng hp, k thut chn t ng kim tra chc chn s kin xy ra
trong thit k l ng nh mong i. iu ny c ngha lm gim s cn thit cho vic x
l mt danh sch di cc u ra v dng sng.
[Type text]
Page 288
9.4 K thut chn (assertion) dng kim tra thit k
Khng ging nh m phng vi mt testbench hoc con ngi gii thch kt qu,
trong k thut chn kim tra kt qu chng trnh gim st chu trch nhim pht hnh
mt thng bo nu c mt iu g xy ra khng nh mong i. Trong Verilog, cc trnh gim
st l cc module, v chng c khi to trong mt thit k kim tra cc thuc tnh ca thit
k. Th hin ca mt module chn (assertion module) khng c xem nh l mt module phn
cng. Thay vo , loi th hin ny ging nh mt th tc lun lun hot ng v lin tc
kim tra cc s kin trong module thit k.
Thit lp hin ti ca mt trnh gim st chn (assertion monitor) c sn trong mt th vin
c bit n nh l mt th vin kim tra m (OVL). Ngi thit k c th pht trin cc ci
t ring ca h vo trong module chn. Nhng g tn ti trong trnh gim st kim tra gi tr
ca tn hiu, quan h ca mt vi tn hiu vi cc ci khc, s tun t ca cc s kin, v cc
m hnh d kin trn vector hoc nhm tn hiu. s dng k thut chn, ngi thit k
bin dch OVL v th vin c sn trong thit k cn kim tra.
Khi mt thit k c pht trin, k thut chn s thay th cc im cn thit trong thit k
kim tra cc chc nng cn thit. Khi thit k c m phng nh mt thnh phn n
chun, hoc trong mt cu trc phn cp ca mt thit k ln, trnh gim st kim tra tn
hiu cho cc gi tr ngoi l. Nu tn hiu khng c gi tr ngoi l bng s gim st, trnh gim
st chn vo s hin th mt thng ip v thi gian s khc bit (vi phm ca cc thuc tnh)
xy ra. Thng thng, thng ip xut hin trong vng bo co ca m phng, bn dch hoc
khung hin th iu khin (console).
9.4.1
Li ch ca k thut chn kim tra.
Cch tm ni chn mt trnh gim st sao cho c li nht s c tho lun trong phn
ny.
K lut thit k: Khi mt ngi thit k t mt ni chn trong thit k, ngi thit k
cn phi t yu cu bn thn mnh xem xt cn thn thit k v trch xut cc thuc tnh cn
thit.
Kh nng quan st: Chn thm cc trnh gim st vo cc im cn gim st ca thit k lm
sao cho d quan st nht.
Qu trnh kim tra chnh thc sn sng: Cc chng trnh chn tng ng vi cc thuc tnh
c s dng trong cng c kim tra chnh thc. C chn vo mt trnh gim vo mt thit
k, sn sng cho n kim tra bng cng c kim tra thit k chnh thc.
[Type text]
Page 289
Thc thi ch thch: Trnh gim st chn vo c th xem nh l ch thch ch thch mt
vi tnh nng hoc hnh vi ca thit k. Cc ch thch ny to ra mt thng ip khi
hnh vi ca chng c gii thch l vi phm.
T thit k kn: Mt thit k vi k thut chn gim st m t thit k v cc th tc
kim tra n trong mt module Verilog.
9.4.2
Th vin thit k m (OVL)
OVL c sn t t chc Accellera (http://www.accellera.org/activities/ovl/) v cc t chc

EDA khc. Hng dn tham kho ngn ng, hng dn s dng, v th vin chng trnh ca
Verilog v VHDL cng c sn trong cc t chc EDA ny. Danh sch cc chng trnh chn c
sn c lit k trong danh sch sau:
assert_change
assert_decrement
assert_even_parity
assert_frame
assert_implication
assert_never
assert_next
assert_no_transition
assert_odd_parity
assert_one_hot
assert_quiescent_state
Mt assertion c t trong chng trnh ging nh mt th hin ca module. Cu trc
sau m t mt khai bo th hin module assertion.
C php 9-1
assert_name
#(static_parameters)
instance_name
(dynamic_arguments);
N bt u vi tn ca module assertion, theo sau l cc tham s tnh (satatic_parameters)
nh l kch thc ca vector hoc cc ty chn. Sau l tn duy nht bt k ca th hin, v
phn cui cng l mt trnh gim st chn vo bao gm cc tham chiu, gim st tn hiu v cc
[Type text]
Page 290
i s ng khc. Cc i s ng ny l cc cng ca module v cng c xem nh l cc
cng ca assertion module.
9.4.3
S dng k thut chn gim st.
assert_always
C php s dng k thut chn gim st c m t nh sau:
C php 9-2
assert_always
#( severity_level, property_type, msg, coverage_level )
instance_name ( clk, reset_n, test_expr )
Lnh ny s lin tc chn kim tra test_expr chc chn n lun lun ng trn mi cnh
ca clock. Nu biu thc kim tra sai, mt thng ip tng ng s c hin th.
V d 9.13
module BCD_Counter (input rst, clk, outputreg [3:0] cnt);
if (rst || cnt >= 10) cnt = 0;
else cnt = cnt + 1;
end
assert_always #(1, 0, Err: Non BCD Count, 0)
AA1 (clk, 1b1, (cnt >= 0) && (cnt <= 9));
endmodule
Testbench kim tra module:
module BCD_Counter_Tester;
reg r, c;
wire [3:0] count;
BCD_Counter UUT (r, c, count);
initial begin
r = 0; c = 0;
end
initial repeat (200) #17 c= ~c;
initial repeat (03) #807 r= ~r;
endmodule
assert_change
[Type text]
Page 291
Lnh chn ny gim st kim tra trong mt s chu k ng h sau s kin bt u, biu thc
kim tra s thay i, c php
c s dng nh sau:
C php 9-3
assert_change
#( severity_level, width, num_cks,
action_on_new_start, property_type,
msg, coverage_level )
instance_name ( clk, reset_n, start_event,
test_expr )
assert_one_hot
K thut chn gim st ny dng kim tra ch mt bit trong n bit ca biu thc kim
tra l 1 trong khi trnh gim st vn ang hot ng, c php nh sau:
C php 9-4
assert_one_hot
#( severity_level, width, property_type,
instance_name ( clk, reset_n, test_expr )
assert_cycle_sequence
K thut chn ny dng kim tra my trng thi, c php nh sau:
C php 9-5
assert_cycle_sequence
#( severity_level, num_cks, necessary_condition,
property_type,
instance_name ( clk, reset_n, event_sequence )
[Type text]
Page 292
Chng 9. Kim tra thit k

assert_next: k thut chn ny s dng c php bn di v kim tra cc s kin xy ra
ti cc chu k ng h gia s kin bt u v kt thc:
C php 9-6
assert_next
#( severity_level, num_cks, check_overlapping, check_missing_start, property_type,
instance_name ( clk, reset_n, start_event, test_expr )
9.5 Bi tp
1. Ti sao phi kim tra thit k? C my cch kim tra thit k, nu c th?
2. Phn bit hai hnh thc kim tra thit k s dng testbench v verification?
3. Cc k thut to mt testbench hiu qu ?
4. Vit testbench cho mch t hp v mch tun t c g khc nhau?
5. Th no l chn kim tra thit k (assertion verification)? Li ch ca k thut ny?
6. Th vin mi OVL bao gm nhng cu lnh chn c bn no v cc s dng chng?

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I HC QUC GIA THNH PH H CH MINH

TRNG I HC CNG NGH THNG TIN

Gio trnh ngn ng Verilog HDL

Chng 1: Dn nhp thit k h thng s vi Verilog. Chng ny s gii thiu lch

Chng 2: Trnh by cc t kha c s dng trong mi trng m t thit k bi

Chng 3: Trnh by cc loi d liu c s dng trong thit k mch bi Verilog,

Chng 4: Trnh by cc ton t cng nh cc dng biu thc c h tr bi Verilog.

Gio trnh ngn ng Verilog HDL

Chng 8: Trnh by phng php thit k v s dng tc v v hm.

Gio trnh ngn ng Verilog HDL

Bin dch v tng hp thit k.................................................................................16

Khai bo bin chui.......................................................................................................30

Gio trnh ngn ng Verilog HDL

Wand v triand Nets......................................................................................................75

Gio trnh ngn ng Verilog HDL

Ton t thao tc trn bit (&, |, ^, ~, ~^, ^~)...........................................................104

Ton t ghp ni {}.................................................................................................109

Gio trnh ngn ng Verilog HDL

S kt hp gia nhng tn hiu c mnh r rng.....................................................147

S suy gim mnh bng nhng linh kin khng tr.........................................158

mnh ca net tri0, tri1........................................................................................159

tr hon cng (gate) v net...............................................................................159

Qu trnh phn r in tch.......................................................................................162

Mch t hp vi php gn qui trnh kn.......................................................................228

Php gn qui trnh h (non-blocking assignment).................................................229

Gio trnh ngn ng Verilog HDL

Gio trnh ngn ng Verilog HDL

Gio trnh ngn ng Verilog HDL

1 Chng 1. Dn nhp thit k h thng s vi Verilog

1.1 Qui trnh thit k s

Gio trnh ngn ng Verilog HDL

Hnh 1.1 Lung thit k ASIC

Gio trnh ngn ng Verilog HDL

Bc u tin trong thit k h thng s l bc dn nhp thit k. Trong bc ny, thit k

Testbench trong Verilog

Gio trnh ngn ng Verilog HDL

Mt nhim v quan trng trong bt k thit k s no cng cn l nh gi thit k. nh

Gio trnh ngn ng Verilog HDL

Gio trnh ngn ng Verilog HDL

Hnh 1.3. M t mt on code ca mt mch flip-flop

1.1.3.2 K thut chn kim tra (assertion)

Gio trnh ngn ng Verilog HDL

Bin dch v tng hp thit k

Tng hp l qu trnh to ra phn cng t ng t mt m t thit k phn cng tng ng

Gio trnh ngn ng Verilog HDL

Hnh 1.4. M t qu trnh bin dch v m t hnh nh kt qu ng ra

1.1.4.1 Phn tch

1.1.4.2 To phn cng

Gio trnh ngn ng Verilog HDL

Gio trnh ngn ng Verilog HDL

Hnh 1.5. Minh ha v qu trnh tng hp

M phng sau khi tng hp thit k

Gio trnh ngn ng Verilog HDL

Phn tch thi gian

To linh kin phn cng

1.2 Ngn ng m t phn cng Verilog (Verilog HDL)

Qu trnh pht trin Verilog

Verilog c ra i vo u nm 1984 bi Gateway Design Automation. Khi u, ngn

Gio trnh ngn ng Verilog HDL

Nhng c tnh ca Verilog

Verilog l mt ngn ng m t phn cng dng c t phn cng t mc transistor n

1.2.2.1 Mc chuyn mch

Gio trnh ngn ng Verilog HDL