Apple Macbook Pro A1297 (K92, 820-2914)

8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
Date
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
Sync
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
ECN
DESCRIPTION OF REVISION
Table of Contents
K17_MLB
System Block Diagram
K60_MLB
2
3
Revision History
K17_MLB
Revision History
K17_MLB
4
5
BOM Configuration
04/26/2010
04/26/2010
04/26/2010
04/26/2010
04/26/2010
04/26/2010
04/26/2010
04/26/2010
K17_MLB
Functional / ICT Test
K17_MLB
Power Aliases
K17_MLB
Signal Aliases
K17_MLB
CPU DMI/PEG/FDI/RSVD
K60_MLB
10
11
CPU CLOCK/MISC/JTAG
07/16/2010
04/26/2010
07/16/2010
04/26/2010
07/21/2010
07/21/2010
10/19/2010
K91_MLB
12
CPU DDR3 INTERFACES
K60_MLB
13
CPU POWER
K91_MLB
14
CPU POWER AND GND
K60_MLB
16
CPU DECOUPLING-I
K91_MLB
17
CPU DECOUPLING-II
K91_MLB
PCH SATA/PCIE/CLK/LPC/SPI
K91_MLB
PCH DMI/FDI/GRAPHICS
K91_MLB
18
19
20
PCH PCI/FLASHCACHE/USB
10/17/2010
10/20/2010
10/20/2010
07/09/2010
05/20/2010
08/06/2010
10/17/2010
K91_MLB
21
PCH MISC
K91_MLB
22
PCH POWER
K91_MLB
23
PCH GROUNDS
K92_YUN
24
PCH DECOUPLING
K91_YUN
CPU & PCH XDP
K91_MLB
25
26
USB HUBS
06/29/2010
06/29/2010
06/14/2010
05/14/2010
06/14/2010
04/26/2010
08/26/2010
K92_BEN
28
Chipset Support
K91_MLB
29
DDR3 SO-DIMM Connector A
K92_YUN
30
DDR3 Byte/Bit Swaps
K92_YUN
31
DDR3 SO-DIMM Connector B
K92_YUN
32
CPU Memory S3 Support
K17_MLB
FSB/DDR3/FRAMEBUF Vref Margining
K91_YUN
33
34
X19/ALS/CAMERA CONNECTOR
10/21/2010
07/27/2010
11/09/2010
11/09/2010
11/09/2010
10/19/2010
08/24/2010
10/20/2010
10/20/2010
07/22/2010
11/08/2010
08/24/2010
K91_MLB
35
ExpressCard Connector
K92_ERIC
36
T29 Host (1 of 2)
T29_REF
37
T29 Host (2 of 2)
T29_REF
38
T29 Power Support
T29_REF
39
ETHERNET PHY (CAESAR IV)
K92_ERIC
Ethernet Connector
K92_ERIC
40
41
FireWire LLC/PHY (FW643)
K91_MLB
42
FireWire Port & PHY Power
K91_MLB
43
FireWire Connector
K91_MLB
45
SATA Connectors
K92_ERIC
External USB Connectors
K92_ERIC
46
47
PROJECT SPECIFIC CONNS
07/22/2010
04/26/2010
07/12/2010
K92_ERIC
48
Front Flex Support
K17_MLB
49
SMC
K91_BEN
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
CK
APPD
DATE
2009-05-19
rev3.11.3
(.csa)
Date
Page
04/27/2010
Contents
Sync
50
SMC Support
K91_BEN
LPC+SPI Debug Connector
K91_YUN
51
52
K92 SMBus Connections
K17_MLB
Voltage & Load Side Current Sensing
K92_DINESH
53
54
High Side and CPU/AXG Current Sensing
(.csa)
07/12/2010
09/23/2010
04/26/2010
09/24/2010
10/29/2010
09/24/2010
04/26/2010
10/11/2010
07/27/2010
K92_DINESH
55
Thermal Sensors
K92_DINESH
56
Fan Connectors
K17_MLB
57
WELLSPRING 1
K92_ERIC
WELLSPRING 2
K92_ERIC
58
59
Digital Accelerometer
06/02/2010
05/27/2010
07/30/2010
06/16/2010
10/22/2010
10/22/2010
11/02/2010
K92_DINESH
61
SPI ROM
K92_BEN
62
AUDIO:CODEC
K92_KAVITHA
63
AUDIO: LINE IN
K92_AUDIO
65
AUDIO: HEADPHONE OUT
K92_KAVITHA
66
AUDIO:SPEAKER AMP
K92_KAVITHA
AUDIO: JACKS
K92_KAVITHA
AUDIO: JACK TRANSLATORS
K92_KAVITHA
DC-In & Battery Connectors
K92_CHANG
PBus Supply & Battery Charger
K91_CHANG
System Agent Supply
K91_CHANG
5V / 3.3V Power Supply
K92_ERIC
1.5V DDR3 Supply
K91_CHANG
CPU IMVP7 & AXG VCore Regulator
K92_ERIC
CPU IMVP7 & AXG VCore Output
K92_ERIC
CPU VCCIO (1.05V) Power Supply
K92_ERIC
Misc Power Supplies
K91_CHANG
Power FETs
K91_MLB
Power Control 1/ENABLE
K92_YUAN
Whistler PCI-E
K91_MLB
Whistler CORE/FB POWER
K92_BEN
Whistler FRAME BUFFER I/F
K18_MLB
GDDR5 Frame Buffer A
K91_YUN
GDDR5 Frame Buffer B
K91_YUN
Whistler LVDS/DP/GPIO
K92_SUMA
Whistler GPIOs & STRAPs
K91_MLB
67
68
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Date
Page
Contents
Sync
99
07/30/2010
Power Sequencing EG/PCH S0
K92_YUAN
CPU Constraints
K91_MLB
Memory Constraints
K17_MLB
PCH Constraints 1
K92_YUN
PCH Constraints 2
K91_MLB
Ethernet/FW Constraints
K91_MLB
T29 Constraints
T29_REF
SMC Constraints
K17_MLB
GPU (Whistler) CONSTRAINTS
K91_MLB
Project Specific Constraints
K91_MLB
PCB Rule Definitions
K17_MLB
PCH Power Aliases
K17_MLB
DEBUG SENSORS AND ADC
K92_DINESH
DEBUG SENSORS AND ADC 2
K92_DINESH
Power Supplies BIST
K92_DINESH
100
07/22/2010
101
05/14/2010
102
06/25/2010
103
07/22/2010
104
07/22/2010
105
10/20/2010
106
05/14/2010
107
07/21/2010
108
07/22/2010
109
05/14/2010
121
04/27/2010
130
09/07/2010
131
07/28/2010
132
08/23/2010
11/22/2010
69
06/28/2010
70
07/21/2010
71
07/21/2010
72
08/30/2010
73
07/21/2010
74
11/09/2010
75
09/27/2010
76
09/23/2010
77
07/21/2010
78
10/18/2010
79
07/22/2010
80
10/19/2010
81
06/03/2010
82
04/27/2010
84
08/23/2010
85
08/23/2010
86
10/21/2010
87
07/17/2010
88
06/01/2010
Whistler DP PWR/GNDs
K92_BEN
GPU (Whistler) CORE SUPPLY
K91_CHANG
LVDS Display Connector
K17_MLB
Muxed Graphics Support
K92_YUN
DisplayPort/T29 A MUXing
K91_MLB
DisplayPort/T29 A Connector
K91_MLB
1V0 GPU / 1V5 FB Power Supply
K91_CHANG
Graphics MUX (GMUX)
K92_YUAN
LCD Backlight Driver (LP8545)
K92_DINESH
89
07/21/2010
90
04/26/2010
92
06/25/2010
93
10/22/2010
94
10/22/2010
95
07/21/2010
96
07/28/2010
09/07/2010
97
98
04/26/2010
LCD Backlight Support
K17_MLB
ALIASES RESOLVED
SCHEM,BLACK_PEARL,MLB,K92
(.csa)
Page
2
REV
pre-evt 11/22/10
D
A
DRAWING TITLE
SCHEM,MLB,K92
DRAWING NUMBER
Schematic / PCB #s
PART NUMBER
QTY
Apple Inc.
DESCRIPTION
REFERENCE DES
CRITICAL
051-8618
SCHEM,BLACK_PEARL,MLB,K92
SCH
CRITICAL
820-2914
PCBF,BLACK_PEARL,MLB,K92
PCB
CRITICAL
BOM OPTION
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Tue Nov 23 20:44:38 2010
SIZE
D
REVISION
BRANCH
PAGE
1 OF 132
SHEET
1 OF 105
J2500
INTEL CPU
U8000
XDP CONN
WHISTLBR
PG 23
SANDYBRIDGE
PG 9-13
PG 74
J2900
2 UDIMMs
DDR3 /1333MHZ
DIMM
J6900/J6950
PG 26,28
DC/BATT
POWER SUPPLY
PG 63
GPIO
PG 19
FDI
DMI
RTC
PG 17
PG 17
PG 16
U4900
TEMP SENSOR
CLOCK
CK505
U2700
Misc
PG 52
CLK
PG 19
U6100
BUFFER
P8 24
PG 16
J4500
SATA
Conn
HD
SPI
J4501
SATA 3.0/ 6GHZ.
PG 53
INTEL
SATA
U4900
ADC
B,0 BSB
COUGAR POINT
SMC
LPC
PG 16
SATA 2.0 /3GHZ.
FAN CONN AND CONTROL
PG 58
SATA
PG 84
J5650,5660
PG 16
P8 41
CBTL06141EE
U9320
POWER PGSENSE
51
SPI
Boot ROM
Fan Ser
Prt
J5100
PG 54
LPC Conn
Port80,serial
PG 47
Conn
ODD
PG 16
U1800
P8 41
PWR
J9400
CTRL
DP OUT
DISPLAY PORT
CONN
U3600
PG 17
RGB OUT
USBDN4
PG 85
HDMI OUT
U9600
GMUX
XP25-5
LVDS OUT
PG 87
USB
PG 18
PG 18
TMDS OUT
PCI
PG 18
J9000
LVDS
CONN
(UP TO 14 DEVICES)
DVI OUT
0 1 2 3 4 5 6 7 8 9 10 11 12 13
USX2061
USBDN3
USBDN2
PG 73
USBDN1
J5713/J5800
J3401
Bluetooth
PG 31
EXTA
J3500
TRACKPAD/
KEYBOARD
J4600,J4610,4720
EXTERNAL
USB
EXPRESSCARD
PG 53/54
PG 32
PG 41
EXTC
EXTB
U3600
USBDN4
JTAG
USX2061 USBDN3
SMB
PG 83
PG 16
PG 16
PEG
PERN2
PG 16
IHDA
PCI-E
PERN3
PERN1
PERN4
USBDN2
PG 73
SMB
CONN
PG 16
DIMMs
USBDN1
PG 48
EXPRESSCARD
PG 16
J3402
J4800
CAMERA
PG 31
IR
PG 44
U6200
AudioCodec
CS4206ACNZC
PG 57
LINE IN
U6500
U4100
U3900
U6610,6620,6630,6640,6650
J3500
GB
E-NET
FW643
BCM57765
EXPRESSCARD
CONN
HEADPHONE
Amp
Speaker
Amps
PG 38
SYNC_MASTER=K60_MLB
SYNC_DATE=04/26/2010
PAGE TITLE
System Block Diagram
PG 60
PG 36
PG 32
DRAWING NUMBER
LINE OUT
J3401
J4310
Mini PCI-E
AIRPORT
Apple Inc.
J4000
FW-800
Conn
E-NET
Conn
PG 40
PG 37
J6780,6781,6782,6700,6750
Audio
Conns
PG 31

PG 61
SIZE
D
REVISION
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PAGE
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SHEET
2 OF 105
K92 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H_OR_PBUS_R
D6990
SMC PWRGD
NCP303LSN
U5000
(PAGE 46)
R6990
SMC_RESET_L
ENABLE
SMC AVREF SUPPLY
3.425V G3HOT
J6900
F7040
PP3V42_G3H
SMC_TPAD_RST_L
U7000
VIN
PPVBAT_G3H_CHGR_REG
PP5V_S3_GFXIMVP6_VDD
VDD
F7041
8A FUSE
ISL6259HRTZ
PBUS SUPPLY/
BATTERY CHARGER
VOUT
VR_ON
VIN
PP1V0_FW
TPS22924
VOUT
(PAGE 70)
FW_PWR_EN
EN
CHGR_BGATE
PPCPUVCCIO_S3
PGOOD
EN
PGOOD
CPU VCORE
VOUT
VIN
ISL95831
CPUIMVP7_VR_ON
U7400
VR_ON
SMC_CPU_HI_ISENSE
SMC_CPU_FSB_ISENSE
CPUVTTS0_PGOOD
CPUVTTS0_EN
R5388
PPVBAT_G3H_CHGR_R
PPCPUVTT_S0
ISL95870
U7600
(PAGE 82)
Q7055
VOUT
1.05V
GPUVCORE_PGOOD
(PAGE 64)
PPVBATT_G3H_CONN
PP5V_S0_CPUVTTS0
VIN
SMC_GPU_ISENSE
GPUVCORE_EN
SMC_BATT_ISENSE
J6950
PPVCORE_GPU
U5410
ISL6263C
U8900
U5001
R7640
SMC_GPU_VSENSE
GPU VCORE
R7050
VIN
VOUT
SMC_DCIN_ISENSE
PPVCORE_S0_CPU
COUGAR_POINT
PM_PWRBTN_L
PWRBTN#
SMC_CPU_ISENSE
SYS_RERST#
RSMRST#
CPUIMVP7_PGOOD
PGOOD
ACPRESENT
PM_PCH_PWRGD
PLT_RERST_L
PS_PWRGD
PLTRST#
PP5V_S3
U1800
GMUX
U9600
XP25-5
EG_RAIL1_EN
PB17A
EG_RAIL2_EN
P3V3GPU_EN
PB17B
EG_RAIL3_EN
GPUVCORE_EN
PB18A
EG_RAIL4_EN
R7350/U5440
PM_ALL_GPU_PGOOD
P1V0GPU_EN
EN1
PP1V0_S0GPU
VIN
VOUT1
P1V5FB_EN
SMC
P3V3S5_EN
VOUT2
EN2
1.8V(R/H)
ISL6236
U9500
(PAGE 86)
U4900
P1V0GPU_PGOOD
POK2
P1V5FB_PGOOD
VIN
P3V3S5_EN
Q9806
EN1
5V
EN2
3.3V
VREG5
TPS51916
DDRREG_PGOOD
U7300 PGOOD
(PAGE 67)
BKLT_PLT_RST_L
&&
LCD_BKLT_EN
DDRREG_EN
DELAY
U1800
P3V3S3_EN
VIN
LP8545SQX
U9701
BKLT_EN
CPU
ENA
VOUT
PP1V5_S3RS0
PP3V3_S0
Q7860
VOUT
ON SLG5AP020
MAX8840
VOUT
EN
(PAGE 57)
P5VS0_EN
PP5V_S3
PP5V_S3
PM_ALL_GPU_PGOOD
PP3V3_S5
VIN
TPS61045
VOUT2
U5805
(R/H)
VOUT
U7980
PP18V5_S3
RSMRST_PWRGD
P5VS3_PGOOD
PPVOUT_S0_LCDBKLT
P1V5_S0_EN EN
P3V3GPU_EN
ISL8009B
U7710
OUT
PP1V5_S0
Q7922
LTC1872
U7790
IMVP_VR_ON
PM_SYSRST_L
PP3V3_ENET
PP3V3_S0_PWRCTL
U4201
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S5_L
P5VS3_PGOOD
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN
SLP_S5_L(P95)
PM_SLP_S4_L
RES*
SMC_RESET_L
SLP_S4_L(P94)
TPS22924
PP3V3_S0_FET
VOUT
99ms DLY
IMVP_VR_ON(P16)
P1V8S0_PGOOD
Q7830
VIN
PM_RSMRST_L
RSMRST_OUT(P15)
PWR_BUTTON(P90)
SYSRST(PA2)
PP3V3_S3
PP10V_FW
RSMRST_IN(P13)
(PAGE 71)
Q7810
Q4260
SLP_S3#(P12)
(P64)
SMC_ONOFF_L
VIN
SMC_ADAPTER_EN
PWRGD(P12)
PP3V3_S0_GPU
P3V3S3_EN
(PAGE 16-21)
SMC
ALL_SYS_PWRGD
(PAGE 54)
Q7870
P3V3S5_PGOOD
PM_SLP_S3_L
RESET*
(PAGE 9-14)
PP4V5_AUDIO_ANALOG
U6201
PP5V_S0_FET
(PAGE 88)
PM_SLP_S4_L
SM_DRAMPWROK
U1000 VCCCPUPWRGD
RD220
VOUT1
TPS51980
U7201
(PAGE 66)
PGOOD1
PGOOD2
P5VS3_EN
DELAY
SLP_S4#(H7)
PPVTT_S0_DDR_LDO
U7801
(PAGE 54)
(L/H)
RC
PP1V5_S3
VIN
PM_SLP_S5_L
RC
PPDDR_S3_REG
VOUT1
PP5V_S5
P1V5CPU_EN
P5VS3_EN
VLDOIN
1.5V
S3 0.75V
VOUT2
SMC_GPU_1V5_ISENSE
POK1
COUGAR_POINT
SLP_S5#(E4)
S5
PP1V5R1V35_GPU_FB_ISNS
DELAY
SMC_PM_G2_EN
(PAGE 16-21)
R5410
1.103V(L/H)
RC
U2850
SMC_DDR_ISENSE
VIN
DDRREG_EN
(PAGE 87)
(PAGE 45)
DRAMPWROK
MEMVTT_EN
P60
CPU_PWRGD
PROCPWRGD
PM_MEM_PWRGD
PB16B
PL32A
U4202
(PAGE 39)
SMC_CPU_VSENSE
(PAGE 68)
SMC_ONOFF_L
DCIN(16.5V)
IN
2S4P
REF3333VOUT
(PAGE 46)
R7020
ADAPTER
(6 TO 8.4V)
VIN
PPBUS_G3H
F6905
6A FUSE
AC
Q5315
PP3V3_S5_AVREF_SMC
PP3V42_G3H
PM6640
U6990
(PAGE 63)
SMC_PBUS_VSENSE
S0PGOOD_PWROK
PP3V3_FW_FWPHY
PM_SLP_S3_L
SLP_S3_L(P93)
H8S2117
U4900
(PAGE 45)
(PAGE 39)
(PAGE 71)
PP3V3_S0
P3V3S0_EN
FW_PWR_EN
SMC_ADAPTER_EN&&PM_SLP_S3_L
VCC
R7978
PP3V3_S0_VMON
VIN
PM_SLP_S3_L_R
P1V8_S0_EN
EN
ISL8014
VOUT
U7720
PGOOD
PP1V8_S0
PP1V5_S0_VMON
P1V8S0_PGOOD
PP1V05_S0_VMON
(PAGE 70)
RC
DELAY
RC
DELAY
P1V8S0_EN
PP3V3_FW_FET
PP1V2_S0
P5VS0_EN
V3MON
RST*
PG
V4MON(PAGE 73)
TRST = 200mS
P1V2ENET_PGOOD
SYNC_MASTER=K17_MLB
P1V2S0_EN
P3V3S0_EN
RC
DELAY
CPUVTTS0_EN
RC
DELAY
P1V5CPU_EN
PAGE TITLE
Revision History
P1V2ENET_EN
EN
Q7850
U7971
V2MONISL88042IRTJJZ
ISL8014A
DRAWING NUMBER
P1V2GMUX_EN
VIN
U7760 VOUT
PP1V2_ENET
Apple Inc.
R
(PAGE 71)
PBUSVSENS_EN

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SHEET
3 OF 105
8
PROTO2/EVT 11/11/10
PROTO2/EVT 11/15/10
PROTO2/EVT 11/19/10
EVT 11/22/10 rev3.9
rev3.0 for board 820-2914-05.brd release

for board 820-2914-07.brd release
SYNC_MASTER=K17_MLB
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
R

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SHEET
4 OF 105
Alternate Parts
TABLE_ALT_HEAD
BOM Variants
PART NUMBER
ALTERNATE FOR
PART NUMBER
157S0058
BOM OPTION
REF DES
COMMENTS:
157S0055
ALL
Delta alt to TDK Magnetics
152S0896
152S0518
ALL
MAG LAYERS ALT TO CYNTEC
152S0915
152S0796
ALL
MAG LAYERS ALT TO CYNTEC
155S0457
155S0329
ALL
MAG LAYERS ALT TO MURATA
516S0805
516S0806
ALL
FOXCONN ALT TO MOLEX
353S2805
353S2603
ALL
Fairchild 8 alt to 6wafer
127S0111
127S0060
ALL
Rohm alt to Kemet
353S3085
353S1658
ALL
ST Micro alt to LT
152S0905
152S1307
ALL
Cyntec (used on K90i) as alt
353S3055
353S3151
ALL
Pericom alt to NXP DP Mux
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
639-1303
PCBA,MLB,K92
K92_COMMON,CPU:2_2GHZ,FB_1G_SAMSUNG,EEEE_DG5Y
639-1464
PCBA,MLB,CFG2,K92
K92_COMMON,CPU:2_2GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG60
639-1466
PCBA,MLB,CFG3,K92
K92_COMMON,CPU:2_3GHZ,FB_1G_SAMSUNG,EEEE_DG62
639-1465
PCBA,MLB,CFG4,K92
K92_COMMON,CPU:2_3GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG61
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
085-1898
K92 MLB DEVELOPMENT BOM
K92_DEVEL:ENG
TABLE_ALT_ITEM
TABLE_ALT_ITEM
K92 BOM GROUPS
(U5850)
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
TABLE_BOMGROUP_ITEM
K92_COMMON
ALTERNATE,COMMON,K92_COMMON1,K92_COMMON2,K92_PROGPARTS
K92_COMMON1
CPUMEM_S0,EXT_HP_AMP,SMC_DEBUG_YES,USBHUB_2514B
376S0855
376S0613
ALL
radar8515240 Toshiba FET
870-1939
870-1698
ALL
Silver alt to Gold tall pogo pins
GPUVID_1P11V,HUB1_2NONREM,HUB2_2NONREM,KB_BL,ENET:B0,T29BST:Y,T29:YES,T29_DP_HPD:ALL_OR
SNB_CPT_XDP,DEBUG_ADC,LPCPLUS:YES,VREFMRGN,GMUX_JTAG_CONN,S0PGOOD_ISL,BMON:ENG,CPURIPPLE_ENG,IMVPISNS_ENG,SDRVI2C:MCU
TABLE_ALT_ITEM
870-2015
870-1699
ALL
Silver alt to Gold short pogo pins
376S0972
376S0612
ALL
add ROHM part as 2nd source
138S0676
138S0691
ALL
add Murata part as 2nd source
128S0327
128S0264
ALL
add NEC part as 2nd source
376S0977
376S0859
ALL
add new part as 2nd source
138S0681
138S0638
ALL
add new part as 2nd source
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
K92_DEVEL:PVT
TABLE_ALT_ITEM
SNB_CPT_XDP,LPCPLUS:YES,VREFMRGN_NOT
TABLE_BOMGROUP_ITEM
K92_PROGPARTS
TABLE_ALT_ITEM
SMC_PROG:EVT,BOOTROM_PROG:EVT,ENETROM_PROG:B0_NOSD,TPAD_PROG:EVT,T29ROM:PROG,GMUX_PROG,T29MCU:PROG
TABLE_BOMGROUP_ITEM
K92_PVT
VREFMRGN_NOT,XDP,XDP_CPU_BPM,BMON:PROD
SNB_CPT_XDP
XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH
(Q3200, etc)
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
K92_COMMON2
(U9390)
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
K92_DEVEL:ENG
(L7630)
TABLE_ALT_ITEM
BOM OPTIONS
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
(Q3888,Q9430)
Bar Code Labels / EEEE #s

PART NUMBER
DESCRIPTION
REFERENCE DES
826-4393
QTY
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_DG5Y]
CRITICAL
CRITICAL
BOM OPTION
EEEE_DG5Y
826-4393
[EEEE_DG60]
CRITICAL
EEEE_DG60
826-4393
[EEEE_DG61]
CRITICAL
EEEE_DG61
338S0895
IC,SMC,HS8/2117,9MMX9MM,TLP
826-4393
[EEEE_DG62]
CRITICAL
EEEE_DG62
341S2855
IC,SMC,DEVELOPMENT-PROTO,K92
341S2855
IC,SMC,DEVELOPMENT-PROTO1,K92
341S2995
IC,SMC,DEVELOPMENT-PROTO2,K92
341S2862
IC,SMC,DEVELOPMENT-EVT,K92
341S2865
IC,SMC,DEVELOPMENT-DVT,K92
341S2868
IC,SMC,DEVELOPMENT-PVT,K92
SMC
PART NUMBER
Module Parts
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
QTY
DESCRIPTION
337S4032
IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA
337S4033
IC,CPU,SNB,SR00U,PRQ.D2,2.3,45W,4+2,1.30,8M,BGA
337S4029
IC,PCH,COUGARPOINT SLH9D,PRQ,BD82HM63
343S0534
IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8
343S0494
IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8
338S0753
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
U1000
U1000
U1800
U3900
U3900
U4100
333S0543
IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_512_SAMSUNG
335S0740
64 MBIT SPI SERIAL DUAL I/O FLASH
333S0564
IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V
U8400,U8450,U8500,U8550
CRITICAL
FB_512_HYNIX
341S2893
IC,EFI,ROM,PROTO, K90/K90I/K91/K91F/K92
333S0571
IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_1G_SAMSUNG
341S2934
IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92
333S0572
IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
FB_1G_HYNIX
341S2991
IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92
337S3936
IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES
341S2894
IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92
338S0945
Light Ridge,S LHAJ,FCBGA,15x15mmm
341S2895
IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92
353S3055
IC, P13VEDP212,x2 DISPLAYPORT 2:1 MUX, QFN
341S2896
IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92
U8000
U3600
U9390
CRITICAL
CPU:2_2GHZ
CRITICAL
CPU:2_3GHZ
335S0777
QTY
1
DESCRIPTION
341S2899
IC,T29 EEPROM,K92
341S2384
IR,ENCORE II, CY7C63833-LFXC
335S0724
IC,GPU ROM,K91/F,K92
341S2957
IC,GPU ROM,K91/F,K92
336S0042
IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA
341S2996
IC,GMUX,K92
337S3997
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
341S2939
IC,PROGRAMMED MCU,32B,LPC1112A,16KB/2KB,HVQFN25
CRITICAL
BOM OPTION
CRITICAL
SMC_BLANK
CRITICAL
SMC_PROG:PROTO0
CRITICAL
SMC_PROG:PROTO1
CRITICAL
SMC_PROG:PROTO2
CRITICAL
SMC_PROG:EVT
CRITICAL
SMC_PROG:DVT
CRITICAL
SMC_PROG:PVT
CRITICAL
ENET:B0
CRITICAL
ENET:A0
EFI
PART NUMBER
CRITICAL
CRITICAL
CRITICAL
T29:YES
CRITICAL
QTY
DESCRIPTION
REFERENCE DES
U6100
U6100
U6100
U6100
U6100
U6100
U6100
CRITICAL
BOM OPTION
CRITICAL
BOOTROM_BLANK
CRITICAL
BOOTROM_PROG:PROTO0
CRITICAL
BOOTROM_PROG:PROTO1
CRITICAL
BOOTROM_PROG:PROTO2
CRITICAL
BOOTROM_PROG:EVT
CRITICAL
BOOTROM_PROG:DVT
CRITICAL
BOOTROM_PROG:PVT
Ethernet
PART NUMBER
REFERENCE DES
IC,EEPROM,SERIAL,8KB,SOIC
U4900
U4900
U4900
U4900
U4900
U4900
U4900
CRITICAL
Programmed Parts-All Builds

PART NUMBER
REFERENCE DES
U3690
U3690
U4800
U8701
U8701
U9600
U9600
U9330
U9330
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
T29ROM:BLANK
T29ROM:PROG
QTY
DESCRIPTION
335S0539
IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC
341S2685
IC,ENET ROM,PROTO1,K92
341S3027
IC,ENET ROM, PROTO2, EVT,DVT,PVT,K92
REFERENCE DES
U3990
U3990
U3990
CRITICAL
BOM OPTION
CRITICAL
ENETROM_BLANK
CRITICAL
ENETROM_PROG:A0_SD
CRITICAL
ENETROM_PROG:B0_NOSD
CRITICAL
GPUROM will NOSUFFED @EVT
CRITICAL
GPUROM:BLANK
CRITICAL
GPUROM:PROG
CRITICAL
GMUX_BLANK
CRITICAL
GMUX_PROG
341S2902
IC,TP PSOC,PROTO,K90,K90i,K91,K91F,K92
CRITICAL
T29MCU:BLANK
341S3024
IC,TP PSOC,proto2,K90,K90i,K91,K91F,K92T
CRITICAL
T29MCU:PROG
341S3024
IC,TP PSOC,proto1,EVT,K90,K90i,K91,K91F,K92T
341S3024
IC,TP PSOC,proto1,DVT,pVT,K90,K90i,K91,K91F,K92T
PSOC
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
U5701
U5701
U5701
U5701
CRITICAL
BOM OPTION
CRITICAL
TPAD_PROG:PROTO1
CRITICAL
TPAD_PROG:PROTO2
CRITICAL
TPAD_PROG:EVT
CRITICAL
TPAD_PROG:DVTPVT
SYNC_MASTER=K17_MLB
PAGE TITLE
BOM Configuration
DRAWING NUMBER
Apple Inc.
R

SIZE
D
REVISION
BRANCH
PAGE
5 OF 132
SHEET
5 OF 105
J5650 (LEFT FAN CONN)

FAN_LT_PWM
FAN_LT_TACH
TRUE
PP5V_S0
TRUE
TRUE
I1488
J5660 (RIGHT FAN CONN)

FAN_RT_PWM
TRUE
FAN_RT_TACH
TRUE
PP5V_S0
GND
TRUE
FUNC_TEST
I1561
TRUE
52
I1051
TRUE
52
I1050
TRUE
47
6 7 8
22 41
52
54
65 68
69 70
73
87 104 105
GND
TRUE
2 TPs
I1053
2 TPs
52
I557
I558
I559
TRUE
I1054
TRUE
I1056
TRUE
54 65 68 69 70 73 87 104 105 I1058

47
6 7 8
I1057
22 41
52
2 TPs
J6780 (MIC FR CONN)

AUD_DMIC_CLK_FR
TRUE
AUD_DMIC_SDA_FR
TRUE
AUD_DMIC_PWR_FR
TRUE
GND
TRUE
2 TPs
I1490
I1491
I1492
TRUE
I985
I987
TRUE
I986
TRUE
I988
TRUE
TRUE
TRUE
TRUE
WIFI_EVENT_L
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
AP_CLKREQ_Q_L
PCIE_WAKE_L
AP_RESET_CONN_L
5
I1103
31 45 46
I1102
31 95
I1104
31 95
I1105
16 31 95
I1107
16 31 95
I1106
31 100
I1108
31 100
I1109
31
I1110
6 17 25 31 32 85
I1111
31
I1112
I1059
TRUE
PP3V3_WLAN
I1061
TRUE
I1060
TRUE
I1063
TRUE
I1066
TRUE
PP3V3_S3_BT_F
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
USB_BT_P
USB_BT_N
I1065
J6783 (MIC BK CONN)

AUD_DMIC_CLK_BK
TRUE
AUD_DMIC_SDA_BK
TRUE
AUD_DMIC_PWR_BK
TRUE
GND
TRUE
TRUE
I1052
I1055
2 TPs
6
J3401(AIRPORT/BT CONN)
Functional Test Points
TRUE
TRUE
31 46
3 TP needed
I1113
I1114
31
I1115
31 45 48 51 80 98
I1117
31 45 48 51 80 98
I1116
24 31 94
24 31 94
GND
6 TP needed
61
61
61
2 TPs
I1062
I1064
J6781 (LEFT SPEAKER)

SPKRAMP_FL_OUT_P
SPKRAMP_FL_OUT_N
SPKRAMP_BL_OUT_P
SPKRAMP_BL_OUT_N
I1451
60 61
I1479
60 61
I1478
60 61
J3402 (CAMERA/ALS CONN)

USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
PP5V_S3_ALSCAMERA_F
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
GND
TRUE
31 94
31 94
31
6 31 45 48 54 55 98
6 31 45 48 54 55 98
2 TP needed
60 61
J6782 (RIGHT & SUB SPEAKER)

TRUE
I989
I990
TRUE
I992
TRUE
I991
TRUE
I994
TRUE
I993
TRUE
J3500 (EXPRESS CARD CONN)
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
SPKRAMP_FR_OUT_P
SPKRAMP_FR_OUT_N
SPKRAMP_BR_OUT_P
SPKRAMP_BR_OUT_N
I1067
TRUE
I1068
TRUE
60 61
I1069
TRUE
60 61
I1071
TRUE
I1070
TRUE
I1072
TRUE
I1074
TRUE
I1073
TRUE
I1075
TRUE
60 61
60 61
J9000 (LVDS CONN)
I995
TRUE
I996
TRUE
I997
TRUE
I998
TRUE
I1000
TRUE
I1001
TRUE
I1002
TRUE
I1004
TRUE
I1003
TRUE
I1005
I1007
TRUE
I1006
TRUE
I1009
TRUE
I1008
TRUE
I1010
TRUE
I1011
TRUE
I1012
TRUE
TRUE
I1014
TRUE
I1013
TRUE
I1015
TRUE
I1016
TRUE
I1017
TRUE
I1018
TRUE
I1019
TRUE
I1020
TRUE
I1022
TRUE
I1021
TRUE
TRUE
I1024
TRUE
I1026
TRUE
I1025
TRUE
I1028
TRUE
I1027
TRUE
I1029
TRUE
TRUE
PP3V3_SW_LCD
PP3V3_S0
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
GND
J4500 (SATA ODD CONN)
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
GND
83 84 85
54 57 61
46 48 49
32 35 36
6 7 12
23 25 26 28
39 40 41
50 51 52
62 72 73 80
88 89 91 100 102
2 TPs
2 TPs
2 TPs
83 84
83 84 99
I1076
TRUE
I1077
TRUE
I1079
TRUE
I1078
TRUE
83 84 99
I1081
TRUE
83 84 99
I1080
TRUE
83 84 99
I1082
TRUE
83 84 99
I1083
83 84 99
I1084
I1031
TRUE
I1033
TRUE
I1472
TRUE
I1473
TRUE
I1474
TRUE
I1475
TRUE
I1476
TRUE
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
PP5V_S3_IR_R
IR_RX_OUT
SYS_LED_ANODE_R
GND
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
TRUE
TRUE
PP1V5_S0_EXCARD_SWITCH
32
PCIE_WAKE_L
6 17 25 31 32 85
SMBUS_PCH_CLK
16 23 26 28 30 32
95
SMBUS_PCH_DATA
16 23 26 28 30 32
48 62 89 95
32
32
USB2_EXCARD_CONN_N
32 100
USB2_EXCARD_CONN_P
32 100
EXCARD_CPUSB_L
32
EXCARD_CLKREQ_CONN_L
32
EXCARD_CPPE_L
32
PLT_RESET_SWITCH_L
32
PCIE_EXCARD_D2R_P
16 32 100
PCIE_EXCARD_D2R_N
16 32 100
PCIE_EXCARD_R2D_P
32 100
PCIE_EXCARD_R2D_N
32 100
PCIE_CLK100M_EXCARD_CONN_P 32 100
PCIE_CLK100M_EXCARD_CONN_N 32 100
2 TP needed
POWER RAILS
FUNC_TEST
41 48 62 89
TRUE
41
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PM_SLP_S3_L
PPBUS_G3H
PP3V42_G3H
PP5V_S3
PP5V_S0
PPVCORE_S0_CPU
PP3V3_S5
PP3V3_S3
PP3V3_S0
TRUE
PP1V2_S0
TRUE
PP1V8_S0
TRUE
PPVTTDDR_S3
TRUE
PPVP_FW
17 29 45 73
7 8 35 39 49 50 63
64 90
104
6 7 25 42 44 45 46
47 48 53 63 64 73
87 104 105
6 7 8 22 41 47 52
54 65 68 69 70 73
7 12 14 49 69 105
2 TPs
54 55
6 7 8 18 24 25 29
30 31 32 48 49 50
73 88 104
6
32 35 36
7 12 23 25 26 28
39 40 41 46 48
49 50 51 52 54
61 62 72 73
88 57
80 83 84 85 88
7 89
91 100 102
71
7 14 20 25 71 72
88 102
83 99
83 84 99
I1085
TRUE
83 84 99
I1086
TRUE
83 84 99
I1087
TRUE
83 84 99
I1273
TRUE
83 84 99
I1089
TRUE
83 84 99
I1088
TRUE
I1090
TRUE
83 99
83 99
I1091
TRUE
83 89
I1098
TRUE
83 89
I1097
TRUE
83 89
I1095
TRUE
83 89
I1484
TRUE
83 89
I1485
TRUE
83 89
5 TPs
I1096
TRUE
I1092
TRUE
I1093
3 TPs
TRUE
I1094
TRUE
I1099
TRUE
I1100
TRUE
41 104
41 45
41 94
I1101
TRUE
41 94
TRUE
PP3V3_S3
PP18V5_S4
PP3V3_S4
Z2_CS_L
Z2_DEBUG3
Z2_MISO
Z2_BOOST_EN
Z2_MOSI
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
Z2_HOST_INTN
Z2_SCLK
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
GND
TRUE
6 7 8 18 24 25 29 30
31 32 48 49 50 54 55 73 88 104
6 54
PP3V3_S0GPU
7 72 75 79 80 82
84
TRUE
TRUE
PP3V3_S5_AVREF_SMC
45 46
TRUE
PP18V5_S4
6 54
TRUE
PPDCIN_G3H
7 49 63 64
TRUE
53 54
53 54
53 54
54
7 75 79 81 103
7 49 75 82
7 72 103
53 54
53 54
FUNC_TEST
SYS_LED_ANODE_R
TRUE
LPC_CLK33M_LPCPLUS
TRUE
53 54
53 54
53 54
TRUE
53 54
LPC_AD<0..3>
53 54
TRUE
SPI_ALT_MOSI
53 54
TRUE
25 47 95
16 45 47 88 95
47
53 54
TRUE
53 54
TRUE
SMC_TMS
45 46 47
6 31 45 48 54 55 98
TRUE
LPCPLUS_RESET_L
25 47 88 95
TRUE
6 31 45 48 54 55 98
2 TPS
47
16 45 47 88 95
17 45 47
TRUE
SMC_TDO
45 46 47
TRUE
SMC_TRST_L
45 47
TRUE
SMC_MD1
45 47
41 94
41 94
4 TPs
I1134
41
3 TPs
I1135
41 94
I1137
41 94
J6950 (MAIN BATT CONN)

PPVBAT_G3H_CONN
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SYS_DETECT_L
TRUE
GND
TRUE
63 64
5 TPs
TRUE
SMC_TX_L
TRUE
SPIROM_USE_MLB
19 47 56
TRUE
SPI_ALT_CLK
47
TRUE
SPI_ALT_CS_L
47
TRUE
LPC_SERIRQ
16 45 47
TRUE
LPC_PWRDWN_L
17 45 47
TRUE
SMC_TDI
45 46 47
TRUE
SMC_TCK
63
5 TPs
6 41 94
6 41 94
6 44
I1148
6 44
I1150
6 44
I1149
I1151
J4800 (FRONT CABLE CONN)

PP3V42_G3H_LIDSWITCH_R
PP5V_S3_IR_R
TRUE
SMC_LID_R
TRUE
IR_RX_OUT
TRUE
SYS_LED_ANODE
TRUE
GND
TRUE
TRUE
42 45 46 47
6 45 48 63 64 98
6 45 48 63 64 98
45 46 47
45 47
TRUE
SMC_RESET_L
SMC_NMI
SMC_RX_L
TRUE
LPCPLUS_GPIO
19 47
TRUE
45 46 53
TRUE
44
TRUE
6 44
45 46 47 64
6 44
I1599
I1600
97
I1601
97
I1602
SATA_HDD_R2D_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_RC_UF_N
SATA_HDD_R2D_RC_UF_P
SATA_HDD_R2D_RDRVR_OUT_N
I1541
79
I1542
79 80
I1543
12
I1544
12
I1545
9
I1546
51
I1547
9 17 92
I1549
9 17 92
I1550
17 6
17 6
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
17 6
17 6
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
17 6
18 6
18 6
18 6
16 6
16 6
9 17 92
16 6
17 6
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
6 17
17 6
6 17
6 17
17 6
NC_CRT_IG_DDC_CLK
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE
MAKE_BASE=TRUE
6 17
17 6
NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
17 6
6 17
17 6
6 18
6 18
17 6
6 18
17 6
17 6
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
6 17
6 16
17 6
17 6
6 16
17 6
NO_TEST
6
6
18 6
18 6
8 85
85 97
17 6
NC_PCI_AD<31..0>
NC_PCI_C_BE_L<3..0>
NC_PCI_GNT3_L
NC_PCI_GNT2_L
NC_PCI_GNT1_L
NC_PCI_GNT0_L
NC_PCI_PAR
NC_PCI_RESET_L
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_NV_DQ<15..0>
TP_NV_DQS<1..0>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_NV_DQ<15..0>
NC_NV_DQS<1..0>
TP_NV_CE_L<3..0>
TRUE
MAKE_BASE=TRUE
NC_NV_CE_L<3..0>
NC_NV_ALE
NC_NV_CLE
NC_NV_RB_L
TP_NV_WR_RE_L<1..0>
TP_NV_WE_CK_L<1..0>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_NV_ALE
NC_NV_CLE
NC_NV_RB_L
NC_NV_WR_RE_L<1..0>
NC_NV_WE_CK_L<1..0>
85 97
85 97
8 85
8 85
8 85
8 85
6
6 41 94
6
6 41 94
16 6
41 94
16 6
41 94
19 6
41 94
19 6
41 94
41 94
41 94
19 6
19 6
53 6
16 41 94
6
16 41 94
6
6 41 94
6
6 41 94
6
16 41 94
16 6
16 41 94
16 6
41 94
16 6
SATA_HDD_D2R_RDRVR_OUT_P
41 94
SATA_HDD_D2R_RDRVR_IN_N
41 94
SATA_HDD_D2R_RDRVR_IN_P
41 94
16 6
6
6
6 41 94
6
6 41 94
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_SSD2_D2RN
NC_SATA_SSD2_D2RP
NC_SATA_SSD2_R2D_CN
NC_SATA_SSD2_R2D_CP
TRUE
54
TRUE
PM_SYSRST_L
17 25 45
I1146
54
TRUE
LCD_BKLT_PWM
88 89
44 46
TRUE
NC_BCM57765_SPD100LED_L
NC_BCM57765_TRAFFICLED_L
NC_CE_L_MS_INS_L
38 40
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
NC_SDVO_STALLN
NC_SDVO_STALLP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN
NC_SDVO_INTP
NC_GPU_BUFRST_L
NC_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
NC_GPU_MIOA_DE
6
6
6
6
6
6 18
6 18
NC_LVDS_EG_B_CLKN
NC_LVDS_EG_B_CLKP
NC_LVDS_EG_BKL_PWM
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_BKL_PWM
18 8
18 8
NC_PCH_SST
NC_PCH_NC1
NC_PCH_NC2
NC_PCH_NC3
NC_PCH_NC4
NC_PCH_NC5
NC_PCH_TP19
NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12
NC_PCH_TP11
NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1
6
6
6
6
6
6
6
6 16
6
6 16
6
6 19
6
6 19
6
6 19
6
6 19
6
6 53
6
6
6
6
6
6
6
6
6
6 16
6
6 16
6
6 16
6
6 16
6
6
6
6
6
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
6
6
I1436
TRUE
I1437
TRUE
I1438
TRUE
I1439
TRUE
I1440
TRUE
6 36
6 36
I1441
TRUE
I1442
TRUE
6 36
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
I1443
TRUE
I1444
TRUE
I1445
TRUE
I1446
TRUE
I1447
TRUE
I1448
TRUE
I1449
TRUE
I1450
TRUE
I1142
I1141
I1143
I1486
I1131
I1132
J6995 (BAT LED CONN)

PP3V42_G3H
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMC_BIL_BUTTON_L
TRUE
SMC_LID_R
TRUE
GND
TRUE
J6900 (DC POWER CONN)
ADAPTER_SENSE
PP18V5_DCIN_FUSE
TRUE
GND
TRUE
TRUE
6 17
6 17
6 17
17
17
6 17
6 17
6 17
6 17
6 17
17
17
6 17
6 17
6 17
6 17
6 17
6 17
6 17
NC_LVDS_EG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLKP
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
6
6
PAGE TITLE
Functional / ICT Test
6 7 25 42 44 45 46 47 48 53 63 64 73 104
DRAWING NUMBER
6 45 48 63 64 98
6 45 48 63 64 98
Apple Inc.
45 46 63
R

63
3 TPs
4 TPs
SIZE
D
REVISION
6 44
63
BRANCH
PAGE
7 OF 132
SHEET
6 OF 105
NC_PCH_SST
NC_PCH_NC1
NC_PCH_NC2
NC_PCH_NC3
NC_PCH_NC4
NC_PCH_NC5
NC_PCH_TP19
NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12
NC_PCH_TP11
NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1
SYNC_MASTER=K17_MLB
I1140
has TP
6 38
6 17
NC_GPU_BUFRST_L
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<0>
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<1>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D<9..0>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
TRUE
NC_CE_L_MS_INS_L
MAKE_BASE=TRUE
NC_FW643_AVREG
NC_FW643_TDI
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
TRUE
MAKE_BASE=TRUE
36 6
38 40
NC_DP_IG_D_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PSOC_P1_3
TRUE
MAKE_BASE=TRUE
NC_SATA_C_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_C_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_C_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_C_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SATA_SSD2_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_SSD2_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CP
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
36 6
38 40
NC_DP_IG_D_HPD
NC_DP_IG_D_CTRL_CLK
TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_MLN<3..0>
NC_DP_IG_D_AUXP
NC_DP_IG_D_AUXN
8 85
85 97
has TP
38 40
NC_DP_IG_C_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLP<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLN<3..0>
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
TRUE
MAKE_BASE=TRUE
18 8
85
38 40
38 40
NC_DP_IG_C_HPD
NC_DP_IG_C_CTRL_CLK
TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_MLN<3..0>
NC_DP_IG_C_AUXP
NC_DP_IG_C_AUXN
6 16
NC NO_TESTs
38 40
38 40
MAKE_BASE=TRUE
6 17
17 6
45 46
45 46
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
NC_PCI_GNT3_L
NC_PCI_GNT2_L
NC_PCI_GNT1_L
NC_PCI_GNT0_L
NC_PCI_PAR
NC_PCI_RESET_L
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
NBC
TP_FW643_AVREG
NC_FW643_TDI
38
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
45 46
45 46
9 17 92
17 6
17 6
NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
9 17 92
97
97
NC NO_TESTs
9 17 92
NO_TEST
17 6
8 85
SATA_HDD_R2D_RDRVR_IN_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
DMI_S2N_P<1..0>
DMI_S2N_N<1..0>
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_N2S_P<3>
DMI_N2S_N<3>
I1540
79
17 6
8 85
SATA_HDD_R2D_RDRVR_IN_N
SATA_HDD_D2R_RDRVR_OUT_N
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NO_TEST
TRUE
TRUE
TRUE
TRUE
I1539
79
NC NO_TESTs
SATA_HDD_R2D_RDRVR_OUT_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA_HDD_R2D_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_D2R_N
SATA_HDD_D2R_P
79
38 6
36 6
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TP_DVPCLK
TP_DVPCNTL<2..0>
TP_DVPCNTL_M<1..0>
TP_DVPDATA<23..0>
TP_GPU_JTAG_TRST_L
TP_DC_TEST_A4
TP_DC_TEST_D1
TP_EDP_TX_P<3..0>
TP_T29_SENSOR_ALERT
42 45 46 47
TRUE
J5815 (KBD BACKLIGHT CONN)

KBDLED_ANODE
SMC_KDBLED_PRESENT_L
GND
TRUE
DP_A_BIAS_N_0
DP_A_BIAS_P_0
DP_A_BIAS_N_2
DP_A_BIAS_P_2
DP_A_BIAS
DP_SDRVA_ML_R_N<0>
DP_SDRVA_ML_R_P<0>
DP_SDRVA_ML_R_N<2>
DP_SDRVA_ML_R_P<2>
T29_A_BIAS_R2D_N0
T29_A_BIAS_R2D_P0
T29_A_BIAS_R2D_N1
T29_A_BIAS_R2D_P1
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
6 44
I1145
I1152
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I1548
ISSP_SCLK_P1_1
ISSP_SDATA_P1_0
SMC_ONOFF_L
4 TPs
T29_D2R_P<1..0>
33 85 97
T29_D2R_N<1..0>
33 85 97
T29_D2R_C_P<1..0>
85 86 97
T29_D2R_C_N<1..0>
85 86 97
T29_R2D_C_P<1..0>
33 85 97
T29_R2D_C_N<1..0>
33 85 97
T29_R2D_P<1..0>
85 97
T29_R2D_N<1..0>
85 97
T29DPA_ML_P<3..0>
85 86 97
T29DPA_ML_N<3..0>
85 86 97
DP_T29SNK0_AUXCH_C_P 33 79 97
DP_T29SNK0_AUXCH_C_N 33 79 97
DP_T29SNK0_AUXCH_P
33 97
DP_T29SNK0_AUXCH_N
33 97
DP_T29SNK0_ML_C_P<3..0> 33 79
DP_T29SNK0_ML_C_N<3..0> 33 79
DP_T29SNK0_ML_P<3..0> 33 97
DP_T29SNK0_ML_N<3..0> 33 97
DP_T29SNK1_AUXCH_C_P 33 79 97
DP_T29SNK1_AUXCH_C_N 33 79 97
DP_T29SNK1_AUXCH_P
33 97
DP_T29SNK1_AUXCH_N
33 97
DP_T29SNK1_ML_C_P<3..0> 33 79
DP_T29SNK1_ML_C_N<3..0> 33 79
DP_T29SNK1_ML_P<3..0> 33 97
DP_T29SNK1_ML_N<3..0> 33 97
TP_DP_T29SRC_AUXCH_CN 33
TP_DP_T29SRC_AUXCH_CP 33
TP_DP_T29SRC_ML_CP<3..0> 33
TP_DP_T29SRC_ML_CN<3..0> 33
DP_SDRVA_ML_C_P<0>
85 97
DP_SDRVA_ML_C_N<0>
85 97
DP_SDRVA_ML_C_P<2>
85 97
DP_SDRVA_ML_C_N<2>
85 97
DP_SDRVA_ML_P<0>
85 97
DP_SDRVA_ML_N<0>
85 97
DP_SDRVA_ML_P<2>
85 97
DP_SDRVA_ML_N<2>
85 97
TP_T29_PCIE_RESET0_L 33
T29DPA_D2R1_AUXCH_N 86 97
T29DPA_D2R1_AUXCH_P 86 97
T29_D2R1_BIAS
DP_EXTA_ML_P<3..0>
85
6 44
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
53 54
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
7 39 40
PP1V8_S0GPU
PPVCORE_GPU
PP1V8_S0GPU_ISNS_R
TRUE
6 7 46 53 54 72
3
NO_TEST=TRUE
7 30 67
J5800 (IPD FLEX CONN)
I1136
TRUE
48 53 63 64
6 7 25 42
44 45 46 47
73 104
53
83 99
J4501 (SATA HDD CONN)

I1032
6 7 46 53 54 72
60 61
60 61
4
NO_TEST=TRUE
J5713 (KEY BOARD CONN)

PP3V3_S4
TRUE
PP3V42_G3H
TRUE
WS_KBD1
TRUE
WS_KBD2
TRUE
WS_KBD3
TRUE
WS_KBD4
TRUE
WS_KBD5
TRUE
WS_KBD6
TRUE
WS_KBD7
TRUE
WS_KBD8
TRUE
WS_KBD9
TRUE
WS_KBD10
TRUE
WS_KBD11
TRUE
WS_KBD12
TRUE
WS_KBD13
TRUE
WS_KBD14
TRUE
WS_KBD15_CAP
TRUE
WS_KBD16_NUM
TRUE
WS_KBD17
TRUE
WS_KBD18
TRUE
WS_KBD19
TRUE
WS_KBD20
TRUE
WS_KBD21
TRUE
WS_KBD22
TRUE
WS_KBD23
TRUE
WS_KBD_ONOFF_L
TRUE
WS_LEFT_SHIFT_KBD
TRUE
WS_LEFT_OPTION_KBD
TRUE
WS_CONTROL_KBD
TRUE
GND
TRUE
"G3Hot" (Always-Present) Rails

90 64 63
35 8 7 6
50 49 39
PPBUS_G3H
PPBUS_G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
PPBUS_G3H
PPBUS_G3H
70
65 50 7
69 68 67
PPVIN_S5_HS_COMPUTING_ISNS
6 7 8 35 39 49 50 63 64 90
6 7 8 35 39 49 50 63 64 90
6 7 8 35 39 49 50 63 64 90
6 7 8 35 39 49 50 63 64 90
7 50 65 67 68 69 70
7 50 65 67 68 69 70
7 50 65 67 68 69 70
7 50 65 67 68 69 70
7 50 65 67 68 69 70
7 50 66
VOLTAGE=12.8V
MAKE_BASE=TRUE
PPVIN_S5_HS_OTHER_ISNS
82 50 7
87
PPVIN_S5_HS_GPU_ISNS
7 50 66
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
PPDCIN_G3H
PP3V42_G3H
6 7 49 63 64
VOLTAGE=18.5V
MAKE_BASE=TRUE
17 16 7
25 20
PPVRTC_G3H
104 103 72 66 54 7
PP5V_S5
5V Rails
B
104 82
42 31 29 7 6
72 67 46 44 43
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
PP3V3_S3
6 7 25 42 44 45 46
47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
PP5V_S3
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
6 7 25 42 44 45 46 47 48 53 63 64 73 104
7 16 17 20 25
VOLTAGE=3.42V
MAKE_BASE=TRUE 32 31 30 29 25 24 18 8 7 6
104 88 73 55 54 50 49 48
PP5V_S5
7 54 66 72 103 104
7 54 66 72 103 104
7 54 66 72 103 104
7 54 66 72 103 104
7 54 66 72 103 104
PP5V_S3
6 7 29 31 42 43 44 46 67 72 82 104
VOLTAGE=5V
MAKE_BASE=TRUE
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
6 7 29 31 42 43 44 46 67 72 82 104
PP5V_S3_ISNS_R
7 66 104
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S3_ISNS_R
PP5V_S0
7 66 104
PP5V_S0
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
104 72 7
PP5V_S0_ISNS_R
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
PP5V_S0_ISNS_R
PP5V_S0_ISNS_R
72 22 7
PP5V_SUS
7 72 104
7 72 104
7 22 72
PP5V_SUS
PP1V0_FW_FWPHY
VOLTAGE=5V
MAKE_BASE=TRUE
104 73 29 15 13 10 7
PP1V5_S3RS0_CPUDDR
7 66 104
PP3V3_FW_FWPHY
7 38 39 40
PP3V3_FW_FWPHY
7 38 39 40 67 30 7 6
PP1V0_FW_FWPHY
7 38 39
VOLTAGE=1.0V
MAKE_BASE=TRUE
PPVTTDDR_S3
67 29 28 26 7
PP0V75_S0_DDRVTT
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 16 20 22 25 32
41 57 71
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
48 49 50 54 55 73 88 104
7 8 18 24 25 29 30 31 32
6 35 23 14 13 12 10 9 7
105 104 102 73 70 68 45 39
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 8 18 24 25 29 30 31
32 48 49 50 54 55 73 88 104
PP1V05_S0
? mA
6 7 8
73 88
6 7 8
73 88
6 7 8
73 88
18 24 25 29 30 31 32 48 49 50 54 55
104
18 24 25 29 30 31 32 48 49 50 54 55
104
18 24 25 29 30 31 32 48 49 50 54 55
104
6 7 8
73 88
6 7 8
73 88
18 24 25 29 30 31 32 48 49 50 54 55
104
18 24 25 29 30 31 32 48 49 50 54 55
104
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
PP3V3_S3_ISNS_R
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S3_ISNS_R
PP3V3_S0
7 72 104
105 69 49 14 12 7 6
PPVCORE_S0_CPU
80 79 75 72 7 6
84 82
VOLTAGE=1.2V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PPVCORE_S0_AXG
PPVCCSA_S0_CPU
PP1V5_S3_CPU_VCCDQ
PP1V05_S0_CPU_VCCPQE
PP3V3_ENET
PP1V05_S0
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V5_S0GPU_ISNS_R
7 9
103 78
7 9
104
51 52 54 57 61 62 72 73 80 83 84 85 88
6 7 12 23 25 26 28 32 35
36 39 40 41 46 48 49 50
89 91 100 102
6
48 49 50 51 52 54 57 61 62
7 12 23 25 26 28 32 35 36 39 40 41 46
72 73 80 83 84 85 88 89 91 100 102
PP1V2_ENET
13 14 23 35 39 45 68 70 73 102
14 23 35 39 45 68 70 73 102
39 45 68 70 73 102 104 105
14
7
14 23 35 39 45 68 70 73 102
PP1V0_S0GPU_ISNS_R
103 87 7
6 7 12 14 49 69 105
6 7 12 14 49 69 105
103 81 79 75 74 7
7 12 13 15 49 69
7 12 13 15 49 69
PPVCCSA_S0_CPU
7 12 15 65
VOLTAGE=1.5V
MAKE_BASE=TRUE
103 72 7 6
PP1V8_S0GPU_ISNS_R
7 10 12 14
VOLTAGE=1.05V
MAKE_BASE=TRUE
103 81 79 75 7 6
PP3V3_ENET
PP1V05_T29
6 7 12 23 2552 35 34 7
26 28 32 35 36 39 40 41 46 48 49 50 51
54 57 61 62 72 73 80 83 84 85 88 89 91
100 102 6
7 12 23 25 26 28 32 35 36 39 40
28 32 3541 46 48 49 50 51 52 54 57 61
6 7 124162 72 73 80 83 84 85 88 89 91
23 25 26100 102
36 39 40
61 62 72 73 80 83 84 85
46 48 49 50 51 52 54 57
7 25 36 71 73
88 89 91 100 86 35 8 7
102
7 25 36 71 73
7 25 36 71 73
7 36 71
VOLTAGE=1.2V
MAKE_BASE=TRUE
7 36 71
7 16 19 25 33 34 35 88
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 75 76 77 78 103
7 87 103
7 87 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
7 74 75 79 81 103
6 7 72 103
6 7 72 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
6 7 75 79 81 103
PAGE TITLE
Power Aliases
DRAWING NUMBER
7 16 19 25 33 34 35 88
Apple Inc.
7 16 19 25 33 34 35 88
R
VOLTAGE=1.05V
MAKE_BASE=TRUE

7 34 35
7 8 35 86
VOLTAGE=15V
MAKE_BASE=TRUE
35
7
8
86

SIZE
D
REVISION
7 34 35
PP15V_T29
7 75 76 77 78 103
7 16 19 25 33 34 35 88
PP15V_T29
PP15V_T29
7 75 76 77 78 103
SYNC_MASTER=K17_MLB
7 16 19 25 33 34 35 88
PP1V05_T29
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
7 75 76 77 78 103
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
PP1V8_S0GPU
7 25 36 71 73
PP3V3_T29
PP3V3_T29
PP3V3_T29
PP3V3_T29
PP1V05_T29
7 75 76 77 78 103
VOLTAGE=1.8V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP1V2_ENET
7 87 103
PP1V8_S0GPU_ISNS_R
PP1V8_S0GPU
PP1V8_S0GPU
ENET Rails
PP3V3_T29
102
51 52 54 57 61 62 72 73 80 83 84 85 88
23 25 26 28 32 35 36 39 40 41 46 48 49
6 7
89 91 100
12 80 83 84 85 88 89 91 100 102
50 46 48 49 50 51 52 54 57 61 62 72 73
6 7 12 23 25 26 28 32 35 36 39 40 41
102
57 61 62 72 73 80 83 84 85 88 89 91 100
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
PP1V5_S0GPU_ISNS_R
PP1V8_S0GPU_ISNS_R
T29 Rails
PP3V3_T29
7 87 103
VOLTAGE=1.8V
MAKE_BASE=TRUE
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
88 35 34 33 25 19 16 7
6 7 72 75 79 80 82 84
7 12 15
PP1V2_ENET
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
84 85 88 89 91 100 102
6 7 72 75 79 80 82 84
PP1V0_S0GPU
PP1V0_S0GPU
PP1V0_S0GPU
PP1V0_S0GPU
PP1V0_S0GPU
PP1V0_S0GPU
PP1V0_S0GPU
7 12 15 65
PP1V5_S3_CPU_VCCDQ
6 7 72 75 79 80 82 84
VOLTAGE=1.0V
MAKE_BASE=TRUE
VOLTAGE=0.9V
MAKE_BASE=TRUE
PPVCCSA_S0_CPU
6 7 72 75 79 80 82 84
PP1V0_S0GPU_ISNS_R
PP1V0_S0GPU
PP1V0_S0GPU
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCORE_S0_AXG
6 7 72 75 79 80 82 84
VOLTAGE=1.0V
MAKE_BASE=TRUE
VOLTAGE=1.1V
MAKE_BASE=TRUE
PPVCORE_S0_AXG
6 7 72 75 79 80 82 84
PP1V0_S0GPU_ISNS_R
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
PPVCORE_S0_CPU
6 7 72 75 79 80 82 84
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
Chipset Rails
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
13 14 23 35 39 45 68 70 73 102
13
35
13
75
13
6 7 72 75 79 80 82 84
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
PP3V3_ENET
PP3V3_ENET
PP3V3_ENET
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
10 12
105
10 12
105
10 12
105
23
10 12
77 76
10 12
105
6 7 49 75 82
PP1V5_S0GPU_ISNS_R
7 9 10 103 87 7
12 13 14 23 35 39 45 68 70 73 102 104 105
7 9
104
7 9
104
7 9
104
6 7 49 75 82
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
7 23 71
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
7 26 28 29 67
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 23 71
PP1V05_SUS
7 26 28 29 67
PPVCORE_GPU
PP3V3_S0GPU
PP3V3_S0GPU
VOLTAGE=1.05V
MAKE_BASE=TRUE
51 52 54 57 61 62 72 73 80 83 84 85 88
6 7 12 23 25 26 28 32 35
36 39 40 41 46 48 49 50
89 91 100 102
6
48 49 50 51 52 54 57 61 62
887 12 23 25 26 28 32 35 36 39 40 41 46
4972 73 80 83 84 85 88 89 91 100 102
6
7 12 23 25 26 28 32 35 36 39 40 41 46 48
50 51 52 54 57 61 62 72 73 80 83 84 85
896 91 100 102
7
83 84 85 88 89 91 100 102
1212 23 25 26 28 32 35 36 39 40 41 46
6 48 49 50 51 52 54 57 61 62 72 73 80
7
23 25 26 28 32 35 36 39 40 41 46 48 49
50 51 52 54 57 61 62 72
73 80 83 84 85 88 89 91
100 6102 48 49 50 51 52 54 57 61 62 72 73
88 7 12 23 25 26 28 32 35 36 39 40 41 46
49 80 83 84 85 88 89 91 100 102
6 7
12 23 25 26 28 32 35 36 39 40 41 46 48
50 51 52 54 57 61 62 72 73 80 83 84 85
89 91 100 102
84 85 88 89 14 12 10 7
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
91 100 102
6
48 49 50 51 52 54 57 61 62 72
887 12 23 25 26 28 32 35 36 39 40 41 46
4973 80 83 84 85 88 89 91 100 102
6
7 12 23 25 26 28 32 35 36 39 40 41 46 48
50 51 52 54 57 61 62 72 73 80 83 84 85
89 91 100 102
73 71 36 25 7
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP1V05_SUS
PPVCORE_S0_CPU
80 83 84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
100 102 48 49 50 51 52 54 57 61 62 72 73
73 80 83 84 85 88 89 91
62 72
57 61 69 49 15 13 12 7
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
7 26 28 29 67
VOLTAGE=1.15V
MAKE_BASE=TRUE
6 7 71 88
7 72 104
7 26 28 29 67
PPVCORE_GPU
PPVCORE_GPU
7 16 20 22 25 32 41 57 71
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
6 7 30 67
"GPU" Rails
7 16 20 22 25 32 41 57 71
7 16 17 18 19 20 22 46 71 72 73
PP3V3_S3
PPVTTDDR_S3
7 10 13 15 29 73
104
7 16 20 22 25 32 41 57 71
PP1V2_S0
PP1V05_SUS
7 10 13 15 29 73
104
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
7 16 20 22 25 32 41 57 71
PP1V2_S0
7 16 17 18 19 20 22 46 71
72 73
71 23 7
7 16 17 18 19 20 22 46 71 72 73
PP1V5_S3RS0_CPUDDR
PP1V5_S3RS0_CPUDDR
PP0V75_S0_DDRVTT
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 16 17 18 19 20 22 46 71 72 73
7 10 13 15 29 73
104
MIN_LINE_WIDTH=2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
7 38 39
7 16 17 18 19 20 22 46 71 72 73
PP1V2_S0
7 72 100 104
VOLTAGE=0.75V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=3.3V
7 16 17 18 19 20 22 46
71 72 73
7 16 17 18 19 20 22 46 71 72 73
7 72 100 104
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP1V5_S0
PP1V5_S0
PP1V5_S0
7 16 17 18 19 20 22 46 71 72 73
7 26 28 29 67 72
VOLTAGE=1.5V
MAKE_BASE=TRUE
6 7 39 40
PP1V5_S0
7 66 104
7 26 28 29 67 72
PP1V5_S3RS0_CPUDDR
6 7 39 40
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0
VOLTAGE=12.8V
MAKE_BASE=TRUE
PP1V5_S0
PP1V5_S0
7 26 28 29 67 72
PP1V5_S3RS0
1.5V/1.05V Rails
6 7 46 53 54 72 20 16 7
71 57 41 32 25 22
7 26 28 29 67 72
6 7 39 40
6 7 46 53 54 72
6 7 46 53 54 72
7 26 28 29 67 72
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 12 14
PP1V0_FW_FWPHY
MAKE_BASE=TRUE
VOLTAGE=3.3V
7 22 72
PP1V5_S3RS0
VOLTAGE=1.8V
MAKE_BASE=TRUE
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_SUS
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
6 7 14 20 25 71 72 88 102
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
39 38 7
PP3V3_S0
105 104 87
54 52 47 41 22 8 7 6
73 70 69 68 65
PP3V3_S3_ISNS_R
54 66 72 103 104
100 91 89 88 85 84 7
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
102
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3_ISNS_R
PP3V3_FW_FWPHY
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
7 54 66 72 103 104
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
104 66 7
PP3V3_S3
6 7 14 20 25 71 72 88 102
PPVP_FW
PPVP_FW
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
PP3V3_S3
PP3V3_S3
VOLTAGE=5V
MAKE_BASE=TRUE
7 54 66 72 103 104
104 72 7
7 54 66 72 103 104
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
6 7 14 20 25 71 72 88 102
PPVP_FW
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
40 39 38 7
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3RS0
6 7 14 20 25 71 72 88 102
"FW" (FireWire) Rails
PPVP_FW
7 26 28 29 67 72
VOLTAGE=1.5V
MAKE_BASE=TRUE
6 7 14 20 25 71 72 88 102
PP1V8_S0_CPU_VCCPLL_R
6 7 25 42 44 45 46 47 48 53 63 64 73 104
7 16 17 20 25
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP1V5_S3
PP1V5_S3
6 7 14 20 25 71 72 88 102
104 100 72 7
6 7 17 19 20 22 23 24
25 29 46 48 56 14 12 7
71 72 73 83 86
916 100 102 104
7
1717 19 20 22 23 24 25 29 46 48 56 71
6 72 73 83 86 91 100 102 104
83 86 91
7
19 20 22 23 24 25 29 46 48 56 71 72 73
100 102 104
91 100 102 104
6 7 17 19 20 40 39 7 6
22 23 24 25 29 46 48 56 71 72 73 83 86
PP3V3_SUS
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
24 25 29 46 48 56 71
102 104
24 25 29 46 48 56 71
102 104
24 25 29 46 48 56 71
102 104
PP1V8_S0
PP3V3_S5_ISNS_R
PP3V3_SUS
PP1V8_S0
102 88 72 71 25 20 14 7 6
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
PP3V3_S5_ISNS_R
6 7 25 42 44 45 46 47 48 53 63 64 73 104
PPVRTC_G3H
PP3V3_S5_ISNS_R
VOLTAGE=3.42V
MAKE_BASE=TRUE
PPVRTC_G3H
66 7
104
6 7 49 63 64
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V3_S4
PP3V3_S4
PP1V8_S0
6 7 17 19 20 22 23
72 73 83 86 91 100
6 7 17 19 20 22 23
72 73 83 86 91 100
6 7 17 19 20 22 23
72 73 83 86 91 100
PP3V3_S4
6 7 49 63 64
72 71 46 22 20 19 18 17 16 7
73
PP3V42_G3H
72 54 53 46 7 6
7 50 82 87
PPDCIN_G3H
PPDCIN_G3H
64 63 53
45 44 42 25 7 6
48 47 46
104 73
PP3V3_S4
7 50 82 87
PPDCIN_G3H
2
72 67 29 28 26 7
29 46 48 56 71 72 73 83 86 91 100 102 104

6 7 17 19 20 22 23 24 25
102 88 72 71 25 20 14 7 6
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
7 50 82 87
VOLTAGE=12.8V
MAKE_BASE=TRUE
64 63 49 7 6
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
7 50 65 67 68 69 70
VOLTAGE=5V
MAKE_BASE=TRUE
DDR Rails
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
6 7 8 35 39 49 50 63 64 90
PP3V3_S5
6 7 8 35 39 49 50 63 64 90
66 50 7
PP3V3_S5
6 7 8 35 39 49 50
63 64 90
6 7 8 35 39 49 50 63 64 90
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
5
3.3V/1.8V Rails
BRANCH
PAGE
8 OF 132
SHEET
7 OF 105
91 88 87 82 74 8
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
8 74 82 87 88 91
Top GPU Center

TM Hole
88 8
TP_LVDS_MUX_SEL_EG
EG_RESET_L
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0980
88 18 8
LVDS_IG_BKL_ON
88 18 8
LVDS_IG_PANEL_PWR
GFXIMVP_VID<0..6>
94 18 8
NC_LVDS_IG_A_DATAP<3>
TP_LVDS_MUX_SEL_EG
8 88
EG_RESET_L
8 74 88
LVDS_IG_BKL_ON
8 18 88
LVDS_IG_PANEL_PWR
8 18 88
94 18 8
NC_LVDS_IG_A_DATAN<3>
MEMVTT_EN
8 29 67
8 18 94
8 18 94
NC_LVDS_IG_B_DATAP<3>
8 18
NC_LVDS_IG_B_DATAN<3>
8 18
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LCD_BKLT_EN
8 88 90
9
NC_PEG_D2R_P<15..12>
NC_PEG_D2R_N<15..12>
=PEG_D2R_P<15..12>
MAKE_BASE=TRUE
18 8 6
PEX_CLKREQ_L
PEG_CLKREQ_L
88 16 8
TP_LVDS_IG_B_CLKP
6 8 18
TP_LVDS_IG_B_CLKN
18 8 6
TP_LVDS_IG_BKL_PWM
TP_LVDS_IG_B_CLKN
6 8 18
TP_LVDS_IG_BKL_PWM
6 8 18
MAKE_BASE=TRUE
=PEG_R2D_C_N<15..12>
NC_PEG_R2D_C_N<15..12>
TP_LVDS_IG_B_CLKP
18 8 6
MAKE_BASE=TRUE
8 80 88
PEG_CLKREQ_L
=PEG_R2D_C_P<15..12>
NC_PEG_R2D_C_P<15..12>
PEX_CLKREQ_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
=PEG_D2R_N<15..12>
MAKE_BASE=TRUE
88 80 8
NO_TEST=TRUE
18 8
MAKE_BASE=TRUE
Bottom GPU Left

TM Hole
NC_GPU_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
Unused PEG lanes
ZT0987
MAKE_BASE=TRUE
MAKE_BASE=TRUE
8 16 88
MAKE_BASE=TRUE
SH0936
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0920
1
61
SM
1
ZT0915
GND
GND
GND
GND
SM
Frame Holes
GND_CHASSIS_AUDIO_JACK
GND
92 74
PEG_D2R_N<7..0>
92 74
SH0910
3R2P5
SM
8 24 32
USB_EXTC_OC_L
8 24 43
USB_EXCARD_N
8 24 32 100
USB_EXCARD_P
8 24 32 100
USB_EXTC_OC_L
43 24 8
=PEG_D2R_N<7..0>
=PEG_R2D_C_P<7..0>
100 32 24 8
USB_EXCARD_N
=PEG_R2D_C_N<7..0>
100 32 24 8
USB_EXCARD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
92 74
PEG_R2D_C_P<7..0>
92 74
PEG_R2D_C_N<7..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SM
DP_IG_AUX_CH_P
94 84 17 8
DP_IG_AUX_CH_P
8 17 84 94
DP_IG_AUX_CH_N
8 17 84 94
DP_IG_DDC_CLK
8 17 80 84
DP_IG_DDC_DATA
8 17 80 84
MAKE_BASE=TRUE
DP_IG_AUX_CH_N
94 84 17 8
1
39 19 8
ZT0960
FW_PLUG_DET_L
FW_PLUG_DET_L
8 19 39
3R2P5
DP_IG_DDC_CLK
84 80 17 8
39 38 8
FW643_WAKE_L
8 38 39
MAKE_BASE=TRUE
36
TP_SDCONN_DATA<0..7>
36 8
TP_SDCONN_CLK
36 8
TP_SDCONN_CMD
SDCONN_DATA<0..7>
8 36
8 36
SM
TP_SDCONN_DETECT_L
36 8
TP_SDCONN_WP
36 8
TP_ENET_CR_PWREN
TP_SDCONN_DETECT_L
NC_ISNS_P3V3S0MPCH_N
NC_ISNS_P3V3S0MPCH_P
NC_ISNS_P3V3S0MPCH_N
NC_ISNS_P3V3S0MPCH_P
NC_ISNS_PVTTS0PCH_N
NC_ISNS_PVTTS0PCH_P
MAKE_BASE=TRUE
95 33
PCIE_T29_D2R_N<3..0>
95 33
PCIE_T29_R2D_C_P<3..0>
95 33
36 8
=PEG_D2R_N<11..8>
=PEG_R2D_C_P<11..8>
PCIE_T29_R2D_C_N<3..0>
NC_ISNS_PVTTS0PCH_N
NC_ISNS_PVTTS0PCH_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_ISNS_P1V05S0PCH_P
MAKE_BASE=TRUE
=PEG_D2R_P<11..8>
MAKE_BASE=TRUE
TP_SDCONN_CLK
TP_SDCONN_CMD
MAKE_BASE=TRUE
3R2P5
PCIE_T29_D2R_P<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_ISNS_P1V05S0PCH_N
8 17 84
T29 Signals
95 33
SH0914
NC_ISNS_P1V05S0PCH_P
MAKE_BASE=TRUE
DP_IG_HPD
Unused SD card signals
ZT0940
MAKE_BASE=TRUE
SM
DP_IG_HPD
84 17 8
SM
NC_ISNS_P1V05S0PCH_N
MAKE_BASE=TRUE
DP_IG_DDC_DATA
84 80 17 8
SH0912
MAKE_BASE=TRUE
FW643_WAKE_L
MAKE_BASE=TRUE
SH0913
Rev. A NCs
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ZT0971
EXCARD_OC_L
MAKE_BASE=TRUE
=PEG_D2R_P<7..0>
MAKE_BASE=TRUE
ZT0932
EXCARD_OC_L
32 24 8
PEG_D2R_P<7..0>
GND
SH0911
USB Hub Aliases
GPU signals
GND
MAKE_BASE=TRUE
3R2P5
8 92
NO_TEST=TRUE
MAKE_BASE=TRUE
MEMVTT_EN
MAKE_BASE=TRUE
18 8
LCD_BKLT_EN
90 88 8
Bottom CPU Left

TM Hole
3R2P5
NC_GPU_XTALOUT
MAKE_BASE=TRUE
67 29 8
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
MAKE_BASE=TRUE
=PEG_R2D_C_N<11..8>
MAKE_BASE=TRUE
8 36
MAKE_BASE=TRUE
TP_SDCONN_WP
8 36
TP_ENET_CR_PWREN
8 36
Unused T29 Ports
MAKE_BASE=TRUE
ZT0970
3R2P5
SH0923
97
T29_D2R_P<2..3>
97
T29_D2R_N<2..3>
NC_T29_D2RP<2..3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AUDIO ALIASES
SH0924
97
T29_R2D_C_P<2..3>
97
T29_R2D_C_N<2..3>
ZT0934
SM
ZT0931
XW0900
1
STDOFF-4.0OD3.35H-TH STDOFF-4.0OD3.35H-TH
87 73 70 69 68 65 54 52 47 41 22 7 6
105 104
PP5V_S0_AUDIO
ZT0988
T29_A_BIAS_R
SH0917
2.0DIA-TALL-EMI-MLB-M97-M98
ZT0989
XW0902
SM
STDOFF-4.5OD.98H-1.1-3.48-TH
T29_LSEO_LSOE3
T29_LSEO_LSOE3
8 33
T29_LSEO_LSOE2
8 33
MAKE_BASE=TRUE
NO_TEST=TRUE
T29_LSEO_LSOE2
33 8
T29_A_BIAS_R
88 33 23 19 8
JTAG_ISP_TCK
88 33 19 8
JTAG_ISP_TDI
88 18 8
LVDS_IG_PANEL_PWR
JTAG_ISP_TCK
8 19 23 33 88
JTAG_ISP_TCK
8 19 23 33 88
JTAG_ISP_TDI
8 19 33 88
JTAG_ISP_TDO
8 19 33 88
MAKE_BASE=TRUE
1
GND
SH0919
R0902
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.11MM
VOLTAGE=0V
JTAG_ISP_TDO
5%
1/16W
MF-LF
2 402
86 8
86 8
T29_A_BIAS_R
SM
PP3V3_S3
SH0931
ZT0958
R0915
SM
1
1
SH0922
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
USB_T29A_P
51
5%
1/20W
MF
201
24 94
T29_A_BIAS_R
24 94
85 6
DP_A_BIAS_N_2
1
SH0941
STDOFF-4.0OD1.85H-SM
85 6
DP_A_BIAS_P_2
SH0901
1
SM
SIGNAL_MODEL=EMPTY 1
C0910
Heat spreader mounting boss for PCH
0.01UF
10%
2 10V
X5R
201
Signal Aliases
10%
10V
2 X5R
201
DRAWING NUMBER
Apple Inc.
T29BST:N
SH0942
SH0943
1
R0950
90 64 63 50 49 39 35 7 6
PPBUS_G3H
5%
1/8W
MF-LF
805
C0908
PP15V_T29
7 35 86

SIZE
D
REVISION
SIGNAL_MODEL=EMPTY
1
PAGE TITLE
C0911
0.01UF
10%
10V
2 X5R
201
DP_A_BIAS_N_0
C0905
0.01UF
85 6
SYNC_MASTER=K17_MLB
SM
SIGNAL_MODEL=EMPTY
DP_A_BIAS_P_0
0.01UF
SM
85 6
SH0935
SM
0.01UF
10%
10V
2 X5R
201
DP_A_BIAS caps
SH0940
SH0903
6 85
C0904
10%
Heat spreader mounting boss for T29 router
SH0933
10%
2 10V
X5R
201
SM
SM
T29_A_BIAS_R2D_N1
0.01UF
2 10V
X5R SIGNAL_=EMPTY
SH0900
DP_A_BIAS caps
86
C0907
201
51
5%
1/20W
MF
201
T29_A_BIAS_D2R_N1
1
SM
0.01UF
R0927
T29_A_BIAS_R
SH0934
C0903
10% SIGNAL_MODEL=EMPTY
10V
2 X5R
201
SIGNAL_MODEL=EMPTY
86 8
SH0932
6 85
R0924
86 8
201
SM
SIGNAL_MODEL=EMPTY
0.01UF
2 10V
X5R
R0916
USB_T29A_N
T29_A_BIAS_R2D_P1
86
C0906
10K
SM
SH0902
51
5%
1/20W
MF
201
T29_A_BIAS_D2R_P1
1
6 7 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
4.0OD1.65H-M1.6X0.35
5%
1/20W
MF
201
51
Unused USB ports
SH0921
4.0OD1.65H-M1.6X0.35
0.01UF
R0926
ZT0957
6 85
C0902
10%
2 10V
X5R SIGNAL_MODEL=EMPTY
201
SIGNAL_MODEL=EMPTY
SM
Bosses for Flex Protector Bracket
T29_A_BIAS_R
T29_A_BIAS caps
R0923
MAKE_BASE=TRUE
100K
SM
SH0930
88 33 19 8
T29_A_BIAS_R2D_N0
SIGNAL_MODEL=EMPTY
SM
1
0.01UF
2 10V
X5R
201
5%
1/20W
MF
201
MAKE_BASE=TRUE
51
T29 / GMUX JTAG Signals
60
6 85
C0901
R0922
86 8
VOLTAGE=5V
Digital Ground
SIGNAL_MODEL=EMPTY
T29_LSEO_LSOE2
MAKE_BASE=TRUE
NO_TEST=TRUE
SH0918
T29_A_BIAS_R2D_P0
5%
1/20W
MF
201
60
VOLTAGE=5V
PP5V_S0_AUDIO_AMP_L
51
NO_TEST=TRUE
SM
ZT0991
T29_LSEO_LSOE3
33 8
PP5V_S0_AUDIO_AMP_R
XW0901
SM
STDOFF-4.5OD.98H-1.1-3.48-TH
86 8
33
57
VOLTAGE=5V
SM
SH0916
STDOFF-4.5OD.98H-1.1-3.48-TH
R0921
NO_TEST=TRUE
SM
PP5V_S0
SIGNAL_MODEL=EMPTY
33
NC_T29_R2D_CN<2..3>
MAKE_BASE=TRUE
T29_A_BIAS caps
33
NO_TEST=TRUE
NC_T29_R2D_CP<2..3>
MAKE_BASE=TRUE
33
NO_TEST=TRUE
NC_T29_D2RN<2..3>
MAKE_BASE=TRUE
SM
CPUIMVP_VID<0..6>
MAKE_BASE=TRUE
GFX_VID<0..6>
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
Left CPU
TM Hole
TP_CPU_VTT_SELECT
92 8
MAKE_BASE=TRUE
92
MAKE_BASE=TRUE
ZT0930
STDOFF-4.5OD.98H-1.1-3.48-TH
CPU_VID<0..6>
92
MAKE_BASE=TRUE
88 74 8
MAKE_BASE=TRUE
ZT0983
CPU signals
ZT0981
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
Right CPU
ZT0984 TM Hole
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0982
4
GMUX ALIASES
Thermal Module Holes

Bottom GPU Right
TM Hole
BRANCH
PAGE
9 OF 132
SHEET
8 OF 105
PP1V05_S0
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
R1010
24.9
1%
1/16W
MF-LF
2 402
IN
92 17
IN
92 17 6
IN
92 17 6
IN
92 17
IN
92 17
IN
92 17
OUT
92 17
OUT
92 17 6
OUT
92 17
OUT
92 17 6
OUT
92 17
OUT
92 17 6
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
OUT
92 17
IN
92 17
IN
92 17
92 17
92 17
FDI_TX_0*
FDI_TX_1*
FDI_TX_2*
FDI_TX_3*
FDI_TX_4*
FDI_TX_5*
FDI_TX_6*
FDI_TX_7*
FDI_TX_0
FDI_TX_1
FDI_TX_2
FDI_TX_3
FDI_TX_4
FDI_TX_5
FDI_TX_6
FDI_TX_7
FDI0_FSYNC
FDI1_FSYNC
IN
FDI_LSYNC<0>
FDI_LSYNC<1>
AB7
AB3
FDI0_LSYNC
FDI1_LSYNC
TP_EDP_TX_N<0>
TP_EDP_TX_N<1>
TP_EDP_TX_N<2>
TP_EDP_TX_N<3>
AG2
AF1
AE6
AG6
R1030
24.9
EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*
TP_EDP_TX_P<0>
TP_EDP_TX_P<1>
TP_EDP_TX_P<2>
TP_EDP_TX_P<3>
AG4
AF3
AF7
AG8
EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3
TP_EDP_AUX_P
TP_EDP_AUX_N
AE4
AE2
EDP_AUX
EDP_AUX*
CPU_EDP_COMP
AB1
AC2
EDP_ICOMPO
EDP_COMPIO
AE8
EDP_HPD
PLACE_NEAR=U1000.AB1:12.7mm
CPU_EDP_HPD
10K PU disables eDP HPD
CPU_CFG<4> should be pulled down to enable EDP
92 23 9
92 23 9
92 23 9
92 23 9
92 23 9
CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>
92 23 9
92 23 9
92 23 9
92 23 9
NOSTUFF 1
EDP
NOSTUFF1
NOSTUFF1
NOSTUFF1
NOSTUFF1
NOSTUFF1
R1044
R1046
R1047
R1040
R1041
R1043
1K
1K
1K
1K
1K
1K
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
92 23 9
92 23 9
CPU_PEG_COMP
92 23 9
92 23 9
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
F23
H23
H21
H19
J20
G18
K17
F15
H15
H13
H11
J12
E8
G10
J8
F7
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
NC_PEG_D2R_N<12>
NC_PEG_D2R_N<13>
NC_PEG_D2R_N<14>
NC_PEG_D2R_N<15>
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
G22
K23
K21
F19
K19
H17
K15
G14
J16
K13
F11
K11
F9
H9
H7
G6
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
NC_PEG_D2R_P<12>
NC_PEG_D2R_P<13>
NC_PEG_D2R_P<14>
NC_PEG_D2R_P<15>
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
A22
B23
C18
D21
B19
E20
A14
D17
B15
E16
D13
A10
B11
D9
B7
E12
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
NC_PEG_R2D_C_N<12>
NC_PEG_R2D_C_N<13>
NC_PEG_R2D_C_N<14>
NC_PEG_R2D_C_N<15>
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
C22
D23
A18
B21
D19
F21
C14
B17
D15
F17
B13
C10
D11
B9
D7
F13
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
NC_PEG_R2D_C_P<12>
NC_PEG_R2D_C_P<13>
NC_PEG_R2D_C_P<14>
NC_PEG_R2D_C_P<15>
IN
92 23 9
IN
92 23 9
IN
92 23 9
IN
92 23
IN
92 23
IN
92 23
IN
92 23
IN
23
IN
23
IN
23
IN
23
IN
92 23 9
IN
92 23
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
B57
D57
B55
A54
A58
D55
C56
E54
J54
G56
F55
K55
F57
E58
H57
H55
D53
K57
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTE:
Intel is investigating processor driven VREF_DQ generation.
This connection is to support the same.
NOSTUFF
R1021
30 26
PP0V75_S3_MEM_VREFDQ_A
R1020
1%
1/16W
MF-LF
402
NOSTUFF
R1023
30 28
PP0V75_S3_MEM_VREFDQ_B
0
5%
1/16W
MF-LF
402
2
1
R1022
1K
1%
1/16W
MF-LF
402
AD5 RSVD_25
AH5 RSVD_26
AJ6 RSVD_27
NC
NC
G52 RSVD_38
G64 RSVD_39
NC
AJ10 RSVD_40
BI
CPU_THERMD_P
CPU_THERMD_N
BE6
AA4
AC4
AC6
RSVD_53
RSVD_54
RSVD_55
RSVD_56
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_61
RSVD_62
RSVD_63
RSVD_64
RSVD_65
RSVD_66
RSVD_67
RSVD_68
F5
K9
H5
L10
G4
K7
K5
M9
L6
J2
L2
P7
M5
J4
L4
N6
RSVD_69
RSVD_70
RSVD_71
RSVD_72
G48
K49
H49
J50
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_84
RSVD_85
RSVD_86
RSVD_87
RSVD_88
RSVD_89
RSVD_90
RSVD_91
RSVD_92
RSVD_93
RSVD_94
RSVD_95
RSVD_96
RSVD_97
AY13
BB13
BB15
AY15
AW14
BD13
BA16
BE16
BD15
BC14
BF19
BH19
BF21
BH21
BF23
BH23
BF25
BH25
BJ22
BG22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RSVD_28 (DDR_VREF0)
RSVD_29 (DDR_VREF1)
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
D49 RSVD_35
B53 RSVD_36
NC
NC
NC
NC
NC
BI
BF3
BG4
BD19
AY45
AY41
BG62
BB43
NC
NC
NC
100 51
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
NC
NC
NC
NC
NC
NC
NC
100 51
CFG_5 (IPU) RESERVED

CFG_6 (IPU)
CFG_7 (IPU)
OMIT
CFG_8 (IPU)
CFG_9 (IPU)
CFG_10 (IPU)
CFG_11 (IPU)
CFG_12 (IPU)
CFG_13 (IPU)
CFG_14 (IPU)
CFG_15 (IPU)
CFG_16 (IPU)
CFG_17 (IPU)
AW50 RSVD_22
BB57 RSVD_23
BF63 RSVD_24
NC
NC
NC
NC
NC
1K
BB17
AY17
BD29
BD33
BC30
BE32
AW42
BA48
BC42
AW46
BG26
BB25
BG34
BH35
BJ34
BF35
BF41
BH43
BJ42
BF43
CFG_0 (IPU) U1000

CFG_1 (IPU)SANDY-BRIDGE
CFG_2 (IPU) MOBILE-REV1
CFG_3 (IPU)
BGA
CFG_4 (IPU) (5 OF 11)
NC
NC
NC
CPU_MEM_VREFDQ_A
CPU_MEM_VREFDQ_B
5%
1/16W
MF-LF
402
CPU_CFG<16>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>
R1042
R1045
92
92 23 9
DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3
FDI_INT
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*
AD9
IN
BGA
(SYM 1 OF 11)
OMIT
FDI_INT
AC8
AA2
FDI_FSYNC<0>
FDI_FSYNC<1>
10K
W6
W10
Y9
AA10
U2
W4
V3
AA6
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
PP1V05_S0
R1031
V7
W8
AA8
AC10
U4
W2
V1
Y5
PEG_ICOMPI G2
PEG_ICOMPO H1
PEG_RCOMPO F3
SANDY-BRIDGE
MOBILE-REV1
DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3
IN
102
68 45 39 35
13 12 10 9 7
23 14
73 70
105 104
N2
R2
P3
T5
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
OUT
92 17
N4
R4
P1
U6
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
OUT
92 17
N8
T9
R6
U8
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
OUT
92 17 6
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
U1000
DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
PCI EXPRESS BASED INTERFACE SIGNALS
IN
92 17
N10
R10
R8
U10
DMI
92 17 6
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
IN
EMBEDDED DISPLAY PORT
92 17 6
RSVD_41
RSVD_42
RSVD_43
RSVD_44
C52 RSVD_45
D3
C4
C24
D25
B25
RSVD_46
RSVD_47
RSVD_48
RSVD_49
RSVD_50
K47 RSVD_51 (THERMDA)

H47 RSVD_52 (THERMDC)
NOSTUFF1
R1049
1K
5%
1/16W
MF-LF
402
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
These can be Placed close to J2500 and Only for debug access
DRAWING NUMBER
Apple Inc.
FOR SANDYBRIDGE PROCESSOR
SIZE
D
REVISION
CFG
CFG
CFG
CFG
CFG
[7] :PEG DEFER TRAINING

[6:5] :PCIE BIFURCATION
[4] :eDP ENABLE/DISABLE
[3] :PCIE x4 LANE REVERSAL
[2] :PCIE x16 LANE REVERSAL
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB

0 = WAIT FOR BIOS
11 = 1 X16 (DEFAULT)
10 = 2 X8
01 = RSVD
00 = X8, X4, X4
1 = DISABLED
0 = ENABLED
1 = NORMAL OPERATION
0 = LANES REVERSED
1 = NORMAL OPERATION
0 = LANES REVERSED

BRANCH
PAGE
10 OF 132
SHEET
9 OF 105
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
PP1V05_S0
7 12 14
R1140
PP1V05_S0
1
R1100
1
1K
R1101
5%
1/20W
MF
201 2
68
5%
1/16W
MF-LF
NOSTUFF
1
R1104
R1102
BGA
(2 OF 11)
OMIT
5%
1/20W
MF
5%
1/16W
MF-LF
402
2 201
2 402
NC
92 17
AH9 PROC_SELECT*
CPU_PROC_SEL_L
OUT
R1103
CPU_PROCHOT_L
CPU_CATERR_L
H53 CATERR*
92 45 19
BI
CPU_PECI
F53 PECI
CPU_PROCHOT_R_L
H51 PROCHOT*
OUT
PM_THRMTRIP_L
F51 THERMTRIP*
R11261
75
1%
1/16W
MF-LF
402 2
25 23
IN
92 19
43.2 1
1%
1/16W
MF-LF
402
92 17
IN
PM_SYNC
K53 PM_SYNC
92 23 19
IN
CPU_PWRGD
C60 UNCOREPWRGOOD
PP1V5_S3RS0_CPUDDR
29
BE24 SM_DRAMRST*
PLACE_NEAR=R1121.2:1mm
BJ44 SM_VREF
CPU_DDR_VREF
R1120
1%
1/16W
MF-LF
402 2
IN
R1121
2
PM_MEM_PWRGD
R1120 and R1121 are Intel recommended
130
BCLK D5
BCLK* C6
(IPD)
(IPU)
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
IN
16 92
IN
16 92
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
IN
16 92
IN
16 92
J62
H65
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
TCK J58
TMS H59
H63
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L
TDI K61
TDO K59
XDP_CPU_TDI
XDP_CPU_TDO
XDP_DBRESET_L
OUT
23 25 92
DBR* H61
(IPU) BPM_0*
(IPU) BPM_1*
(IPU) BPM_2*
(IPU) BPM_3*
(IPU) BPM_4*
(IPU) BPM_5*
(IPU) BPM_6*
(IPU) BPM_7*
C62
D61
E62
F63
D59
F61
F59
G60
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
OUT
23 92
IN
23 92
IN
23 92
IN
23 92
IN
23 92
IN
23 92
OUT
23 92
BI
23 92
BI
23 92
BI
23 92
BI
23 92
BI
23 92
BI
23 92
BI
23 92
BI
23 92
R1141
1K
1
1
1%
1/16W
values
MF-LF
402
PLACE_NEAR=U1000.AY25:51.562mm
R1112
2
104 73 29 15 13 10 7
BJ46 SM_RCOMP_0
BG46 SM_RCOMP_1
BF45 SM_RCOMP_2
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
200
Unused eDP CLK
(IPU) TRST*
AY25 SM_DRAMPWROK
CPU_MEM_RESET_L
OUT
DPLL_REF_CLK
DPLL_REF_CLK_L
BCLK_ITP K63
BCLK_ITP* K65
(IPU)
K51 RESET*
PLT_RESET_LS1V1_L
PM_MEM_PWRGD_R
92 29 17
DPLL_REF_CLK AJ4
DPLL_REF_CLK* AJ2
(IPU) PREQ*
R1125
PLT_RST_CPU_BUF_L
104 73 29 15 13 10 7
5%
1/16W
MF-LF
2 402
(IPU) PRDY*
5%
1/16W
MF-LF
402
PP1V05_S0
OUT
JTAG & BPM
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
BI
92
PWR MGMT
92 68 46
56
B59 PROC_DETECT*
THERMAL
1K
SANDY-BRIDGE
MOBILE-REV1
1K
51
NOSTUFF
CLOCKS
NOSTUFF
U1000
DDR3 MISC
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
R1113
R1114
R1111
140
25.5
200
10K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
PLACE_NEAR=U1000.BF45:12.7mm
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
PLACE_NEAR=U1800.AY11:157mm
PP1V5_S3RS0_CPUDDR
R11301
PLACE_NEAR=U1000.BG46:12.7mm
NOSTUFF
100
PLACE_NEAR=U1000.BJ44:2.54mm
1%
1/16W
MF-LF
402
NOSTUFF
R11311
PLACE_NEAR=U1000.BJ44:2.54mm 100
1%
1/16W
MF-LF
402
C1130
0.1UF
10%
NOSTUFF
2 16V
X5R
402
A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
11 OF 132
SHEET
10 OF 105
U1000
SANDY-BRIDGE
MOBILE-REV1
BGA
(SYM 3 OF 11)
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
93 27
BI
93 27
BI
93 27
BI
93 27
BI
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27 26
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 26
OUT
93 26
OUT
93 26
OUT
93 26
OUT
93 26
OUT
93 26
OUT
AL6
AL8
AP7
AM5
AK7
AL10
AN10
AM9
AR10
AR8
AV7
AY5
AT5
AR6
AW6
AT9
BA6
BA8
BG6
AY9
AW8
BB7
BC8
BE4
AW12
AV11
BB11
BA12
BE8
BA10
BD11
BE12
BB49
AY49
BE52
BD51
BD49
BE48
BA52
AY51
BC54
AY53
AW54
AY55
BD53
BB53
BE56
BA56
BD57
BF61
BA60
BB61
BE60
BD63
BB59
BC58
AW58
AY59
AL60
AP61
AW60
AY57
AN60
AR60
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
BA36
BC38
BB19
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
BE44
BE36
BA44
OMIT
BGA
(SYM 4 OF 11)
SA_CK_0 BB31
SA_CK_0* BA32
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
SA_CKE_0 BC18
MEM_A_CKE<0>
SA_CK_1 AW34
SA_CK_1* AY33
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
SA_CKE_1 BD17
MEM_A_CKE<1>
SA_CS_0* BD41
SA_CS_1* BD45
SA_ODT_0 BB41
SA_ODT_1 BC46
MEMORY CHANNEL A
BI
93 27
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
U1000
SANDY-BRIDGE
MOBILE-REV1
93 27
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
AN8
AU6
BC6
BD9
BC50
BB55
BD59
AU60
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AN6
AU8
BD5
BC10
BB51
BD55
BD61
AV61
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
BD27
BA28
BB27
AW26
BB23
BA24
AY21
BD21
BC22
BB21
AW38
AW22
BA20
BB45
BE20
AW18
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
93 27
26 93
BI
OUT
OUT
93 27
BI
26 93
93 27
BI
OUT
26 93
93 27
BI
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
93 27
BI
93 27
BI
93 27
BI
OUT
OUT
26 93
26 93
BI
26 27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
BI
27 93
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
BI
BI
27 93
27 93
BI
27 93
BI
27 93
BI
27 93
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
27 93
BI
27 93
BI
27 93
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 28 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
OUT
26 93
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
93 27
BI
SA_BS_0
SA_BS_1
SA_BS_2
93 28
OUT
93 28
OUT
93 28
OUT
SA_CAS*
SA_RAS*
SA_WE*
93 28
OUT
93 28
OUT
93 28
OUT
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
AL4
AK3
AP3
AR2
AL2
AK1
AP1
AR4
AV3
AU4
BA4
BB1
AV1
AU2
BA2
BB3
BC2
BF7
BF11
BJ10
BC4
BH7
BH11
BG10
BJ14
BG14
BF17
BJ18
BF13
BH13
BH17
BG18
BH49
BF47
BH53
BG50
BF49
BH47
BF53
BJ50
BF55
BH55
BJ58
BH59
BJ54
BG54
BG58
BF59
BA64
BC62
AU62
AW64
BA62
BC64
AU64
AW62
AR64
AT65
AL64
AM65
AR62
AT63
AL62
AM63
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
BJ38
BD37
AY29
SB_BS_0
SB_BS_1
SB_BS_2
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
BH39
BG38
BF39
SB_CAS*
SB_RAS*
SB_WE*
OMIT
MEMORY CHANNEL B
SB_CK_0 BF33
SB_CK_0* BH33
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
28 93
OUT
28 93
SB_CKE_0 BD25
MEM_B_CKE<0>
OUT
28 93
SB_CK_1 BF37
SB_CK_1* BH37
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
28 93
OUT
28 93
SB_CKE_1 BJ26
MEM_B_CKE<1>
OUT
28 93
SB_CS_0* BE40
SB_CS_1* BH41
MEM_B_CS_L<0>
MEM_B_CS_L<1>
OUT
28 93
OUT
28 93
SB_ODT_0 BG42
SB_ODT_1 BH45
MEM_B_ODT<0>
MEM_B_ODT<1>
OUT
28 93
OUT
28 93
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
AN4
AW2
BH9
BF15
BF51
BH57
AY63
AN62
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
AN2
AW4
BF9
BH15
BH51
BF57
AY65
AN64
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
BF31
BH31
BB37
BC34
BF27
BB33
BH27
BG30
BH29
BF29
AY37
BJ30
AW30
BA40
BB29
BE28
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
BI
27 28 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 28 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
BI
27 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
OUT
28 93
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
12 OF 132
SHEET
11 OF 105
D
85 88 89 91 100 102
6 7 23 25 26 28 32 35 36 39 40 41 46 48
49 50 51 52 54 57 61 62 72 73 80 83 84
PP3V3_S0
105 69 49 14 12 7 6
PPVCORE_S0_CPU
For Future Compatibility
R1320
PPVCORE_S0_CPU
10K
65 15 12 7
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
PP1V05_S0
PLACE_NEAR=R1310.1:2.54mm
1
R1300
R1302
2
BI
130 PLACE_NEAR=U1000.A50:2.54mm
1%
1/16W
MF-LF
402
CPU_VIDSOUT
7 9 10 12 13 14 23 35 39 45 68 70 73
102 104 105
75
92 68
PP1V05_S0
5%
1/16W
MF-LF
402
PPVCCSA_S0_CPU
R1312
402 1/16W
0 1
CPU_VIDSCLK
402 1/16W
0 1
CPU_VIDALERT_L
402 1/16W
1%
1/16W
MF-LF
402
CPU_VIDSOUT_R
2 5% MF-LF
R1311
92 68
OUT
92 68
IN
CPU_VIDSCLK_R
2 5% MF-LF
R1310
PPVCORE_S0_CPU
PP1V05_S0
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
100
PLACE_NEAR=U1000.B47:50.8mm
1%
1/16W
MF-LF
402 2
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
NOSTUFF
R1362
R13641
R1366
100
1%
1/16W
MF-LF
402
1% NOSTUFF
1/16W
MF-LF
402
6 7 12 14
49 69 105
7 12 13 15 49
69
PLACE_SIDE=BOTTOM
PPVCCSA_S0_CPU
49.9
R1370
OUT
92 68
OUT
92 68
OUT
92 68
OUT
92 70
OUT
92 70
OUT
A50
D51
B51
49.9
NOSTUFF
PLACE_SIDE=BOTTOM
1%
1/20W
MF
201
R1368
100
1%
1/20W
MF
201
1%
1/16W
MF-LF
2 402
OUT
65
OUT
PLACE_NEAR=U1000.F49:50.8mm
92 68
7 12
15 65
NOSTUFF
100
PPVCORE_S0_CPU
PPVCORE_S0_AXG
7 12 13
15 49 69
PLACE_NEAR=U1000.AW10:50.8mm
R13601
PLACE_NEAR=U1000.B51:38mm
6 7 12 14 49 69 105
PPVCORE_S0_AXG
NOSTUFF
CPU_VIDALERT_L_R
2 5% MF-LF
43
W17
W15
W12
U17
U15
U12
T16
T14
T11
N18
N16
N14
M17
M15
M12
M11
L18
L14
AE10
AG10
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
B47
A46
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
F49
E50
AW10
AU10
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
AY19
AW20
TP_CPU_VDDQSENSE_P
TP_CPU_VDDQSENSE_N
PLACE_NEAR=U1000.E50:50.8mm
1 PLACE_SIDE=BOTTOM
R1367
100
65
1%
1/16W
MF-LF
402
OUT
K3
CPU_VCCSASENSE
NOSTUFF
TP_CPU_DIE_SENSE
F47
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
D47
C48
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
B49
A48
R1314
1 1
10K
5%
1/16W
MF-LF
402
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.A46:50.8mm
PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM
R1361
100
R1363
1%
1/16W
MF-LF
402 2
49.9
100
NOSTUFF
1%
1/16W
MF-LF
402
R13651
1%
1/20W
MF
201
R1371
49.9
NOSTUFF
NOSTUFF
2
2
1%
1/20W
MF
201
PLACE_SIDE=BOTTOM
NOSTUFF
R1313
10K
2 2
5%
1/16W
MF-LF
402
VCCSA_0
U1000
VCCIO_SEL
VCCSA_1 SANDY-BRIDGE
MOBILE-REV1 VCCDQ_0
VCCSA_2
BGA
VCCDQ_1
VCCSA_3
(9 OF 11)
VCCDQ_2
VCCSA_4
VCCDQ_3
VCCSA_5
OMIT
VCCSA_6
VCCPLL_0
VCCSA_7
VCCPLL_1
VCCSA_8
VCCPLL_2
VCCSA_9
VCCPQE_0
VCCSA_10
VCCPQE_1
VCCSA_11
VCCPQE_2
VCCSA_12
VCCPQE_3
VCCSA_13
VCCSA_14
VSS_NCTF_0
VCCSA_15
VSS_NCTF_1
VCCSA_16
VSS_NCTF_2
VCCSA_17
VSS_NCTF_3
VSS_NCTF_4
VIDSOUT
VSS_NCTF_5
VIDSCLK
VSS_NCTF_6
VIDALERT*
VSS_NCTF_7
VCCSA_VID_0
VSS_NCTF_8
VCCSA_VID_1 (IPU)
VSS_NCTF_9
VSS_NCTF_10
VCC_SENSE
VSS_NCTF_11
VSS_SENSE
VSS_NCTF_12
VAXG_SENSE
VSS_NCTF_13
VSSAXG_SENSE
VSS_NCTF_14
VSS_NCTF_15
VCCIO_SENSE
VSS_SENSE_VCCIO
DC_TEST_A4
DC_TEST_A62
VDDQ_SENSE
DC_TEST_A64
VSS_SENSE_VDDQ
DC_TEST_B3
VCCSA_SENSE
DC_TEST_B63
DC_TEST_B65
VCC_DIE_SENSE
DC_TEST_BF1
VCC_VAL_SENSE
DC_TEST_BF65
VSS_VAL_SENSE
DC_TEST_BG2
DC_TEST_BG64
VAXG_VAL_SENSE
DC_TEST_BH1
VSSAXG_VAL_SENSE
DC_TEST_BH3
DC_TEST_BH63
DC_TEST_BH65
DC_TEST_BJ2
DC_TEST_BJ4
DC_TEST_BJ62
DC_TEST_BJ64
DC_TEST_C2
DC_TEST_C64
DC_TEST_D1
DC_TEST_D65
AJ8
R46
R42
R40
R36
R34
R29
R27
R23
R21
N45
N43
N39
N37
N33
N30
N26
N24
N20
M46
M42
M40
M36
M34
M29
M27
M23
M21
L44
L40
L38
L34
L32
L28
L26
L22
K45
K43
K41
K37
K35
K31
K29
K25
J44
J40
J38
J34
J32
J28
J26
H45
H43
H41
H37
CPU_VCCIO_SEL
AV23
AT23
AP23
AL23
PP1V5_S3_CPU_VCCDQ
AK65
AK63
AK61
AV21
AT21
AP21
AL21
7 15
7 14
7 10 14
BJ60
BJ6
BH61
BH5
BE64
BE2
BD65
BD1
F65
F1
E64
E2
B61
B5
A60
A6
A4
A62
A64
B3
B63
B65
BF1
BF65
BG2
BG64
BH1
BH3
BH63
BH65
BJ2
BJ4
BJ62
BJ64
C2
C64
D1
D65
TP_DC_TEST_A4
TP_DC_TEST_A62
DC_TEST_B63_A64
DC_TEST_B3_C2
DC_TEST_B65_C64
TP_DC_TEST_BF1
TP_DC_TEST_BF65
DC_TEST_BH1_BG2
DC_TEST_BG64_BH65
DC_TEST_BH3_BJ2
DC_TEST_BJ64_BH63
TP_DC_TEST_BJ4
TP_DC_TEST_BJ62
TP_DC_TEST_D1
TP_DC_TEST_D65
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
U1000
SANDY-BRIDGE
MOBILE-REV1
BGA
(6 OF 11)
CORE POWER
OMIT
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
6 7 12 14 49 69 105
H35
H31
H29
H25
G44
G40
G38
G34
G32
G28
G26
F45
F43
F41
F37
F35
F31
F29
F25
E44
E40
E38
E34
E32
E28
E26
D45
D43
D41
D37
D35
D31
D29
C44
C40
C38
C34
C32
C28
C26
B45
B43
B41
B37
B35
B31
B29
A44
A40
A38
A34
A32
A28
A26
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
NOTE: Intel validation sense lines per doc 439028 rev1.0
HR_PPDG sections 6.2.1 and 6.3.1.
SYNC_MASTER=K91_MLB
PAGE TITLE
CPU POWER
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
13 OF 132
SHEET
12 OF 105
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
U1000
SANDY-BRIDGE
MOBILE-REV1
BGA
(10 OF 11)
OMIT
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
AW16
AV65
AV63
AV59
AV57
AV50
AV44
AV38
AV31
AV25
AV19
AV9
AV5
AU54
AU47
AU41
AU35
AU28
AU22
AU16
AU14
AT61
AT57
AT50
AT44
AT38
AT31
AT25
AT19
AT11
AT7
AT3
AT1
AR54
AR47
AR41
AR35
AR28
AR22
AP65
AP63
AP57
AP50
AP44
AP38
AP31
AP25
AP19
AP17
AP15
AP12
AP11
AP9
AP5
AN54
AN47
AN41
AN35
AN28
AN22
AM61
AM7
AM3
AM1
AL57
AL50
AL44
AL38
AL31
AL25
AL19
AK16
AK14
AK11
AK9
AK5
AJ64
AJ62
AJ60
AJ57
AH7
AH3
AH1
AG57
AG17
AG15
AG12
AF65
AF63
AF61
AF11
AF9
AF5
AE57
AD16
AD14
AD7
AD3
AD1
AC64
AC62
AC60
AC57
AB11
AB9
AB5
AA57
AA17
AA15
AA12
Y65
Y63
Y61
Y7
Y3
Y1
W57
V16
V14
V11
V9
V5
U64
U62
U60
U57
T7
T3
T1
R57
R50
R44
R38
R31
R25
R19
R17
R15
R12
P65
P63
P61
P11
P9
P5
N54
N47
N41
N35
N28
N22
M57
M50
M44
M38
M31
M25
M19
M7
M3
M1
L64
L62
L60
L58
L54
L50
L46
L42
L36
L30
L24
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
U1000
SANDY-BRIDGE
MOBILE-REV1
BGA
(11 Of 11)
OMIT
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
L20
L16
L12
L8
K39
K33
K27
K1
J64
J60
J56
J52
J48
J46
J42
J36
J30
J24
J22
J18
J14
J10
J6
H39
H33
H27
H3
G62
G58
G54
G50
G46
G42
G36
G30
G24
G20
G16
G12
G8
F39
F33
F27
E60
E56
E52
E48
E46
E42
E36
E30
E24
E22
E18
E14
E10
E6
E4
D63
D39
D33
D27
C58
C54
C50
C46
C42
C36
C30
C20
C16
C12
C8
B39
B33
B27
A56
A52
A42
A36
A30
A24
A20
A16
A12
A8
D
69 49 15 12 7
PPVCORE_S0_AXG
PP1V5_S3RS0_CPUDDR
AH65
AH63
AH61
AH58
AH56
AG64
AG62
AG60
AF58
AF56
AE64
AE62
AE60
AD65
AD63
AD61
AD58
AD56
AB65
AB63
AB61
AB58
AB56
AA64
AA62
AA60
Y58
Y56
W64
W62
W60
V65
V63
V61
V58
V56
T65
T63
T61
T58
T56
R64
R62
R60
R55
R53
R48
N64
N62
N60
N58
N56
N52
N49
M65
M63
M61
M59
M55
M53
M48
L56
L52
L48
VAXG_0
VAXG_1
VAXG_2
VAXG_3
VAXG_4
VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25
VAXG_26
VAXG_27
VAXG_28
VAXG_29
VAXG_30
VAXG_31
VAXG_32
VAXG_33
VAXG_34
VAXG_35
VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_49
VAXG_50
VAXG_51
VAXG_52
VAXG_53
VAXG_54
VAXG_55
VAXG_56
VAXG_57
VAXG_58
VAXG_59
VAXG_60
VAXG_61
VAXG_62
VAXG_63
U1000
SANDY-BRIDGE
MOBILE-REV1
BGA
(8 OF 11)
OMIT
IO POWER DDR3
BJ56
BJ52
BJ48
BJ40
BJ32
BJ24
BJ20
BJ16
BJ12
BJ8
BG60
BG56
BG52
BG48
BG44
BG36
BG28
BG24
BG20
BG16
BG12
BG8
BF5
BE62
BE58
BE54
BE50
BE46
BE42
BE38
BE34
BE30
BE26
BE22
BE18
BE14
BE10
BD35
BD7
BD3
BC60
BC56
BC52
BC48
BC44
BC40
BC36
BC32
BC28
BC26
BC24
BC20
BC16
BC12
BB65
BB63
BB47
BB39
BB9
BB5
BA58
BA54
BA50
BA46
BA42
BA38
BA34
BA30
BA26
BA22
BA18
BA14
AY61
AY11
AY7
AY3
AY1
AW56
AW52
AW48
AW44
AW40
AW36
AW32
AW28
AW24
GRAPHIC CORE POWER
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44
VDDQ_45
VDDQ_46
VDDQ_47
VDDQ_48
VDDQ_49
VDDQ_50
VDDQ_51
VDDQ_52
VDDQ_53
VDDQ_54
VDDQ_55
VDDQ_56
VDDQ_57
VDDQ_58
VDDQ_59
VDDQ_60
VDDQ_61
VDDQ_62
VDDQ_63
VDDQ_64
VDDQ_65
VDDQ_66
VDDQ_67
VDDQ_68
BJ36
BJ28
BG40
BG32
BD47
BD43
BD39
BD31
BD23
BB35
AY47
AY43
AY39
AY35
AY31
AY27
AY23
AV46
AV42
AV40
AV36
AV34
AV29
AV27
AU45
AU43
AU39
AU37
AU33
AU30
AU26
AU24
AT46
AT42
AT40
AT36
AT34
AT29
AT27
AR45
AR43
AR39
AR37
AR33
AR30
AR26
AR24
AP46
AP42
AP40
AP36
AP34
AP29
AP27
AN45
AN43
AN39
AN37
AN33
AN30
AN26
AN24
AL46
AL42
AL40
AL36
AL34
AL29
AL27
7 10 15 29 73 104
PP1V05_S0
PP1V05_S0
105
35 23 14 13 12 10 9 7
104 102 73 70 68 45 39
AV55
AV53
AV48
AV17
AV15
AV12
AU58
AU56
AU52
AU49
AU20
AU18
AT55
AT53
AT48
AT17
AT15
AT12
AR58
AR56
AR52
AR49
AR20
AR18
AR16
AR14
AP55
AP53
AP48
AN58
AN56
AN52
AN49
VCCIO_0
U1000
VCCIO_1 SANDY-BRIDGE
VCCIO_2 MOBILE-REV1
VCCIO_3
BGA
VCCIO_4
(7 OF 11)
IO POWER
VCCIO_5
VCCIO_6
VCCIO_7
OMIT
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49
VCCIO_50
VCCIO_51
VCCIO_52
VCCIO_53
VCCIO_54
VCCIO_55
VCCIO_56
VCCIO_57
VCCIO_58
VCCIO_59
VCCIO_60
VCCIO_61
VCCIO_62
VCCIO_63
VCCIO_64
VCCIO_65
7 9 10 12 13 14 23 35 39 45
68 70 73 102 104 105
AN20
AN18
AN16
AN14
AM11
AL55
AL53
AL48
AL17
AL15
AL12
AK58
AK56
AJ17
AJ15
AJ12
AH16
AH14
AH11
AF16
AF14
AE17
AE15
AE12
AD11
AC17
AC15
AC12
AB16
AB14
Y16
Y14
Y11
A
PAGE TITLE
CPU POWER AND GND

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
14 OF 132
SHEET
13 OF 105
CPU VCORE DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)
Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)
PLACEMENT_NOTE (C1600-C16C7):
105 69 49 12 7 6
PPVCORE_S0_CPU
Place on bottom side of U1000

U100.
1
C1600
1UF
1UF
20%
6.3V
2 X5R
0201
1UF
NOSTUFF
C16C1
1UF
20%
2 6.3V
X5R
0201
1UF
20%
2 6.3V
X5R
0201
1UF
20%
2 6.3V
X5R
0201
20%
2 6.3V
X5R
0201
20%
2 6.3V
X5R
0201
1UF
C16B3
1UF
20%
6.3V
2 X5R
0201
20%
6.3V
2 X5R
0201
C16B4
1UF
C16B5
1UF
20%
6.3V
2 X5R
0201
20%
6.3V
2 X5R
0201
1UF
C16B7
1UF
20%
6.3V
2 X5R
0201
1UF
20%
6.3V
2 X5R
0201
NOSTUFF
1
C1619
10%
2 10V
X5R
402
10%
2 10V
X5R
402
NOSTUFF
C16B6
C1618
1UF
10%
2 10V
X5R
402
NOSTUFF
1
C1617
1UF
10%
2 10V
X5R
402
NOSTUFF
1
C1616
1UF
10%
2 10V
X5R
402
NOSTUFF
1
C1615
1UF
10%
2 10V
X5R
402
NOSTUFF
C16B2
C1614
1UF
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
C1613
1UF
NOSTUFF
C16B1
1UF
20%
6.3V
2 X5R
0201
10%
2 10V
X5R
402
NOSTUFF
C16B0
C1612
1UF
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
C1611
1UF
NOSTUFF
C16A9
1UF
20%
6.3V
2 X5R
0201
10%
2 10V
X5R
402
NOSTUFF
C16A8
C1610
1UF
10%
2 10V
X5R
402
NOSTUFF
C16B8
1UF
C16B9
1UF
20%
6.3V
2 X5R
0201
20%
6.3V
2 X5R
0201
NOSTUFF
C16C6
C16C7
1UF
1UF
20%
2 6.3V
X5R
0201
20%
2 6.3V
X5R
0201
C1609
1UF
NOSTUFF
C16A7
20%
6.3V
2 X5R
0201
NOSTUFF
1
1UF
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
C16C5
1UF
C1608
1UF
NOSTUFF
C16A6
NOSTUFF
C16C4
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
NOSTUFF
C16C3
C1607
1UF
NOSTUFF
C16A5
1UF
20%
6.3V
2 X5R
0201
NOSTUFF
C16C2
10%
2 10V
X5R
402
NOSTUFF
C16A4
C1606
1UF
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
1UF
NOSTUFF
1
1UF
C1605
10%
2 10V
X5R
402
C16A3
C1604
1UF
NOSTUFF
C16A2
NOSTUFF
C16C0
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
C1603
1UF
NOSTUFF
C16A1
NOSTUFF
10%
2 10V
X5R
402
1UF
20%
6.3V
2 X5R
0201
C1602
1UF
NOSTUFF
C16A0
10%
2 10V
X5R
402
NOSTUFF
1
C1601
1UF
10%
2 10V
X5R
402
20%
2 6.3V
X5R
0201
PLACEMENT_NOTE (C1620-C1623):
Place near U1000 on bottom side
1
C1620
10UF
C1622
10UF
20%
2 6.3V
CERM-X5R
0402-1
CRITICAL
C1621
10UF
20%
2 6.3V
CERM-X5R
0402-1
CRITICAL
C1623
10UF
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
CRITICAL
CRITICAL
PLACEMENT_NOTE (C1624-C16D5):
Place near inductors on bottom side.
CRITICAL
1
CRITICAL
C1624
CRITICAL
C1625
22UF
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1626
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1627
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1628
22UF
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1629
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1630
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1631
22UF
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1632
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
C1633
22UF
20%
2 6.3V
X5R-CERM1
0603
C1635
22UF
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
CRITICAL
C1634
20%
2 6.3V
X5R-CERM1
0603
C1636
22UF
20%
2 6.3V
X5R-CERM1
0603
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
1
C1637
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
1
C1638
22UF
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
1
NOSTUFF
C1639
22UF
NOSTUFF
C16D0
22UF
20%
2 6.3V
X5R-CERM1
0603
NOSTUFF
C16D1
22UF
20%
2 6.3V
X5R-CERM1
0603
NOSTUFF
C16D2
22UF
20%
2 6.3V
X5R-CERM1
0603
C16D3
22UF
20%
2 6.3V
X5R-CERM1
0603
20%
2 6.3V
X5R-CERM1
0603
CRITICAL
1
CRITICAL
C1640
20%
2 2.0V
POLY-TANT
D2T-SM
CRITICAL
C1641
470UF-4MOHM
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM
CRITICAL
1 NOSTUFF
C1642
C1643
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
C1644
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
CPU
VCCIO/VCCPQ DECOUPLING
Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF
0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
73 70 68
13 12 10 9 7
45 39 35 23
105 104 102
PP1V05_S0
CPU VCCPLL DECOUPLING

U100.
1
C1646
1UF
10%
2 10V
X5R
402
C1647
1UF
C1648
1UF
10%
2 10V
X5R
402
C1649
1UF
C1650
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1651
1UF
C1652
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1653
1UF
C1654
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1655
1UF
10%
2 10V
X5R
402
C1656
1UF
C1657
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
R1600
C1658
1UF
10%
2 10V
X5R
402
102 88 72 71 25 20 7 6
PP1V8_S0
10%
2 10V
X5R
402
7 12
CRITICAL
5%
1/16W
MF-LF
402
2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
C1685
C1686
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
C1687
330UF-0.006OHM
20%
2V
2 POLY
CASE-D2-SM
PLACE_NEAR=U1000.AK61:5 mm
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
C1659
1UF
10%
2 10V
X5R
402
C1660
1UF
C1661
1UF
10%
2 10V
X5R
402
C1662
1UF
10%
2 10V
X5R
402
C1663
1UF
1UF
C1665
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1664
C1666
1UF
10%
2 10V
X5R
402
C1667
1UF
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1668
10%
2 10V
X5R
402
C1669
1UF
10%
2 10V
X5R
402
C1670
1UF
10%
2 10V
X5R
402
C1671
CPU VCCPLL Low pass filter
1UF
10%
2 10V
X5R
402
Place near U1000 on bottom side
1
C1672
10UF
20%
2 6.3V
X5R
603
C1673
10UF
20%
2 6.3V
X5R
603
C1674
10UF
20%
2 6.3V
X5R
603
C1675
10UF
20%
2 6.3V
X5R
603
CRITICAL
CRITICAL CRITICAL
CRITICAL
Place near inductors on bottom side
1
C1682
C1676
10UF
20%
2 6.3V
X5R
603
CRITICAL
C1677
10UF
20%
2 6.3V
X5R
603
CRITICAL
C1678
10UF
20%
2 6.3V
X5R
603
CRITICAL
C1679
10UF
20%
2 6.3V
X5R
603
C1680
10UF
20%
2 6.3V
X5R
603
CRITICAL
CRITICAL
C1681
10UF
20%
2 6.3V
X5R
603
CRITICAL
C1683
330UF-0.006OHM 330UF-0.006OHM
20%
2V
POLY
CASE-D2-SM
20%
2V
2 POLY
CASE-D2-SM
CRITICAL
CRITICAL
SYNC_MASTER=K91_MLB
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
R1601
0.0102
1
Apple Inc.
1%
1/4W
MF
0603
7 10 12
C1684
1UF

10%
10V
402
2 X5R
SIZE
REVISION
BRANCH
PAGE
16 OF 132
SHEET
14 OF 105
VAXG DECOUPLING
Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 6x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
69 49 13 12 7
PPVCORE_S0_AXG

U100.
NOSTUFF
1
C1700
1UF
C1701
1UF
10%
2 10V
X5R
402
C1702
1UF
10%
10V
2 X5R
402
C1703
10%
10V
2 X5R
402
C1704
1UF
C1706
1UF
10%
10V
2 X5R
402
10%
2 10V
X5R
402
C1705
1UF
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1707
1UF
C1708
1UF
NOSTUFF
C1709
1UF
10%
10V
2 X5R
402
10%
2 10V
X5R
402
1UF
10%
10V
2 X5R
402
NOSTUFF
C1710
10%
10V
2 X5R
402
C1711
1UF
10%
2 10V
X5R
402
NOSTUFF
1
C1712
1UF
10%
10V
2 X5R
402
NOSTUFF
1
C1713
1UF
NOSTUFF
1
C1714
1UF
10%
2 10V
X5R
402
NOSTUFF
1
C1715
1UF
C1716
1UF
10%
10V
2 X5R
402
10%
2 10V
X5R
402
NOSTUFF
1
NOSTUFF
1
C1717
1UF
10%
10V
2 X5R
402
10%
10V
2 X5R
402
Place close to U1000 on bottom side
NOSTUFF
1
C1718
10UF
C1719
C1720
10UF
20%
6.3V
2 CERM-X5R
0402-1
C1721
10UF
20%
6.3V
2 CERM-X5R
0402-1
C1722
10UF
20%
6.3V
2 CERM-X5R
0402-1
C1723
10UF
20%
6.3V
2 CERM-X5R
0402-1
10UF
20%
6.3V
2 CERM-X5R
0402-1
NOSTUFF
C1724
10UF
20%
6.3V
2 CERM-X5R
0402-1
C1725
10UF
20%
6.3V
2 CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
1
C1726
22UF
C1727
22UF
20%
2 6.3V
X5R-CERM1
0603
C1728
22UF
20%
2 6.3V
X5R-CERM1
0603
20%
2 6.3V
X5R-CERM1
0603
C1729
22UF
20%
2 6.3V
X5R-CERM1
0603
C1730
22UF
20%
2 6.3V
X5R-CERM1
0603
NOSTUFF
1
C1731
NOSTUFF
C1732
22UF
20%
2 6.3V
X5R-CERM1
0603
22UF
20%
2 6.3V
X5R-CERM1
0603
C1733
22UF
20%
2 6.3V
X5R-CERM1
0603
NOSTUFF
1
C1734
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
C1735
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
C1737
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM
CPU VCCSA DECOUPLING
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

104 73 29 13 10 7
PP1V5_S3RS0_CPUDDR

U100.
1
C1738
1UF
10%
2 10V
X5R
402
C1739
1UF
65 12 7
C1740
1UF
C1741
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1742
1UF
10%
2 10V
X5R
402
C1743
1UF
C1744
1UF
10%
2 10V
X5R
402
C1745
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1746
1UF
10%
2 10V
X5R
402
PPVCCSA_S0_CPU

U100.
C1747
1UF
C1758
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1759
1UF
C1760
1UF
10%
2 10V
X5R
402
C1761
1UF
10%
2 10V
X5R
402
10%
2 10V
X5R
402
C1762
1UF
10%
2 10V
X5R
402
Place close to U1000 on bottom side

1
C1748
10UF
20%
2 6.3V
X5R
603
C1749
10UF
C1750
10UF
20%
2 6.3V
X5R
603
C1751
10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
C1752
10UF
20%
2 6.3V
X5R
603
C1753
10UF
20%
2 6.3V
X5R
603
C1754
10UF
C1755
10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
C1763
10UF
20%
2 6.3V
X5R
603
Place near inductors on bottom side
C1764
10UF
20%
2 6.3V
X5R
603
C1765
10UF
20%
2 6.3V
X5R
603
C1766
10UF
20%
2 6.3V
X5R
603
C1767
10UF
20%
6.3V
2 X5R
603
CRITICAL
1
C1756
330UF-0.006OHM
20%
2V
2 POLY
C1768
270UF
CASE-D2-SM
20%
2 2V
TANT
CASE-B4-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1700
0.0102
1%
1/4W
MF
0603
PP1V5_S3_CPU_VCCDQ
1
7 12
C1757
1UF
10%
10V
2 X5R
402
SYNC_MASTER=K91_MLB
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
17 OF 132
SHEET
15 OF 105
INTRUDER*
C17
INTVRMEN
95 16
HDA_BIT_CLK_R
N34
HDA_BCLK
95 16
HDA_SYNC_R
L34
HDA_SYNC
6
6
IN
K34
E34
G34
C34
A34
A36
C36
N32
JTAG_T29_TMS
ENET_MEDIA_SENSE_RDIV
HDA_RST*
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
IN
XDP_PCH_TCK
J3
JTAG_TCK
23
IN
XDP_PCH_TMS
H7
JTAG_TMS
23
95 47
95 47
IN
XDP_PCH_TDI
K5
JTAG_TDI
OUT
XDP_PCH_TDO
H1
JTAG_TDO
T3
SPI_CLK_R
OUT
SPI_CS0_R_L
OUT
TP_SPI_CS1_L
SPI_CS0*
T1
SPI_CS1*
95 47
OUT
SPI_MOSI_R
V4
SPI_MOSI
95 47
IN
SPI_MISO
U3
SPI_MISO
LPC_R_AD<2> R18621
MF
MF
1
5% 1/20W
TP_LPC_DREQ0_L
T29_PWR_EN
MF
201
MF
6 45 47 88 95
BI
6 45 47 88 95
201
1%
1/20W
MF
201
R1820
6 45 47 88 95
10K
BI
6 45 47 88 95
5%
1/20W
MF
201
OUT
6 45 47 88 95
MF 1%
1/20W
95 36
IN
95 36
IN
95 36
OUT
95 36
OUT
(IPU)
LPC_SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AM3
AM1
AP7
AP5
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TP_SATA_B_R2D_CP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
IN
6 41 94
95 31
6 45 47
BI
IN
OUT
95 31
OUT
95 38
IN
IN
6 41 94
95 38
IN
6 41 94
95 38
OUT
OUT
6 41 94
95 38
OUT
100 32 6
100 32 6
41 94
IN
41 94
OUT
41 94
OUT
41 94
IN
IN
100 32
OUT
100 32
OUT
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
BG34
BJ34
AV32
AU32
PERN1
PERP1
PETN1
PETP1
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
BE34
BF34
BB32
AY32
PERN2
PERP2
PETN2
PETP2
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
BG36
BJ36
AV34
AU34
PERN3
PERP3
PETN3
PETP3
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
6
6
6
6
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
94
SATAICOMPO Y11
SATAICOMPI Y10
PCH_SATAICOMP
SATALED* P3
PPVCCIO_S0_PCH
PCH_SATALED_L
SATA0GP/GPIO21 V14
SATA1GP/GPIO19 P1
94
16 17 20 22 102 104
95 36
OUT
95 36
OUT
DP_AUXCH_ISOL
OUT
SATARDRVR_EN
OUT
R18311
16 23
85
16 23 41
49.9
1%
1/20W
MF
201
PCH_SATA3COMP
PCH_SATA3RBIAS
R18321
750
5%
1/20W
MF
201
AB49
AB47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
AA48
AA47
CLKOUT_PCIE2N
CLKOUT_PCIE2P
R1878
R1843
R18481 R18461 R18451 R18441
10K
25 20 17 7
5%
1/20W
MF
201
PPVRTC_G3H
R1800 1
330K
5%
1/20W
MF
201
R1802 1
R1801 20K
5%
1M
5%
1/20W
MF
201
1/20W
MF
201
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
R1877
10K
4.7K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
16
16
102 22 20 19 18 17 16
PP3V3_S0_PCH
PP3V3_SUS
72 71 46 22 20 19 18 17 16 7
73
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
95 16
95 16
95 16
16 95
IN
16 95
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
IN
16 95
IN
16 95
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
16 95
IN
16 95
PCH_CLK14P3M_REFCLK
IN
16 95
PCH_CLK33M_PCIIN
IN
25 95
CLKIN_DOT_96N G24
CLKIN_DOT_96P E24
CLKIN_SATA_N AK7
CLKIN_SATA_P AK5
CLKOUT_PCIE3N
CLKOUT_PCIE3P
XTAL25_IN V47
XTAL25_OUT V49 NC
SYSCLK_CLK25M_SB_R
PCIE_CLK100M_T29_N
PCIE_CLK100M_T29_P
Y43
Y45
CLKOUT_PCIE4N
CLKOUT_PCIE4P
XCLK_RCOMP Y47
PCH_XCLK_RCOMP
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0/GPIO64 K43
TP_PCH_GPIO64_CLKOUTFLEX0
PCIECLKRQ5_L_GPIO44
L14
PCIECLKRQ5*/GPIO44
CLKOUTFLEX1/GPIO65 F47
CLKOUTFLEX2/GPIO66 H47
CLKOUTFLEX3/GPIO67 K49
AB42
AB40
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
IN
T29_CLKREQ_L
IN
PEG_CLKREQ_L
PEG_B_CLKRQ_L_GPIO56
M10
E6
PEG_A_CLKRQ*/GPIO47
PEG_B_CLKRQ*/GPIO56
31 23 16
IN
32 16
IN
ENET_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
35 16
88 16 8
16
CLKOUT_ITPXDP_N AK14
CLKOUT_ITPXDP_P AK13
PP1V5_S0
B
16 23 92
16 23 92
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
CL_CLK1 M7
71 57 41 32 25 22 20 7
48 95
16
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
CLKIN_GND1_N BJ30
CLKIN_GND1_P BG30
48 95
OUT
DOES THIS NEED LENGTH MATCH???
PCIECLKRQ0*/GPIO73
PCIECLKRQ1*/GPIO18
PCIECLKRQ3*/GPIO25
PCIECLKRQ4*/GPIO26
IN
REFCLK14IN K45
CLKIN_PCILOOPBACK H45
J2
M1
A8
L12
36 16
R1840
92 23 16
ITPXDP_CLK100M_P
R1841
NOSTUFF
R18661
1 5% 1/20W
MF
ITPCPU_CLK100M_N
10 92
MF
ITPCPU_CLK100M_P
10 92
10K
5%
1/20W
MF
201
201
1 5% 1/20W
NOSTUFF
1
TP_CLINK_CLK
CL_DATA1 T11
TP_CLINK_DATA
CL_RST1* P10
TP_CLINK_RESET_L
R1849
10K
5%
1/20W
MF
201
HDA_SYNC_R
HDA_SDOUT_R
DP_AUXCH_ISOL
16 23 85
SATARDRVR_EN
16 23 41
R1849 cannot be used w/ VCCSUSHDA on S0

16 95
16 95
PLACE_NEAR=U1800.N34:1.27mm
HDA_BIT_CLK_R
33
5%
1/20W
MF
201
16
95 16
R1811
33
1
R1812
95 16
HDA_RST_R_L
R1897
10K
R1891 1R1892 1R1893 1R1894 1R1895 1R1896

10K
10K
10K
10K
10K
10K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
95 16
HDA_SDOUT_R
SYSCLK_CLK25M_SB
PP3V3_SUS
HDA_RST_L
OUT
33
57 95
R1855
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
2 201
16
1.8V -> 1.1V

R1873
R1853
10K
2 201
SYNC_MASTER=K91_MLB
PAGE TITLE
PCH SATA/PCIE/CLK/LPC/SPI
DRAWING NUMBER
5%
1/20W
MF
Apple Inc.
2 201
SIZE
D
REVISION
HDA_SDOUT
OUT
57 95
SML_PCH_0_ALERT_L
SML_PCH_1_ALERT_L
16
16
NOSTUFF
45 19
5%
1/20W
MF
R1813
5%
1/20W
MF
201
SYSCLK_CLK25M_SB_R
1%
1/20W
MF
1
10K
1K
OUT
IN
SMC_SCI_L
R1888
1 5% 1/20W
MF
16
PCH_GPIO11
UNUSED clock terminations for FCIM MODE
604
72 71 46 22 20 19 18 17 16 7
73
57 95
HDA_SYNC
201
1%
1/16W
MF-LF
402
R1854
2
5%
1/20W
MF
201
IN
33
1
57 95
5%
1/20W
MF
201
PLACE_NEAR=U1800.K34:1.27mm
OUT
PLACE_NEAR=U1800.L34:1.27mm
HDA_SYNC_R
R1871
R1872
25
HDA_BIT_CLK
10K
5%
1/20W
MF
201
R1810
95 16
R18701
201
IN
Y37
Y36
NOSTUFF
PCH_CLK14P3M_REFCLK
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
Q1850 376S0859
376S0859 VGS 0.35~1V
ITPXDP_CLK100M_N
PCIECLKRQ5_L_GPIO44
95 16
92 23 16
R18331 R18341
10K
95 16
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
NOSTUFF
NOSTUFF
5%
1/20W
MF
201
95 16
CLKIN_DMI_N BF18
CLKIN_DMI_P BE18
OUT
16
1UF
95 16
OUT
BI
16
C1803
10%
10V
X5R
402
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
OUT
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
JTAG_T29_TMS
16 33
PCH_SPKR
16
FW_CLKREQ_L
16 23 39
AP_CLKREQ_L
16 23 31
PCH_SATALED_L
16
EXCARD_CLKREQ_L
16 32
T29_CLKREQ_L
16 35
PEG_CLKREQ_L
8 16 88
PEG_B_CLKRQ_L_GPIO56 16
ENET_CLKREQ_L
16 36
R18471
10 92
CLKOUT_DP_N AM12
CLKOUT_DP_P AM13
95 32
R1876
20K
1UF
10%
10V
X5R
402
10K
5%
1/20W
MF
201
R1842
R1803
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
C1802
10K
5%
1/20W
MF
201
R1869
10K
5%
1/20W
MF
201
10 92
OUT
95 32
4.7K
OUT
PCIECLKRQ2*/GPIO20
PP3V3_S0_PCH
1
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
V10
74 95
CLKOUT_DMI_N AV22
CLKOUT_DMI_P AU22
FW_CLKREQ_L
16
74 95
OUT
IN
OUT
OUT
OUT
16
PEG_CLK100M_N
PEG_CLK100M_P
CLKOUT_PEG_A_N AB37
CLKOUT_PEG_A_P AB38
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
OUT
48 95
OUT
OUT
95 33
BI
48 95
SML_PCH_1_CLK
SML_PCH_1_DATA
95 38
73
102 22 20 19 18 17 16
SML1CLK/GPIO58 E14
SML1DATA/GPIO75 M16
OUT
SML_PCH_1_ALERT_L
95 38
95 33
BI
6 23 26 28 30 32
41 48 62 89 95
6 23 26 28 30 32
41 48 62 89 95
16
SML_PCH_0_CLK
SML_PCH_0_DATA
OUT
88 35 34 33 25 19 7
OUT
SML_PCH_0_ALERT_L
OUT
PLACE_NEAR=U1800.AH1:2.54mm
PP3V3_T29
102 22 20 19 18 17 16 PP3V3_S0_PCH
46 22 20 19 18 17 16 7 PP3V3_SUS
SML0ALERT*/GPIO60 A12
SML1ALERT*/PCHHOT*/GPIO74 C13
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
16
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML0CLK C8
SML0DATA G12
CLKOUT_PCIE0N
CLKOUT_PCIE0P
201
PCH_GPIO11
SMBCLK H14
SMBDATA C9
95 31
39 23 16
FCBGA
(2 OF 10)
OMIT
Y40
Y39
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
SMBALERT*/GPIO11 E12
U1800
COUGAR-POINT
MOBILE
95 31
16
(IPU)
SATA3COMPI AB13
SATA3RCOMP0 AB12
SATA3RBIAS AH1
72 71
IN
OUT
IN
90.9
37.4
95 31 6
35
R1890
R1830 1
95 31 6
SERIRQ V5
PPVCCIO_S0_PCH
PLACE_NEAR=U1800.Y47:2.54mm
PLACE_NEAR=U1800.Y11:2.54mm
33 LPC_FRAME_L
BI
BI
201
33 LPC_AD<3>
1
5% 1/20W
201
33 LPC_AD<2>
LPC_R_AD<3> R1863
201
33 LPC_AD<1>
5% 1/20W
LPC_FRAME_R_L R1864
SPI_CLK
Y14
MF
1
5% 1/20W
LPC_AD<0>
33
R1861
LDRQ0* E36
LDRQ1*/GPIO23 K36
HDA_SDO
HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13
LPC_R_AD<1>
FWH4/LFRAME* D36
SPKR
23
23
HDA_RST_R_L
HDA_SDOUT_R
95 16
OUT
T10
HDA_SDIN0
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
IN
6
25
PCH_SPKR
C38
A38
B37
C37
1
5% 1/20W
SMBUS
K22
PCH_INTVRMEN_L
1
104 102 22 20 17 16
R1860
PEG
PCH_INTRUDER_L
16
95 16
33 16
SRTCRST*
16
16
95 57
RTCRST*
FROM CLK BUFFER
G22
FCBGA
(1 OF 10)
OMIT
RTC
LPC
PCH_SRTCRST_L
COUGAR-POINT
MOBILE
IHDA
RTC_RESET_L
16
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
SATA
16
D20
U1800
RTCX1
RTCX2
JTAG
NC
A20
C20
SPI
SYSCLK_CLK32K_RTC
IN
PPVCCIO_S0_PCH
PP3V3_S0_PCH
LPC_R_AD<0>
25
CLOCK
FLEX
104 102 22 20 17 16
102 22 20 19 18 17 16
PCI-E*

BRANCH
PAGE
18 OF 132
SHEET
16 OF 105
7
PP3V3_SUS
PPVCCIO_S0_PCH
7 16 17 18 19 20 22 46 71 72 73
16 20 22 102 104
R1905
10K
R1900
49.9
92 9
IN
92 9 6
IN
92 9
IN
92 9 6
IN
92 9
IN
92 9 6
IN
92 9
IN
92 9 6
IN
92 9 6
OUT
92 9 6
OUT
92 9
OUT
92 9
OUT
92 9 6
OUT
92 9 6
OUT
92 9
OUT
92 9
OUT
U1800
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
PCH_DMI2RBIAS
BH21
DMI2RBIAS
FCBGA
(3 OF 10)
OMIT
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BJ24
BG25
PCH_DMI_COMP
750
1%
1/20W
MF
2 201
45 25 6
IN
PM_SYSRST_L
91 23
IN
PM_PCH_SYS_PWROK
P12
SYS_PWROK
IN
PM_PCH_PWROK
L22
PWROK
B13
DRAMPWROK
91 17
K3
DMI_ZCOMP
DMI_IRCOMP
SYSTEM POWER
MANAGEMENT
R1920
SYS_RESET*
9 92
9 92
FDI_INT
PCIE_WAKE_L
IN
CLKRUN*/GPIO32 N3
PM_CLKRUN_L
BI
SUS_STAT*/GPIO61 G8
APWROK
RSMRST*
17
OUT
SUSWARN_L
K16
SUSWARN*/SUSPWRDNACK/GPIO30
IN
PM_PWRBTN_L
E20
PWRBTN*
SUSCLK/GPIO62 N14
SLP_S5*/GPIO63 D10
OUT
6 45 47
PM_CLK32K_SUSCLK_R
OUT
46
PM_SLP_S5_L
OUT
17 45 73
PM_SLP_S4_L
OUT
17 29 42 45 66 73
SLP_S3* F4
PM_SLP_S3_L
OUT
6 17 29 45 73
25 20 16 7
TP_PM_SLP_A_L
TP23 AY16
OUT
PCH_DF_TVS
R1980
17
1K
5%
1/20W
MF
201
1 5% 1/20W
MF
390K
5%
1/20W
MF
201 2
CPU_PROC_SEL_L
6
6
6
10 92
6
201
6
DSWVRMEN A18
G16
SLP_SUS*
PCH_DSWVRMEN
PM_SLP_SUS_L
OUT
SUSACK* C12
PCH_SUSACK_L
IN
6
17 73
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
SDVO_STALLN AM42
SDVO_STALLP AM40
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
SDVO_CTRLCLK P38
SDVO_CTRLDATA M39
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DP_IG_AUX_CH_N
DP_IG_AUX_CH_P
DP_IG_HPD
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
NC_DP_IG_C_CTRL_CLK
DDPC_AUXN AP47
DDPC_AUXP AP49
DDPC_HPD AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
17
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
NC_DP_IG_C_AUXN
NC_DP_IG_C_AUXP
NC_DP_IG_C_HPD
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
NC_DP_IG_C_MLN<0>
NC_DP_IG_C_MLP<0>
NC_DP_IG_C_MLN<1>
NC_DP_IG_C_MLP<1>
NC_DP_IG_C_MLN<2>
NC_DP_IG_C_MLP<2>
NC_DP_IG_C_MLN<3>
NC_DP_IG_C_MLP<3>
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC
PCH_DAC_IREF
T43
T42
DAC_IREF
CRT_IRTN
NC_DP_IG_D_CTRL_CLK
DDPD_AUXN AT45
DDPD_AUXP AT43
DDPD_HPD BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
6
6
6
6
6
6
8 80 84
8 80 84
8 84 94
8 84 94
8 84
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
DDPD_CTRLCLK M43
DDPD_CTRLDATA M36
1
R1915
2.2K
10 92
SDVO_TVCLKINN AP43
SDVO_TVCLKINP AP45
SDVO_INTN AP39
SDVO_INTP AP40
20 22 102
R1981
GPIO29_SLP_LAN_L
DF_TVS AY1
FCBGA
(4 OF 10)
OMIT
PPVRTC_G3H
PP1V8_S0_PCH
PM_SYNC
SLP_LAN*/GPIO29 K14
U1800
COUGAR-POINT
MOBILE
TP_PCH_TP23
PMSYNCH AP14
6 17 45 47
SLP_S4* H4
SLP_A* G10
BATLOW*/GPIO72
6 17 25 31 32 85
LPC_PWRDWN_L
100K
5%
1/20W
MF
201
9 92
WAKE* B9
C21
R1909
9 92
9 92
9 92
L10
RI*
9 92
OUT
PM_RSMRST_L
A10
9 92
9 92
PM_PCH_PWROK
IN
9 92
9 92
IN
PCH_RI_L
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
OUT
IN
E10
9 92
FDI_LSYNC<0>
FDI_LSYNC<1>
73
H20 ACPRESENT/GPIO31
9 92
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
91 17
PM_BATLOW_L
9 92
9 92
DPWROK
SMC_ADAPTER_EN
9 92
OUT
E22
IN
9 92
9 92
PM_DSW_PWRGD
46
9 92
OUT
IN
73 46 45
9 92
OUT
OUT
PD on SMC page
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AT1 RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
NC
AT3
NC
AT4
NC
AT5
NC
AT8
NC
AT10
NC
AT12
NC
AU2
NC
AU3
NC
AV1
NC
AV3
NC
AV5
NC
AV7
NC
AV10
NC
AY3
NC
AY5
NC
AY7
NC
BA2
NC
BA3
NC
BB1
NC
BB3
NC
BB5
NC
BB7
NC
BC8
NC
BD4
NC
BE8
NC
BF3
NC
BF6
NC
BG4
NC
9 92
FDI_FSYNC<0>
FDI_FSYNC<1>
45
45 23 17
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
PM_MEM_PWRGD
92 29 10
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_INT AW16
PLACE_NEAR=U1800.BH21:2.54mm
1
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
COUGAR-POINT
MOBILE
DIGITAL DISPLAY INTERFACE
1%
1/20W
MF
201
CRT
DMI
FDI
5%
1/20W
MF
2 201
NC_DP_IG_D_AUXN
NC_DP_IG_D_AUXP
NC_DP_IG_D_HPD
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
NC_DP_IG_D_MLN<0>
NC_DP_IG_D_MLP<0>
NC_DP_IG_D_MLN<1>
NC_DP_IG_D_MLP<1>
NC_DP_IG_D_MLN<2>
NC_DP_IG_D_MLP<2>
NC_DP_IG_D_MLN<3>
NC_DP_IG_D_MLP<3>
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low
Set to Vcc when High
R1951
1K
PLACE_NEAR=U1800.T43:2.54mm
5%
1/20W
MF
2 201
17
R1986
SUSWARN_L
1 5% 1/20W
MF
PCH_SUSACK_L
17
201
102 22 20 19 18 16
T29 WAKE
85 32 31 25 17 6
PCIE_WAKE_L
IN
PCIE_WAKE_L
OUT
PP3V3_S0_PCH
R19911
6 17 25 31 32 85
8.2K
MAKE_BASE=TRUE
5%
1/20W
MF
201
PM_CLKRUN_L
PP3V3_SUS
PP3V3_S5
6 17 45 47
71 46 22 20 19 18 17 16 7
73 72
102 100 91 86
24 23 22 20 19 7 6
83 73 72 71 56 48 46 29 25
104
PP3V3_SUS
46 22 20 19 18 17 16 7
73 72 71
R1925
1K
R1985
1K
1%
1/20W
MF
201
1%
1/20W
MF
201
R19821
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
73 45 29 17 6
R19831
10K
73 17
73 45 17
73 66 45 42 29 17
PM_SLP_S3_L
PM_SLP_SUS_L
PM_SLP_S5_L
PM_SLP_S4_L
A
PAGE TITLE
SUSWARN_L
GPIO29_SLP_LAN_L
PM_PWRBTN_L
PCIE_WAKE_L
R1921
17
17
17 23 45
R1922
R1923
100K
100K
100K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
R1924
PCH DMI/FDI/GRAPHICS
100K
5%
1/20W
MF
201
DRAWING NUMBER
Apple Inc.
2

R
6 17 25 31 32 85
SIZE
REVISION
BRANCH
PAGE
19 OF 132
SHEET
17 OF 105
10K
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
18
18
18
R2030
R2014
R2031
10K
10K
10K
5%
1/20W
MF
201
62
5%
1/20W
MF
201
5%
1/20W
MF
201
85
62
39 29 25
OUT
95 25
OUT
25
OUT
R2050
OUT
94 88
OUT
94 88
OUT
94 88
OUT
94 8
OUT
OUT
94 88
OUT
94 8
OUT
94 88
OUT
94 88
OUT
94 88
OUT
94 88
OUT
94 88
OUT
OUT
94 88
OUT
94 88
OUT
94 88
OUT
OUT
8 6
OUT
8 6
OUT
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
PCI_INTE_L
AUD_IP_PERIPHERAL_DET
T29_MCU_INT_L
AUD_I2C_INT_L
G42
G40
C42
D44
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
NC_PCI_PME_L
K10
PME*
C6
H49
H43
J48
K42
H40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
D47
E42
F46
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
OUT
94 88
PCH_PCI_GNT1_L
PCH_PCI_GNT2_L
PCH_PCI_GNT3_L
1%
1/20W
MF
201
8 6
OUT
88 18 8
OUT
88 18 8
OUT
84
OUT
84
OUT
6
6
88 18 8
18
18
18
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
AK39
AK40
LVDSA_CLK*
LVDSA_CLK
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
AH45
AH47
AF49
AF45
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
AF40
AF39
LVDSB_CLK*
LVDSB_CLK
PCH_LVDS_IBG
NC_PCH_LVDS_VBG
AF37
AF36
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
2.37K
PLACE_NEAR=U1800.AF37:2.54mm
FCBGA
(5 OF 10)
C46
C44
E40
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_GMUX_R
NC_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
94 88
COUGAR-POINT
MOBILE
JTAG_GMUX_TMS
PCH_GPIO52
PCI_REQ3_L
PLT_RESET_L
25
25
U1800
PIRQA*
PIRQB*
PIRQC*
PIRQD*
OMIT
88
5%
K40
K38
H38
G38
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
P45
J47
M45
T45
P39
T40
K47
TP_LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
NC_LVDS_IG_CTRL_CLK
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
USB
10K
10K
10K
10K
PCI
R2016
R2017
R2018
88 18 8
PP3V3_S0_PCH
R2010
R2011
R2012
R2013
USBP0N C24
USBP0P A24
USB_HUB1_UP_N
USB_HUB1_UP_P
USBP1N C25
USBP1P B25
NC_USB_1N
NC_USB_1P
Unused
USBP2N C26
USBP2P A26
NC_USB_2N
NC_USB_2P
Unused
USBP3N K28
USBP3P H28
NC_USB_3N
NC_USB_3P
Unused
USBP4N E28
USBP4P D28
NC_USB_4N
NC_USB_4P
Unused
USBP5N C28
USBP5P A28
NC_USB_5N
NC_USB_5P
Unused
USBP6N C29
USBP6P B29
NC_USB_6N
NC_USB_6P
Unused
USBP7N N28
USBP7P M28
NC_USB_7N
NC_USB_7P
Unused
USBP8N L30
USBP8P K30
USB_HUB2_UP_N
USB_HUB2_UP_P
USBP9N G30
USBP9P E30
USB_CAMERA_N
USB_CAMERA_P
USBP10N C30
USBP10P A30
NC_USB_10N
NC_USB_10P
USBP11N L32
USBP11P K32
NC_USB_11N
NC_USB_11P
USBP12N G32
USBP12P E32
NC_USB_12N
NC_USB_12P
USBRBIAS* C33
USBRBIAS B33
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
BI
24 94
BI
24 94
BI
24 94
BI
24 94
USB HUB 1
USB HUB 2
31
31
Camera
PP3V3_S3
6 7 8 24 25 29 30 31 32 48 49 50 54 55 73
88 104
PP3V3_SUS
7 16 17 19 20 22 46 71 72 73
Unused
1
R2065
Unused
5%
1/20W
MF
201
R2061
R2068
10K
2
2
NC_USB_13N
NC_USB_13P
R2067
PCH_USB_RBIAS
A14
K20
B17
C16
L16
A16
D14
C14
73 31
R20621
10K
5%
1/20W
MF
201
R2064
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
10K
1
R2060
10K
5%
1/20W
MF
201
Unused
94
10K
Unused
USBP13N C32
USBP13P A32
LVDS
102 22 20 19 17 16
2
2
5%
1/20W
MF
201
5%
1/20W
MF
201
2 201
R2069
10K
5%
1/20W
MF
201
AP_PWR_EN
USB_HUB_SOFT_RESET_L 23 24
SDCONN_STATE_RST_L 23
ENET_PWR_EN
23
PCH_GPIO43_OC4_L
23
SDCONN_STATE_CHANGE 23
PCH_GPIO10_OC6_L
23
PCH_GPIO14_OC7_L
23
R2070
22.6
1%
1/20W
MF
201
2
L_BKLTCTL
L_BKLTEN
L_VDD_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
LVDS_IG_PANEL_PWR
R2015
LVDS_IG_BKL_ON
100K
PCH_PCI_GNT3_L
PCH_PCI_GNT2_L
PCH_PCI_GNT1_L
5%
1/16W
MF-LF
2 402
NOSTUFF
R20521
10K
5%
1/20W
MF
201
NOSTUFF
R20531
NOSTUFF
R20541
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
R2055
100K
5%
1/20W
MF
2 201
SYNC_MASTER=K91_MLB
PAGE TITLE
PCH PCI/FLASHCACHE/USB
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
20 OF 132
SHEET
18 OF 105
88 33 23 19 8
JTAG_ISP_TCK
41 19
ODD_PWR_EN_L
88 19
102 22 20 19 18 17 16
PP3V3_S0_PCH
T7
PCH_GPIO0
39 19 8
IN
FW_PLUG_DET_L
A42
TACH1/GPIO1
88 19
IN
GMUX_INT
H36
TACH2/GPIO6
46 45 19
IN
SMC_RUNTIME_SCI_L
E38
TACH3/GPIO7
(IPU)
GMUX_INT
1
R2190
19
100K
R21111
R21121
R21131
20K
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
47 6
BI
41 19
OUT
45 19 16
29 23
19
R2193
10K
10K
100K
5%
1/20W
MF
201
5%
1/20W
MF
201 2
88 33 19 8
5%
1/20W
MF
201
88 33 19 8
73 19
19
PCH_GPIO24
E8
5%
1/20W
MF
201
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
72 71 46 22 20 19 18 17 16 7
73
TP7 AH37
NC
OUT
JTAG_ISP_TDI
SDATAOUT0/GPIO39
OUT
WOL_EN
T13
TP8 AK43
NC
PCIECLKRQ6*/GPIO45
K12
TP9 AK45
NC
PCH_GPIO46
PCIECLKRQ7*/GPIO46
V13
TP10 C18 NC
SDATAOUT1/GPIO48
TP11 N30 NC
SATA5GP/GPIO49
TP12 H3
72 71 56 48 46 29 25 24 23 22 20 17 7 6
104 102 100 91 86 83 73
TP13 AH12
NC
TACH4/GPIO68
TP14 AM4 NC
19
PCH_GPIO69_TACH5
B41
TACH5/GPIO69
19
PCH_GPIO70_TACH6
C41
TP15 AM5 NC
TACH6/GPIO70
PCH_GPIO71_TACH7
A40
TP16 Y13 NC
19
TACH7/GPIO71
TP17 K24 NC
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
TP18 L24 NC
AH8
AK11
AH10
AK10
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
U47
VSSADAC
2
19
19 23
PP3V3_S5
R21731 R21721
10K
10K
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
D6
GPIO57
R21911
R21751 R21741
10K
5%
1/20W
MF
201
390
NOSTUFF
OUT
R2130 1
10 23 92
1K
PM_THRMTRIP_L
IN
5%
1/20W
MF
201
10 92
5%
1/20W
MF
201
102 22 20 19 18 17 16
PP3V3_S0_PCH
R21951
R21961
NOSTUFF 1
R2197
10K
10K
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
T29_SW_RESET_L
SMC_RUNTIME_SCI_L
PCH_GPIO49_SATA5GP
88 35 34 33 25 19 16 7
19 35
19 45 46
PP3V3_T29
R21991
10K
5%
1/20W
MF
201
JTAG_ISP_TDI
PCH_GPIO36_SATA2GP
ENET_LOW_PWR
TP19 AB46
NC
TP20 AB45
NC
R21981
TP21 B21 NC
10K
5%
1/20W
MF
201
TP22 M20 NC
TP24 BG46
NC
8 19 33 88
19 23
19 32 36
NOSTUFF
R21161
10K
5%
1/20W
MF
201
TP25 BE28
NC
TP26 BC30
NC
TP27 BE32
NC
TP28 BJ32
NC
TP29 BC28
NC
TP30 BE30
NC
TP31 BF32
NC
TP32 BG32
NC
TP33 AV26
NC
TP34 BB26
NC
TP35 AU28
NC
TP36 AY30
NC
NC_1 P37 NC
INIT3_3V* T14
TP38
TP37
TP39
TP40
PCH_INIT3V3_L
AY26
NC
AU26
NC
AV28
NC
AW30
19
This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
NC
SYNC_MASTER=K91_MLB
PAGE TITLE
2
SMC_SCI_L
PCH MISC
16 19 45
DRAWING NUMBER
Apple Inc.
PCH_GPIO68_TACH4
PCH_GPIO69_TACH5
PCH_GPIO70_TACH6
PCH_GPIO71_TACH7
23
NC
C40
PP3V3_S0_PCH
V3
PCH_GPIO68_TACH4
19
PCH_GPIO15
102
18 17 16
22 20 19
TP6 AH38
NC
SLOAD/GPIO38
19 23
PCH_GPIO46
SATA3GP/GPIO37
N2
R21171
M5
M3
19 39
10K
PM_THRMTRIP_L_R
CPU_PWRGD
R2156
TP5 BG16
NC
JTAG_ISP_TDO
8 19 39
5%
1/20W
MF
201
46
MF
TP4 BJ16
NC
IN
8 19 33 88
10K
TP3 BH25
NC
JTAG_ISP_TCK
SPIROM_USE_MLB
5%
1/20W
MF
201
THRMTRIP* AY10
OUT
BI
10K
0
5%
201
SATA2GP/GPIO36
FW_PWR_EN
5%
1/20W
MF
201
1
1/20W
GPIO35
NOSTUFF
R21151
PCH_PROCPWRGD
V8
PP3V3_SUS
R21141
PROCPWRGD AY11
PCH_GPIO36_SATA2GP
6 19 47 56
NOSTUFF
R2140
K4
ENET_LOW_PWR
PCH_INIT3V3_L
19
PCH_RCIN_L
NC_GPIO35
WOL_EN
RCIN* P5
TP2 BJ26
NC
OUT
45 92
MF
SCLOCK/GPIO22
GPIO24/MEM_LED
CPU_PECI 10
STP_PCI*/GPIO34
73 19
43
5%
201
K1
OUT
JTAG_ISP_TDO
FW_PLUG_DET_L
FW_PWR_EN
PCH_GPIO0
T29_SW_RESET_L
R21851 R21861
10K
PCH_PECI
OUT
PP3V3_S0_PCH
10K
10K
5%
1/20W
MF
201
TP1 BG26
NC ALL RSVD TPs NC-ed per INTEL approval
PP3V3_T29
10K
TACH0/GPIO17
R21551
R2170
1/20W
SATA4GP/GPIO16
GPIO28
25 19 16 7
88 35 34 33
R21601 R21841
U2
PCH_A20GATE
NOSTUFF
PECI AU16
16 17 18 19 20 22 102
10K
5%
1/20W
MF
201
GPIO27
(PUs necessary?)
22 20 19 18 17 16
102
GPIO15
T5
39 19
56 47 19 6
G2
D40
36 32 19
19
MISC
GPIO8
A20GATE P4
R21501
P8
23 19
PCH_GPIO12
PCH_GPIO24
SPIROM_USE_MLB
LAN_PHY_PWR_CTRL/GPIO12
ODD_PWR_EN_L
CLKOUT_PCIE7N V38
CLKOUT_PCIE7P V37
PP3V3_S0_PCH
6
E16
PP3V3_SUS
R21941
FCBGA
(6 OF 10)
OMIT
ISOLATE_CPU_MEM_L
23 19
R21921
SMC_SCI_L
(NC-ed per Intel chklist)
88 33 23 19 8
CLKOUT_PCIE6N V40
CLKOUT_PCIE6P V42
IN
35 19
71 46 22 20 19 18 17 16 7
73 72
(IPU)
COUGAR-POINT
MOBILE
C4
LPCPLUS_GPIO
(PU necessary?)
PCH_GPIO12
PCH_GPIO15
19
PD on audio page
62 23
OUT AUD_IPHS_SWITCH_EN
NC
C10
U1800
BMBUSY*/GPIO0
GPIO
IN
RSVD
23 19
CPU
NCTF
19
SIZE
D
REVISION
R
19
19

19
BRANCH
PAGE
21 OF 132
SHEET
19 OF 105
MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V
C2210
102 88 72 71 25 20 14 7 6
20%
10V
22
PLACE_NEAR=U1800.V16:2.54mm
AF17
PPVCCIO_S0_PCH
104 102 22 20 17 16
PP1V05_S0_PCH_VCCADPLLA_F BD47
PP1V05_S0_PCH_VCCADPLLB_F BF47
22
402
Y49
PP1V8_S0
0.1UF
2 CERM
N16
AF33
AF34
AG34
PPVCCIO_S0_PCH
55mA Max, 5mA Idle
104 102 22 20 17 16
104 102 22 20 17 16
AG33
PPVCCIO_S0_PCH
V16
PPVOUT_S0_PCH_DCPSST
VOLTAGE=3.3V
T17
C2222
NC-ed per DG
0.1UF
2
20%
10V
CERM
402
104 102 22 20 17 16
25 17 16 7
NC
V19
NC
BJ8 V_PROC_IO
PPVCCIO_S0_PCH
A22 VCCRTC
PPVRTC_G3H
C2231
C2232
1UF
0.1UF
10%
6.3V
CERM
402
20%
10V
CERM
402
AA16
W16
T34
PP3V3_S0_PCH
AJ2
PP3V3_S0_PCH
16 17 18 19 20 22 102
PPVCCIO_S0_PCH
16 17 20 22 102 104
16 17 18 19 20 22 102
104 102 22 20 17 16
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
PPVCCIO_S0_PCH
1.44 A Max, 474mA Idle
AF13
AH13
AH14
AF14
AK1
NC VCCAPLLSATA pin left as NC per DG
AF11
PP1V8_S0
6 7 14 20 25 71 72 88 102
AC16
AC17
AD17
PPVCCIO_S0_PCH
16 17 20 22 102 104
T21
V21
T19
PPVCCIO_S0_PCH
N26
P26
P28
T27
T29
PPVCCIO_S0_PCH
16 17 20 22 102 104
104 102 22 20 17 16
104 102 22 20 17 16
PP3V3_SUS
T26
PPVCCIO_S0_PCH
16 17 20 22 102 104
PP5V_SUS_PCH_V5REFSUS
22
M26
AN23
NC-ed per DG
AN24
PP3V3_SUS
NC
VCCSUSHDA P32
U1800
COUGAR-POINT
MOBILE
TP_1V05_S0_PCH_VCCAPLLEXP
BJ22 VCCAPLLEXP
PPVCCIO_S0_PCH
AN16 VCCIO_17_FDI
AN17 VCCIO_18_FDI
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
7 16 17 18 19 20 22 46 71 72 73
VCCIO_19_PCIE
VCCIO_20_PCIE
VCCIO_21_PCIE
VCCIO_22_PCIE
VCCIO_23_PCIE
VCCIO_24_PCIE
VCCIO_25_PCIE
VCCIO_26_PCIE
AN33 VCCIO_27_DP
AN34 VCCIO_28_DP
102 22 20 19 18 17 16
FCBGA
(7 OF 10)
OMIT
VCCALVDS AK36
PP3V3_S0_PCH
16 17 18 19 20 22 102
VSSALVDS AK37
AM37
AM38
AP36
AP37
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCC3_3_6_HVCMOS V33
VCC3_3_7_HVCMOS V34
VCCVRM_3_DMI AT16
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
22
PP3V3_S0_PCH
16 17 18 19 20 22 102
PPVCCIO_S0_PCH
PP1V05_S0_PCH_VCCCLKDMI_F
AG16
AG17
AJ16
AJ17
VCCSPI V1
VCCADAC U48
VCCVRM_2_FDI AP16
VCCAFDIPLL BG6 NC
PP1V8_S0_PCH_VCCTX_LVDS_F
PP1V8_S0
VCCDMI_1_DMI AT20
VCCCLKDMI AB36
AN19 VCCIO_11_PLLPCIE
PPVCCIO_S0_PCH
16 17 20 22 102 104
T23
T24
V23
V24
P24
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
LVDS
7 16 17 18 19 20 22 46 71 72 73
VCC CORE
22
PP3V3_SUS
HVCMOS
PP5V_S0_PCH_V5REF
N20
N22
P20
P22
DMI
PCI/GPIO/
LPC
SATA
CLK/MISC
P34
DFT/SPI
PCH output, for decoupling only

PPVOUT_G3_PCH_DCPRTC
MISC
USB
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
PPVCCIO_S0_PCH
CPU
AL24
NC
HDA
AL29
AL24 left as NC per DG
RTC
BH23
NC
PPVCCIO_S0_PCH
104 102 22 20 17 16
T38
PP3V3_S0_PCH_VCC3_3_CLK_F
VCCAPLLDMI2 pin left as NC per DG

104 102 22 20 17 16
V5REF
FCBGA
(8 OF 10)
OMIT VCCSUS3_3_5_GPIO
VCC3_3_4_CLK
VCCSUS3_3_6_GPIO
VCCSUS3_3_7_GPIO
VCCAPLLDMI2
VCCSUS3_3_8_GPIO
VCCIO_12_PLLCLK
VCC3_3_2_GPIO
VCC3_3_3_GPIO
DCPSUS_0_CLK
VCC3_3_1_GPIO
VCCASW_3_CLK
VCCASW_4_CLK
VCC3_3_0_SATA
VCCASW_5_CLK
VCCASW_6_CLK
VCCIO_5_PLLSATA
VCCASW_7_CLK
VCCIO_15_SATA3
VCCASW_8_CLK
VCCIO_16_SATA3
VCCASW_9_CLK
VCCASW_10_CLK
VCCIO_9_PLLSATA3
VCCASW_11_CLK
VCCAPLLSATA
VCCASW_12_CLK
VCCVRM_1_SATA
VCCASW_13_CLK
VCCASW_14_CLK
VCCIO_6_SATA
VCCASW_15_CLK
VCCIO_7_SATA
VCCASW_16_CLK
VCCIO_8_SATA
VCCASW_17_CLK
VCCASW_18_CLK
VCCASW_2_MISC
VCCASW_19_CLK
VCCASW_1_MISC
VCCASW_20_CLK
VCCASW_0_MISC
VCCASW_21_CLK
VCCASW_22_CLK
VCCIO_0_USB
VCCIO_1_USB
DCPRTC
VCCIO_2_USB
VCCVRM_0_CLK
VCCIO_3_USB
VCCADPLLA
VCCIO_4_USB
VCCADPLLB
VCCSUS3_3_1_USB
VCCSUS3_3_2_USB
VCCIO_13_CLK
VCCSUS3_3_3_USB
VCCDIFFCLKN_0
VCCSUS3_3_4_USB
VCCDIFFCLKN_1
VCCSUS3_3_9_USB
VCCDIFFCLKN_2
VCCIO_14_PLLUSB
VCCSSC
V5REF_SUS
DCPSST
DCPSUS_3_SUS
DCPSUS_1_CLK
DCPSUS_2_CLK
VCCSUS3_3_0_SUS
V12 DCPSUSBYP
TP_PPVOUT_PCH_DCPSUSBYP
22
U1800
COUGAR-POINT
MOBILE
CRT
T16 VCCDSW3_3
VCCIO
AD49 VCCACLK
NC
PP3V3_S5
FDI
VCCACLK pin left as NC per DG

71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
6 7 14 20 25 71 72 88 102
16 17 20 22 102 104
22
PP1V8_S0_PCH
17 22 102
PP3V3_S5
100 102 104

6 7 17 19 20 22 23 24 25 29
46 48 56 71 72 73 83 86 91
PP3V3_S0_PCH_VCCA_DAC_F
22
PP1V8_S0
6 7 14 20 25 71 72 88 102
VCCAFDIPLL pin left as NC per DG
VCCIO_10_PLLFDI AP17
PPVCCIO_S0_PCH
VCCDMI_0_FDI AU20
PPVCCIO_S0_PCH
16 17 20 22 102 104
16 17 20 22 102 104
BH29 VCC3_3_5_PCI
PP3V3_S0_PCH
B
7 16 17 18 19 20 22 46 71 72 73
PP1V5_S0
7 16 22 25 32 41 57 71
10 mA Max, 1mA Idle
C2233
0.1UF
20%
10V
CERM
402
A
PAGE TITLE
PCH POWER
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
22 OF 132
SHEET
20 OF 105
AJ3
N24
BG29
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD14
AD16
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD47
AD8
AE2
AE3
AF10
AF12
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
AK38
AK4
AK42
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
COUGAR-POINT
MOBILE
FCBGA
(9 OF 10)
VSS
OMIT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP13
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV11
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AY12
AY22
AY28
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35 VSS
B39 VSS
B43 VSS
B7 VSS
BB12 VSS
BB16 VSS
BB20 VSS
BB22 VSS
BB24 VSS
BB28 VSS
BB30 VSS
BB38 VSS
BB4 VSS
BB46 VSS
BC14 VSS
BC18 VSS
BC2 VSS
BC22 VSS
BC26 VSS
BC32 VSS
BC34 VSS
BC36 VSS
BC40 VSS
BC42 VSS
BC48 VSS
BD3 VSS
BD46 VSS
BD5 VSS
BE10 VSS
BE22 VSS
BE26 VSS
BE40 VSS
BF10 VSS
BF12 VSS
BF16 VSS
BF20 VSS
BF22 VSS
BF24 VSS
BF26 VSS
BF28 VSS
BF30 VSS
BF38 VSS
BF40 VSS
BF8 VSS
BG17 VSS
BG21 VSS
BG22 VSS
BG24 VSS
BG33 VSS
BG41 VSS
BG44 VSS
BG8 VSS
BH11 VSS
BH15 VSS
BH17 VSS
BH19 VSS
BH27 VSS
BH31 VSS
BH33 VSS
BH35 VSS
BH39 VSS
BH43 VSS
BH7 VSS
C22 VSS
D12 VSS
D16 VSS
D18 VSS
D22 VSS
D24 VSS
D26 VSS
D3 VSS
D30 VSS
D32 VSS
D34 VSS
D38 VSS
D42 VSS
D8 VSS
E18 VSS
E26 VSS
F3 VSS
F45 VSS
G14 VSS
G18 VSS
G20 VSS
G26 VSS
G28 VSS
G36 VSS
U1800
COUGAR-POINT
MOBILE
FCBGA
(10 OF 10)
VSS
OMIT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G48
H10
H12
H16
H18
H22
H24
H26
H30
H32
H34
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
M14
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
N47
P11
P16
P18
P30
P40
P43
P47
P7
R2
R48
T12
T31
T33
T36
T37
T4
T46
T47
T8
V11
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W34
W48
Y12
Y38
Y4
Y42
Y46
Y8
V17
AP3
AP1
BE16
BC16
BG28
BJ28
SYNC_MASTER=K92_YUN
PAGE TITLE
PCH GROUNDS
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
23 OF 132
SHEET
21 OF 105
CRITICAL
PP1V8_S0_PCH
102 22 20 17
PPVCCIO_S0_PCH
PCH VCCSUS3_3 BYPASS
L2406
10UH-0.45A
22 20 17 16
104 102
(PCH SUSPEND USB 3.3V PWR)
R2415
1
2 PP1V05_S0_PCH_VCCCLKDMI_R 1
VOLTAGE=1.05V
1210-HF
72 71 46 22 20 19 18 17 16 7
73
20
PP1V05_S0_PCH_VCCCLKDMI_F
1
1
C2411
1UF
10%
16V
C2484
C2413
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
C2440
0.1UF
PLACE_NEAR=U1800.AJ16:2.54mm
2
402
C2444
PCH VCCIO BYPASS

(PCH USB 1.05V PWR)
PPVCCIO_S0_PCH
20 17 16
C2452
1UF
20%
10V
CERM
402
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2446
1UF
PLACE_NEAR=U1800.P28:2.54mm
2
10%
6.3V
CERM
402
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm
2 X5R
PPVCCIO_S0_PCH
104 102 22
PP3V3_SUS
VOLTAGE=1.05V
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
104 102 22 20 17 16
PCH VCCSUSHDA BYPASS
71 57 41 32 25 20 16 7
PP1V5_S0
CRITICAL
L2407
0.1UH
PP1V8_S0_PCH
22 20 17
102
20
PP1V8_S0_PCH_VCCTX_LVDS_F
VOLTAGE=1.8V
0805
104 102 22 20 17 16
PPVCCIO_S0_PCH
C2406
C2408
C2416
22UF
0.01UF
0.01UF
4.7UF
20%
6.3V
CERM
805
10%
16V
CERM
402
10%
16V
CERM
402
20%
6.3V
X5R
402
C2417
0.1UF
2
1
1
10%
6.3V
CERM
402
C2442
1UF
PP3V3_S0_PCH_VCCA_DAC_F
20
10%
6.3V
CERM
402
104 102 22 20 17 16
PPVCCIO_S0_PCH
104 102 22 20 17 16
PPVCCIO_S0_PCH
MAKE_BASE=TRUE
5%
1/20W
MF
201
VOLTAGE=3.3V
PCH VCCIO BYPASS
C2434
PPVCCIO_S0_PCH
10%
6.3V
CERM
402
2
1
C2455
0.1UF
10%
16V
X5R
402
1
2
0.01UF
10%
16V
CERM
402
10%
6.3V
CERM
402
PP3V3_S5
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
C2499
20%
10V
CERM
402
104 102 22 20 17 16
CRITICAL
100
C2439
10%
10V
X5R
402
5%
1/16W
MF-LF
402
SOT-363
PP3V3_S0_PCH_VCC3_3_CLK_R
VOLTAGE=3.3V
C2453
20%
6.3V
X5R
603
10%
10V
X5R
402
104 102 22 20 17 16
10
NC
10UH-0.12A-0.36OHM
5%
1/16W
MF-LF
402
L2491
10UH-0.12A-0.36OHM
PP1V05_S0_PCH_VCCADPLLB_R
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
102 22 20 19 18 17 16
C2420
C2426
C2456
C2496
C2428
1UF
1UF
1UF
22UF
22UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20
68 mA
C2492
1UF
10%
2 6.3V
CERM
402
2
0603
C2493 1
220UF
20%
2.5V 2
POLY-TANT
CASE-B2-SM1
PP3V3_S0_PCH
104 102 22 20 17 16
PPVCCIO_S0_PCH
PCH VCCADPLLB Filter

(PCH DPLLB PWR)
CRITICAL
20 22
R2491
PP1V05_S0_PCH_VCCADPLLA_F
VOLTAGE=1.05V
CRITICAL
PP3V3_S0_PCH
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM
<1 MA S0-S5
NO STUFF
C2491 1
20 22
102 22 20 19 18 17 16
2
0603
220UF
NEED PWR CONSTRAINT
0.1UF
20%
10V
CERM
402
VOLTAGE=1.05V
BAT54DW-X-G
VOLTAGE=5V
MAKE_BASE=TRUE
PP1V05_S0_PCH_VCCADPLLA_R
SOT-363
3
20%
6.3V
CERM
805
PPVCCIO_S0_PCH
PCH VCCADPLLA Filter

(PCH DPLLA PWR)
20%
2.5V 2
POLY-TANT
CASE-B2-SM1
C2438
D2400
NC
5%
1/16W
MF-LF
402
PLACE_NEAR=U1800.M26:2.54mm
PPVCCIO_S0_PCH
4
2
10UF
PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)
R2404 2
104 102 22 20 17 16
1 mA S0-S5
C2460
10%
6.3V
CERM
402
20 22
R2490
CRITICAL1
1UF
PP3V3_SUS
PP5V_SUS
C2483
10%
6.3V
CERM
402
1UF
2
L2490
72 7
1UF
C2454
CRITICAL
72 71 46 22 20 19 18 17 16 7
73
C2482
10%
6.3V
CERM
402
CRITICAL
<1 MA
PP5V_S0_PCH_V5REF
10UF
NEED PWR CONSTRAINT

PP5V_S0_PCH_V5REF
20 22
VOLTAGE=5V
MAKE_BASE=TRUE
1UF
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
20 PP3V3_S0_PCH_VCC3_3_CLK_F
VOLTAGE=3.3V
1
0603
1UF
BAT54DW-X-G
NC
NC
5%
1/16W
MF-LF
402 1
PP3V3_S0_PCH
D2400
10UH-0.12A-0.36OHM
R2451
102 22 20 19 18 17 16
R2405 2
C2481
L2451
PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)
1 mA
PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)
PPVCCIO_S0_PCH
PP3V3_S0_PCH
PP5V_S0
0.1UF
PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)
PLACE_NEAR=U1800.AT20:2.54mm
104 87 73 70 69 68 65 54 52 47 41 8 7 6
105
10%
6.3V
CERM
402
C2419
PLACE_NEAR=U1800.U48:2.54mm
102 22 20 19 18 17 16
1UF
C2451
10UF
C2469
1UF
1UF
104 102 22 20 17 16
20%
6.3V
CERM
805
10%
6.3V
CERM
402
PP3V3_S5
CRITICAL
C2450 1
C2476
1UF
1UF
10%
16V
X5R
402
C2475
C2430
R2450
0
PP3V3_SUS
0.1UF
10%
16V
X5R
402
48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72 71 56
72 71 46 22 20 19 18 17 16 7
73
PPVCCIO_S0_PCH
PLACE_NEAR=U1800.AM37:2.54mm
PP3V3_S0_PCH
104 102 22 20 17 16
20%
10V
CERM
402
CRITICAL
C2400 1
22 20
17 16
19 18
102
C2441
0.1UF
PP1V05_S0_PCH_VCCADPLLB_F
VOLTAGE=1.05V
20
69 mA
2
NO STUFF
C2494
C2429
0.1UF
C2423
C2407
C2463
C2401
1UF
1UF
1UF
10UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
16V
X5R-CERM
0805
1UF
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.BF47:2.54MM
PLACE_NEAR=U1800.BF47:2.54MM
C2421
C2414
1UF
PLACE_NEAR=U1800.AN27:2.54mm
CRITICAL
0.1UF
10%
16V
2 X5R
402
10%
16V
X5R
402
PLACE_NEAR=U1800.BH29:2.54mm
SYNC_MASTER=K91_YUN
102 22 20 19 18 17 16
PCH DECOUPLING
1
C2424
102 22 20 19 18 17 16
0.1UF
DRAWING NUMBER
PP3V3_S0_PCH
Apple Inc.
10%
2 16V
X5R
402
C2486
0.1UF
2
C2485
SIZE
D
REVISION
0.1UF
10%
25V
X5R
402
10%
25V
X5R
402

PLACE_NEAR=U1800.AA16:2.54mm
PAGE TITLE
PP3V3_S0_PCH
BRANCH
PAGE
24 OF 132
SHEET
22 OF 105
PROCESSOR MINI XDP
DESIGN NOTE:
ODT AVAILABLE ON JTAG
102 100 91 89 88 85
48 46 41 40 39 36 35 32 28 26 25 12 7 6
84 83 80 73 72 62 61 57 54 52 51 50 49
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
PP3V3_S0
NOSTUFF
1
CRITICAL
XDP_CONN
1K
5%
1/16W
MF-LF
402
92 10
92 10
IN
92 10
IN
92 10
IN
92 10
IN
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
0
0
R2560 5% 1
R2561 5%MF1
R2562 5%MF1
R2563 5%MF1
2
2
XDP_CPU_BPM
XDP_CPU_BPM
XDP_CPU_BPM
XDP_CPU_BPM
1/20W
201
1/20W
201
1/20W
201
1/20W
201
MF
IN
92 10
IN
92 10
92 10
92 10
IN
92 9
IN
92 9
IN
IN
IN
IN
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
R2564 5% 1
R2565 5%MF1
R2566 MF
5% 1
R2567 5%MF1
0
0
MF
PLACE_NEAR=U1000.C60:2.54mm
IN
IN
CPU_PWRGD
5%
1K
92
95
30 28 26 23 16 6
89 62 48 41 32
XDP
30 28 26 23 16 6
89 62 48 41 32
95
R2501
OUT
CPU_CFG<0>
5%
1K
OBSDATA_B2
OBSDATA_B3
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
1/20W
MF
201
92 23 9
OBSDATA_B0
OBSDATA_B1
XDP_CPU_CFG<0>
XDP_VR_READY
XDP
R2502
0
2
PM_PWRBTN_L
5% 1
OUT
45 23 17
OBSFN_B0
OBSFN_B1
1/20W
MF
201
OBSDATA_A2
OBSDATA_A3
XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>
XDP
1
OBSDATA_A0
OBSDATA_A1
XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>
R2500
92 19 10
OBSFN_A0
OBSFN_A1
CPU_CFG<10>
CPU_CFG<11>
XDP_CPU_CFG
XDP_CPU_CFG
XDP_CPU_CFG
XDP_CPU_CFG
1/20W
201
1/20W
201
2 1/20W
201
2 1/20W
201
F-ST-SM-HF
XDP_BPM_L<2>
XDP_BPM_L<3>
IN
1/20W
92 23 10
MF
201
IN
SMBUS_PCH_DATA
SMBUS_PCH_CLK
OUT
XDP_CPU_TCK
BI
SDA
SCL
TCK1
TCK0
XDP
OUT
PM_PCH_SYS_PWROK
5%
330
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
C2500
1/20W
10%
16V
X5R
402
MF
201
OBSFN_C0
OBSFN_C1
CPU_CFG<16>
CPU_CFG<17>
IN
9 92
IN
9 92
OBSDATA_C0
OBSDATA_C1
CPU_CFG<0>
CPU_CFG<1>
IN
9 23 92
92 23 10
IN
9 92
92 23 10
OBSDATA_C2
OBSDATA_C3
CPU_CFG<2>
CPU_CFG<3>
IN
9 92
IN
9 92
OBSFN_D0
OBSFN_D1
CPU_CFG<8>
CPU_CFG<9>
IN
9 92
IN
9 92
OBSDATA_D0
OBSDATA_D1
CPU_CFG<4>
CPU_CFG<5>
IN
9 92
IN
9 92
51
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
IN
9 92
IN
9 92
XDP
PLACE_NEAR=U1000.H63:2.54mm
CPU_CFG<6>
CPU_CFG<7>
517S0774
2
PLACE_NEAR=U1000.J58:2.54mm
R25141
51
51
5%
1/20W
MF
201
5%
1/20W
MF
201
PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*
TERM NEAR CPU
R2515
5%
MF
201
1/20W
ITPXDP_CLK100M_P
IN
16 92
R2516
5%
1/20W
ITPXDP_CLK100M_N
IN
16 92
1/20W
PLT_RST_CPU_BUF_L
IN
10 25
MF
201
XDP
OUT
R2505
10 23 25 92
5%
IN
OUT
10 23 92
OUT
10 23 92
OUT
10 23 92
1K
MF
201
10 23 92
PLACE_NEAR=U1000.G3:2.54mm
C
PP1V05_SUS
XDP
PLACEMENT NOTE:
C2501
PLACE TDO TERM NEAR

PCH XDP CONN
0.1uF
XDP
R25131
XDP
XDP
92 XDP_CPU_CLK100M_P
ITPCLK/HOOK4
92 XDP_CPU_CLK100M_N
ITPCLK#/HOOK5
VCC_OBS_CD
92 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
XDP_CPU_TDO
TDO
XDP_CPU_TRST_L
TRSTn
XDP_CPU_TDI
TDI
XDP_CPU_TMS
TMS
XDP_PRESENT#
92 23 10
OBSDATA_D2
OBSDATA_D3
XDP
R25121
51
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
92 23 10
92 23 10
0.1uF
XDP
R25111
51
PLACE_NEAR=J2500.52:2.54mm2
XDP
R2504
91 17
XDP
R25101
DF40C-60DS-0.4V
2
XDP_BPM_L<0>
XDP_BPM_L<1>
IN
PLACE TDO TERM NEAR

SNB XDP CONN
J2500
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
BI
92 10
45 68 70 73
7 9 10 12 13
14 23 35 39
102 104 105
PLACEMENT NOTE:
R2540
PP1V05_S0
PP1V05_S0
XDP1
10%
16V
X5R
402
XDP
R25511
R2550
PLACE_NEAR=J2550.52:2.54mm
7 71
XDP
R25521
51
51
51
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK
23 16
23 16
23 16
23 16
PCH MINI XDP
XDP
R25561
72 71 56 48 46 29 25 24 22 20 19 17 7 6
104 102 100 91 86 83 73
PP3V3_S5
51
5%
1/20W
MF
201
CRITICAL
XDP_CONN
J2550
DF40C-60DS-0.4V
F-ST-SM-HF
XDP
B
19
IN
PCH_GPIO46
24 18
IN
USB_HUB_SOFT_RESET_L
18
IN
SDCONN_STATE_RST_L
PLACE_NEAR=U1800.C16:2.54mm
18
IN
ENET_PWR_EN
18
IN
SDCONN_STATE_CHANGE
91 88 73 45
IN
ALL_SYS_PWRGD
45 23 17
OUT
PM_PWRBTN_L
5% 1
MF
TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>
2 1/20W
201
XDP
R2580
5% 1
MF
XDP_PCH_GPIO46
XDP_PCH_USB_HUB_SOFT_RST_L
2 1/20W
201
XDP
5% 1
MF
2 1/20W
201
5% 1
MF
18
IN
R2581
5% 1
MF
2 1/20W
201
XDP
18
IN
18
IN
R2584
5% 1
MF
1K
OBSFN_B0
OBSFN_B1
PCH_GPIO43_OC4_L
XDP_PCH_SDCONN_DET_L
OBSDATA_B0
OBSDATA_B1
PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L
OBSDATA_B2
OBSDATA_B3
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
2 1/20W
201
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP
R2585
5% 1
MF
R2578
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2 1/20W
201
XDP
OBSDATA_A2
OBSDATA_A3
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>
XDP
R2587
0
OBSDATA_A0
OBSDATA_A1
XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN
R2586
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
2 1/20W
201
62 48 41 32 30 28 26 23
95
62 48 41 32 30 28 26 23
95
OBSFN_A0
OBSFN_A1
16 6
89
16 6
89
23 16
BI
IN
OUT
SMBUS_PCH_DATA
SMBUS_PCH_CLK
XDP_PCH_TCK
NC
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
2 1/20W
201
R2576
XDP_FW_CLKREQ_L
XDP_AP_CLKREQ_L
5% 1
MF
DP_AUXCH_ISOL
IN
16 85
SATARDRVR_EN
IN
16 41
OBSFN_D0
OBSFN_D1
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
OBSDATA_D0
OBSDATA_D1
PCH_GPIO36_SATA2GP
JTAG_ISP_TCK
IN
19
IN
8 19 33 88
IN
19 29
5% 1
MF
FW_CLKREQ_L
IN 16
2 1/20W
201
XDP
OBSDATA_C2
OBSDATA_C3
ISOLATE_CPU_MEM_L
XDP
19
PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*
TERM NEAR PCH
39
PLACE_NEAR=U1800.M1:2.54mm
2 1/20W
201
AP_CLKREQ_L
IN
16 31
26
28
29
30
31
32
R2579
33
34
35
36
37
38
39
40
41
42
43
44
OBSDATA_D2
OBSDATA_D3
TP_XDP_PCH_HOOK4
ITPCLK/HOOK4
TP_XDP_PCH_HOOK5
ITPCLK#/HOOK5
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
XDP_PCH_TDO
TDO
TP_XDP_PCH_TRST_L
TRSTn
XDP_PCH_TDI
TDI
XDP_PCH_TMS
TMS
XDP_PRESENT#
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
XDP_PCH_AUD_IPHS_SWITCH_EN
PCH_GPIO49_SATA5GP
5% 1
MF
IN
IN
OUT
XDP
2 1/20W
201
AUD_IPHS_SWITCH_EN
IN
19 62
19
25
1K series R on PCH Support P. 28
10 23 25 92
IN
16 23
OUT
16 23
OUT
16 23
SYNC_MASTER=K91_MLB
PAGE TITLE
CPU & PCH XDP

DRAWING NUMBER
XDP
1
0.1uF
10%
16V
X5R
402
5% 1
MF
IN
R2577
XDP
C2580
XDP_PCH_ISOLATE_CPU_MEM_L
PCH_GPIO0
27
45
SDA
SCL
TCK1
TCK0
XDP
R2582
PLACE_NEAR=U1800.J3:2.54mm
517S0774
C2581
Apple Inc.
0.1uF
10%
16V
X5R
402

SIZE
REVISION
BRANCH
PAGE
25 OF 132
SHEET
23 OF 105
L2600
VOLTAGE=3.3V
0402
C2600
0.01UF
C2601 C2602
100PF
10UF
20%
6.3V 2
X5R
603
5%
2 50V
CERM
402
10%
2 16V
CERM
402
C2603
C2606 C2607
100PF
10UF
5%
2 50V
CERM
402
20%
6.3V 2
X5R
603
C2608
C2609
0.1UF
0.1UF
10%
16V
X7R-CERM 2
402
10%
16V
X7R-CERM 2
402
C2610
Y2600
SM-2
VDDA33
C2619
10K
100
5%
1/16W
MF-LF
402
24
R2604
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
USB_HUB_RESET_L 26
100PF
10%
16V
2 CERM
402
5%
50V
2 CERM
402
1
2
USB_T29A_N
USB_T29A_P
BI
8 94
BI
8 94
44 94
BI
44 94
USB_HUB1_NONREM0
28
6
7
USB_EXTB_N
USB_EXTB_P
BI
42 94
BI
42 94
USB_HUB1_NONREM1
22
USBDN3_DM/PRT_DOS_M3
SUSP_IND/LOCAL_PWR/NON_REM0
USBDN3_DP/PRT_DIS_P3
SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4
SCL/SMBCLK/CFG_SEL0
8
9
USB_EXTC_N
USB_EXTC_P
BI
43 94
BI
43 94
HS_IND/CFG_SEL1
PRTPWR1
PRTPWR2
PRTPWR3
PRTPWR4
12
16
18
20
TP_USB_HUB1_PRTPWR1
NC_USB_HUB1_PRTPWR2
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR4
OCS1*
OCS2*
OCS3*
OCS4*
13
17
19
21
TP_USB_HUB1_OCS1
NC_USB_HUB1_OCS2
USB_EXTB_OC_L
USB_EXTC_OC_L
RBIAS
35
VBUS_DET
27
USB_HUB1_VBUS_DET
USBUP_DM
USBUP_DP
30
31
USB_HUB1_UP_N
USB_HUB1_UP_P
USB_HUB1_CFG_SEL0
24
USB_HUB1_CFG_SEL1
25
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
IPU
IPU
IPU
IPU
C2653 1
20%
6.3V
X5R 2
603
0.1UF
0.1UF
10%
16V
X7R-CERM 2
402
10%
16V
X7R-CERM 2
402
1 VOLTAGE=3.3V
0.1UF
10%
16V
X7R-CERM 2
402
VDDA33
C2669
18PF
HUB2_NONREM0_1 402
R26511
R2653
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
HUB2_NONREM1_0
CRITICAL
2 4
5%
50V
CERM 2
HUB2_NONREM1_1
3
1
R2680
1
1M
18PF
5%
1/16W
MF-LF
402
100
5%
1/16W
MF-LF
402
CRITICAL
R2654
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
USB_HUB2_TEST
2
24
11
USB_HUB_RESET_L 26
USB_HUB2_XTAL1
USB_HUB2_XTAL2
33
32
OMIT
XTAL1/CLKIN
XTAL2
28
SUSP_IND/LOCAL_PWR/NON_REM0
22
SDA/SMBDATA/NON_REM1
USB_HUB2_CFG_SEL0
24
SCL/SMBCLK/CFG_SEL0
USB_HUB2_CFG_SEL1
25
HS_IND/CFG_SEL1
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
10%
2 16V
CERM
402
VOLTAGE=1.8V
USBHUB_2061
SMSC USB2514B
U2600,U2650
338S0721
SMSC USX2061
U2600,U2650
CRITICAL
8 43
5%
1/16W
MF-LF
2 402
PP3V3_S3
54 50 49 48 32 31 30 29 25 24 18 8 7 6
104 88 73 55
PP3V3_S5
CRITICAL
BI
18 94
BI
18 94
20K
72 71 56 48 46 29 25 23 22 20 19 17 7 6
104 102 100 91 86 83 73
5%
1/16W
MF-LF
402
R2600
12K
1%
1/16W
MF
2 402
R2641
10K
R2642
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
NOSTUFF
1
C2641
2402
100PF
5%
50V
2 CERM
402
USB_HUB_RESET
USB_HUB_RESET_L
0.01UF
10%
2 16V
CERM
402
P3V3S3_EN_RC
Q2640
C2667
0.1UF
C2665
C2666
1UF
10%
16V
2 X7R-CERM
402
Q2640
2N7002DW-X-G
SOT-363
0.1UF
2N7002DW-X-G
SOT-363
C2640
0.47UF
C2668
10%
6.3V
2 CERM-X5R
402
1UF
10%
16V
2 X5R
402
10%
2 16V
X5R
402
D2600
SOD-523
23 18
IN
USB_HUB_SOFT_RESET_L
BAT54XV2T1
1
2
USB_BT_N
USB_BT_P
3
4
USBDN3_DM/PRT_DOS_M3
6
7
8
9
THRML_PAD
37
USBHUB_2514B
338S0824
C2664
10%
2 16V
X7R-CERM
402
IPU
IPU
IPU
IPU
(SYM-VER1)
USBHUB_2514
R2640
BI
6 31 94
BI
6 31 94
USB_TPAD_N
USB_TPAD_P
BI
53 94
BI
53 94
USB_EXTA_N
USB_EXTA_P
BI
42 94
BI
42 94
BI
8 32
100
BI
8 32 100
RESET*
USB_HUB2_NONREM1
10K
CRITICAL
10K
IN
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
C2663
0.01UF
10%
2 16V
X7R-CERM
402
R2656 1R2657
C2662
0.1UF
USX2061
TEST
USB_HUB2_NONREM0
10K
U2600,U2650
CRITICAL
QFN
R2655
HUB2_NONREM0_0
R26521
SMSC USB2514
U2650
C2670
5%
50V
2 CERM
402
R2620
42
PPUSB_HUB2_VDD1V8PLL
Y2650
SM-2
BOM OPTION
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
PPUSB_HUB2_VDD1V8
24.000MHZ-16PF
CRITICAL
1
IN
VOLTAGE=1.8V
CRITICAL
CRITICAL
10%
2 16V
X7R-CERM
402
PPUSB_HUB2_VDDA3V3
10UF
C2661
0.1UF
VDD33 23
100PF
5%
50V
2 CERM
402
PP3V3_S3
USB_HUB1_RBIAS
PP3V3_S3
C2659 1 C2660
REFERENCE DESIGNATOR(S)
External C
100K
10%
16V
X7R-CERM 2
402
C2658 1
DESCRIPTION
External B
0.1UF
QTY
IR Receiver
THRML_PAD
(SYM-VER1)
NON_REM0
DESCRIPTION
All ports are removable
Port 1 is non removable
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable
TABLE_5_ITEM
T29 unused USB port, only has pull up
BI
C2656 C2657 1
1UF
10%
16V
2 X5R
402
0
1
0
1
BOM TABLE
USB_IR_N
USB_IR_P
VDD33CR 15
10%
16V
2 CERM
402
1UF
NON_REM1
0
0
1
1
C2618
TABLE_5_ITEM
OMIT
VDD33PLL 36
0.01UF
20%
6.3V
2 X5R
603
C2655
10%
16V
2 X7R-CERM
402
C2616
10%
16V
2 X5R
402
RESET*
5
29
10
10UF
3
4
0402
C2654
0.1UF
C2615
FERR-120-OHM-1.5A
HUB2_NONREM1_1,HUB2_NONREM0_1
TABLE_5_HEAD
USX2061
TEST
L2651
C2617
VOLTAGE=3.3V
20%
6.3V
X5R 2
603
HUB2_3NONREM
PART#
PPUSB_HUB2_VDDPLL3V3
10UF
HUB2_2NONREM
TABLE_BOMGROUP_ITEM
XTAL1/CLKIN
XTAL2
10K
C2651 C2652 1
TABLE_5_ITEM
VDD18PLL 34
HUB2_1NONREM
TABLE_BOMGROUP_ITEM
10%
2 16V
CERM
402
338S0720
VDD18 14
0.01UF
0.01UF
37
C2650
HUB2_ALLREM
TABLE_BOMGROUP_ITEM
C2614
0.1UF
0402
1
10%
16V
2 X7R-CERM
402
FERR-120-OHM-1.5A
1
10%
2 16V
CERM
402
VOLTAGE=1.8V
L2650
PP3V3_S3
C2613
0.01UF
10%
2 16V
X7R-CERM
402
R2606 R2607
104 88
30 29 25 24 18 8 7 6
73 55 54 50 49 48 32 31
0.1UF
33
32
USB_HUB1_XTAL1
USB_HUB1_XTAL2
R2602
11
USB_HUB1_TEST
HUB1_NONREM0_0
QFN
R2605
5%
50V
2 CERM
402
CRITICAL
5%
1/16W
MF-LF
2 402
HUB1_NONREM1_0
1M
HUB1_3NONREM
U2600
C2620
18PF
5%
1/16W
MF-LF
402
R2603
10K
5%
1/16W
MF-LF
402 2
R2630
5%
50V
CERM 2
HUB1_NONREM0_1 402
R26011
CRITICAL
2 4
18PF
HUB1_NONREM1_1
C2612
PPUSB_HUB1_VDD1V8PLL
24.000MHZ-16PF
1
PPUSB_HUB1_VDD1V8
10%
16V
X7R-CERM 2
402
CRITICAL
CRITICAL
104
6 7 8 18 24 25 29 30 31
32 48 49 50 54 55 73 88
VOLTAGE=1.8V
0.1UF
VDD33 23
0.01UF
1 VOLTAGE=3.3V
VDD33CR 15
C2605
10%
2 16V
CERM
402
10%
2 16V
X7R-CERM
402
PPUSB_HUB1_VDDA3V3
C2611
0.1UF
VDD33PLL 36
10UF
20%
2 6.3V
X5R
603
HUB1_2NONREM
TABLE_BOMGROUP_ITEM
PP3V3_S3
5
29
10
C2604
TABLE_BOMGROUP_ITEM
10%
16V
X7R-CERM 2
402
0402
1
HUB1_1NONREM
TABLE_BOMGROUP_ITEM
L2601
0.1UF
FERR-120-OHM-1.5A
1
BOM OPTIONS
HUB1_ALLREM
TABLE_BOMGROUP_ITEM
VDD18 14
BOM GROUP
TABLE_BOMGROUP_ITEM
PPUSB_HUB1_VDDPLL3V3
VDD18PLL 34
PP3V3_S3
1
TABLE_BOMGROUP_HEAD
FERR-120-OHM-1.5A
104
31 30 29 25 24 18 8 7 6
88 73 55 54 50 49 48 32
USB_EXCARD_N
USB_EXCARD_P
PRTPWR1
PRTPWR2
PRTPWR3
PRTPWR4
12
16
18
20
OCS1*
OCS2*
OCS3*
OCS4*
13
17
19
21
TP_USB_HUB2_OCS1
NC_USB_HUB2_OCS2
USB_EXTA_OC_L
EXCARD_OC_L
USB_HUB2_RBIAS
Bluetooth
Trackpad/Keyboard
External A
SD Card/Express Card
TP_USB_HUB2_PRTPWR1
NC_USB_HUB2_PRTPWR2
NC_USB_HUB2_PRTPWR3
NC_USB_HUB2_PRTPWR4
RBIAS
35
VBUS_DET
27
USB_HUB2_VBUS_DET
USBUP_DM
USBUP_DP
30
31
USB_HUB2_UP_N
USB_HUB2_UP_P
PP3V3_S3
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
R2670
10K
IN
42
IN
8 32
SYNC_MASTER=K92_BEN SYNC_DATE=06/29/2010
5%
1/16W
MF-LF
2 402
PAGE TITLE
USB HUBS
DRAWING NUMBER
Apple Inc.
CRITICAL
BI
BI
18 94
R2650
SIZE
D
REVISION
12K
18 94
1%
1/16W
MF
2 402

BRANCH
PAGE
26 OF 132
SHEET
24 OF 105
Platform Reset Connections

Unbuffered
Ethernet WAKE# Isolation
PCH Reset Button

1
CRITICAL
R2895
4.7K
92 23 10
IN
XDP_DBRESET_L
PM_SYSRST_L
6 17 45
BI
85 32 31 17 6
PCIE_WAKE_L
OUT
OUT
6 25 47 88 95
OUT
6 25 47 88 95
OUT
45
R2883
33
SMC_LRESET_L
5%
1/16W
MF-LF
402
R2871
0
ENET_WAKE_L
36 25
ENET_WAKE_L
MAKE_BASE=TRUE
LPCPLUS_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
7 25 36 71 73
5%
1/16W
MF-LF
2 402
SOD-VESM-HF
5%
1/16W
MF-LF
402
10K
SSM3K15FV
5%
1/16W
MF-LF
402
R2830
Q2830
5%
1/16W
MF-LF
2 402
33
XDP
R2896
R2881
PLT_RESET_L
MAKE_BASE=TRUE
PP3V3_ENET
PP3V3_S0
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
IN
PCA9557D_RESET_L
OUT
30
XDPPCH_PLTRST_L
OUT
23
5%
1/16W
MF-LF
402
IN
25 36
XDP
R2889
OMIT
1
1K
R2897
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
R2887
SILK_PART=SYS RESET
GMUX_RESET_L
ENET_MEDIA_SENSE ISOLATION CIRCUIT
25 88
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
GMUX_RESET_L
OUT
25 88
PLACE_NEAR=U1800.N32:5mm
R2810
36
IN
ENET_MEDIA_SENSE
12K
402 MF-LF
55 54 50 49 48 32 31 30 29 24 18 8 7 6
104 88 73
5%
ENET_MEDIA_SENSE_RDIV
CRITICAL
SSM6N37FEAPE3
D
PP3V3_S3
Q2810
R2819
16
PLT_RESET_L
Series R is R4283
OUT
18 25 29 39
10K
5%
1/20W
MF
201
SOT563
R2811 1
OUT
1/16W
100K
5%
1/20W
MF
201
R2855
95 18
IN
PLACE_NEAR=U1800.N52
LPC_CLK33M_SMC_R
22
LPC_CLK33M_SMC
5%
1/20W
MF
201
18
IN
PLACE_NEAR=U1800.P46
25 18
18
IN
IN
LPC_CLK33M_GMUX_R
LPC_CLK33M_GMUX_R
25 18
22
MAKE_BASE=TRUE
Buffered
Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
45 95
OUT
22
LPC_CLK33M_LPCPLUS
PP3V3_S0
SSM6N37FEAPE
22 20 16 7 PP1V5_S0
71 57 41 32
6 47 95
OUT
R2812
LPC_CLK33M_GMUX
22
SOT563
16 95
OUT
SC70-HF
U2880 4
35
32 25
PLT_RST_BUF_L
PLT_RST_BUF_L
5%
1/16W
MF-LF
2 402
20%
10V
CERM 2
402
25 32 35
OUT
25 32 35
ENET_RESET_L_R
OUT
32
AP_RESET_L
OUT
31
OUT
90
PLT_RST_BUF_L
Series R is R3803
100K
0.1UF
OUT
MAKE_BASE=TRUE
R2880
C2880 1
ENET_MEDIA_SENSE_EN
5%
1/20W
MF
201
CRITICAL
MC74VHC1G08
PCH_CLK33M_PCIIN
5%
1/16W
MF-LF 2
402
R2859
88
OUT
5
1
Q2810
5%
1/20W
MF
201
5%
1/20W
MF
201
PCH_CLK33M_PCIOUT
R2856
R2857
1
ENET_MEDIA_SENSE_EN_L
LPC_CLK33M_LPCPLUS_R
R2882
1
5%
1/16W
MF-LF
402
R2888
1
System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: T29 power rail for XTAL circuit. 73 64 63
53 48 47 46 45 44 42 7 6
104
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

72 71 56 48 46 29 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73
GreenClk 25MHz Power
73 71 36 25 7
PP3V3_ENET
PP3V42_G3H
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
C2824
0.1UF
C2822
0.1UF
20%
C2820 1
0.1UF
20%
10V
CERM 2
20%
10V
CERM 2
402
10V
CERM 2
402
402
C2802
1UF
VBAT 13
U2800
10%
10V
2 X5R
402-1
SLG3NB148V
TQFN
CRITICAL
11
6
14
R2805
SYSCLK_CLK25M_X2
NC
NC
12PF
1
SM-3.2X2.5MM
SYSCLK_CLK25M_X2_R
NO STUFF
3
4
X2
X1
R2806
1M
GND
5%
1/16W
MF-LF
2 402
PLT_RST_CPU_BUF_L
PLT_RST_CPU_BUF_L
OUT
1 3
NC
R2890
100K
5%
1/16W
MF-LF
2 402
32KHZ_A 12
SYSCLK_CLK32K_RTC
25MHZ_A 9
25MHZ_B 8
25MHZ_C 15
SYSCLK_CLK25M_SB
OUT
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_T29
OUT
PPVRTC_G3H
7 16 17 20
For SB RTC Power
THRM
PAD
C2810
OUT
16
16
33
R2800
1
SYSCLK_CLK25M_ENET 36
SYNC_MASTER=K91_MLB
PAGE TITLE
5%
1/20W
MF
201
Chipset Support
DRAWING NUMBER
1UF
10%
6.3V
2 CERM
402
Apple Inc.
SIZE
D
REVISION
NOTE: 30 PPM crystal required
10 23 25
VTT voltage divider on CPU page
+V3.3A should be first

available ~3.3V power
to reduce VBAT draw.
SYSCLK_CLK25M_X1
VBAT and +V3.3A are

internally ORed to
create VDD_RTC_OUT.
VDD_RTC_OUT 1
5%
50V
CERM
402
5%
1/16W
MF-LF
402
25.000MHZ-12PF-30PPM
3
C2806
CRITICAL
Y2805
2 4
5%
50V
CERM
402
7
10
16
12PF
VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C
20%
10V
CERM 2
402
APN:359S0178
17
C2805
25
23 10
MAKE_BASE=TRUE
NC
+V3.3A 2
BKLT_PLT_RST_L
U2890
74LVC1G07
SC70
4
0.1UF
PP3V3_ENET
PP1V8_S0
PP3V3_T29
CRITICAL
5
PP3V3_S5
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
VDD_25M 5
5%
1/16W
MF-LF
402
Buffered CPU reset
PP3V3_S0
C2890 1
Ethernet XTAL Power
73 71 36 25
SB XTAL Power
102 88 72 71 20 14 7
T29 XTAL Power
88 35 34 33 19 16
R2893
1
5%
1/16W
MF-LF
402
BRANCH
PAGE
28 OF 132
SHEET
25 OF 105
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
72 67 29 28 7
PP1V5_S3
Power aliases required by this page:

- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
Signal aliases required by this page:
C2900
10UF
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
BOM options provided by this page:
20%
2 6.3V
X5R
603
C2911
0.1UF
C2912
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
C2913
0.1UF
20%
2 10V
CERM
402
C2914
0.1UF
20%
2 10V
CERM
402
C2915
0.1UF
20%
2 10V
CERM
402
C2916
0.1UF
C2917
0.1UF
20%
2 10V
CERM
402
C2918
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2919
0.1UF
20%
2 10V
CERM
402
C2920
0.1UF
20%
2 10V
CERM
402
C2921
0.1UF
C2922
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2923
0.1UF
20%
2 10V
CERM
402
C2901
10UF
20%
2 6.3V
X5R
603
PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

30 9
(NONE)
C2930
C2931
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
1
73
MEM_A_CKE<0>
NC
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
93 11
IN
IN
MEM_A_BA<2>
75
77
79
81
83
MEM_A_A<12>
MEM_A_A<9>
85
87
89
MEM_A_A<8>
MEM_A_A<5>
91
93
95
MEM_A_A<3>
MEM_A_A<1>
97
99
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
101
MEM_A_A<10>
MEM_A_BA<0>
107
MEM_A_WE_L
MEM_A_CAS_L
113
MEM_A_A<13>
MEM_A_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
27
BI
27
BI
27
BI
27
BI
27
BI
27
BI
125
127
=MEM_A_DQ<32>
=MEM_A_DQ<33>
129
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
135
=MEM_A_DQ<34>
=MEM_A_DQ<35>
141
143
131
133
137
139
145
27
BI
27
BI
=MEM_A_DQ<40>
=MEM_A_DQ<41>
147
149
151
153
155
27
BI
27
BI
27
BI
27
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43>
157
=MEM_A_DQ<48>
=MEM_A_DQ<49>
163
165
159
161
167
27
BI
27
BI
27
BI
27
BI
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
169
171
173
=MEM_A_DQ<50>
=MEM_A_DQ<51>
175
177
179
27
BI
27
BI
=MEM_A_DQ<56>
=MEM_A_DQ<57>
181
183
185
187
189
27
BI
27
BI
=MEM_A_DQ<58>
=MEM_A_DQ<59>
191
193
195
102 100 91 89 88 85
54 52 51 50 49
28 25 23 12 7 6
48 46 41 40 39 36 35 32
84 83 80 73 72 62 61 57
MEM_A_SA<0>
197
199
MEM_A_SA<1>
201
PP3V3_S0
203
1
1
C2940
2.2UF
20%
6.3V
CERM
402-LF
R2940
J2900
74
MEM_A_CKE<1>
76
78
IN
11 93
27
27
MEM_A_A<15>
MEM_A_A<14>
80
82
84
MEM_A_A<11>
MEM_A_A<7>
86
88
90
MEM_A_A<6>
MEM_A_A<4>
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
IN
11 93
IN
11 93
BI
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
IN
11 93
27
BI
IN
11 93
27
BI
MEM_A_BA<1>
MEM_A_RAS_L
IN
11 93
27
BI
IN
11 93
27
BI
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
11 93
27
BI
IN
11 93
27
BI
IN
=MEM_A_DQ<0>
=MEM_A_DQ<1>
7
9
11
MEM_A_A<2>
MEM_A_A<0>
MEM_A_ODT<1>
3
5
11 93
NC
27
BI
27
BI
13
15
=MEM_A_DQ<2>
=MEM_A_DQ<3>
17
19
21
=MEM_A_DQ<8>
=MEM_A_DQ<9>
23
25
27
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
29
31
=MEM_A_DQ<10>
=MEM_A_DQ<11>
33
=MEM_A_DQ<16>
=MEM_A_DQ<17>
39
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
45
=MEM_A_DQ<18>
=MEM_A_DQ<19>
51
53
35
37
41
43
47
49
124
55
126
128
130
132
134
=MEM_A_DQ<36>
MEM_A_DQ<37>
142
144
27
BI
11 27 93
146
148
150
152
154
156
158
160
162
164
166
=MEM_A_DQ<38>
=MEM_A_DQ<39>
BI
27
BI
27
=MEM_A_DQ<44>
=MEM_A_DQ<45>
BI
27
BI
27
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
BI
27
BI
27
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
27
BI
27
=MEM_A_DQ<52>
=MEM_A_DQ<53>
BI
27
BI
27
=MEM_A_DQ<54>
=MEM_A_DQ<55>
BI
27
BI
27
=MEM_A_DQ<60>
=MEM_A_DQ<61>
BI
27
BI
27
BI
27
BI
57
59
=MEM_A_DQ<24>
=MEM_A_DQ<25>
61
BI
63
65
136
138
140
27
27
BI
27
BI
67
=MEM_A_DQ<26>
=MEM_A_DQ<27>
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
J2900
2
4
6
=MEM_A_DQ<4>
=MEM_A_DQ<5>
BI
27
BI
27
MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
BI
11 27 93
BI
27
=MEM_A_DQ<6>
=MEM_A_DQ<7>
BI
27
BI
27
=MEM_A_DQ<12>
=MEM_A_DQ<13>
BI
27
BI
27
30
32
MEM_RESET_L
IN
34
=MEM_A_DQ<14>
=MEM_A_DQ<15>
BI
27
BI
27
=MEM_A_DQ<20>
=MEM_A_DQ<21>
BI
27
BI
27
=MEM_A_DQ<22>
=MEM_A_DQ<23>
BI
27
BI
27
=MEM_A_DQ<28>
=MEM_A_DQ<29>
BI
27
BI
27
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
BI
27
BI
27
=MEM_A_DQ<30>
=MEM_A_DQ<31>
BI
27
BI
27
8
10
12
14
16
18
20
22
24
26
28
36
38
40
42
44
28 29
46
48
50
52
54
56
58
60
62
64
66
68
70
72
KEY
516-0229
168
170
172
174
176
178
180
182
184
186
188
PP0V75_S3_MEM_VREFCA_A
C2935
C2936
2.2UF
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
BI
27
BI
27
=MEM_A_DQ<62>
=MEM_A_DQ<63>
BI
27
BI
27
20%
6.3V
CERM
402-LF
30
0.1UF
2
20%
10V
CERM
402
190
192
194
196
198
200
202
MEM_EVENT_L
SMBUS_PCH_DATA
SMBUS_PCH_CLK
OUT
28 45
BI
IN
"Factory" (top) slot
6 16 23 28 30 32 41 48 62 89 95
6 16 23 28 30 32 41 48 62 89 95
204
PP0V75_S0_DDRVTT
7 28 29 67
R2941
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-K6
93 11
KEY
(SYMBOL 1 OF 2)
DDR3-SODIMM-DUAL-K6
C2910
0.1UF
- =PP0V75_S0_MEM_VTT_A
516-0229
C2950
1UF
SPD ADDR=0xA0(WR)/0xA1(RD)
10%
2 10V
X5R
402
C2951
1UF
10%
2 10V
X5R
402
C2952
1UF
10%
2 10V
X5R
402
C2953
SYNC_MASTER=K92_YUN
1UF
10%
2 10V
X5R
402
PAGE TITLE
DDR3 SO-DIMM Connector A

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
29 OF 132
SHEET
26 OF 105
CPU CHANNEL A DQS 0 -> DIMM A DQS 0

93 27 26 11
93 11
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
11 26 27 93 93 28 27 11
26
93 28 27 11
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
11 27 28 93
11 27 28 93
MAKE_BASE=TRUE
93 11
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
=MEM_A_DQ<1>
=MEM_A_DQ<0>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MAKE_BASE=TRUE
93 11
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
93 11
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
26
93 11
26
93 11
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
26
93 11
93 11
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MAKE_BASE=TRUE
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
26
93 11
26
93 11
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQ<17>
=MEM_A_DQ<16>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
93 11
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
26
93 11
26
93 11
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQ<29>
=MEM_A_DQ<28>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
26
93 11
93 11
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
93 11
93 27 26 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
26
93 11
26
93 11
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
MEM_A_DQ<37>
=MEM_A_DQ<36>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
26
93 11
26
93 11
11 26 27 93 93 28 27 11
26
26
93 11
93 11
26
93 11
26
93 11
26
93 11
93 11
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
93 11
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
26
93 11
26
93 11
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<41>
=MEM_A_DQ<40>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
26
93 11
93 11
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
26
93 11
26
93 11
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
=MEM_A_DQ<53>
=MEM_A_DQ<52>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<49>
=MEM_A_DQ<48>
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
93 11
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28
28
28
28
MAKE_BASE=TRUE
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<19>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<16>
28
28
28
28
28
28
28
28
28
MAKE_BASE=TRUE
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
28
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<27>
=MEM_B_DQ<26>
=MEM_B_DQ<25>
=MEM_B_DQ<24>
28
28
28
28
28
28
28
28
MAKE_BASE=TRUE
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<39>
=MEM_B_DQ<38>
MEM_B_DQ<37>
=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
28
28
28
11 27 28 93
28
28
28
28
28
MAKE_BASE=TRUE
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQ<45>
=MEM_B_DQ<44>
=MEM_B_DQ<43>
=MEM_B_DQ<42>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
28
28
28
28
28
28
28
28
28
MAKE_BASE=TRUE
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
28
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DQ<53>
=MEM_B_DQ<52>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<49>
=MEM_B_DQ<48>
28
28
28
28
28
28
28
28
28
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
93 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
28
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<12>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<9>
=MEM_B_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
93 11
MAKE_BASE=TRUE
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
MAKE_BASE=TRUE

93 11
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
93 11
28
MAKE_BASE=TRUE
93 11
28
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<12>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<9>
=MEM_A_DQ<8>
MAKE_BASE=TRUE
93 11
MAKE_BASE=TRUE
28
MAKE_BASE=TRUE
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE

93 11
MAKE_BASE=TRUE
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
26
93 11
26
93 11
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
28
28
MAKE_BASE=TRUE
SYNC_MASTER=K92_YUN
93 11
93 11
93 11
93 11
93 11
93 11
93 11
93 11
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
MAKE_BASE=TRUE
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
26
93 11
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<63>
=MEM_B_DQ<62>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
DDR3 Byte/Bit Swaps
28
DRAWING NUMBER
28
28
Apple Inc.
28
SIZE
D
REVISION
R
28
28

28
MAKE_BASE=TRUE
PAGE TITLE
28
BRANCH
PAGE
30 OF 132
SHEET
27 OF 105
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
72 67 29 26 7
PP1V5_S3

- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
C3100
10UF
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
20%
2 6.3V
X5R
603
C3111
0.1UF
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
20%
2 10V
CERM
402
C3112
0.1UF
C3113
0.1UF
C3114
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3115
0.1UF
20%
2 10V
CERM
402
C3116
0.1UF
C3117
0.1UF
20%
2 10V
CERM
402
C3118
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3119
0.1UF
20%
2 10V
CERM
402
C3120
0.1UF
20%
2 10V
CERM
402
C3121
0.1UF
20%
2 10V
CERM
402
C3122
0.1UF
20%
2 10V
CERM
402
C3123
0.1UF
20%
2 10V
CERM
402
C3101
10UF

20%
2 6.3V
X5R
603
30 9
(NONE)
C3130
C3131
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
1
73
NC
93 11
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
IN
93 11
93 11
MEM_B_BA<2>
IN
203
205
207
MTG PIN
MTG PIN
209
211
MTG PIN
MTG PIN
85
87
89
MEM_B_A<8>
MEM_B_A<5>
91
93
95
MEM_B_A<3>
MEM_B_A<1>
IN
79
81
83
MEM_B_A<12>
MEM_B_A<9>
IN
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
VDD F-RT-BGA6 VDD
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
75
77
97
99
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
101
MEM_B_A<10>
MEM_B_BA<0>
107
MEM_B_WE_L
MEM_B_CAS_L
113
MEM_B_A<13>
MEM_B_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
27
BI
27
BI
27
BI
27
BI
27
BI
27
BI
125
127
=MEM_B_DQ<32>
=MEM_B_DQ<33>
129
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
135
=MEM_B_DQ<34>
=MEM_B_DQ<35>
141
143
131
133
137
139
145
27
BI
27
BI
=MEM_B_DQ<40>
=MEM_B_DQ<41>
147
149
151
153
155
27
BI
27
BI
27
BI
27
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43>
157
=MEM_B_DQ<48>
=MEM_B_DQ<49>
163
165
159
161
167
27
BI
27
BI
27
BI
27
BI
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
169
171
173
=MEM_B_DQ<50>
=MEM_B_DQ<51>
175
177
179
27
BI
27
BI
=MEM_B_DQ<56>
=MEM_B_DQ<57>
181
183
185
187
189
27
BI
27
BI
=MEM_B_DQ<58>
=MEM_B_DQ<59>
191
193
195
102 100
62 61 57 54 52 51
32 26 25 23 12 7 6
50 49 48 46 41 40 39 36 35
91 89 88 85 84 83 80 73 72
MEM_B_SA<0>
197
199
MEM_B_SA<1>
201
PP3V3_S0
1
1
C3140
2.2UF
20%
6.3V
CERM
402-LF
R3140
R3141
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
J3100
(2 OF 2)
MEM_B_CKE<0>
IN
DDR3-SODIMM
93 11
KEY
MTG PINS
MTG PIN
MTG PIN
MTG PIN
MTG PIN
74
MEM_B_CKE<1>
76
78
IN
11 93
27
27
MEM_B_A<15>
MEM_B_A<14>
80
82
84
MEM_B_A<11>
MEM_B_A<7>
86
88
90
MEM_B_A<6>
MEM_B_A<4>
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
IN
11 93
IN
11 93
BI
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
IN
11 93
27
BI
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
IN
11 93
27
BI
IN
11 93
27
BI
MEM_B_BA<1>
MEM_B_RAS_L
IN
11 93
27
BI
IN
11 93
27
BI
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
11 93
27
BI
IN
11 93
27
BI
11 93
NC
27
BI
27
BI
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<36>
MEM_B_DQ<37>
142
144
146
148
150
152
154
156
158
160
162
164
166
19
21
23
25
27
29
31
33
=MEM_B_DQ<16>
=MEM_B_DQ<17>
39
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
45
=MEM_B_DQ<18>
=MEM_B_DQ<19>
51
53
35
37
41
43
47
49
27
BI
11 27 93
=MEM_B_DQ<38>
=MEM_B_DQ<39>
BI
27
BI
27
=MEM_B_DQ<44>
=MEM_B_DQ<45>
BI
27
BI
27
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
BI
27
BI
27
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
27
BI
27
=MEM_B_DQ<52>
=MEM_B_DQ<53>
BI
27
BI
27
=MEM_B_DQ<54>
=MEM_B_DQ<55>
BI
27
BI
27
=MEM_B_DQ<60>
=MEM_B_DQ<61>
BI
27
BI
27
27
BI
27
BI
=MEM_B_DQ<24>
=MEM_B_DQ<25>
57
59
61
BI
63
65
136
138
140
17
55
126
128
132
134
13
15
=MEM_B_DQ<10>
=MEM_B_DQ<11>
124
130
7
9
11
IN
IN
=MEM_B_DQ<0>
=MEM_B_DQ<1>
BI
MEM_B_A<2>
MEM_B_A<0>
MEM_B_ODT<1>
3
5
27
BI
27
BI
=MEM_B_DQ<26>
=MEM_B_DQ<27>
67
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA6
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
J3100
(1 OF 2)
DDR3-SODIMM
C3110
0.1UF
- =PP0V75_S0_MEM_VTT_B
2
4
6
=MEM_B_DQ<4>
=MEM_B_DQ<5>
BI
27
BI
27
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
11 27 93
BI
11 27 93
=MEM_B_DQ<6>
=MEM_B_DQ<7>
BI
27
BI
27
=MEM_B_DQ<12>
=MEM_B_DQ<13>
BI
27
BI
27
30
32
MEM_RESET_L
IN
34
=MEM_B_DQ<14>
=MEM_B_DQ<15>
BI
27
BI
27
=MEM_B_DQ<20>
=MEM_B_DQ<21>
BI
27
BI
27
=MEM_B_DQ<22>
=MEM_B_DQ<23>
BI
27
BI
27
=MEM_B_DQ<28>
=MEM_B_DQ<29>
BI
27
BI
27
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
BI
27
BI
27
=MEM_B_DQ<30>
=MEM_B_DQ<31>
BI
27
BI
27
8
10
12
14
16
18
20
22
24
26
28
36
38
40
42
44
26 29
46
48
50
52
54
56
58
60
62
64
66
68
70
72
KEY
516S0806
168
170
172
174
176
178
180
182
184
186
188
PP0V75_S3_MEM_VREFCA_B
C3135
C3136
2.2UF
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
BI
27
BI
27
=MEM_B_DQ<62>
=MEM_B_DQ<63>
BI
27
BI
27
30
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
190
192
194
196
198
200
202
MEM_EVENT_L
SMBUS_PCH_DATA
SMBUS_PCH_CLK
OUT
26 45
BI
IN
6 16 23 26 30 32 41 48 62 89 95
"Expansion" (bottom) slot
6 16 23 26 30 32 41 48 62 89 95
204
206
208
210
212
PP0V75_S0_DDRVTT
C3150
1UF
10%
2 10V
X5R
402
C3151
1UF
10%
2 10V
X5R
402
C3152
1UF
10%
2 10V
X5R
402
7 26 29 67
C3153
SYNC_MASTER=K92_YUN
1UF
10%
2 10V
X5R
402
PAGE TITLE
DDR3 SO-DIMM Connector B

DRAWING NUMBER
516S0806
Apple Inc.
SPD ADDR=0xA4(WR)/0xA5(RD)
SIZE
D
REVISION

BRANCH
PAGE
31 OF 132
SHEET
28 OF 105
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPUs SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW:
CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN
= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
1V5 S0 "PGOOD" for CPU
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PP3V3_S5
72 71 56 48 46 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73
73 66 45 42 17
IN
PM_SLP_S4_L
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1
R3205
104 73 15 13 10 7
PP1V5_S3RS0_CPUDDR
PM_MEM_PWRGD
1
10K
5%
1/16W
MF-LF
2 402
OUT
CRITICAL
CPUMEM_S0
PP3V3_S3
R3220 1
72
1%
1/16W
MF-LF
402
SSM6N15FEAPE
R3201 1
5%
1/16W
MF-LF
402
CRITICAL
27.4K
Q3205
CPUMEM_S0
10 17 92
10K
P1V5CPU_EN
55 54 50 49 48 32 31 30 25 24 18 8 7 6
104 88 73
OUT
R3222
Q3220
DMB53D0UV
SOT-563
PM_MEM_PWRGD_L
2
SOT563
100K
5%
1/16W
MF-LF
402
CRITICAL
3
2
P1V5_S0_DIV
Q3220
DMB53D0UV
SOT-563
P1V5CPU_EN_L
4
CPUMEM_S0
CPUMEM_S0
Q3200
SSM6N15FEAPE
IN
1%
1/16W
MF-LF
402
SOT563
NO STUFF
C3220
33.2K
SSM6N15FEAPE
SOT563
23 19
R3221
Q3205
0.001UF
20%
50V
CERM
402
ISOLATE_CPU_MEM_L
PM_SLP_S3_L
IN
6 17 45 73
CPUMEM_S0
1
R3210
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN
PP5V_S3
104 82 72 67 46 44 43 42 31 29 7 6
OUT
CRITICAL
CPUMEM_S0
CPUMEM_S0
R3215
Q3210
CPUMEM_S0
R3202
100K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8 29 67
MEMVTT Clamp
6
Ensures CKE signals are held low in S3
SSM6N15FEAPE
SOT563
67 28 26 7
PP0V75_S0_DDRVTT
CPUMEM_S0
MEMVTT_EN_L
CRITICAL
R3250
CPUMEM_S0
CPUMEM_S0
Q3200
Q3215
5%
1/10W
MF-LF
603
Q3210
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
SSM6N15FEAPE
104 82 72 67 46 44 43 42 31 29 7 6
PP5V_S3
Q3250
CPUMEM_S0
PLT_RESET_L
IN
18 25 39
SSM6N15FEAPE
R3251 1
VTTCLAMP_L
2
75mA max load @ 0.75V

60mW max power
CRITICAL
CPUMEM_S0
SOT563
10
CPUMEM_S0
SOT563
100K
5%
1/16W
MF-LF
402
CRITICAL
CPUMEM_S0
PP1V5_S3
Q3215
CPUMEM_S0
1
G
CPU_MEM_RESET_L
MAKE_BASE=TRUE
29
10
CPUMEM_S0
Q3250
0.1UF
5%
1/16W
MF-LF
402
10%
16V
X5R
402
MEM_RESET_L
OUT
20%
50V
CERM
402
26 28
67 29 8
CPUMEM_S3
IN
0.001UF
SOT563
NO STUFF
C3251
SSM6N15FEAPE
CPU_MEM_RESET_L
IN
2
29 10
C3216
20K
SOT563
VTTCLAMP_EN
CPUMEM_S0
R3216
SSM6N15FEAPE
MEMRESET_ISOL_LS5V_L
7 26 28 67 72
MEMVTT_EN
R3217
1
5%
1/16W
MF-LF
402
Step
S0
to
S3
to
S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0
1
2
3
ISOLATE_CPU_MEM_L
1
0
0
0
PLT_RESET_L
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
X
CPU_MEM_RESET_L
1
1
1
MEM_RESET_L
MEMVTT_EN
1
1
0
0
P1V5CPU_EN
1
1
1
0
4
5
6
7
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
0 (*)
1
1
1
1
1
CPU_MEM_RESET_L
0
1
1
1
1
1
1
1
SYNC_MASTER=K17_MLB
CPU Memory S3 Support

DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.

Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
SIZE
D
REVISION
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition.
PAGE TITLE
BRANCH
PAGE
32 OF 132
SHEET
29 OF 105
50 49 48 32 31 29 25 24 18 8 7 6
104 88 73 55 54
NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.
PP3V3_S3
VREFMRGN
OMIT
R3318
SHORT2
NONE
NONE
NONE
402
67 7 6
PP3V3_S3_VREFMRGN_DAC
MIN_NECK_WIDTH=0.2 mm VREFMRGN
VOLTAGE=3.3V
C3300 1
2.2UF
20%
6.3V 2
CERM
402-LF
VREFMRGN
1
C3301
VREFMRGN
0.1UF
62 48 41 32 30 28 26 23 16 6
95 89
0.1UF
20%
10V
CERM 2
402
U3300
IN
SMBUS_PCH_CLK
6 SCL
BI
SMBUS_PCH_DATA
7 SDA
10 A1
VOUTB 2
VREFMRGN_SODIMMB_DQ
VOUTC 4
VREFMRGN_SODIMMS_CA
B1
V+
UCSP
A1
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
R3301
C3
PP3V3_S3_VREFMRGN_CTRL
B1
Addr=0x30(WR)/0x31(RD)
62 48 41 32 30 28 26 23 16 6
95 89
62 48 41 32 30 28 26 23 16 6
95 89
IN
BI
UCSP
C1
VREFMRGN_DQ_SODIMMB_BUF
SMBUS_PCH_CLK
SMBUS_PCH_DATA
V-
100K
NC
5%
1/16W
MF-LF
2 402
16
GND
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
VREFMRGN
VREFMRGN
C3304 1
0.1UF
20%
10V
CERM 2
402
A2
B1
V+
A3
UCSP
A1
VREFMRGN_CA_SODIMMA_BUF
2
VREFMRGN
C2
V+
C3
CRITICAL
B1
QTY
DESCRIPTION
REFERENCE DES
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3303,R3305
VREFMRGN_NOT
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3309,R3311
VREFMRGN_NOT
VREFMRGN_CA_SODIMMB_BUF
133
V-
28
2
VREFMRGN
R3308
VREFMRGN
100K
CRITICAL
VREFMRGN
C3305 1
5%
1/16W
MF-LF
2 402
0.1UF
20%
10V
CERM 2
402
C2
B1
V+
C3
VREFMRGN
U3304
MAX4253
R3314
UCSP
C1
VREFMRGN_MEMVREG_BUF 133.2K2
1%
1/16W
MF-LF
402
C4
V-
B4
Page Notes
VREFMRGN
R33161
0
5%
1/16W
MF-LF
402 2

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
1%
1/16W
MF-LF
402
C4
PP0V75_S3_MEM_VREFCA_B
VOLTAGE=0.75V
BOM OPTION

- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
R3312
B4
PART NUMBER
VREFMRGN
U3303
MAX4253
UCSP
C1
200
1%
1/16W
MF-LF
402
CRITICAL
5%
1/16W
MF-LF
2 402
PCA9557D_RESET_L
Required zero ohm resistors when no VREF margining circuit stuffed
VREFMRGN
VREFMRGN_FRAMEBUF_BUF
VREFMRGN
R3313
100K
5%
1/16W
MF-LF
2 402
A2
B1
V+
A3
VREFMRGN_MEMVREG_FBVREF_R

VREFMRGN
- Stuffs VREF Margining
Circuitry.
VREFMRGN_NOT - Bypasses VREF Margining
Circuitry.
26
R3311
NOTE: Margining will be disabled across all

soft-resets and sleep/wake cycles.
A
1
133
PP0V75_S3_MEM_VREFCA_A
VOLTAGE=0.75V
VREFMRGN
RST* on platform reset so that system

watchdog will disable margining.
DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:
NC
100K
MEM A VREF DQ
1%
1/16W
MF-LF
402
A4
B4
R3307
200
R3310
V-
VREFMRGN
IN
VREFMRGN
U3303
MAX4253
25
1%
1/16W
MF-LF
402
RESET* 15
PAD
9 28
R3309
R3302
QFN
(OD) P0 6
P1 7
P2 9
P3 10
P4 11
P5 12
P6 13
P7 14
17
THRM
133
VOLTAGE=0.75V
VREFMRGN
VREFMRGN
U3301
1 SCL
2 SDA
2 PLACE_NEAR=J3100.1:2.54mm
1%
1/16W
MF-LF
402
C4
PCA9557
3 A0
4 A1
5 A2
200
R3306
CRITICAL
VREFMRGN
VCC
20%
10V
CERM 2
402
VREFMRGN
U3302
MAX4253
B4
0.1UF
9 26
1%
1/16W
MF-LF
402
VREFMRGN
C2
OMIT
C3302 1
VOLTAGE=0.75V
R3305
VREFMRGN
V+
VREFMRGN
VREFMRGN
NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable
both at the same time!
R3319
NONE
NONE
NONE
402
133
1%
1/16W
MF-LF
402
B4
5%
1/16W
MF-LF
2 402
VOLTAGE=3.3V
R3304
100K
SHORT2
1
200
VREFMRGN
U3302
MAX4253
VREFMRGN_MEMVREG_FBVREF
VOUTD 5
GND
3
A2
A3
VREFMRGN_SODIMMA_DQ
1
MSOP VOUTA
9 A0
Addr=0x98(WR)/0x99(RD)
R3303
1%
1/16W
MF-LF
402
VREFMRGN
C3303 1
CRITICAL
VREFMRGN
20%
2 10V
CERM
402
DAC5574
62 48 41 32 30 28 26 23 16 6
95 89
PPVTTDDR_S3
10mA max load
CRITICAL
8
VDD
U3304
DDRREG_FB
OUT
67
VREFMRGN
1
R3317
MAX4253
UCSP
A1
A4
V-
VREFMRGN_FRAMEBUF_BUF_R
B4
5%
1/16W
MF-LF
2 402
VREFMRGN
1
R3315
100K
5%
1/16W
MF-LF
2 402
MEM B VREF DQ
MEM A VREF CA
B
2
C
3
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
MEM B VREF CA
C
4
MEM VREG
GPU Frame Buffer (1.8V, 70% VRef)
D
5
1.5V (DAC: 0x3A)
1.000V - 2.000V (+/- 500mV)
0.000V - 3.000V (0x00 - 0x74)
+61uA - -61uA (- = sourced)
D
6
1.267V (DAC: 0x8B)
1.056V - 1.442V (+/- 180mV)
0.000V - 3.300V (0x00 - 0xFF)
+6.0mA - -5.0mA (- = sourced)
SYNC_MASTER=K91_YUN
PAGE TITLE
FSB/DDR3/FRAMEBUF Vref Margining

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
33 OF 132
SHEET
30 OF 105
OMIT_TABLE
L3470
95
C3431
PCIE_AP_R2D_PI_P
10%
0.6NH+/-0.1NH-0.85A
PCIE_AP_R2D_C_P
0.1UF
16 95
IN
16V X5R 402-1
0201
NOSTUFF
PART NUMBER
NOSTUFF
1 C3470
0.1UF
1 C3471
10%
16V
X5R-CERM
0201
QTY
117S0002
0.1UF
DESCRIPTION
REFERENCE DES
RES, 0OHM, 0201
L3470,L3471,L3473,L3474
CRITICAL
BOM OPTION
10%
16V
X5R-CERM
0201
L3471
95
PCIE_AP_R2D_PI_N
1
10%
0.6NH+/-0.1NH-0.85A
NOSTUFF
NOSTUFF
OMIT_TABLE
1 C3472
BI
SMBUS_SMC_0_S0_SCL
IN
6 45 48 51 80 98
0.1UF
PCIE_AP_R2D_C_N
IN
10%
16V
X5R-CERM
0201
6 45 48 51 80 98
3V S3 WLAN FET
16 95
16V X5R 402-1
MOSFET
TPCP8102
CHANNEL
P-TYPE
1 C3473
0.1UF
SMBUS_SMC_0_S0_SDA
C3430
0201
0.1UF
RDS(ON)
20-30 MOHM @2.5V
10%
16V
X5R-CERM
0201
LOADING
1 A (EDP)
OMIT_TABLE
L3473
0.1UF
OUT
6 16 95
155S0367
10%
16V
X5R-CERM
0201
PCIE_AP_D2R_N
CRITICAL
J3401
95
PCIE_AP_D2R_PI_P
0.1UF
10%
NOSTUFF
16V
OMIT_TABLE
X5R-CERM
0201
95
C3422
10%
16V
X5R-CERM
0201
1%
MIN_LINE_WIDTH=1 mm
1W MIN_NECK_WIDTH=0.5 mm
MF
0612
PP3V3_WLAN_F
2
4
1
3
C3421
PP3V3_WLAN_R
0.033UF
20%
10V
CERM
402
10%
16V
X5R
402
PLACE_NEAR=J3401.29:2.54MM
C3450
0.1UF
90-OHM-100MA
DLP11S
100 6
100 6
R3450
P3V3WLAN_SS
54 55 73 88 104
6 7 8 18 24 25 29
30 31 32 48 49 50
R3451
10K
33K
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
IN
73
5%
1/16W
MF-LF
402
10%
16V
X5R
402-1
ISNS_AIRPORT_P
PCIE_CLK100M_AP_P
IN
16 95
PCIE_CLK100M_AP_N
IN
16 95
OUT
100 103
OUT
100 103
ISNS_AIRPORT_N
BLUETOOTH
PP3V3_S3_BT_F
USB_BT_N BI
6 24 94
PP3V3_S3
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
FERR-120-OHM-1.5A
R3453
0402-LF
1%
1/16W
MF-LF
402
R3454
VDD
232K
OUT
U3440
1%
1/16W
MF-LF
2 402
C3440
0.1uF
SLG4AP016V
P3V3WLAN_VMON
2
6 7 8 18 24 25 29 30 31 32 48 49 50 54 55
73 88 104
CRITICAL
100K
PCIE_WAKE_L
PP3V3_S3
1
10%
16V
CERM
402
PP3V3_WLAN_F
31 104
0.01UF
6 24 94
L3406
1 C3432
33
Delay = 60 ms +/- 20%
USB_BT_P BI
TDFN
20%
2 10V
CERM
402
SENSE +
0.7V -
DLY
AP_RESET_CONN_L
4 RESET*
AP_CLKREQ_Q_L
1
R3455
(OD)
THRM
PAD
GND
IN
25
IN
18 73
OUT
16 23
AP_PWR_EN
EN 6
OUT 8
7 IN
6 17 25 32 85
AP_RESET_L
MR* 3
Supervisor & CLKFREG # Isolation
34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
C3451
0.1uF
20%
10V
CERM
402
SYM_VER-1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
PP3V3_S3
1
0.1uF
AIRPORT
L3401
PCIE_AP_D2R_PI_N
31
104
2
0603
23V1K-SM
0.005
6 16 95
0.1UF
CRITICAL
F-ST-SM
32
31
OUT
1 C3477
0201
500913-0302
MIN_LINE_WIDTH=1 mm
NOSTUFF
0.6NH+/-0.1NH-0.85A
1 C3476
516S0582
PP3V3_WLAN 1
TPCP8102
R3452
FERR-120-OHM-3A
46 6
MIN_LINE_WIDTH=1 mm
L3404
1A PEAK
L3474
1
Q3450
CRITICAL
0.1UF
10%
NOSTUFF
16V
X5R-CERM
0201
CRITICAL
107S0137
NOSTUFF
1 C3475
PCIE_AP_D2R_P
0201
1 2 3
0.6NH+/-0.1NH-0.85A
1 C3474
6 45 46
PCIE_AP_R2D_P
PCIE_AP_R2D_N
4G
IN
95 6
5 6 7 8
WIFI_EVENT_L
AP_CLKREQ_L
100K
1%
1/16W
MF-LF
2 402
518S0816
CRITICAL
J3402
CCR20-6K710S
F-RT-SM
8
5
4
94 6
94 6
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
IN
BI
6 45 48 54 55 98
275 mA peak
206 mA nominal max
6 45 48 54 55 98
ALS
CAMERA
CRITICAL
L3407
90-OHM
L3408
FERR-120-OHM-1.5A
2
PP5V_S3
SYNC_MASTER=K91_MLB
6 7 29 42 43 44 46 67 72 82 104
C3452
DRAWING NUMBER
0.1uF
DLP0NS
SYM_VER-1
USB_CAMERA_P
BI
18
USB_CAMERA_N
BI
18
PAGE TITLE
X19/ALS/CAMERA CONNECTOR
0402-LF
Apple Inc.
20%
2 10V
CERM
402

SIZE
REVISION
BRANCH
PAGE
34 OF 132
SHEET
31 OF 105
OMIT
R3504
104
31 30 29 25 24 18 8 7 6
88 73 55 54 50 49 48 32
PP3V3_S3
SHORT
OUTPUT DECOUPLING
NONE NONE
2 32 PP3V3_S3_EXCARD_R
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V
NONE
402
MIN_LINE_WIDTH=.3mm
C3500
R3503
PP3V3_S0
SHORT
NONE NONE
2
PP3V3_S0_EXCARD_R
VOLTAGE=3.3V
NONE
402
CRITICAL
SHORT
PP1V5_S0
71 57 41 32 25 22 20 16 7
NONE NONE
2
PP1V5_S0_EXCARD_R
12
32 31 30 29 25 24 18 8 7 6
104 88 73 55 54 50 49 48
TP_EXCARD_STBY_L
EXCARD_RESET_R_L
STBY*
SYSRST*
OC*
19
4
NC0
NC1
CPPE*
11
27
26
MIN_LINE_WIDTH=.6mm
25
1
C3501
C3504
0.1UF
10uF
10
10%
16V
X5R
402-1
20%
6.3V
X5R
603
CPUSB*
6 32
VOLTAGE=3.3V
100 32 6
100 16 6
OUT
13
14
NC2
NC3
16
NC4
18 EXCARD_RCLKEN
32 6
32 6
6 32
32 6
VOLTAGE=1.5V
MIN_LINE_WIDTH=.6mm
THRML_PAD
21
C3502
C3505
0.1UF
GND
All pull-ups to AUXIN rail
21
PCIE_EXCARD_D2R_N
PCIE_CLK100M_EXCARD_CONN_P
EXCARD_CPPE_L
PLT_RESET_SWITCH_L
PCIE_WAKE_L
SMBUS_PCH_CLK
BI
18
PCIE_CLK100M_EXCARD_CONN_N
SMBUS_PCH_DATA
17
16
15
14
13
12
11
10
9
8
7
6
NC
10uF
10%
16V
X5R
402-1
89 62 48 41 30 28 26 23 16 6
95
20%
6.3V
X5R
603
32 6
100 32 6
6 32 100
23
22
19
32
PCIE_EXCARD_R2D_P
24
PCIE_EXCARD_R2D_N
PCIE_EXCARD_D2R_P
20
100 32 6
(IPU)
5
4
EXCARD_CPUSB_L
USB2_EXCARD_CONN_N
OUT
6 16 100
6 32 100
6 32
6 32
6 32
OUT
6 17 25 31 85
6 32
6 16 23 26 28 30 41 48 62 89
95
BI
NC
USB2_EXCARD_CONN_P
6 32 100
2
5
EXCARD_CPUSB_L
EXCARD_CPPE_L
28
74HC1G00GWDG
SC70-5
U3551
32 6
(IPU)
RCLKEN
0.1uF
32 6
D
CRITICAL
32 6
PP3V3_S3
20%
10V
CERM
402
29
PERST*
SHDN*
402
NC
NC
NC
NC
NC
C3550
20%
6.3V
X5R
603
15
1/16W
5%
EXCARD_OC_L
OUT
10uF
20%
10V
CERM
402
502250-8627
F-RT-SM
AUXOUT
24 8
1
MF-LF
0.1uF
J3500
VOUT3P3
VOUT1P5
VIN3P3
VIN1P5
20
PLT_RST_BUF_L
QFN
AUXIN
VOLTAGE=1.5V
R3505
IN
EXPRESSCARD/34 FLEX CONNECTOR
C3503
TPS2231
17
NONE
402
35 25
U3500
OMIT
R3502
(IPU)
83 80 73 72 62 61 57 54 52
35 32 28 26 25 23 12 7 6
51 50 49 48 46 41 40 39 36
102 100 91 89 88 85 84
6 32
VOLTAGE=3.3V
OMIT
PLT_RESET_SWITCH_L
EXCARD_CP
EXCARD_CPPE_L
6 32
EXCARD_CPUSB_L
6 32
6 32
518S0647
DETECT-CHANGED PCH GPIO LATCH CIRCUIT

PP3V3_S3
54 50 49 48 32 31 30 29 25 24 18 8 7 6
104 88 73 55
L3502
90-OHM
DLY block is 20ms nominal

When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for >80ms, then asserts for
10ms regardless of RST_IN# state.
Otherwise RST_OUT# follows RST_IN#
DLP0NS
SYM_VER-1
100 32 24 8
100 32 24 8
BI
BI
USB_EXCARD_N
USB_EXCARD_N
C3510 1
USB2_EXCARD_CONN_N
1UF
6 32 100
MAKE_BASE=TRUE
USB_EXCARD_P
USB_EXCARD_P
USB2_EXCARD_CONN_P
10%
10V 2
X5R
402-1
6 32 100
Must STUFF R3512 and NOSTUFF R3514

when R3511 is NOT STUFFED.
MAKE_BASE=TRUE
PLACE_NEAR=J3500.3:4mm
L3503
CRITICAL
90-OHM-100MA
DLP11S
R3514 and R3512 mutually exclusive

to bypass reset logic
VDD
SYM_VER-1
95 16
IN
PCIE_CLK100M_EXCARD_CONN_N
6 32 100
95 16
IN
PCIE_CLK100M_EXCARD_CONN_P
6 32 100
U3511
SLG4AP014V
TDFN
25
C3571
100 16
IN
100 16
IN
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
1
10%
0.1UF
10%
0.1UF
16V X5R 402-1
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_P
IN
IN
ENET_RESET_L_R
6 32 100
R3514
LOW_PWR
RST
LOGIC
RST_IN*
DET_IN
(IPU)
RST_OUT*
SLG_ENET_RESET_OUT_L
OUT
36
96
NOSTUFF
DLY
6 32 100
16V X5R 402-1
C3570
(OD)
DET_CHNGD*
(OD)
R3512
NC
0
5%
1/16W
MF-LF
2 402
NC
DET_OUT
GND
5
ENET_RESET_L
5%
1/16W
MF-LF
402
THRM
PAD
9
ENET_LOW_PWR
XOR
36 19
INPUT DECOUPLING
32
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S3_EXCARD_R
1
C3530
0.1uF
2
20%
10V
CERM
402
PP3V3_S0
C3531
10uF
20%
6.3V
X5R
603
5
32
EXCARD_RCLKEN
74HC1G00GWDG
SC70-5
U3560
R3561
EXCARD_CLKREQ_CONN
100K
25 22 20 16 7
71 57 41 32
1%
1/16W
MF-LF
402
PP1V5_S0
1
C3534
0.1uF
2
20%
10V
CERM
402
C3535
32 6
20%
6.3V
X5R
603
EXCARD_CLKREQ_L
OUT
16
SYNC_MASTER=K92_ERIC
A2
U3561
SN74LVC1G04YZPR
10uF
2
B1
C2
BGA
C1
C3560
20%
10V
CERM
402
PAGE TITLE
ExpressCard Connector
0.1uF
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
35 OF 132
SHEET
32 OF 105
CRITICAL
95 8
IN
PCIE_T29_R2D_C_P<0>
C3600
95 8
IN
PCIE_T29_R2D_C_N<0>
C3601
OMIT_TABLE
10%
0.1uF
1
16V
X5R
402
95
95
10%
0.1uF
16V
X5R
V19
T19
PCIE_T29_R2D_P<0>
PCIE_T29_R2D_N<0>
U3600
PER_0_P
PER_0_N
PET_0_P
PET_0_N
T29
V21
T21
95
95
C3640
PCIE_T29_D2R_C_P<0>
PCIE_T29_D2R_C_N<0>
FCBGA
402
0.1uF
C3641
0.1uF
PCIE_T29_D2R_P<0>
10%
16V
PCIE_T29_D2R_N<0>
X5R
10%
16V
PCIE_T29_D2R_P<1>
X5R
402
402
OUT
8 95
OUT
8 95
OUT
8 95
OUT
8 95
OUT
8 95
OUT
8 95
OUT
8 95
OUT
8 95
10%
0.1uF
C3603
10%
C3604
95 8
IN
PCIE_T29_R2D_C_N<2>
C3605
10%
IN
PCIE_T29_R2D_C_P<3>
C3606
IN
PCIE_T29_R2D_C_N<3>
C3607
X5R
402
16V
X5R
402
16V
X5R
402
10%
95
10%
16V
X5R
5%
C3615
TP_T29_MONOBSP
3.3K
5%
1/16W
MF-LF
402 2
R3691
3.3K
5%
1/16W
MF-LF
2 402
C3690 1
C3616
8
VCC
5
CRITICAL
OMIT_TABLE
U3690
M95160
2KX8-1.8V
(T29_SPI_CS_L)
S_L
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
R3622
10K
10%
16V
(T29_SPI_MISO)
10%
16V
W_L
T29ROM_HOLD_L
HOLD_L
0.1uF
C3643
0.1uF
PET_2_P
PET_2_N
PET_3_P
PET_3_N
K21
H21
95
95
C3644
PCIE_T29_D2R_C_P<2>
PCIE_T29_D2R_C_N<2>
0.1uF
C3645
F21
D21
95
95
C3646
PCIE_T29_D2R_C_P<3>
PCIE_T29_D2R_C_N<3>
0.1uF
C3647
1/16W MF-LF 402
X5R
X5R
WAKE*
MONOBSP
M17
MONOBSN
402
16V
PCIE_T29_D2R_N<1>
10%
16V
X5R
PCIE_T29_D2R_P<2>
X5R
X5R
402
402
10%
16V
PCIE_T29_D2R_N<2>
10%
16V
PCIE_T29_D2R_P<3>
X5R
X5R
402
402
10%
16V
PCIE_T29_D2R_N<3>
10%
16V
F1
R3651
T29_PCIE_WAKE_L
X5R
402
402
PERST*
E6
T29_RESET_L
RSENSE
E14
T29_RSENSE
IN
7 16 19 25 33 34 35 88
1
5%
10K
K17
402
10%
2
PP3V3_T29
1/16W MF-LF 402
35
R36551
1.0K
E16
T29_RBIAS
PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*
K1
J2
K3
J4
Not used in host mode.

TP_T29_PCIE_RESET0_L
TDI
TMS
TCK
TDO
T3
R4
R2
T1
JTAG_ISP_TDI
JTAG_T29_TMS
JTAG_ISP_TCK
JTAG_ISP_TDO
REFCLK_100_IN_P
REFCLK_100_IN_N
H17
G16
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
XTAL_25_IN
XTAL_25_OUT
P17
R16
SYSCLK_CLK25M_T29_R
TP_T29_XTAL25OUT
TMU_CLK_OUT
TMU_CLK_IN
U2
E2
RBIAS
R3621
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
OUT
R3693
3.3K
97
97
VSS
C3642
PCIE_T29_D2R_C_P<1>
PCIE_T29_D2R_C_N<1>
0.1uF
97
T29ROM_WP_L
PER_3_P
PER_3_N
95
0.5%
1/16W
MF-LF
603 2
5%
1/16W
MF-LF
2 402
MLP
MONDC1
T29_MONOBSN
1
Q
MONDC0
A20
1/16W MF-LF 402
T29_MONOBSP
35
(T29_SPI_CLK)
10K
0.1uF
PP3V3_T29
R36231
3.3K
10%
6.3V
CERM 2
402
(T29_SPI_MOSI)
R36921
1UF
T29_MONDC0
B21
T29_MONDC1
0.1uF
TP_T29_MONOBSN
F19
D19
95
0.1uF
R3611
DEBUG: For monitoring clock
R36901
PCIE_T29_R2D_P<3>
PCIE_T29_R2D_N<3>
P21
M21
402
5%
0
NO STUFF
88 35 34 33 25 19 16 7
PER_2_P
PER_2_N
PET_1_P
PET_1_N
NO STUFF
R3610
TP_T29_MONDC1
95
0.1uF
TP_T29_MONDC0
K19
H19
PCIE_T29_R2D_P<2>
PCIE_T29_R2D_N<2>
DEBUG: For monitoring current/voltage
95
95
10%
0.1uF
95 8
16V
0.1uF
95 8
402
0.1uF
X5R
PER_1_P
PER_1_N
97
THM
PAD
9
100 51
T29_CLKREQ_ISOL_L
T29_GPIO<1>
T29_GPIO<2>
T29_RSVD
P3
N4
M3
L4
PCIE_CLKREQ_0*
PCIE_CLKREQ_1*
PCIE_CLKREQ_2*
PCIE_CLKREQ_3*
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29_SPI_CLK
P1
M1
N2
L2
EE_DI
EE_DO
EE_CS*
EE_CLK
T29_THERMD_P
A2
THERM_DP
E4
P5
N6
M5
L6
TEST_EN
TEST_POINT_0
TEST_POINT_1
TEST_POINT_2
TEST_POINT_3
Use B1 GND ball for THERM_DN
T29_TEST_EN
TP_T29_TEST_POINT_0
TP_T29_TEST_POINT_1
TP_T29_TEST_POINT_2
T29_TEST_POINT_3
R3625
0
5%
1/16W
MF-LF
2 402
JTAG
PCIE_T29_R2D_C_P<2>
16V
P19
M19
PCIE_T29_R2D_P<1>
PCIE_T29_R2D_N<1>
POWER ON RESET
IN
95
0.1uF
95 8
95
CLOCKS
PCIE_T29_R2D_C_N<1>
402
MISC
IN
X5R
CLK REQUEST
95 8
16V
TRANSMIT
C3602
TEST PORT
PCIE_T29_R2D_C_P<1>
RECEIVE
IN
EEPROM
95 8
PCIE GEN2
(SYM 1 OF 2)
6
6
6
6
IN
8 19 88
PP3V3_T29
IN
16
IN
8 19 23 88
OUT
R3698
8 19 88
IN
16 95
IN
16 95
7 16 19 25 33 34 35 88
10K
5%
1/16W
MF-LF
2 402
R3695
1
R36961
T29_TMU_CLK_OUT
T29_TMU_CLK_IN
NO STUFF
1K
806
SYSCLK_CLK25M_T29
IN
25
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
R36991
10K
0.1uF
97 79 6
IN
DP_T29SNK0_ML_C_P<1>
C3622
0.1uF
97 79 6
IN
DP_T29SNK0_ML_C_N<1>
C3623
0.1uF
DP_T29SNK0_ML_N<0>
10%
X5R
97 33 6
97 33 6
DP_T29SNK0_ML_P<1>
6 33 97
97 33 6
16V
402
97 33 6
DP_T29SNK0_ML_N<1>
10%
X5R
6 33 97
16V
402
10%
X5R
6 33 97
16V
402
97 33 6
97 33 6
97 79 6
IN
C3624
0.1uF
97 79 6
IN
C3625
0.1uF
97 79 6
IN
C3626
0.1uF
97 79 6
IN
C3627
0.1uF
DP_T29SNK0_ML_P<2>
10%
X5R
DP_T29SNK0_ML_N<2>
6 33 97
OUT
R36301
100K
DP_T29SNK0_ML_P<3>
DP_T29SNK0_ML_N<3>
97 33 6
5%
1/16W
MF-LF
402 2
6 33 97
16V
402
10%
X5R
84 80
16V
402
10%
X5R
6 33 97
16V
402
10%
X5R
97 33 6
97 33 6
6 33 97
16V
402
97 33 6
97 33 6
97 79 6
BI
DP_T29SNK0_AUXCH_C_P
C3628
0.1uF
97 79 6
BI
DP_T29SNK0_AUXCH_C_N
C3629
0.1uF
10%
X5R
DP_T29SNK0_AUXCH_P
6 33 97
DP_T29SNK0_AUXCH_N
6 33 97
97 33 6
16V
402
10%
X5R
97 33 6
16V
402
97 33 6
97 33 6
SNK1 AC Coupling
DP_T29SNK1_ML_C_P<0> C3630
10% 16V
1
97 79 6
IN
97 79 6
IN
C3631
97 79 6
IN
C3632
IN
0.1uF
1
0.1uF
1
0.1uF
97 79 6
C3633
0.1uF
97 79 6
IN
C3634
0.1uF
97 79 6
IN
C3635
0.1uF
97 79 6
IN
C3636
0.1uF
97 79 6
IN
C3637
0.1uF
97 79 6
BI
C3638
BI
C3639
0.1uF
97 79 6
0.1uF
X5R
6 33 97
OUT
100K
DP_T29SNK1_ML_N<2>
5%
1/16W
MF-LF
402 2
DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>
97 85 6
IN
97 85 6
IN
85
OUT
85
IN
97 85 6
OUT
97 85 6
OUT
97 85 6
IN
6 33 97
97 85 6
6 33 97
DP_T29SNK0_ML_P<1>
DP_T29SNK0_ML_N<1>
DPSNK0_ML_LANE_1P
DPSNK0_ML_LANE_1N
DP_T29SNK0_ML_P<0>
DP_T29SNK0_ML_N<0>
AA10
Y9
DPSNK0_ML_LANE_0P
DPSNK0_ML_LANE_0N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
V1
W2
DPSNK0_AUX_CHP
DPSNK0_AUX_CHN
DP_T29SNK0_HPD
V5
DPSNK0_HOT_PLUG_DET
DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>
V9
U8
DPSNK1_ML_LANE_3P
DPSNK1_ML_LANE_3N
DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>
V11
U10
DPSNK1_ML_LANE_2P
DPSNK1_ML_LANE_2N
DP_T29SNK1_ML_P<1>
DP_T29SNK1_ML_N<1>
V13
U12
DPSNK1_ML_LANE_1P
DPSNK1_ML_LANE_1N
DP_T29SNK1_ML_P<0>
DP_T29SNK1_ML_N<0>
V15
U14
DPSNK1_ML_LANE_0P
DPSNK1_ML_LANE_0N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
V7
U6
DPSNK1_AUX_CHP
DPSNK1_AUX_CHN
DP_T29SNK1_HPD
U4
DPSNK1_HOT_PLUG_DET
T29_R2D_C_P<0>
T29_R2D_C_N<0>
A6
A4
PRT0_T29T_P
PRT0_T29T_N
T29_D2R_P<0>
T29_D2R_N<0>
C4
C2
PRT0_T29R_P
PRT0_T29R_N
T29_LSEO<0>
T29_LSOE<0>
J6
K5
T29_0_LSEO
T29_0_LSOE
DPSRC0_ML_LANE_3P
DPSRC0_ML_LANE_3N
AA18
Y17
TP_DP_T29SRC_ML_CP<3>
TP_DP_T29SRC_ML_CN<3>
DPSRC0_ML_LANE_2P
DPSRC0_ML_LANE_2N
AA16
Y15
DPSRC0_ML_LANE_1P
DPSRC0_ML_LANE_1N
AA14
Y13
DPSRC0_ML_LANE_0P
DPSRC0_ML_LANE_0N
AA12
Y11
W16
U16
TP_DP_T29SRC_AUXCH_CP
TP_DP_T29SRC_AUXCH_CN
V3
DP_T29SRC_HPD
Y19
Y21
AA20
T29_DP_ATEST
DPSRC0_AUX_CHP
DPSRC0_AUX_CHN
DPSRC0_HOT_PLUG_DET
DP_ATEST
DP_RES_0
DP_RES_1
6
6
6
6
6
6
6
6
6
6
100pF SRF > 40MHz

BYPASS=U3600.Y19::2mm
BYPASS=U3600.Y19::5.08mm
C3685
T29_DP_RES
100PF
1
R3685
14.0K
1%
1/16W
MF-LF
402 2
R3632
100K
5%
50V
CERM 2
402
C3686
0.01UF
10%
2 16V
CERM
402
5%
1/16W
MF-LF
2 402
IN
85
OUT
85
IN
97 85 48
BI
97 85 48
OUT
A10
A8
PRT1_T29T_P
PRT1_T29T_N
T29_D2R_P<1>
T29_D2R_N<1>
C8
C6
PRT1_T29R_P
PRT1_T29R_N
T29_LSEO<1>
T29_LSOE<1>
G6
H5
T29_1_LSEO
T29_1_LSOE
I2C_T29_SDA
I2C_T29_SCL
F3
F5
T29_SDA
T29_SCL
T29_R2D_C_P<1>
T29_R2D_C_N<1>
PRT2_T29T_P
PRT2_T29T_N
A14
A12
NC_T29_R2D_CP<2>
NC_T29_R2D_CN<2>
PRT2_T29R_P
PRT2_T29R_N
C12
C10
OUT
OUT
NC_T29_D2RP<2>
NC_T29_D2RN<2>
IN
IN
G4
H3
T29_LSEO_LSOE2
T29_LSEO_LSOE2
OUT
8 33
IN
8 33
PRT3_T29T_P
PRT3_T29T_N
A18
A16
NC_T29_R2D_CP<3>
NC_T29_R2D_CN<3>
OUT
OUT
PRT3_T29R_P
PRT3_T29R_N
C16
C14
NC_T29_D2RP<3>
NC_T29_D2RN<3>
IN
IN
G2
H1
T29_LSEO_LSOE3
T29_LSEO_LSOE3
OUT
8 33
IN
8 33
T29_2_LSEO
T29_2_LSOE
6 33 97
SYNC_MASTER=T29_REF
PAGE TITLE
T29_3_LSEO
T29_3_LSOE
6 33 97
16V
402
OUT
6 33 97
16V
402
DP_T29SNK1_AUXCH_N
OUT
97 85 6
6 33 97
16V
402
DP_T29SNK1_AUXCH_P
97 85 6
6 33 97
16V
402
10%
X5R
DPSNK0_ML_LANE_2P
DPSNK0_ML_LANE_2N
AA8
Y7
R36311
16V
402
10%
X5R
DP_T29SNK1_ML_P<1>
DP_T29SNK1_ML_P<2>
10%
X5R
6 33 97
16V
402
10%
X5R
DP_T29SNK1_ML_N<0>
84 80
16V
402
10%
X5R
6 33 97
DP_T29SNK1_ML_N<1>
10%
X5R
DP_T29SNK1_ML_P<0>
16V
402
10%
X5R
97 33 6
16V
402
10%
X5R
AA6
Y5
402
10%
X5R
DP_T29SNK0_ML_P<2>
DP_T29SNK0_ML_N<2>
PORT2
C3621
97 33 6
PORT3
97 33 6
402
SOURCE PORT 0
IN
97 33 6
5%
1/16W
MF-LF
402 2
6 33 97
SINK PORT 0
97 79 6
X5R
DP_T29SNK0_ML_P<0>
5%
1/16W
MF-LF
402 2
DISPLAY
0.1uF
DPSNK0_ML_LANE_3P
DPSNK0_ML_LANE_3N
PORTS
AA4
Y3
PORT0
IN
SNK0 AC Coupling
C3620
10% 16V
DP_T29SNK0_ML_P<3>
DP_T29SNK0_ML_N<3>
PORT1
97 79 6
97 33 6
SINK PORT 1
R36291
NOTE: All unused LSOE/EO pairs should be aliased

together. Other signals okay to float (TP/NC).
T29 Host (1 of 2)
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
36 OF 132
SHEET
33 OF 105
PP3V3_T29
7 16 19 25
135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA
CRITICAL
PP1V05_T29
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
OMIT_TABLE
C3700
10UF
20%
6.3V 2
X5R
603
C3701
10UF
20%
6.3V 2
X5R
603
C3705
1UF
10%
6.3V
2 CERM
402
C3710
1UF
10%
6.3V
2 CERM
402
C3706
1UF
10%
6.3V
2 CERM
402
C3711
1UF
10%
6.3V
2 CERM
402
C3707
1UF
10%
6.3V
2 CERM
402
C3712
1UF
10%
6.3V
2 CERM
402
C3708
1UF
10%
6.3V
2 CERM
402
C3713
1UF
10%
6.3V
2 CERM
402
C3709
1UF
10%
6.3V
2 CERM
402
C3714
1UF
10%
6.3V
2 CERM
402
R3720
1
5%
1/16W
MF-LF
402
PP1V05_T29_VDD_DP
VOLTAGE=1.05V
C3720
1UF
10%
2 6.3V
CERM
402
C3721
1UF
10%
2 6.3V
CERM
402
C3722
H9
H11
H13
K9
K11
K13
M9
M11
M13
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
U3600
VCC3P3
VCC3P3
VCC3P3
T29
FCBGA
(SYM 2 OF 2)
H15
K15
M15
E8
E10
E12
G14
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
R8
R10
R12
VDD1P0_DP_RX1
VDD1P0_DP_TXRX
VDD1P0_DP_TXRX
VCC3P3_T29
VCC3P3_T29
H7
M7
K7
C3744 1
C3743 1
C3745 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
G10
G12
1UF
1UF
C3746
10UF
20%
2 6.3V
X5R
603
P7
R6
C3747
10UF
20%
2 6.3V
X5R
603
PP3V3_T29_DP
VCC3P3_DP_TXRX
VCC3P3_DP_TXRX
P9
P11
VDD3P3DP_PLL
P13
C3753
1UF
10%
6.3V 2
CERM
402
C3752
1UF
C3751
10%
6.3V 2
CERM
402
1UF
10%
6.3V 2
CERM
402
C3750
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
1UF
0-ohms are placeholders for now, replace

with proper values after characterization.
10%
6.3V 2
CERM
402
R3760
PP3V3_T29_PLL
C3760
1UF
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
2.2UF
10%
2 6.3V
CERM
402
20%
6.3V 2
CERM
402-LF
L3730
L3770
FERR-120-OHM-1.5A
1
2
PP1V05_T29_VDD_DPPLL
FERR-120-OHM-1.5A
R14
VOLTAGE=1.05V
VCC3P3_DP_TXRXBIAS
P15
C3730
2.2UF
20%
2 6.3V
CERM
402-LF
VDD1P0_DP_PLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
C18
C20
D1
D3
D5
D7
D9
D11
D13
D15
D17
E18
E20
F7
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
T5
T7
T9
T11
T15
T17
V17
W4
W6
W8
W10
W12
W14
Y1
AA2
VSSDP_PLL
T13
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
F9
F11
F13
F15
F17
G18
G20
J16
J18
J20
L16
L18
L20
N16
N18
N20
R18
R20
U18
U20
W18
W20
PP3V3_T29_DPBIAS
C3770 1
G8
J8
J10
J12
J14
L8
L10
L12
L14
N8
N10
N12
N14
GND
0402
33 35 88
R3750
VCC3P3_DP_RX1
VCC3P3_DP_RX1
VCC
35 7
VOLTAGE=3.3V
2
0402
2.2UF
20%
6.3V 2
CERM
402-LF
SYNC_MASTER=T29_REF
PAGE TITLE
T29 Host (2 of 2)
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
BRANCH
PAGE
37 OF 132
SHEET
34 OF 105
Page Notes
- =PPVIN_SW_T29BST
(8-13V Boost Input)
- =PP18V_T29_REG
(18V Boost Output)
- =PP3V3_T29_P3V3T29FET
(3.3V FET Input)
- =PP3V3_T29_FET
(3.3V FET Output)
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET
(1.05V FET Input)
- =PP1V05_T29_FET
(1.05V FET Output)
Q3880
SI8409DB
PPBUS_G3H
8-13V Input
Changes required
for 2S.
T29BST:Y
D
G
C3880
470K
L3895
T29BST:Y
T29BST:Y
C3890
C3891
R3891
T29BST_SNS1
T29BST:Y
1%
1/16W
MF-LF
402 2
T29BST_PWREN_DIV_L
VIN
<R1> T29BST_EN_UVLO
R3881
25 EN/UVLO
330K
5%
1/16W
MF-LF
402 2
C3892
T29_A_HV_EN
5%
2 50V
CERM
402
T29BST:Y
1
R3892
C3893
0.01UF
1%
1/16W
MF-LF
2 402
10K
1%
1/16W
MF-LF
402 2
10%
2 50V
X7R
402
LT3957
SNS2
30 VC
T29BST_RT
33 RT
41.2K
NC
SGND
C3889
100PF
GND
5%
2 50V
CERM
402
GND_T29BST_SGND
VOLTAGE=0V
SGND shorted to
GND inside package,
no XW necessary.
MF-LF
402 2
<Ra>
T29BST_FBX
T29BST:Y
NO STUFF
1
31
C3894
10%
2 6.3V
CERM-X5R
402
DFLS230L
PLACE_NEAR=C3895.1:2 mm
T29BST_VSNS
T29BST:Y
NO STUFF R38951
137K
C3888
1%
100PF
1/16W
5%
2 50V
CERM
402
34 SYNC
0.33UF
1%
1/16W
MF-LF
402 2
D3895
POWERDI-123
XW3895
SM
32 SS
T29BST:Y
R3894
1
2
10
35
36
CRITICAL
T29BST:Y
T29BST_SNS2
QFN
FBX
UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
Supervisor & CLKREQ# Isolation
T29BST_VC
T29BST_SS
<R2>
R3896
15.8K
1%
1/16W
MF-LF
402 2
<Rb>
PP15V_T29
T29BST:Y
1
T29BST:Y
C3895
4.7UF
C3897
4.7UF
10%
2 50V
X7R-CERM
1206
10%
2 50V
X7R-CERM
1206
T29BST:Y
T29BST:Y
C3896
C3898
4.7UF
4.7UF
10%
50V
X7R-CERM 2
1206
10%
50V
X7R-CERM 2
1206
7 8 86
Vout = 15.47V
Max Current = 1A
Freq = 300KHz
T29BST:Y
1
C3899
0.001UF
10%
50V
2 X7R
402
Vout = 1.6V * (1 + Ra / Rb)
PP3V3_S0
PP3V3_T29
T29BST:Y
7 16 19 25 33 34 35 88
6 D
0.1UF
PLT_RST_BUF_L
SLG4AP016V
PP1V05_T29
TDFN
R38032
1 S
7 34 35
G 2
R3887
IN
T29_SW_RESET_L
3 MR*
16
OUT
T29_CLKREQ_L
6 EN
8 OUT
5%
1/16W
MF-LF
2 402
T29BST:Y
3 D
330K
RESET* 4
IN 7
(OD)
Pull-up provided by SB page.
R3888
T29BST_SHDN_DIV
T29BST:Y
DLY
19
T29BST:Y
1
330K
Max Vgs: 10V
5%
1/16W
MF-LF
402 1
T29_RESET_L
DLY = 60 ms +/- 20%
T29_CLKREQ_ISOL_L
T29_CLKREQ_ISOL_L
SOT563
4 S
IN
Q3888
SSM6N37FEAPE
5%
1/16W
MF-LF
2 402
33
OUT
MAKE_BASE=TRUE
THRM
PAD
33 35
G 5
SMC_DELAYED_PWRGD
33 35
IN
45 91
GND
5
SOT563
+ SENSE 2
- 0.7V
10K
Open-Drain GPIO
R3807
5%
1/16W
MF-LF
2 402
U3800
Q3888
SSM6N37FEAPE
100K
VDD
10%
25V 2
X5R
402
Platform (PCIe) Reset
CRITICAL
C3800 1
IN
SNS1
NC
R38931
T29BST_VC_RC
T29BST:Y
T29BST:Y
1
S 2
73.2K
32 25
U3890
5%
1/16W
MF-LF
402 2
SW
T29BST:Y
C3887
100PF
10%
10V 2
X5R
805
SOD-VESM-HF
1
NO STUFF
4.7UF
SSM3K15FV
100 91 89 88 85 84 83 80 73 72 62
39 36 35 32 28 26 25 23 12 7 6
61 57 54 52 51 50 49 48 46 41 40
102
CRITICAL
T29BST:Y
4
23
24
37
T29BST:Y
D 3
Q3805
R38891
T29BST:Y
IN
28 INTVCC
T29BST_INTVCC
T29BST_PWREN_L
86 85
T29BST_BOOST
SWITCH_NODE=TRUE
DIDT=TRUE
10%
25V
X5R 2
805
200K
T29BST:Y
PCMB063T-100MS
10UF
10%
25V
X5R 2
805
10%
25V
2 X5R
402
10UF
T29BST:Y
0.1UF
5%
1/16W
MF-LF
402 2

T29BST:Y - Stuffs 18V boost circuitry.
T29BST:Y
R38801

- =T29_CLKREQ_L
- =T29_RESET_L
10UH-4A-68-MOHM
1
Voltage not specified here,
add property on another page.
CRITICAL
T29BST:Y
PPVIN_SW_T29BST
BGA
T29 15V Boost Regulator
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
CRITICAL
T29BST:Y
90 64 63 50 49 39 8 7 6
8
9
20
21
38
12
13
14
15
16
17
27
3.3V T29 Switch

102 100 91
73 72 62 61
48 46 41 40
25 23 12 7
36 35 32 28
54 52 51 50
88 85 84 83
89
57
39
6
26
49
80
U3810
TPS22924
PP3V3_S0
A2
B2
CSP
VIN
VOUT
PP3V3_T29
7 16 19 25 33 34
Max Current = 1.7A (85C)
A1
B1
U3810 & U3815/U3816
CRITICAL
C2 ON
1UF
GND
Part
TPS22924C
10%
6.3V 2
CERM
402
C1
C3810 1
35 88
Type
Load Switch
R(on)
18 mOhm Typ
50 mOhm Max
Max Output: 2A per IC
1.05V T29 Switch

U3815
104 102 73 70
13 12 10 9 7
68 45 39 23 14
105
TPS22924
PP1V05_S0
A2
B2
C3815 1
10%
6.3V
CERM 2
402
VOUT
A1
B1
PP1V05_T29
7 34 35
CRITICAL
C2 ON
GND
C1
1UF
CSP
VIN
SYNC_MASTER=T29_REF
PAGE TITLE
T29 Power Support
U3816
TPS22924
A2
B2
CSP
VIN
VOUT
DRAWING NUMBER
A1
B1
Apple Inc.
T29_PWR_EN
C2 ON
U3816.A2: PLACE_NEAR=U3815.B2:3 mm
GND

C1
IN
Pull-up provided by SB page.
CRITICAL
16
SIZE
REVISION
BRANCH
PAGE
38 OF 132
SHEET
35 OF 105
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
73 71 36
25 7 PP3V3_ENET
281mA (1000base-T max power, Caesar IV)
36
CRITICAL
ENET_SR_LX
71
L3900
PP1V2_ENET
7 36 71
Internal 1.2V Switching Regulator pins.
VOLTAGE=3.3V
SM
C3900
CRITICAL
L3920
FERR-600-OHM-0.5A
VOLTAGE=1.2V
10%
16V
X7R-CERM 2
402
CRITICAL
FERR-600-OHM-0.5A
1
2
PP3V3_S3_ENET_PHY_BIASVDDH
SM
C3921 1
10%
16V
X7R-CERM 2
402
10%
2 6.3V
X5R-CERM
603
0.1UF
L3905
VOLTAGE=3.3V
C3905
10%
2 16V
X7R-CERM
402
5%
1/16W
MF-LF
402 2
0.1UF
C3931 1
ENET_VMAIN_PRSNT
0.1uF
1
2
10%
16V
X5R
402
95
95
0.1uF
95 16
95 16
IN
IN
PCIE_ENET_R2D_C_P
2
10%
16V
X5R
402
PCIE_ENET_R2D_C_N
C3956
0.1uF
1
R3943
25
OUT
ENET_WAKE_L
(See note)
95
2
10%
16V
X5R
402
33 PCIE_RXD_P
34 PCIE_RXD_N
IN
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
IN
ENET_RESET_L
11 PERST*
OUT
ENET_CLKREQ_L
12 CLKREQ* (OD)
IN
95 16
96 32
32 19
35
61
GPHY_PLLVDDL 36
29
32
39
45
51
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
ENET_LOW_PWR
IN
36
36
36
36
6
6
25
6 SMB_CLK
10 SMD_DATA (IPD)
BCM57765_SCLK
BCM57765_MISO
BCM57765_MOSI
BCM57765_CS_L
66
64
65
63
NC
BCM57765_RDAC
SCLK
SI/LINKLED*
SO
CS*
2 SPD100LED*/SERIAL_DO
67 TRAFFICLED*/SERIAL_DI
SYSCLK_CLK25M_ENET
IN
CRITICAL
(IPD)
(OD)
(OD)
18 XTALI
19 XTALO
38 RDAC
10%
2 6.3V
X5R
805
C3935
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

the card reader on-chip I/O.
Connect only to U3900 pin 20.
10UF
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
40
41
44
43
46
47
50
49
5
8
9
37 96
BI
37 96
BI
37 96
BI
37 96
BI
37 96
BI
37 96
BI
37 96
BI
37 96
MAKE_BASE=TRUE
VOLTAGE=1.8V
C3970
4.7UF
10%
2 6.3V
X5R-CERM
603
C3971
0.1UF
10%
2 16V
X7R-CERM
402
C3972
0.1UF
10%
2 16V
X7R-CERM
402
ENET_MEDIA_SENSE
o1
OUT
25
TP_SDCONN_DETECT_L
IN
26
TP_SDCONN_CMD
IN
CR_CLK/RY_BY* 21
TP_SDCONN_CLK
OUT
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
25
24
23
22
52
53
54
55
CE*/MS_INS*
CR_LED/ALE
CR_WP*/XD_WP*
XD_DETECT
59
60
57
68
TP_SDCONN_DATA<0>
TP_SDCONN_DATA<1>
TP_SDCONN_DATA<2>
TP_SDCONN_DATA<3>
TP_SDCONN_DATA<4>
TP_SDCONN_DATA<5>
TP_SDCONN_DATA<6>
TP_SDCONN_DATA<7>
NC_CE_L_MS_INS_L
TP_ENET_CR_PWREN
OUT
BDM57765_SR_DISABLE
R3980
BI
BI
BI
BI
BI
BI
BI
BI
No MS (Memory Stick) Insert feature needed.

Control signal to light LED or control SD bus power.
TP_SDCONN_WP
IN 8
1K 1
2
5%
1/16W MF-LF 402
69
R3965
1.24K
ROM contains MAC address, PCIe config

info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
PP3V3_ENET
73 71 36 25 7
BI
NC
THRM_PAD
PHY Non-Volatile Memory
36
PP3V3R1V8_ENET_LR_OUT_REG 36
BCM57765B0
GPIO_0
GPIO_1/CR_BUS_PWR
RE*/GPIO_2
NOTE: "IPx" == Programmable pull-up/down
3 WAKE*
(OD)
(IPx)
SD_DETECT/WE*
SD_DETECT can only be used active low due to errata.
4 LOW_PWR (IPD)
(IPU) CR_CMD/CLE
BCM57765_SMB_CLK
BCM57765_SMB_DATA
Must isolate from PCIe WAKE# if PHY

is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
ENET_WAKE_R_L
5%
1/16W
MF-LF
402
WAKE#
27 PCIE_TXD_N
28 PCIE_TXD_P
31 PCIE_REFCLK_P
30 PCIE_REFCLK_N
95 16
16
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
CRITICAL
PP3V3R1V8_ENET_LR_OUT_REG
QFN-8X8
95
C3955
58 VMAIN_PRSNT (IPD)
(IPU)
PCIE_ENET_D2R_P
OMIT
U3900
C3951
4.7UF
10%
16V
X7R-CERM 2
402
VDDC
SM
C3930
C3936 1
0.1UF
(IPD)
10%
16V
X5R
402
(IPU)
OUT
5%
Current
1/16W Limiting
MF-LF
Resistor
2 402
(IPU)
95 16
AVDDL
PCIE_PLLVDDL
1K
0.1uF
OUT
VDDO
SR_LX 16
AVDDH
SR_VFB 13
0.1UF
SR_VDD 14
10%
2 16V
X7R-CERM
402
L3930
10%
2 6.3V
X5R-CERM
603
C3916
SR_VDDP 15
10%
6.3V
X5R-CERM 2
603
4.7UF
R3942
C3950
PCIE_ENET_D2R_N
0.1UF
7
20
56
62
C3915 1
5%
1/16W
MF-LF
2 402
CRITICAL
VOLTAGE=1.2V
0.1UF
10%
2 16V
X7R-CERM
402
95 16
4.7UF
10%
16V
X7R-CERM 2
402
4.7K
SM
C3925
10%
2 6.3V
X5R-CERM
603
C3911
XTALVDDH 17
PP3V3_S0
BIASVDDH 37
R3941
5%
1/16W
MF-LF
402 2
L3925
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_GPHYPLL
42
48
4.7K
C3910
0.1UF
4.7K
R39401
10%
16V
X7R-CERM 2
402
L3910
R39101
CRITICAL
VOLTAGE=1.2V
C3926 1
FERR-600-OHM-0.5A
1
2
PP3V3_S3_ENET_PHY_AVDDH
SM
C3920
4.7UF
0.1UF
VOLTAGE=3.3V
2
SM
FERR-600-OHM-0.5A
1
2
PP1V2_ENET_PHY_PCIEPLL
10%
2 16V
X7R-CERM
402
CRITICAL
PP1V2_ENET_PHY_AVDDL
0.1UF
102 100 91 89 88 85
48 46 41 40 39 35 32 28 26 25 23 12 7 6
84 83 80 73 72 62 61 57 54 52 51 50 49
PP1V2_ENET
7 36 71
???mA (1000base-T, Caesar V)
VDD for Card Reader I/O

PP3V3R1V8_ENET_LR_OUT_REG
FERR-600-OHM-0.5A
1
2
PP3V3_S3_ENET_PHY_XTALVDDH
1%
1/16W
MF-LF
2 402
BCM57765 supports both active-levels for WP.
SR_DISABLE must be pulled down to use

internal SR. IPD has a race condition.
C3990
0.1UF
VCC
10%
2 16V
X7R-CERM
402
U3990
AT45DB011D
SOIC-8S1
36
BCM57765_SCLK
SCK
36
BCM57765_CS_L
CS*
WP*
RESET*
OMIT
SI 1
BCM57765_MOSI
36
SO 8
BCM57765_MISO
36
R3990
4.7K
5%
1/16W
MF-LF
2 402
DRAWING NUMBER
R3997
Apple Inc.
4.7K
5%
1/16W
MF-LF
2 402
SIZE
D
REVISION
NOTE: Pull-down on SO plus internal pull-ups on

other 3 SPI pins configures ENET for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: ENETM requires SI pull-down instead of SO.
PAGE TITLE
ETHERNET PHY (CAESAR IV)
NOSTUFF
1
GND
7

BRANCH
PAGE
39 OF 132
SHEET
36 OF 105
Page Notes
(NONE)
(NONE)
(NONE)
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
1 C40021 C40041 C4006

C4000
0.1UF 0.1UF 0.1UF 0.1UF
10%
2 16V
X5R
402-1
10%
2 16V
X5R
402-1
10%
2 16V
X5R
402-1
10%
2 16V
X5R
402-1
CRITICAL
96 36
BI
ENET_MDI_P<0>
96 36
BI
ENET_MDI_N<0>
T4000
SM
12
100
ENETCONN_P<0>
11
100
ENETCONN_N<0>
10
ENET_CTAP0
ENET_CTAP1
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
TLA-6T213HF
10
96 36
BI
ENET_MDI_N<1>
100
ENETCONN_N<1>
96 36
BI
ENET_MDI_P<1>
100
ENETCONN_P<1>
1
2
3
RX
4
5
CRITICAL
96 36
96 36
BI
ENET_MDI_N<2>
BI
ENET_MDI_P<2>
T4001
SM
6
7
12
100
ENETCONN_N<2>
11
100
ENETCONN_P<2>
11
12
10
ENET_CTAP2
ENET_CTAP3
TX
4
96 36
96 36
TLA-6T213HF
514-0636
BI
ENET_MDI_N<3>
100
ENETCONN_N<3>
BI
ENET_MDI_P<3>
100
ENETCONN_P<3>
RX
Transformers should be
1R40011
mirrored on opposite
R4000
75
75
sides of the board
5%
5%
1/16W
MF-LF
4022
1/16W
MF-LF
4022
1R4003
R4002
75
75
5%
1/16W
MF-LF
2402
CRITICAL
5%
1/16W
MF-LF
2402
ENET_BOB_SMITH_CAP
PLACE_NEAR=T4001.1:5mm
SLP2510P8
10%
2KV
CERM
1206
PLACE_NEAR=T4000.5:5mm
NC
IO
NC
IO
NC
IO
NC
IO
6 5 7 4 9 2 10 1
D4000
RCLAMP0524P
GND
D4001
RCLAMP0524P
GND
NC
IO
NC
IO
NC
IO
NC
IO
6 5 7 4 9 2 10 1
C4008
1000PF
SLP2510P8
CRITICAL
NOSTUFF
CRITICAL
NOSTUFF
PAGE TITLE
Ethernet Connector
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
40 OF 132
SHEET
37 OF 105
PP3V3_FW_FWPHY
7 mA I/O
C4120 1
C4121 1 C4122 1
1UF
1UF
10%
6.3V 2
CERM
402
C4123 1 C4124 1
1UF
10%
6.3V 2
CERM
402
7 38 39 40
138 mA
1UF
10%
6.3V 2
CERM
402
1UF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
L4130
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VDDA
114 mA FireWire PHY
C4130 1 C4131 1
1UF
PP1V0_FW_FWPHY
VOLTAGE=1.0V
5%
1/16W
MF-LF
402
135 mA
10%
6.3V 2
CERM
402
L4135
120-OHM-0.3A-EMI
1
2
PP1V0_FW_FWPHY_AVDD
PP1V0_FW_R
25 mA PCIe SerDes
VOLTAGE=1.0V
0402-LF
C4110
1UF
10%
2 6.3V
CERM
402
C4100
1UF
10%
2 6.3V
CERM
402
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
C4111
1UF
C4135 1
C4136 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
10%
2 6.3V
CERM
402
110 mA Digital Core

1
0402-LF
1UF
10%
6.3V 2
CERM
402
L4110
R4100
39 7
C4132 1
1UF
10%
6.3V 2
CERM
402
VOLTAGE=3.3V
VOLTAGE=3.3V
0402-LF
1UF
0 mA VReg PWR
C4101
1UF
10%
2 6.3V
CERM
402
C4102
1UF
10%
2 6.3V
CERM
402
C4103
1UF
10%
2 6.3V
CERM
402
C4104
1UF
C4105
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C4106
C4141 1
1UF
0.1UF
20%
10V
CERM 2
402
10%
2 6.3V
CERM
402
C4140
1UF
10%
2 6.3V
CERM
402
C
VDD10
40
IN
40
IN
40
PPVP_FW_CPS
R41601
200K
1%
1/16W
MF-LF
402 2
IN
40
BI
40 6
BI
96 40
BI
96 40
BI
40 6
BI
40 6
BI
40 6
BI
40 6
BI
96 40
BI
96 40
BI
40 6
BI
40 6
BI
40
BI
40 39
BI
40 6
BI
NC_FW0_TPBIAS
FW_P1_TPBIAS
NC_FW2_TPBIAS
C4150
R4150
22PF
2
1
NC
22PF
Y4150
24.576MHZ
412
1%
1/16W
MF-LF
402
SM-3.2X2.5MM
R41611
2.94K
1%
1/16W
MF-LF
402 2
C4151 NC
2 4
5%
50V
CERM
402
FW_CLK24P576M_XO
CRITICAL
R4170
191
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
R41621
470K
5%
1/16W
MF-LF
402 2
B8
A8
B5
A5
B3
A3
B9
A9
B6
A6
B4
A4
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
K12
L5
L10
L6
L9
REFCLKN N9
REFCLKP N10
PCI EXPRESS PHY
95
95
95
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
C4176
1
0.1UF
TP_FW643_TCK
NC_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-2 (IPU) TRST* N1
FW643_TRST_L
16 95
IN
16 95
POWER MANAGEMENT
NT-12 (IPD)
NT-13
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
C2
D13
E1
D2
L2
16 95
IN
16 95
10%
2 16V PCIE_FW_D2R_N
OUT 16 95
X5R402-1PLACE_NEAR=U1800.BJ36:2.54mm
10%
2 16V PCIE_FW_D2R_P
OUT 16 95
X5R402-1
0.1UF
IN
IN
PLACE_NEAR=U1800.AU34:2.54mm
PCIE_FW_R2D_C_P
PLACE_NEAR=U1800.BG36:2.54mm
C4175
1
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
M4
N2
M1
M3
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
FIXME!!! - TYPO IN SYMBOL REGCTL
PP3V3_FW_FWPHY
7 38 39 40
FW643_LDO
R41651
FW643_WAKE_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_PHY_L
OUT
8 39
OUT
39
5%
1/16W
MF-LF
402 2
R4166
10K
5%
1/16W
MF-LF
2 402
R4164
10K
K1
L8
F13
G13
NAND_TREE
REXT
XO
XI NT-9
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
M13
N13
J2
L13
D12
D1
A10
H13
K13
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
N12
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
5%
1/16W
MF-LF
2 402
MISCELLANEOUS
CHIP RESET
NT-5 PERST*
IN
39
R4163
10K
J12 OCR_CTL_V10
J13 OCR_CTL_V12 (Reserved)
VSS
10%
2 6.3V
CERM-X5R
402
95
BGA
NT-10 (IPD)
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
NC
N8
N7
N5
N6
PCIE_FW_R2D_C_N
10K
B11 R0
B10 TPCPS
0.33UF
FW643
1394 PHY
FW643_R0
FW643_TPCPS
C4162
0.1UF
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
TEST CONTROLLER
10%
2 16V
X5R402-1
10%
2 16V
X5R402-1
C4171
1
VREG_PWR
U4100
B7 TPBIAS0
C3 TPBIAS1
A2 TPBIAS2
TP_FW643_OCR10_CTL
1
VP25
OMIT
CRITICAL
B13 ATBUSB
A13 ATBUSH
A11 ATBUSN
F12 DS0 (IPD) NT-19
E12 DS1 (IPD) NT-20
E13 DS2 (IPD) NT-21
NC_FW0_TPAN
NC_FW0_TPAP
FW_PORT1_TPA_N
FW_PORT1_TPA_P
NC_FW2_TPAN
NC_FW2_TPAP
NC_FW0_TPBN
NC_FW0_TPBP
FW_PORT1_TPB_N
FW_PORT1_TPB_P
NC_FW2_TPBN
NC_FW2_TPBP
VP
5%
1/16W
MF-LF
2 402
VREG_VSS
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
40
FWPHY_DS0
FWPHY_DS1
FWPHY_DS2
VDDH
VDD33
PLACE_NEAR=U1800.AV34:2.54mm
C4170
1
L12
NC
NC
NC
A12
D5
D6
D8
C1
C12
F1
G12
J1
L3
L11
M2
A1
B1
B12
C13
E2
E10
H2
H12
K2
L1
M12
N3
N11
SYNC_MASTER=K91_MLB
PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
41 OF 132
SHEET
38 OF 105
Page Notes
Power aliases required

- =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
- =PP3V3_FW_P3V3FWFET
- =PP3V3_FW_FET
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL
- =PP1V05_FW_P1V0FWFET
- =PP1V0_FW_FET_R
- =PP1V0_FW_FWPHY
FireWire Port Power Switch
by this page:
(FW VP FET Input)
(FW VP FET Output)
(3.3V FET Input)
(3.3V FET Output)
(PHY 3.3V Power)
CRITICAL
Q4260
CRITICAL
FDC638P_G
90 64 63 50 49 35 8 7 6
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5
4
2
(5KPD Bias Rail)

(1.0V FET Input)
(1.0V FET Output)
(PHY 1.0V)
R4262
R4260
10K
FWPORT_FASTOFF_L_DIV

- =FW_CLKREQ_L
- =FW_PME_L
(SYM-VER2)
SOT-363
PPVP_FW
6 7 40
CRS08-1.5A-30V
10%
25V 2
X5R
402
Q4262
R4263
CRITICAL
D
10

(NONE)
MINISMDC110H24 VOLTAGE=12.6V
FWPORT_PWREN_L_DIV
BSS8402DW
PPBUS_FW_FWPWRSW_D
0.1UF
5%
1/16W
MF-LF
2 402
C4260 1
300K
5%
1/16W
MF-LF
402 2
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
D4260
SM
1.1A-24V
6
PPBUS_G3H
CRITICAL
F4260
SM
5%
1/16W
MF-LF
402 2
FWPORT_FASTOFF_L
1
R4261
5%
1/16W
MF-LF
2 402
BSS8402DW
FWPORT_PWREN_L
SOT-363
(SYM-VER1)
40 39 38 7
CRITICAL
D 3
Q4261
40
0.1UF
0.1UF
SOD-VESM-HF
1
C4290 1
NO STUFF
C4261 1
SSM3K15FV
G
S 2
10%
25V 2
X5R
402
29 25 18
IN
R4290
5%
1/16W
MF-LF
2 402
SLG4AP016V
PP1V0_FW_FWPHY
TDFN
10K
5%
1/16W
MF-LF
1 402
39 19
IN
23 16
OUT
7 38 39
2
+ SENSE
- 0.7V
R4283
DLY
FW_RESET_R_L
RESET* 4
3 MR*
FW_PWR_EN
FW_CLKREQ_L
6 EN
8 OUT
FW_RESET_L
OUT
DLY = 60 ms +/- 20%
FW_CLKREQ_PHY_L
FW_CLKREQ_PHY_L
IN 7
(OD)
Pull-up provided by another page.
GND
5
PP1V05_S0
100K
U4290
105
35 23 14 13 12 10 9 7
104 102 73 70 68 45 39
CRITICAL
VDD
10%
25V 2
X5R
402
PLT_RESET_L
FWPORT_PWR_EN
IN
PP3V3_FW_FWPHY
PP3V3_S0
Q4262
PP3V3_S0
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
MAKE_BASE=TRUE
THRM
PAD
IN
38
38 39
38 39
CRITICAL
D
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
Supervisor & CLKREQ# Isolation
470K
FireWire Port 5K Pull-Down Detect

R42751
All FireWire devices require 5K pull-down on TPB pair.

Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.
1K
5%
1/16W
MF-LF
402 2
3.3V FW Switch
FW_PWR_EN_L
U4201
330K
Q4275
SOT-563
IN
FW_PWR_EN
2 G
CRITICAL
5%
1/16W
MF-LF
402 2
Q4270
BC847CDXV6TXG
SOT563
FWDET_MIRROR
CRITICAL
C4270
U4201 & U4202
10%
16V
X5R 2
402
R42721
R42731
5%
1/16W
MF-LF
402 2
PLACE_NEAR=C4360.1:2 mm
5%
1/16W
MF-LF
402 2
1.0V FW Switch
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
TPS22924
PP1V05_S0
A2
B2
CSP
VIN
VOUT
TPS22924C
Type
Load Switch
R(on)
18 mOhm Typ
50 mOhm Max
1UF
40 39 38 7
10%
6.3V 2
CERM
402
C2 ON
R4202
GND
0.549
1%
1/16W
MF
2 402
R4276
FW_PLUG_DET_L
8 19
OUT
Pull-up provided on another page.
3 CRITICAL
100K
5%
1/16W
MF-LF
2 402
FW_WAKE
NO STUFF
6
D
FW643_WAKE_L
C4276
Q4276
DMB53D0UV
SOT-563
SYNC_MASTER=K91_MLB
0.1UF
10%
16V
X5R 2
402
PAGE TITLE
FireWire Port & PHY Power

DRAWING NUMBER
2 G
MAKE_BASE=TRUE
Apple Inc.
CRITICAL
Q4276
S
SIZE
D
REVISION
DMB53D0UV
SOT-563
7 38 39
1) 5K Pull-down Detect when FW_PWR_EN is low.

2) FW643 WAKE# (PME#) when PHY is powered.
10K
FW643_WAKE_L
LSI FireWire PHY requires 1.0V.

To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.
Dual-purpose output:
5%
1/16W
MF-LF
402 2
IN
VOLTAGE=1.05V
PP1V0_FW_FWPHY
PP3V3_FW_FWPHY
R42771
39 38 8
Max Output: 2A
PP1V05_FW_FET
A1
B1
CRITICAL
C4202 1
FW_P1_TPBIAS
FireWire PHY WAKE# Support
Part
U4202
12K
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
PP3V3_FW_FWPHY 7 38 39 40
A1
B1
GND
10%
6.3V
CERM 2
402
SOT-563
0.1UF
BC847CDXV6TXG
SOT563
VOUT
C2 ON
1UF
DMB53D0UV
1
CSP
VIN
CRITICAL
C4201 1
Q4275
FWDET_EMIT
1K
IN
A2
B2
FW_P1_TPBIAS_R
40 38
CRITICAL
Q4270
TPS22924
PP3V3_S0
MAKE_BASE=TRUE
FW_5KPD_DET_RC
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
FW_5KPD_DET_L
56K
5%
1/16W
MF-LF
2 402
DMB53D0UV
39 19
R42711
R4270
C1
CRITICAL
C1

BRANCH
PAGE
42 OF 132
SHEET
39 OF 105
Page Notes
FW643 TPCPS Leakage Protection

- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS
(To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
SOT-363
BSS8402DW
PPVP_FW_CPS
To FW643
R4311
VOLTAGE=12.6V
MAKE_BASE=TRUE
470K
5%
1/16W
MF-LF
402 2

(NONE)
IN
NC_FW0_TPBIAS
BI
NC_FW0_TPAP
40 38
BI
NC_FW0_TPAN
40 38 6
BI
NC_FW0_TPBP
40 38 6
BI
NC_FW0_TPBN
40 38 6
IN
NC_FW2_TPBIAS
40 38 6
BI
NC_FW2_TPAP
40 38 6
BI
NC_FW2_TPAN
40 38 6
BI
NC_FW2_TPBP
40 38 6
BI
NC_FW2_TPBN
38 40
38 40
CPS_EN_L_DIV
1
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
40 38
40 38 6
R4312
330K
5%
1/16W
MF-LF
402 2
NC_FW0_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPAP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPAN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPAP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPAN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBN
MAKE_BASE=TRUE
NO_TEST=TRUE
FireWire PHY Config Straps

Configures PHY for:
- Port "1" Bilingual (1394B)
40 39 38 7
PPVP_FW_CPS
Disabled per LSI instructions

(All unused port signals TP/NC)
Q4300
(SYM-VER2)
PPVP_FW
From Port
40 39 7 6

- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
Unused FireWire Ports
FW643 has internal leakage path from TPCPS pin to VDD33.

FET blocks current to TPCPS until VDD33 is powered.
PP3V3_FW_FWPHY
38 40
R43821
R4380
10K
6 38 40
10K
1%
1/16W
MF-LF
402 2
38 40
1%
1/16W
MF-LF
2 402
6 38 40
FWPHY_DS0
38
40
FWPHY_DS0
MAKE_BASE=TRUE
6 38 40
FWPHY_DS1
40 38
FWPHY_DS1
MAKE_BASE=TRUE
40
38
6 38 40
FWPHY_DS2
FWPHY_DS2
MAKE_BASE=TRUE
6 38 40
D
OUT
38 40
OUT
38 40
OUT
38 40
R4381
10K
6 38 40
1%
1/16W
MF-LF
2 402
6 38 40
6 38 40
CPS_EN_L
6
D
40 39 38 7
CRITICAL
Q4300
PP3V3_FW_FWPHY
2
BSS8402DW
G
S
SOT-363
(SYM-VER1)
39 38
IN
CRITICAL
Cable Power
Termination
Place close to FireWire PHY
40 39 7 6
L4310
FERR-250-OHM Note: Trace PPVP_FW_PORT1 must handle up to 5A

1
2
PPVP_FW_PORT1_F
PPVP_FW
FW_P1_TPBIAS
SM
1
C4314
VOLTAGE=33V
0.01UF
10%
2 50V
X7R
402
C4360
0.33UF
10%
2 6.3V
CERM-X5R
402
(FW_PORT1_TPA_N)
(FW_PORT1_TPA_P)
"Snapback" & "Late VG" Protection

SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
1%
1/16W
MF-LF
2 402
96 40 38
96 40 38
BI
BI
R4361
56.2
1%
1/16W
MF-LF
402 2
C4350
10%
16V 2
X5R
402
FW_PORT1_TPA_P
MAKE_BASE=TRUE
96 40
38
FW_PORT1_TPA_N
FW_PORT1_TPA_N
TP_FWLATEVG_VCLMP
MAKE_BASE=TRUE
96 40 38
BI
FW_PORT1_TPB_P
96 40
38
FW_PORT1_TPB_P
96 40 38
BI
FW_PORT1_TPB_N
96 40
38
FW_PORT1_TPB_N
39
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
R4362
56.2
1%
1/16W
MF-LF
2 402
CRITICAL
J4310
0.1UF
96 40
38
FW_PORT1_TPA_P
BILINGUAL
PLACE_NEAR=U4350.1:2 mm
OUT
U4350
R43501
100K
R4363
(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)
TPD4S1394
3 VCLMP
LLP
CRITICAL
MAKE_BASE=TRUE
F-RT-TH
VCC
4 FWPWR_EN
FWPORT_PWR_EN
1394B-M97
56.2
PORT 1
PP3V3_S0
GND
D1+
D1-
D2+
D2-
NC
(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF
(FW_PORT1_TPA_P)
R4360
88 85 84 83 80 73 72 62 61 57
35 32 28 26 25 23 12 7 6
54 52 51 50 49 48 46 41 39 36
102 100 91 89
5%
1/16W
MF-LF
402 2
56.2
1%
1/16W
MF-LF
402 2
PLACE_NEAR=J4310.5:2 mm
C4319 1
FW_PORT1_TPB_C
0.1uF
C4364
220pF
5%
2 25V
CERM
402
10%
50V 2
X7R
603-1
(FW_PORT1_TPB_N)
R4364
4.99K
(FW_PORT1_TPB_P)
1%
1/16W
MF-LF
402 2
R4319
1M
PLACE_NOTE=J4310.5:2 mm
TPB(R)
TPBTPB<R>
TPB+
VP
OUTPUT
TPB+
VP
SC/NC
NC
VG
TPA-
VG
TPATPA<R>
TPA+
10
11
12
13
INPUT
TPA(R) TPA+
CHASSIS
GND
SYNC_MASTER=K91_MLB
514S0605
FireWire Connector
AREF needs to be isolated from all

local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
PAGE TITLE
5%
1/16W
MF-LF
2 402
TPB-
1
9
2
8
7
6
3
5
4
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
43 OF 132
SHEET
40 OF 105
ODD Power Control

CRITICAL
Q4590
TPCP8102
23V1K-SM
PP5V_SW_ODD_R
VOLTAGE=5V
87 73 70 69 68 65 54 52 47 41 22 8 7 6 PP5V_S0
105 104
5%
1/16W
MF-LF
402
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6 PP3V3_S0
83 80 73 72 62 61 57 54 52 51 50 49 48
0.068UF
5%
1/16W
MF-LF
402
ODD_PWR_EN_LS5V_L
100K
0.01UF
1
ODD_PWR_SS
C4596
5%
1/16W
MF-LF
402
CRITICAL
Q4596
10%
10V
CERM
402
R4595
R4597 1
100K
C4595
100K
R4596 1
NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.
10%
16V
CERM
402
SSM6N15FEAPE
2
CRITICAL
SOT563
R4598
ODD_PWR_EN
Q4596
1 3
ISNS_ODD_P
OUT
100 103
ISNS_ODD_N
OUT
100 103
0.005
2
1%
1W
MF
0612
SSM6N15FEAPE
SOT563
19
ODD_PWR_EN_L
IN
104 6
PP5V_SW_ODD
VOLTAGE=5V
SATA ODD Port
CRITICAL
FL4520
90-OHM-100MA
DLP11S
J4500
55560-0168
CRITICAL
SYM_VER-1
M-ST-SM-LF
3
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6 PP3V3_S0
83 80 73 72 62 61 57 54 52 51 50 49 48
R4590 1
33K
5%
1/16W
MF-LF
402
94 6
94 6
10
94 6
12
11
94 6
14
13
16
15
OUT
94
SATA_ODD_R2D_UF_P
94
SATA_ODD_R2D_UF_N
C4521
10%
16V
CERM
16V
SATA_ODD_R2D_C_P
IN
16 94
SATA_ODD_R2D_C_N
IN
16 94
402
C4520
10%
0.01UF
CERM
402
71 57 41 32 25 22 20 16 7
SATA_ODD_D2R_UF_N
SATA_ODD_D2R_UF_P
FL4525
PP1V5_S0
NO STUFF
R45131 R45151
90-OHM-100MA
DLP11S
4.7K
SYM_VER-1
94
SATA_ODD_D2R_C_N
94
SATA_ODD_D2R_C_P
SMC_ODD_DETECT
C4526
10%
0.01UF
516S0617
45 6
0.01UF
SATA_ODD_R2D_P
SATA_ODD_R2D_N
0.01UF
16V
CERM
C4525
10%
16V
SATA_ODD_D2R_N
OUT
16 94
CERM
SATA_ODD_D2R_P
OUT
16 94
SATARDRVR_I2C_ADDR0 41
402
SATARDRVR_I2C_ADDR1 41
CRITICAL
Internally PD ~150K
Write:0xB6 Read:0xB7
SATA HDD Port

PLACE_NEAR=L4500.1:3mm
71 57 41 32 25 22 20 16 7
C4502
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
CRITICAL
L4500
1
6 PP5V_S0_HDD_FLT
VOLTAGE=5V
GND_VOID=TRUE
1
3
NC
NC
GND_VOID=TRUE
SATA_HDD_D2R_RC_C_P
SATA_HDD_D2R_RC_C_N
6 7 8 22 41 47 52 54 65 68 69 70 73 87 104
105
ISNS_HDD_P
OUT
100 103
ISNS_HDD_N
OUT
100 103
5%
50V
41.2
10
94 6 SATA_HDD_R2D_N
12
94 6 SATA_HDD_R2D_P
13
14
15
16
5%
50V
C4516
CERM
402
CERM
402
GND_VOID=TRUE
10%
0.01UF
16V
CERM
94 6 SATA_HDD_D2R_RDRVR_IN_N
402
94 6 SATA_HDD_R2D_RDRVR_OUT_N
6 SATA_HDD_R2D_RDRVR_OUT_P
94
1%
MF-LF
1/16W 402
23 16
516S0350
FL4501
GND_VOID=TRUE
12-OHM-100MA-8.5GHZ
TCM0806-4SM
4
GND_VOID=TRUE
SATA_HDD_R2D_UF_P
5%
50V
CERM
402
41.2
5%
50V
C4512
0.01UF
SATA_HDD_D2R_N
OUT
6 16 94
SATA_HDD_R2D_C_N
IN
6 16 94
IN
6 16 94
6 16 23 26 28 30 32 48 62 89 95
402
16V
CERM
402
2 GND_VOID=TRUE
10%
16V
CERM
SATA_HDD_R2D_C_P
402
SMBUS_PCH_CLK
IN
B_PRE1/SDA_CTL 17
SMBUS_PCH_DATA
BI
SATARDRVR_I2C_EN_L
SATARDRVR_TEST
R4511
0
16V
CERM
5%
1/16W
MF-LF
402
6 16 23 26 28 30 32 48 62 89 95
10 I2C_EN*
R45121
18 TEST
4.99K
GND THRM
PAD
1%
1/16W
MF-LF
402 2
PAGE TITLE
SATA Connectors
DRAWING NUMBER
338S0907
2 402
Apple Inc.
SIZE
D
REVISION
16V
CERM

402
CERM
402
CERM
A_PRE1/SCL_CTL 19
GND_VOID=TRUE
10%
6 16 94
SATARDRVR_REXT
94 6 SATA_HDD_R2D_RC_UF_P
15PF
GND_VOID=TRUE
94 6 SATA_HDD_R2D_RDRVR_IN_P
REXT 20
16V
2 GND_VOID=TRUE
10%
0.01UF
B_INN 12
B_INP 11
0.01UF
1%
MF-LF
1/16W 402
C4533
OUT
2 GND_VOID=TRUE
10%
C4510
R4533
GND_VOID=TRUE
94 6 SATA_HDD_R2D_RDRVR_IN_N
C4513
SATA_HDD_D2R_P
9 APRE0/I2C_ADDR1
GND_VOID=TRUE
402
8 B_PRE0/I2C_ADDR0
0.01UF
10%
0.01UF
CERM
SATARDRVR_I2C_ADDR1
C4511
2
C4517
16V
SATARDRVR_I2C_ADDR0
10%
41
D2R values for 3dB de-emphasis
94 6 SATA_HDD_R2D_RC_UF_N
CRITICAL
4 B_OUTN
5 B_OUTP
94 6 SATA_HDD_D2R_RDRVR_OUT_N
A_OUTP 15
A_OUTN 14
2 GND_VOID=TRUE
41
R2D values for 3dB de-emphasis
15PF
SATA_HDD_R2D_UF_N
TQFN
0.01UF
7 EN
1%
MF-LF
1/16W 402
C4534
SYM_VER-1
41.2
1 A_INP
2 A_INN
C4518
SATARDRVR_EN
IN
94 6 SATA_HDD_D2R_C_N
R4534
94 6 SATA_HDD_D2R_RDRVR_OUT_P
PS8521A
94 6 SATA_HDD_D2R_RDRVR_IN_P
16V
NC
CRITICAL
0.01UF
VDD
GND_VOID=TRUE
10%
0.01UF
CERM
402
C4519
20%
16V
2 CERM
402
U4510
94 6 SATA_HDD_D2R_C_P
15PF
GND_VOID=TRUE
4.7K
1%
MF-LF
1/16W 402
C4535
9
11
0x96/0x97
0x98/0x99
0xB6/0xB7
0xB8/0xB9
PLACE_NEAR=U4510.16:2mm
R45101
5%
1/16W
MF-LF
402 2
R4535
GND_VOID=TRUE
PP5V_S0
C4515
M-ST-SM
NO STUFF
2
4
15PF
J4501
NC
41.2
C4536
QT500166-L020
20%
10V
2 CERM
402
PP1V5_S0
1%
1W
MF
0612
R4536
CRITICAL
71 57 41 32 25 22 20 16 7
0.005
PP5V_S0_HDD_R
VOLTAGE=5V
0603
C4514
0.1UF
CRITICAL
R4599
21
0.1UF
FERR-70-OHM-4A
Address (R/W)
L
H
L
H
6
16
C4501
3
13
ADDR0
L
L
H
H
1
ADDR1
PP1V5_S0
1
5%
1/16W
MF-LF
402 2
Indicates disc presence
4.7K
5%
1/16W
MF-LF
402 2
402
BRANCH
PAGE
45 OF 132
SHEET
41 OF 105
USB Port Power Switch
Left USB Port A
CRITICAL
FERR-120-OHM-3A
1
2
PP5V_S3_RTUSB_A_F
SON
PM_SLP_S4_L
2 IN_0
3 IN_1
5.1K
5%
1/16W
MF-LF
402 2
C4696
20%
6.3V
POLY-TANT
CASE-B2-SM
OUT
4 EN1
5 EN2
GND
USB_PWR_EN
C4616
C4690 1
220UF-35MOHM
10 FAULT1* ILIM 7
6 FAULT2*
USB_EXTA_OC_L
USB_EXTB_OC_L
CRITICAL
100UF
10%
10V 2
X5R
402
OUT
43
NOSTUFF
CRITICAL
0.47UF
24
24
20%
6.3V
POLY-TANT
CASE-B2-SM
OUT1 9
OUT2 8
10UF
C4691
0.1UF
20%
6.3V 2
X5R
603
PP5V_S3_RTUSB_A_ILIM
VOLTAGE=5V
USB_ILIM
PP5V_S3_RTUSB_B_ILIM
VOLTAGE=5V
0603
C4605
CRITICAL
J4600
0.01uF
VOLTAGE=5V
20%
16V
CERM 2
402
USB
CRITICAL
F-RT-TH-M97-4
5
L4600
90-OHM-100MA
DLP11S
THRM
PAD
SYM_VER-1
R46001 C4695 1
23.2K
1%
1/16W
MF-LF
402 2
20%
2 10V
CERM
402
10UF
20%
6.3V 2
X5R
603
C4617
100
USB2_EXTA_MUXED_N
100
USB2_EXTA_MUXED_P
10UF
20%
6.3V
X5R
603
USB2_LT1_N
100 USB2_LT1_P
100
3
4
2 5 3 4
6 VBUS
NC
IO
NC
IO
R46901
C4692
L4605
TPS2561DR
73 66 45 29 17
CRITICAL
U4600
PP5V_S3
11
104 82 72 67 46 44 43 31 29 7 6
7
8
1 GND
Current limit per port (R4600): 2.18A min / 2.63A max
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
L4615
We can add protection to 5V if we want, but leaving NC for now
FERR-120-OHM-3A
Place L4605 and L4615 at connector pin
1
2
PP5V_S3_RTUSB_B_F
0603
C4615
VOLTAGE=5V
0.01uF
20%
16V
CERM 2
402
USB/SMC Debug Mux
CRITICAL
J4610
USB
F-RT-TH-M97-4
5
CRITICAL
90-OHM-100MA
DLP11S
SMC_DEBUG_YES
R4650
0.1UF
47 46 45 6
IN
OUT
SMC_RX_L
SMC_TX_L
20%
10V
CERM 2
402
5%
1/16W
MF-LF
2 402
VCC
5 M+
4 M-
U4650
94 24
BI
USB_EXTB_N
94 24
BI
USB_EXTB_P
USB_LT2_N
100 USB_LT2_P
100
10K
C4650 1
SYM_VER-1
SMC_DEBUG_YES
47 46 45 6
L4610
PP3V42_G3H
Y+ 1
Y- 2
BI
94 24
BI
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
3
4
7
2 5 3 4
PI3USB102ZLE
94 24
6 VBUS
TQFN
CRITICAL
NC
IO
NC
IO
104
46 45 44 25 7 6
73 64 63 53 48 47
1 GND
SMC_DEBUG_YES
USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB
SEL 10
8 OE*
3
GND
IN
45
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
SMC_DEBUG_NO
R4651
1
5%
1/16W
MF-LF
402
Left USB Port B
DRAWING NUMBER
R4652
0
Apple Inc.
SIZE
D
REVISION
5%
1/16W
MF-LF
402
External USB Connectors
SMC_DEBUG_NO
1
PAGE TITLE

BRANCH
PAGE
46 OF 132
SHEET
42 OF 105
USB Port Power Switch
LEFT USB PORT C
CRITICAL
CRITICAL
U4780
L4725
TPS2557DRB
FERR-120-OHM-3A
SON
24 8
42
OUT
IN
2 IN_0
3 IN_1
PP5V_S3
USB_EXTC_OC_L
8 FAULT*
USB_PWR_EN
4 EN
GND
CRITICAL
C4786
100UF
20%
6.3V
POLY-TANT
CASE-B2-SM
C4780
10UF
2
20%
6.3V
X5R
603
C4781
ILIM 5
THRM
PAD
20%
10V
CERM
402
PP5V_S3_RTUSB_C_ILIM
VOLTAGE=5V
2
0603
C4725
USB_ILIM2
PP5V_S3_RTUSB_C_F
CRITICAL
PLACE_NEAR=J4720.1:8mm VOLTAGE=5V
J4720
0.01uF
20%
16V
CERM
402
USB
CRITICAL
2
F-RT-TH-M97-4
5
L4720
90-OHM-100MA
DLP11S
SYM_VER-1
R47001
44.2K
1%
1/16W
MF-LF
402 2
0.1UF
2
OUT1 6
OUT2 7
104 82 72 67 46 44 42 31 29 7 6
C4785
100
USB_LT3_N
100
USB_LT3_P
10UF
20%
6.3V
X5R
603
NC
IO
NC
IO
2
6 VBUS
7
8
1 GND
Current limit (R4700): 2.19A min / 2.76A max

D4720
RCLAMP0502N
SLP1210N6
94 24
BI
94 24
BI
USB_EXTC_N
USB_EXTC_P
CRITICAL
PAGE TITLE
PROJECT SPECIFIC CONNS

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
47 OF 132
SHEET
43 OF 105
OMIT
R4801
SHORT2
104 82 72 67 46 44 43 42 31 29 7 6 PP5V_S3
PP5V_S3_IR_USB
VOLTAGE=5V
NONE
NONE
NONE
402
C4801
0.1UF
10%
16V
X7R-CERM
402
14
VCC
U4800
CY7C63803-LQXC
QFN
94 24
94 24
BI
BI
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
NC
NC
NC
NC
C4803
1UF
10%
10V
X5R
402-1
NC
NC
NC
NC
NC
NC
NC
NC
P1.0/D+
P1.1/DP1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
8
9
10
20
21 NC
22
23
24
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
R4800
1
IR_RX_OUT_RC
CRITICAL
OMIT
1
IR_RX_OUT
IN
6 44
C4804
0.001UF
THRML
PAD
100
5%
1/16W
MF-LF
402
NC
P/N 338S0633
10%
50V
CERM
402
VSS
11
25
12
13
15
16
17
18
19
R4805
J4800
FF18-6A-R11AD-B-3H
PP3V42_G3H_LIDSWITCH_R
F-RT-SM
CRITICAL
10
1/16W
VOLTAGE=3.42V
R4806
1
PP5V_S3_IR_R
6 7 25 42 45 46 47 48 53 63 64 73 104
402
10
PP5V_S3
5%
MF-LF
R4807
1
SMC_LID_R
100
1/16W
SYS_LED_ANODE_R
SMC_LID
R4808
1
4.7
SYS_LED_ANODE
6 46
402
1/16W
45 46 53
402
5%
MF-LF
4
5
6 7 29 31 42 43 44 46 67 72 82 104
402
1/16W
VOLTAGE=5V
PP3V42_G3H
5%
MF-LF
5%
MF-LF
IR_RX_OUT
6 44
518S0692
1
C4805
0.1UF
2
10%
16V
X7R-CERM
402
C4806
0.1UF
2
10%
16V
X7R-CERM
402
C4807
0.001UF
2
10%
50V
CERM
402
C4808
0.001UF
10%
50V
CERM
402
SYNC_MASTER=K17_MLB
PAGE TITLE
Front Flex Support

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
48 OF 132
SHEET
44 OF 105
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
46 6
104 73 64 63 53 48 47 46 44 42 25 7 6
0.1UF
20%
6.3V
CERM 2
805
C4903
22UF
20%
2 10V
CERM
402
C4905
0.1UF
20%
2 10V
CERM
402
C4906
0.1UF
20%
2 10V
CERM
402
SMC_VCL
91 88 73 23
IN
73 66
IN
17
OUT
91 35
OUT
23 17
OUT
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
PM_PWRBTN_L
46
46
50 46
NC
TP_SMC_P20
TP_SMC_P24
SMC_BMON_MUX_SEL
NC
NC
NC
NC
NC
95 88 47 16 6
BI
95 88 47 16 6
BI
95 88 47 16 6
BI
95 88 47 16 6
BI
95 88 47 16 6
IN
25
IN
95 25
47 16 6
IN
BI
TP_SMC_P41
SMBUS_SMC_MGMT_SDA
TP_SMC_P43
46
NC
46
104 103 98 48
BI
80
OUT
54
OUT
47 46 45 42 6
OUT
47 46 45 42 6
IN
98 80 51 48 31 6
BI
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMBUS_SMC_0_S0_SCL
(OC)
NC
NC
(OC)
SMC_PA0_PU
(OC)
TP_SPI_DESCRIPTOR_OVERRIDE_L
(OC)
PM_SYSRST_L
(OC)
USB_DEBUGPRT_EN_L
(OC)
MEM_EVENT_L
(OC)
WIFI_EVENT_L
(OC)
SYS_ONEWIRE
(OC)
SMC_BATLOW_L
(OC)
46
25 17 6
OUT
42
OUT
28 26
BI
46 31 6
BI
63
BI
73 46
OUT
46 19
OUT
41 6
86 73 46
IN
OUT
46
IN
80
IN
52
OUT
52
OUT
46 6
OUT
46 6
OUT
52
IN
52
IN
46 6
IN
46 6
IN
49 46
IN
49 46
IN
50 46
IN
49 46
IN
50 46
IN
50 46
IN
50 46
IN
50 46
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_S4_WAKESRC_EN
SMC_PB4
46
SMC_DP_HPD_L
SMC_GFX_OVERTEMP_L
P10
P11
P12
P13
P14
P15
P16
P17
D13
E11
D12
F11
E13
E12
F13
E10
P20
P21
P22
P23
P24
P25
P26
P27
A9
D9
C8
B7
A8
D8
D7
D6
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
NC
NC
U4900
B12
A13
A12
B13
D11
C13
C12
D10
D4
A5
B4
A1
C2
B2
C1
C3
DF2117RVPLP20HV
TLP-145V
(1 OF 3)
OMIT
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P60
P61
P62
P63
P64
P65
P66
P67
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_VSENSE
SMC_CPU_ISENSE
SMC_GPU_VSENSE
SMC_GPU_ISENSE
SMC_GFX_VSENSE
SMC_GFX_ISENSE
SMC_P1V5S3_ISENSE
SMC_CPUVCCIO_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_SCI_L
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
(OC) SMBUS_SMC_MGMT_SCL
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
SMC_ONOFF_L
SMC_BC_ACOK
SMC_PME_S4_WAKE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_CLK32K
(OC) SMBUS_SMC_0_S0_SDA
SMC_PM_G2_EN
NC
NC
NC
NC
OUT
PP3V3_S5_SMC_AVCC
0.47UF
0.1UF
20%
10V
CERM 2
402
66 73
AVCC
VCC
VCL AVREF
U4900
DF2117RVPLP20HV
NC E5
10%
6.3V
CERM-X5R 2
402
R49091
10K
NC
5%
1/20W
MF
201 2
TLP-145V
(3 OF 3)
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
17 46 73
IN
46
IN
6 46 63
IN
46 49
IN
46 50
IN
46 49
IN
46 49
IN
46 49
IN
46 50
IN
46 49
IN
46 49
OUT
16 19
OUT
6 17 47
MD1 D1
MD2 H1
OMIT
64 47 46 6
IN
46
46
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
NMI E3
AVSS L9
IN
6 42 45 46 47
IN
6 42 45 46 47
BI
IN
10K
5%
1/20W
MF
2 201
SMC_MD1
IN
6 47
SMC_NMI
IN
6 47
SMC_TRST_L
IN
6 47
R4902
R4998
10K
5%
1/20W
MF
2 201
XW4900
SM
5%
1/20W
MF
2 201
PLACE_NEAR=U4900.L3:4mm
GND_SMC_AVSS
46 49 50
48 98 103 104
6 46 53
IN
46 49 63 64
IN
46 53
IN
6 17 29 73
IN
17 29 42 66 73
IN
17 73
IN
46
BI
R4901
10K
6 17 47
OUT
VSS
SMC_KBC_MDE
ETRST* H3
NC
PLACE_NEAR=U4900.E1:3mm
C4907 1
L11
C4920 1
E1
VOLTAGE=3.3V
D2
L3
F10
B11
C5
TP_SMC_P10
TP_SMC_RSTGATE_L
ALL_SYS_PWRGD
S5_PWRGD
46
OUT
B1
M1
H10
4.7
5%
1/16W
MF-LF
402
C4904
M12
0.1UF
20%
10V
2 CERM
402
R4999 PLACE_NEAR=U4900.M12:3mm
PLACE_NEAR=U4900.M12:3mm
46
PP3V3_S5_AVREF_SMC
PP3V42_G3H
C4902 1
6 31 48 51 80 98
G2 P50
F3 P51
E4 P52
U4900
N3
N1
M3
M2
N2
L1
K3
L2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
SMC_FAN_0_CTL
SMC_FAN_1_CTL
NC_SMC_FAN_2_CTL
NC_SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMC_SA_ISENSE
SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HI_ISENSE
SMC_GPU_HI_ISENSE
SMC_OTHER_HI_ISENSE
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
DF2117RVPLP20HV
TLP-145V
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
K1
J3
K2
J1
K4
K5
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
G3_POWERON_L
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
SMC_SYS_LED
SMC_LID
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0 E2
PH1 F2
PH2 J2
PECI/PH3 A4
PEVREF/PH4 B3
PEVSTP/PH5 C4
NC
NC
TP_SMC_PF5
IN
46
IN
6 46 47
IN
6 46 47
OUT
6 46 47
IN
6 46 47
IN
46
OUT
46
IN
44 46 53
IN
46 55
46
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMS_INT_L
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
SMC_PROCHOT
SMC_THRMTRIP
NC
CPU_PECI_R
PVCCIO_S0_SMC_R
PM_PECI_PWRGD_R
BI
6 48 63 64 98
BI
6 48 63 64 98
BI
6 31 48 54 55 98
BI
6 31 48 54 55 98
BI
48 51 98
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
48 51 98
OUT
46
OUT
46
R4910
1
43
CPU_PECI
10 19 92
5%
1/16W
MF-LF
402
R4911
C4910 1
0.1UF
PP1V05_S0
7 9 10 12 13 14 23 35 39 68 70 73 102 104
105
SYNC_MASTER=K91_BEN
5%
1/16W
MF-LF
402
20%
10V
CERM 2
402
SMC
R4912
1
PAGE TITLE
DRAWING NUMBER
PM_PECI_PWRGD
73
Apple Inc.
5%
1/16W
MF-LF
402

SIZE
REVISION
BRANCH
PAGE
49 OF 132
SHEET
45 OF 105
SMC Reset "Button", Supervisor & AVREF Supply
46 45 6
46 45 6
53 46 45 6
IN
6 MR1* (IPU)
SN0903048
7 MR2* (IPU)
4 DELAY
6 45 46
NC_SMC_FAN_3_CTL
NC_SMC_FAN_3_TACH
102 100 91 89 88 85
48 41 40 39 36 35 32 28 26 25 23 12 7 6
84 83 80 73 72 62 61 57 54 52 51 50 49
6 45 46
NC_SMC_FAN_3_TACH
PP3V3_S0
6 45 46
C5025
10uF
10%
16V
CERM 2
402
20%
6.3V 2
X5R
603
SILK_PART=SMC_RST
C5026
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side

MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
55 46 45
SMS_INT_L
49 46 45
SMC_CPU_VSENSE
50 46 45
SMC_CPU_ISENSE
VOLTAGE=0V
SMC_CPU_VSENSE
SMC_GPU_VSENSE
SMC_GPU_ISENSE
49 46 45
SMC_GFX_VSENSE
SMC_GPU_VSENSE
45 49 50
SMC_GPU_ISENSE
MAKE_BASE=TRUE
49 46 45
SMC_P1V5S3_ISENSE
49 46 45
SMC_CPUVCCIO_ISENSE
49 46 45
SMC_SA_ISENSE
49 46 45
SMC_DCIN_VSENSE
50 46 45
SMC_DCIN_ISENSE
49 46 45
SMC_PBUS_VSENSE
50 46 45
SMC_BMON_ISENSE
50 46 45
SMC_CPU_HI_ISENSE
NOTE: Internal pull-ups are to VIN, not V+.
45 46 49
45 46 49
OUT
45
IN
45
IN
45
Q5060
SOT-563
45 46 49
CPU_PROCHOT_BUF
SMC_GFX_ISENSE
2 G
45 46 50
MAKE_BASE=TRUE
SMC_P1V5S3_ISENSE
TO CPU
45 46 49
MAKE_BASE=TRUE
SMC_CPUVCCIO_ISENSE
MAKE_BASE=TRUE
SMC_SA_ISENSE
45 46 49
92 68 10
BI
R5062
CPU_PROCHOT_L
SMC_DCIN_VSENSE
6 D
45 46 49
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
CRITICAL
Q5060
DMB53D0UV
SOT-563
CRITICAL
Q5059
SSM6N15FEAPE
45 46 50
MAKE_BASE=TRUE
3.3K 2 CPU_PROCHOT_L_R
5%
1/16W
MF-LF
402
45 46 49
MAKE_BASE=TRUE
SOT563
45 46 49
MAKE_BASE=TRUE
SMC_BMON_ISENSE
1 S
45 46 50
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
G 2
SMC_PROCHOT
45 46 50
MAKE_BASE=TRUE
50 46 45
SMC_GPU_HI_ISENSE
50 46 45
SMC_OTHER_HI_ISENSE
SMC_GPU_HI_ISENSE
45 46 50
MAKE_BASE=TRUE
SMC_OTHER_HI_ISENSE
19
45 46 50
OUT
PM_THRMTRIP_L_R
CRITICAL
MAKE_BASE=TRUE
46 45
Debug Power "Buttons"
TP_SMC_P10
TP_SMC_P10
3 D
45 46
MAKE_BASE=TRUE
46 45
TP_SMC_P20
46 45
TP_SMC_P24
TP_SMC_P20
OMIT
R50161
OUT
6 45 46 53
SOT563
50 46 45
R5015
SMC_BMON_MUX_SEL
SMC_BMON_MUX_SEL
4 S
45 46 50
MAKE_BASE=TRUE
PLACE_SIDE=TOP
5%
1/10W
MF-LF
2 603
SILK_PART=PWR_BTN
45 46
MAKE_BASE=TRUE
0
PLACE_SIDE=BOTTOM
5%
1/10W
MF-LF
603 2
TP_SMC_P24
Q5059
SSM6N15FEAPE
45 46
MAKE_BASE=TRUE
SMC_ONOFF_L
OMIT
SILK_PART=PWR_BTN
46 45
TP_SMC_P41
TP_SMC_P41
46 45
TP_SMC_P43
46 45
TP_SMC_PF5
46 45
TP_SMC_RSTGATE_L
TP_SMC_P43
G 5
SMC_THRMTRIP
45 46
MAKE_BASE=TRUE
45 46
MAKE_BASE=TRUE
TP_SMC_PF5
45 46
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
45 46
MAKE_BASE=TRUE
73 64 63 53 48 47 46 45 44 42 25 7 6
104
R5012
17
IN
PM_CLK32K_SUSCLK_R
22
SMC_CLK32K
OUT
45
53 46 45 6
5%
1/16W
MF-LF
402
45
53 45 44
47 45 42 6
47 45 42 6
PP3V3_S4
47 45 6
SMC Crystal Circuit

45
SMC_XTAL
5%
1/16W
MF-LF
402
15pF
SMC_XTAL_R
Y5010 1
20.00MHZ
5X3.2-SM
47 45 6
47 45 6
63 45 6
SMC_DP_HPD_L OUT
Q5020
R5070
R5072
R5071
R5073
R5074
10K
10K
100K
10K
100K
1
1
1
1
1
2
2
2
2
2
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMS_INT_L
R5077
R5078
R5079
R5080
R5081
R5087
R5093
10K
10K
10K
10K
10K
470K
10K
1
1
1
1
1
1
1
2
2
2
2
2
2
2
64 63 49 46 45
45
55 46 45
SMC_PA0_PU
R5091
100K
PP3V42_G3H
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
201
201
201
201
201
5%
5%
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
201
NOSTUFF
5%
1/20W
MF
201
5%
5%
1/20W
1/20W
MF
MF
201
201
5%
5%
1/20W
1/20W
MF
MF
201
201
D 3
SSM3K15FV
SOD-VESM-HF
45
C5011
2
45
47 45 6
100K
CRITICAL
5%
50V
CERM
402
CRITICAL
R5020
5%
1/20W
MF
2 201
C5010
SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L
6 7 46 53 54 72
R5010
CRITICAL
DMB53D0UV
SMC_GFX_VSENSE
MAKE_BASE=TRUE
50 46 45
TO SMC
45 46 50
MAKE_BASE=TRUE
SMC_GFX_ISENSE
5%
1/16W
MF-LF
2 402
SMC_PROCHOT_3_3_L
SMC_CPU_ISENSE
MAKE_BASE=TRUE
49 46 45
10K
5%
1/16W
MF-LF
2 402
45 46 49
MAKE_BASE=TRUE
R5060
100K
45 46 55
MAKE_BASE=TRUE
R5061
45 46 49 63 64
SMS_INT_L
49 46 45
0.01UF
10%
16V
2 CERM
402
SMC_BC_ACOK
MAKE_BASE=TRUE
6 45
PAD
SMC_BC_ACOK
6 45 47 64
VOLTAGE=3.3V
THRM
0.01UF
5%
1/10W
MF-LF
2 603
OUT
PP3V3_S5_AVREF_SMC
CRITICAL REFOUT
GND
SMC_RESET_L
RESET* 5
C5001
5%
1/16W
MF-LF
2 402
VREF-3.3V-VDET-3.0V
SMC_MANUAL_RST_L
OMIT
R5001
1K
U5010
SMC_TPAD_RST_L
SMC_ONOFF_L
R5000
VIN
DFN
64 63 49 46 45
3
V+
10%
6.3V
CERM-X5R 2
402
NC_SMC_FAN_3_CTL
SMC FSB to 3.3V Level Shifting
6 45 46
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
0.47UF
IN
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
C5020 1
53
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
48 47
NC_SMC_FAN_2_CTL
46 45 6
MAKE_BASE=TRUE
PP3V42_G3H
46 45 44 42 25 7 6
104 73 64 63 53
PP3V42_G3H
46 45 44 42 25 7 6
104 73 64 63 53
Desktops: 5V
Mobiles: 3.42V
1
48 47
46 45 6
15pF
SMC_EXTAL
1 G
5%
50V
CERM
402
85 84
IN
S 2
DP_A_EXT_HPD
73 45 17
45
PP3V3_S4
System (Sleep) LED Circuit
45
6 7 46 53 54 72
86 73 45
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5085
R5086
10K
10K
1
1
2
2
SMC_PB4
SMC_S4_WAKESRC_EN
R5088
R5090
10K
100K
1
1
2
2
WIFI_EVENT_L
R5089
10K
R5076
82 72 67 44
7 6
43 42 31 29
104
100K
PP5V_S3
5%
1/20W
MF
2 201
R50311
R5030
523
53 46 45
IN
SMC_PME_S4_WAKE_L
SMC_PME_S4_WAKE_L
MAKE_BASE=TRUE
20
1%
1/16W
MF-LF
402 2
45 46 53
1%
1/16W
MF-LF
2 402
45 31 6
BATLOW# Isolation
SYS_LED_L_VDIV
73 64 63 53 48 47 46 45 44 42 25 7 6
104
45 19
PP3V3_S5
PP3V3_SUS
72 71 56 48 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73
R5032
R50401
DMB54D0UV
100K
SOT-563
5%
1/20W
MF
201 2
SYS_LED_L
Q2
Q1
73 45
IN
SMC_SYS_LED
100K
201
PP3V42_G3H
NOSTUFF
1
2
5%
IN
SYNC_MASTER=K91_BEN
1/20W
MF
201
SMC Support
SOD-VESM-HF
SMC_BATLOW_L
OUT
Internal 20K pull-up on PM_BATLOW_L in PCH.

PM_BATLOW_L
DRAWING NUMBER
Apple Inc.
OUT
17
SIZE
D
REVISION
5%
1/16W
MF-LF
402
6 44
PAGE TITLE
Q5040
SSM3K15FV
R5041
SYS_LED_ANODE
R5094
MF
7 16 17 18 19 20 22 71 72 73
CRITICAL
1
45
SMC_RUNTIME_SCI_L
1/20W
CRITICAL
Q5030
6
D
1%
1/16W
MF-LF
402 2
1.47K
2
5%
SYS_LED_ILIM
PP3V3_WLAN
31 6
OUT

NOSTUFF
BRANCH
PAGE
50 OF 132
SHEET
46 OF 105
LPC+SPI Connector
CRITICAL
LPCPLUS:YES
J5100
55909-0374
M-ST-SM
31
32
PP3V42_G3H
PP5V_S0
6
105
104 73 64 63 53 48 46 45 44 42 25 7 6
104 87 73 70 69 68 65 54 52 41 22 8 7
95 88 45 16 6
95 88 45 16 6
BI
47 6
IN
47 6
OUT
95 88 45 16 6
LPC_AD<0>
LPC_AD<1>
BI
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
IN
45 17 6
OUT
46 45 6
OUT
95 88 25 6
IN
46 45 6
OUT
45 6
IN
45 6
OUT
46 45 42 6
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
6 25 95
BI
6 16 45 88 95
BI
6 16 45 88 95
OUT
6 19 56
IN
6 47
IN
6 47
6 16 45
BI
IN
6 17 45
OUT
6 45 46
OUT
6 45 46
OUT
6 45 46 64
OUT
6 45
OUT
6 42 45 46
OUT
6 19
516S0573
SPI Bus Series Termination

SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
6 47
6 47
6 47
6 47
LPCPLUS:YES LPCPLUS:YES LPCPLUS:YES LPCPLUS:YES

1
R5128
0
PLACE_NEAR=U1800.AV3:5mm
IN
SPI_CS0_R_L
95 16
IN
SPI_CLK_R
PLACE_NEAR=U1800.AY1:5mm
95 16
IN
SPI_MOSI_R
R5111
1
R5112
1
15
15
15
OUT
R5126
47
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
SPI_CS0_L
R5121
95
SPI_CLK
SPI_MOSI
R5123
1
15
47
47
47
SPI_MLB_CS_L
OUT
56
5%
1/16W
MF-LF
402
SPI_MLB_CLK
OUT
56
SPI_MLB_MOSI
OUT
56
SPI_MLB_MISO
IN
56
5%
1/16W
MF-LF
402
R5122
95
SPI_MISO
R5125
R5120
95
5%
1/16W
MF-LF
402
47
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
95 16
R5110
1
PLACE_NEAR=U1800.BA2:5mm
R5127
47
5%
1/16W
MF-LF
2 402
95 16
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
SYNC_MASTER=K91_YUN
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
51 OF 132
SHEET
47 OF 105
PCH SMBus "0" Connections

102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
R5200 1
5%
1/16W
MF-LF
402
U1800
(MASTER)
1K
R5201
SO-DIMM "A"
1K
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
VRef DACs
104 73 64 63 53 47 46 45 44 42 25 7 6
R5250 1
U4900
(MASTER)
32 41 48
6 16 23
26 28 30
62 89 95
32 41 48
6 16 23
26 28 30
62 89 95
48 45 31 6
98 80 51
48 45 31 6
98 80 51
R5251
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
EMC1414: U5550
(Write: 0x98 Read: 0x99)
SMBUS_SMC_0_S0_SDA
80 98
6 31
45 48 51
63 48 45 6
98 64
SMBUS_SMC_0_S0_SDA
80 98
6 31
45 48 51
63 48 45 6
98 64
MAKE_BASE=TRUE
SO-DIMM "B"
95 89
28 26 23 16 6
62 48 41 32 30
SMBUS_PCH_CLK
SMBUS_PCH_CLK
95 89
28 26 23 16 6
62 48 41 32 30
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMBUS_SMC_BSA_SCL
R5281
2.0K
2.0K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Battery Charger
ISL6258 - U7000
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
80 98
6 31
45 48 51
SMBUS_SMC_0_S0_SDA
80 98
6 31
45 48 51
SATA Redriver
X19 Temp
U2901
U4510
(Write: 0xB6 Read: 0xB7)
J3401
J6955
(See Table)
Battery
SMBUS_SMC_0_S0_SCL
Margin Control
6 45 48
63 64 98
MAKE_BASE=TRUE
Battery
Whistler: U8000
32 41 48
6 16 23
26 28 30
62 89 95
32 41 48
6 16 23
26 28 30
62 89 95
6 45 48
63 64 98
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
GPU Temp (Int)
J3100
(Write: 0xA4 Read: 0xA5)
U2900
R5280 1
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
PP3V42_G3H
SMC
GPU Temp (Ext)
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMC "Battery A" SMBus Connections
PP3V3_S0
SMC
J2900
(Write: 0xA0 Read: 0xA1)
5%
1/16W
MF-LF
402
62 48 41
26 23 16 6
32 30 28
MAKE_BASE=TRUE
95 89
62 48 41
26 23 16 6
32 30 28
MAKE_BASE=TRUE
95 89
SMC "0" SMBus Connections
PP3V3_S0
PCH
Battery Manager - (Write: 0x16 Read: 0x17)

Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x92 Read: 0x93)
SMBUS_SMC_BSA_SCL
6 45 48
63 64 98
SMBUS_SMC_BSA_SDA
6 45 48
63 64 98
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
95 89
28 26 23 16 6
62 48 41 32 30
SMBUS_PCH_CLK
SMBUS_PCH_CLK
95 89
28 26 23 16 6
62 48 41 32 30
SMBUS_PCH_DATA
SMBUS_PCH_DATA
32 41 48
6 16 23
26 28 30
62 89 95
32 41 48
6 16 23
26 28 30
62 89 95
SMBUS_SMC_0_S0_SCL
80 98
6 31
45 48 51
SMBUS_SMC_0_S0_SDA
80 98
6 31
45 48 51
72 71 56 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73
PP3V3_S5
R5290 1
SMC
XDP Connectors
ExpressCard Slot
J2600 & J2650

(MASTER)
J3500
(Address via ARP)
89 62 48
26 23 16 6
41 32 30 28
95
89 62 48
26 23 16 6
41 32 30 28
95
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMC "A" SMBus Connections

55 54 50 49 32 31 30 29 25 24 18 8 7 6
104 88 73
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMBUS_SMC_MGMT_SCL
UD100
SMBUS_SMC_MGMT_SCL
104
45 48 98
103
SMBUS_SMC_MGMT_SDA
104
45 48 98
103
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
Sensor ADC B
R5270
48 45 31 6
98 55 54
48 45 31 6
98 55 54
1K
R5271
5%
1/16W
MF-LF
2 402
J5800
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
55 98
6 31
45 48 54
SMBUS_SMC_A_S3_SDA
55 98
6 31
45 48 54
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
UD210
Trackpad
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
32 41 48
6 16 23
26 28 30
62 89 95
32 41 48
6 16 23
26 28 30
62 89 95
SMBUS_PCH_CLK
104 103 98 48
45
Sensor ADC A
PP3V3_S3
SMC
U6800
U9701
(WRITE: 0x58 READ: 0x59)
SMBUS_PCH_CLK
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
5%
1/16W
MF-LF
2 402
NOTE: SMC RMT bus remains powered and may be active in S3 state
Mikey
LED BACKLIGHT
89 62 48
26 23 16 6
41 32 30 28
95
89 62 48
26 23 16 6
41 32 30 28
95
32 41 48
6 16 23
26 28 30
62 89 95
32 41 48
6 16 23
26 28 30
62 89 95
SMBUS_PCH_CLK
103 98 48 45
104
104 103 98 48
45
R5291
4.7K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
103 98 48 45
104
4.7K
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SCL
104
45 48 98
103
SMBUS_SMC_MGMT_SDA
104
45 48 98
103
SDRVI2C:SB
1
SDRVI2C:SB
1
R5237
0
5%
1/16W
MF-LF
402 2
R5236
5%
1/16W
MF-LF
2 402
ALS
U9310
85 48
I2C_DPSDRVA_SCL
85 48
I2C_DPSDRVA_SDA
I2C_DPSDRVA_SCL
48 85
I2C_DPSDRVA_SDA
48 85
MAKE_BASE=TRUE
MAKE_BASE=TRUE
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
Lid Angle detect, SMS

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
T29 SMBus Connections
J3401
DP SDRV "A"
R5230 1
T29
55 98
6 31
45 48 54
97 85 48 33
R5231
4.7K
5%
1/16W
MF-LF
402 2
U3600
(MASTER)
55 98
6 31
45 48 54
4.7K
5%
1/16W
MF-LF
2 402
I2C_T29_SCL
T29 PortA MCU

U9330
I2C_T29_SCL
97 85 48 33
I2C_T29_SDA
33 48 85
97
MAKE_BASE=TRUE
PCH "SMLink 0" Connections
I2C_T29_SDA
33 48 85
97
MAKE_BASE=TRUE
SMS
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
SDRVI2C:MCU
1
U5920
R5210
PCH
U1800
(MASTER)
R5211
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R5234
SMBUS_SMC_A_S3_SCL
55 98
6 31
45 48 54
SMBUS_SMC_A_S3_SDA
55 98
6 31
45 48 54
5%
1/16W
MF-LF
402 2
SDRVI2C:MCU
1
R5235
5%
1/16W
MF-LF
2 402
85 48
95 16
SML_PCH_0_CLK
85 48
SML_PCH_0_DATA
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PCH "SMLink 1" Connections

102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PCH
U1800
R5260 1
SMC
PP3V3_S0
R5220 1
NO STUFF
1
8.2K
5%
1/16W
MF-LF
402
SML_PCH_1_CLK
98 51 48
45
SMBUS_SMC_B_S0_SCL
R5261
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SML_PCH_1_DATA
SMBUS_SMC_B_S0_SCL
R5221
5%
1/16W
MF-LF
402
98 51 48 45
98 51 48
45
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
R5223
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
48 85
45 48 51
98
45 48 51
98
SYNC_MASTER=K17_MLB
5%
1/16W
MF-LF
402
1
K92 SMBus Connections

DRAWING NUMBER
EMC1412: U5520
Apple Inc.
R5222
SMLink 1 is slave port to
SMBUS_SMC_B_S0_SCL
5%
1/16W
MF-LF
402
SMBUS_SMC_B_S0_SDA
SIZE
D
REVISION
R
45 48 51
98

45 48 51
98

access PCH & CPU via PECI.
PAGE TITLE
T29 Temp
MAKE_BASE=TRUE
48 85
I2C_DPSDRVA_SDA
CPU Temp
MAKE_BASE=TRUE
95 16
I2C_DPSDRVA_SCL
EMC1414: U5570
MAKE_BASE=TRUE
8.2K
98 51 48 45
I2C_DPSDRVA_SDA
PP3V3_S0
U4900
(MASTER)
NO STUFF
95 16
I2C_DPSDRVA_SCL
MAKE_BASE=TRUE
SMC "B" SMBus Connections
MAKE_BASE=TRUE
U9310
MAKE_BASE=TRUE
MAKE_BASE=TRUE
95 16
DP SDRV "A"
BRANCH
PAGE
52 OF 132
SHEET
48 OF 105
PBUS Voltage Sense Enable & Filter
GPU VCore Load Side Current Sense / Filter
CRITICAL
Q5300
102 100 91 89 88 85
46 41 40 39 36 35 32 28 26 25 23 12 7 6
84 83 80 73 72 62 61 57 54 52 51 50 48
PP3V3_S0
NTUD3169CZ
SOT-963
N-CHANNEL
Enables PBUS VSense

divider when in S0.
73 72
IN
PM_SLP_S3_R_L
R53021
1
3
39 35 8 7 6
90 64 63 50
82
PBUS_S0_VSENSE
R5305
1%
1/16W
MF-LF
402 2
GFXIMVP6_IMON
IN
1%
1/16W
MF-LF
402
SMC Key VP0R

SMC_ADC11
R53031
1%
1/16W
MF-LF
402 2
PPBUS_G3H
4
PLACE_NEAR=U4900.L8:5MM
SMC_PBUS_VSENSE
R53011
1%
1/16W
MF-LF
402 2
5.49K
IN
SMC_BC_ACOK
45 46 49 50
100 70
CRITICAL
U5310
100 70
IN
6.49K2
CPUVCCIOS0_CS_N
1%
1/16W
MF-LF
402 2
SMC_DCIN_VSENSE
PLACE_NEAR=U4900.N9:5MM
R5314
5.49K
OUT
1M
1M
55 54 50 48 32 31 30 29 25 24 18 8 7 6
104 88 73
20%
2 6.3V
X5R
402
PP3V3_S3
1
IN
1.82K2
VCCSAS0_CS_P
CRITICAL
U5360
1%
1/16W
MF-LF
402
PLACE_NEAR=R7510.2:5 MM
SMC_CPU_VSENSE
15 13 12 7
69
45 46
1%
1/16W
MF-LF
402
20%
2 6.3V
X5R
402
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
45 46 49 50
1%
1/16W
MF-LF
402
OUT
45 46
C5330
45 46 49 50
SMC_ADC2
SMC_GPU_VSENSE
OUT 45
DDR3 1.5V S3 Current Sense / Filter

CRITICAL
U5360
R5373
100 67
IN
5.49K2
ISNS_1V5_S3_P
8
100
ISNS_1V5_S3_R_P
1%
1/16W
MF-LF
402
46
C5335
100 67
0.22UF
IN
ISNS_1V5_S3_N
100
5.49K2
1%
1/16W
MF-LF
402
20%
2 6.3V
X5R
402
V+
VTHRM
R5375
1M
SMC Key IM0C

SMC_ADC6
R5377
ISENSE_P1V5S3_IOUT
4.53K2
1%
1/16W
MF-LF
402
SMC_P1V5S3_ISENSE
OUT
45 46
SYNC_MASTER=K92_DINESH
PAGE TITLE
1
C5377 PLACE_NEAR=U4900.N13:5mm
Voltage & Load Side Current Sensing

DRAWING NUMBER
0.22UF
R5376
1%
1/16W
MF-LF
2 402
ISNS_1V5_S3_R_N
1M
45 46 49 50
OPA2333
DFN
R5374
1
GND_SMC_AVSS
C5367 PLACE_NEAR=U4900.M10:5mm
0.22UF
4.53K2
1
45 46
20%
6.3V
2 X5R
402
R5335
GPUVSENSE_IN
1M
OUT
0.22UF
R5366
1
SMC_SA_ISENSE
1
SMC Key VG0C

1
R5365
SMC Key IC2C

SMC_ADC8
SMC Key VN0R
GPU Vcore Voltage Sense / Filter

XW5335
SM
45 46 49 50
Vi=Voltage across R7350=0.006V=0.018V
PPVCORE_GPU
1%
1/16W
MF-LF
402
GAIN:549X
1%
1/16W
MF-LF
2 402
EDP:18A
82 75 7 6
4.53K2
1
ISENSE_SA_IOUT
1M
SMC_GFX_VSENSE
GND_SMC_AVSS
V-
VCCSAISNS_R_N
1%
1/16W
MF-LF
402
R5367
SMC_ADC4
4.53K2
1%
1/16W
MF-LF
402
1.82K2
PLACE_NEAR=U4900.M10:5mm
OPA2333
V+
THRM
20%
2 6.3V
X5R
402
100
20%
10V
2 CERM
402
DFN
0.22UF
R5330
GFXVSENSE_IN
VCCSAS0_CS_N
C5320
AXG Vcore Voltage Sense / Filter

XW5330
SM
IN
1
GND_SMC_AVSS
PPVCORE_S0_AXG
OUT
VCCSAISNS_R_P
R5364
100 65
4.53K2
8
100
1%
1/16W
MF-LF
402
Key VC0C
SMC_ADC0
R5320
C5360
0.1UF
EDP:6A
45 46 49 50
CPU Vcore Voltage Sense / Filter SMC

CPUVSENSE_IN
45 46 49 50
CPU SA Current Sense / Filter
C5314
0.22UF
1%
1/16W
MF-LF
402 2
R5363
SIGNAL_MODEL=EMPTY
GND_SMC_AVSS
1%
1/16W
MF-LF
402
20%
2 6.3V
X5R
402
R5326
R5325
C5327 PLACE_NEAR=U4900.L12:5mm
0.22UF
Gain: 154x
45 46
OUT
45 46
100 65
CPUVCCIOISNS_R_N
1%
1/16W
MF-LF
2 402
XW5320
SM
SMC_CPUVCCIO_ISENSE
1%
1/16W
MF-LF
402
Vi=Voltage across R7140=0.006V
PPVCORE_S0_CPU
4.53K2
RTHEVENIN = 4573 Ohms
GND_SMC_AVSS
69 14 12 7 6
105
R5327
ISENSE_CPUVCCIO_IOUT 1
P-CHANNEL
PDCINVSENS_EN_L_DIV
VTHRM
SMC Key VD0R

SMC_ADC9
27.4K
1%
1/16W
MF-LF
402 2
V+
SMC Key IC1C

SMC_ADC7
PLACE_NEAR=U4900.L12:5mm
OPA2333
DFN
1%
1/16W
MF-LF
402
R53131
100K
CPUVCCIOISNS_R_P5
R5324
DCIN_S5_VSENSE
R53111
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
3
6.49K2
CPUVCCIOS0_CS_P
R53121
IN
100K
PPDCIN_G3H
CPU 1.05V VCCIO Current Sense / Filter
DCINVSENS_EN_L
45 46 49 50
SIGNAL_MODEL=EMPTY
R5323
64 63 7 6
GND_SMC_AVSS
Vi=Voltage across R7640=0.02139V
0.22UF
20%
6.3V
2 X5R
402
R5307
1%
1/16W
MF-LF
402
SOT-963
63 46 45
64
45 46
C5308 PLACE_NEAR=U4900.N11:5mm
Gain: 3.75x
20%
6.3V
2 X5R
402
NTUD3169CZ
100
OUT
4.02K2
EDP:21.329A
SMC_GPU_ISENSE
CRITICAL
Q5310
6
4.53K2
1%
1/16W
MF-LF
402
GPUISENS_N
SIGNAL_MODEL=EMPTY
2
45 46
DC-In Voltage Sense Enable & Filter
Enables DC-In VSense

divider when AC present.
GPUVCORE_IOUT
V-
C5304
GND_SMC_AVSS
N-CHANNEL
0.22UF
1%
1/16W
MF-LF
402 2
PBUSVSENS_EN_L_DIV
R53041
100K
OUT
10K
1%
1/16W
MF-LF
402
RTHEVENIN = 4573 Ohms
P-CHANNEL
V+
R5308
DFN
THRM
OPA2333
GPUISENS_P
SIGNAL_MODEL=EMPTY
100
R5306
27.4K
2.87K2
SMC Key IG0C

SMC_ADC3
CRITICAL
U5310
Vimon=31xVoltage across R8940=0.868V
100K
S
20%
10V
2 CERM
402
EDP:28A
C5310
0.1UF
PBUSVSENS_EN_L
SIGNAL_MODEL=EMPTY
20%
6.3V
2 X5R
402
GND_SMC_AVSS
1%
1/16W
MF-LF
402
SIZE
D
REVISION
R
45 46 49 50

Gain: 182x
Apple Inc.
BRANCH
PAGE
53 OF 132
SHEET
49 OF 105
Rsense value and INA gain need to be scrubbed!!

COMPUTING High Side Current Sense / Filter
SIGNAL_MODEL=EMPTY
IMVPISNS_ENG
PP3V3_S0
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
C5401
20%
10V
CERM
402
0.1UF
EDP Current:20.1A
70 69 68 67 65 7
OUT
0612
MF
1W
1%
Power Drop across R5400 at EDP becomes 1.21W
V+
SC70
IN-
100
0.003 1
CRITICAL
IN+
45 46
OUT
69 68
IN
5.23K2
C5403
0.22UF
PLACE_NEAR=R7530.3:5MM
X5R
2 402
69 68
GND_SMC_AVSS
IN
R5458
5.23K2
CPUIMVP_ISNS3_P 1
CPUIMVP_ISNS1_N
100
EDP Current:4.9A
0.003
1
CRITICAL
0.1UF
SMC Key IG0R

SMC_ADC14
100
ISNS_HS_GPU_N
R5453
SC70
OUT
CRITICAL
100
ISNS_HS_GPU_P
IN+
REF
SMC_GPU_HI_ISENSE
1%
1/16W
MF-LF
402
PPBUS_G3H
Gain:200x
OUT
IN
SMC Key IC0C

SMC_ADC1
SC70-5
4
PLACE_NEAR=U4900.M11:5MM
R5451
4.53K2
SMC_CPU_ISENSE
CPUIMVP_ISUM_IOUT
1%
1/16W
MF-LF
402
V-
45 46
C5451
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
R5455
1
732K
OUT
IMVPISNS_ENG
IMVPISNS_ENG
R5454
IMVPISNS_ENG
OPA333DCKG4
CPUIMVP_ISUM_R_N
45 46 49 50
732K 2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
MF
402
Gain:139.96x
SIGNAL_MODEL=EMPTY
Scale: 28.58A / V
Max VOut: 3.3V at 94.311A
R5472
5.23K2
CPUIMVP_ISNS3_N
0.5%
SIGNAL_MODEL=EMPTY1/16W
45 46
SIGNAL_MODEL=EMPTY
MF
402
PLACE_NEAR=U4900.K9:5MM
1 C5413
Sense R is R7510, R7520 & R7530

Sense R is 0.75mOhm
0.22UF
20%
6.3V
2 X5R
402
GND
CPUIMVP_ISNS2_N
IMVPISNS_ENG
5.23K2
1
1 +
V+
1%
1/16W
MF-LF
402
R5471
69
14.53K2
HS_GPU_IOUT
IN
CPUIMVP_ISUM_R_P
3.48K2
0.5%
R5413
INA210
IN-
69
U5410
4
0612
MF
1W
1%
IN
20%
10V
CERM
402
V+
R54102
39 35 8 7 6
90 64 63 50 49
OUT
C5411
U5450
100
1%
1/16W
MF-LF
402
IMVPISNS_ENG
MF
402
87 82 7
3.48K2
CPUIMVP_ISNS_P 1
R5470
PP3V3_S0
C5450
20%
10V
2 CERM
402
IMVPISNS_ENG
CRITICAL
R5452
100
5.23K2 CPUIMVP_ISNS_N
0.5%
IN
PLACE_NEAR=U5450.5:3MM
1
IMVPISNS_ENG
MF
402
100 69
IMVPISNS_ENG
PP3V3_S0
0.1UF
0.5%
45 46 49 50
GRAPHICS High Side Current Sense / Filter

102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
100 91 89 88 85 84 83 80 73 72 62 61
39 36 35 32 28 26 25 23 12 7 6
40
102
57 54 52 51 50 49 48 46 41
IMVPISNS_ENG
SIGNAL_MODEL=EMPTY
0.5%
1/16W
MF
IMVPISNS_ENG 402
20%
6.3V
GND
CPU VCore Load Side Current Sense / Filter
CPUIMVP_ISNS2_P 1
PPBUS_G3H
IN
5.23K2
69 68
IN CPUIMVP_ISNS1_P 1
0.5%
1/16W
MF
402
R5457
SMC_CPU_HI_ISENSE
1%
1/16W
MF-LF
402
REF
Gain:50x
63 50 49 39 35 8 7 6
90 64
HS_COMPUTING_IOUT 14.53K2
OUT
CRITICAL
ISNS_HS_COMPUTING_P 4
100
R5403
INA213
ISNS_HS_COMPUTING_N 5
R5456
U5400
R5400 2
100
SMC Key IC0R

SMC_ADC13
EDP: 94A
GND_SMC_AVSS 45
TDP :45A
(Effective Sense R is 0.25mOhm due to summing of the 3 cores)
46 49 50
OTHER High Side Current Sense / Filter

PP3V3_S0
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
66 7
OUT
EDP Current:12.546A
C5431
20%
10V
CERM
402
V+
R5430
0612 2
100
ISNS_HS_OTHER_N 5
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
1 3
ISNS_HS_OTHER_P 4
SC70
OUT
HS_OTHER_IOUT
IN+
REF
Gain:50x
IMVPISNS_ENG
C5433
0.22UF
100 69
R5466
MF-LF
402
IMVPISNS_ENG
100 69
CHARGER BMON High Side (BATTERY DISCHARGE) Current Sense, MUX & Filter
55 54 49 48 32 31 30 29 25 24 18 8 7 6
104 88 73
CRITICAL
100 64
100 64
IN
IN
CHGR_CSO_R_P
5 IN-
CHGR_CSO_R_N
4 IN+
Battery side
C5420
OUT
BMON:ENG
REF
(100V/V)
C5421 1
CRITICAL
BMON:ENG
20%
10V
CERM 2
402
U5421
0.1uF
20%
2 10V
CERM
402
INA214
SC70
IN
SEL 6
2 GND
VCC 5
MF-LF
402
IN
1%
1/16W
MF-LF
402
IMVPISNS_ENG
IMVPISNS_ENG
732K 2
1%
1/16W
MF-LF
402
SMC_GFX_ISENSE
OUT
45 46
1
C5461
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
R5465
1
IMVPISNS_ENG
4CPUIMVP_ISUMG_IOUT 14.53K2
45 46 49 50
Gain:133.33x
SIGNAL_MODEL=EMPTY
Scale: 10A / V
Max VOut: 3.3V at 3.3A
R5464
732K
1%
1/16W
MF-LF
2 402
SIGNAL_MODEL=EMPTY
45 46
R5422
4
B0
145.3K2
BMON_AMUX_OUT
VER 1
1%
1/16W
MF-LF
402
BMON:ENG
1
BMON:PROD
R5420
CHGR_BMON
5%
For engineering, Bmon=6.6A*100*R7050=3.3V
SMC_BMON_MUX_SEL
Gain:100x
From charger
MF-LF
402
R5461
SC70-5
GND
Sense R is R7050, 5mOhm

NOTE: Monitoring current from
battery to PBUS (battery discharge)
64
SC70
1 B1
BMON_INA_OUT
R5463
IMVPISNS_ENG
OPA333DCKG4
V-
IMVPISNS_ENG
R5467
SMC Key IB0R

SMC_ADC12
ISL6259 Gain: 36x
NC7SB3157P6XG
V+
3 -
Sense R is R7550, 0.75mOhm

EDP: 33A
TDP: 21.5A
BMON:ENG BMON:ENG
0.1uF
U5420
EDP Current:6.6A
Charger/Load side
IN
MF-LF
402
SMC Key IN0C

SMC_ADC5
20%
10V
CERM
402
U5460
R5462
CPUIMVP_ISNS1G_N 1 0 2 CPUIMVP_ISNS1G_R_N 15.49K2 CPUIMVP_ISUMG_R_N

5%
1%
1/16W
PP3V3_S3
V+
IMVPISNS_ENG
CPUIMVP_ISNS1G_P 1 0 2 CPUIMVP_ISNS1G_R_P 15.49K2 CPUIMVP_ISUMG_R_P 1

5%
1%
1/16W
IN
GND_SMC_AVSS
IMVPISNS_ENG
2
CRITICAL
45 46
20%
6.3V
2 X5R
402
PPBUS_G3H
C5460
0.1UF
OUT
GND
IN
SMC_OTHER_HI_ISENSE
1%
1/16W
MF-LF
402
CRITICAL
49 39 35 8 7 6
90 64 63 50
IMVPISNS_ENG
1
4.53K2
1
CRITICAL
0.005
PP3V3_S0
R5433
INA213
IN-
GFX/IG VCore Load Side Current Sense / Filter
U5430
MF
1W
1%
SMC Key IO0R

SMC_ADC15
0.1UF
R5423
100K
5%
1/16W
MF-LF
2402
OUT
45 46
0.022UF
10%
16V PLACE_NEAR=U4900.M9:5MM
2 CERM-X5R
402
GND_SMC_AVSS
1/16W
MF-LF
402
For engineering, stuff BMON_ENG

For production, stuff BMON_PROD
SMC_BMON_ISENSE
1 C5422
45 46 49 50
RC values chosen per K17 Radar 7337775
For Production, Bmon=36*18.33A*R7050=3.3V
EDP Current:4.6A
64
IN
CHGR_AMON
R5441
4.53K2
1
1%
1/16W
MF-LF
402
High Side and CPU/AXG Current Sensing
SMC Key ID0R

SMC_ADC10
SMC_DCIN_ISENSE
OUT
DRAWING NUMBER
Apple Inc.
45 46
C5441

0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
SIZE
D
REVISION
1
PAGE TITLE
DC-IN (AMON) Current Sense Filter
45 46 49 50
BRANCH
PAGE
54 OF 132
SHEET
50 OF 105
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

R5550
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
47
PP3V3_S0_GPUTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
100 79
GPU_TDIODE_P
BI
Detect GPU Die Temperature
C5550
0.1uF
20%
R55511
2 10V
CERM
1
C5551
U5550
0.0022uF
100 79
CRITICAL
Q5501
BC846BMXXH
100
Placement note:
GPUTHMSNS_D_P
SIGNAL_MODEL=EMPTY
Q5503
C5552
GPUTHMSNS_THM_L
ALERT*
GPUTHMSNS_ALERT_L
CRITICAL
4 DP2/DN3
SMDATA
SMBUS_SMC_0_S0_SDA
BI
6 31 45 48 80 98
5 DN2/DP3
10
SMBUS_SMC_0_S0_SCL
BI
6 31 45 48 80 98
2
100
SMCLK
GND
6
10%
50V
CERM 2
402
SOT732-3
0.0022uF
BC846BMXXH
Place Q5501 on bottom side

close to the right fin stack
5%
1/16W
MF-LF
2 402
THERM*/ADDR
3 DN1
SOT732-3
10K
MSOP
2 DP1
GPU_TDIODE_N
BI
R5552
EMC1414-A
10%
50V
CERM 2
402
Detect Right Fin Stack Temperature

CRITICAL
5%
1/16W
MF-LF
402 2
1
VDD
SIGNAL_MODEL=EMPTY
10K
402
Placement note:
GPUTHMSNS_D_N
Place U5550 on bottom side under GPU

Detect Left Heat Pipe Temperature
Placement note:
Write Address: 0x98
Read Address: 0x99
Place Q5503 on top side under left heat pipe near GPU
CPU Proximity/CPU Die/PCH Proximity/LVDS Connector Proximity

R5570
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
47
5%
1/16W
MF-LF
402
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
1
1
VDD
2 CERM
402
U5570
100 9
C5571
CPU_THERMD_N
BI
Detect LVDS Connector Proximity Temperature

CRITICAL
CRITICAL
Q5502
100
Q5504
CPUTHMSNS_THM_L
3 DN1
CPUTHMSNS_ALERT_L
R5572
10K
5%
1/16W
MF-LF
2 402
Note: EMC1414 can perform Beta

Compensation for External Diode 1 only
ALERT*
8
9
SMBUS_SMC_B_S0_SDA
BI
45 48 51 98
5 DN2/DP3
10
SMBUS_SMC_B_S0_SCL
BI
45 48 51 98
SMCLK
Placement note:
Place U5570 under CPU
0.0022uF
10%
50V
CERM 2
402
2
100
Write Address: 0x98

Read Address: 0x99
CPUTHMSNS_D2_N
Detect PCH Proximity Temperature
C5590 1
SOT732-3
THERM*/ADDR
SIGNAL_MODEL=EMPTY
BC846BMXXH
Place Q5502 on bottom side

close to the LVDS Connector
2 DP1
CPUTHMSNS_D2_P
SOT732-3
Placement note:
5%
1/16W
MF-LF
402 2
GND
6
10K
CRITICAL
4 DP2/DN3
SMDATA
0.0022uF
10%
50V
CERM 2
402
BC846BMXXH
MSOP
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature
100 9
EMC1414-A
CPU_THERMD_P
BI
C5570
0.1uF R55711
20%
10V
Placement note:
Place Q5504 under PCH
T29 Proximity
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
1
PLACE_NEAR=U3600
PLACE_SIDE=BOTTOM
V+
T29 Die
U5520
BI
T29_THERMD_P
100 51 33
20%
10V
CERM
402
TMP105
WCSP-6
100 51 33
C5520
0.1uF
C1
T29_THERMD_P
98 51 48 45
MAKE_BASE=TRUE
BI
NOSTUFF
98 51 48 45
BI
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
A1
B1
SDA
A0
CRITICAL
SCL
ALERT
C2
SMC Key THSP
B2 TP_T29_SENSOR_ALERT
R5520
PLACE_SIDE=BOTTOM
GNDS
5%
1/16W
MF-LF
A2
2 402
10K
100
PAGE TITLE
T29_THERMD_N
XW5520
Thermal Sensors
Placement note:
SM
DRAWING NUMBER
Place U5520 close to T29 router on BOTTOM side
Apple Inc.
SMB Bus B
Use GND pin B1 on U3600 for N leg

Write Address: 0x90

Read Address: 0x91
SIZE
REVISION
BRANCH
PAGE
55 OF 132
SHEET
51 OF 105
Left Fan
Right Fan
PP5V_S0
PP3V3_S0
PP5V_S0
PP3V3_S0
87 73 70 69 68 65 54 52 47 41 22 8 7 6
105 104
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
87 73 70 69 68 65 54 52 47 41 22 8 7 6
105 104
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
CRITICAL
CRITICAL
J5650
R5650
R5655
45
OUT
SMC_FAN_0_TACH
47K
FAN_LT_TACH
78171-0004
R5660
M-RT-SM
5
47K
5%
1/16W
MF-LF
402
J5660
R5665
1
2
45
OUT
SMC_FAN_1_TACH
45
IN
SMC_FAN_0_CTL
47K
FAN_RT_TACH
1
2
R5661 1
5%
1/16W
MF-LF
402
100K
5%
1/16W
MF-LF
402
R5651 1
5%
1/16W
MF-LF
402
78171-0004
M-RT-SM
5
47K
5%
1/16W
MF-LF
402
100K
5
2N7002DW-X-G
G
2
SOT-363
4
5%
1/16W
MF-LF
402
Q5660
D
518S0521
FAN_LT_PWM
45
IN
SMC_FAN_1_CTL
Q5660
2N7002DW-X-G
G
2
SOT-363
1
518S0521
FAN_RT_PWM
SYNC_MASTER=K17_MLB
PAGE TITLE
Fan Connectors
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
56 OF 132
SHEET
52 OF 105
PSOC USB CONTROLLER

-
R5704
2
BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:5 mm
PP3V3_S4_PSOC
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
220K
5%
1/16W
MF-LF
2 402
54 6
54 6
54 6
54 6
337S2983
TP_PSOC_SCL
TP_PSOC_SDA
NC_PSOC_P1_3
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
1
24
100
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
24
36E-3 W
0.72E-3 W
PSOC
VDD
8MA (TYP) 1.5 OHM

14MA (MAX)
0.012
0.021
V
V
96E-6 W
294E-6 W
18V BOOSTER
VIN
4MA (MAX) 4.7 OHM
0.0188 V
75.2E-6 W
72 54 53 46 7 6
73 64 63 53 48 47 46 45 44 42 25 7 6
104
USB_TPAD_R_N
5%
1/16W
MF-LF
402
PP3V3_S4
PP3V42_G3H
NC
C5702
30
29
WS_KBD1
WS_KBD2
6
WS_KBD3
6
WS_KBD4
6
WS_KBD5
6
WS_KBD6
6
WS_KBD7
6
WS_KBD8
6
WS_KBD9
6
WS_KBD10
6
WS_KBD11
6
WS_KBD12
6
WS_KBD13
6
WS_KBD14
6
6 WS_KBD15_CAP
6 WS_KBD16_NUM
WS_KBD17
6
WS_KBD18
6
WS_KBD19
6
WS_KBD20
6
WS_KBD21
6
WS_KBD22
6
WS_KBD23
6
6 WS_KBD_ONOFF_L
28
53 6
53
53
53
53
6 53
53
6 53
53
6 53
R5714
6 53
6 53
53
WS_KBD15_C
470
6 53
53
WS_KBD16N
10K
53
53
53
53
53
1%
1/16W
MF-LF
402
53
53
53
1%
1/16W
MF-LF
402
6 53
53
53
53
6 53
R5710
6 53
6 53
46 45 6
OUT
6 53
SMC_ONOFF_L
C5710
6 53
0.1UF
6 53
1K
6 53
6 53
53
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
5%
1/16W
MF-LF
402
53 6
53 6
20%
10V
CERM 2
402
6 53
53
27
53 6
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
PLACEMENT_NOTE=NEAR J5713
NC
6 53
31
F-RT-SM
6 53
J5713
CRITICAL
100PF
5%
2 50V
CERM
402
32
FF14-30A-R11B-B-3H
Z2_CLKIN
TP_P7_7
1
100
V
V
53
518S0637
6 53
6 53
6 53
SMC Manual Reset & Isolation
6 54
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
(PP3V3_S4_PSOC)
0.6
0.012
57
USB_TPAD_R_P
R5702
USB_TPAD_N
60MA (MAX)
10 OHM
60MA (MAX) 0.2 OHM
4.7UF
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
5%
1/16W
MF-LF
402
94 24
VDD
VOUT
20%
2 6.3V
X5R
603
WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
2
3V3 LDO
R5715
R5701
USB_TPAD_P
94 24
Keyboard Connector
43
45
46
47
48
49
50
51
52
53
54
(SYM-VER2)
P7_7
24
P7_0
25
P1_0
26
P1_2
27 P1_4
28
P1_6
54 6
POWER
2.55 KOHM 0.0255 V

0.204 V
0.255E-6 W
16.32E-6 W
10UA
80UA
23
54 6
MLF
22 VDD
54 6
CY8C24794
21 D-
54 6
U5701
20 D+
54 6
CRITICAL
OMIT
19 VSS
54 6
NC
TPAD_VBUS_EN
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
IN
P2_3
2 P2_1
3
P4_7
4
P4_5
5 P4_3
6
P4_1
7
P3_7
8
P3_5
9
P3_3
10
P3_1
11
P5_7
12
P5_5
13 P5_3
14
P5_1
18 P1_1
54 6
15 P1_7
WS_CONTROL_KEY
Z2_KEY_ACT_L
53
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
53
V_SNS
V+
C5706
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
55
53
R_SNS
TMP102
53
17 P1_3
54 6
CURRENT
53
16 P1_5
53
10%
2 16V
X7R-CERM
402
SMC_PME_S4_WAKE_L
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
OUT
54 6
C5705
0.1UF
5%
2 50V
CERM
402
R5703
73
100PF
46 45
C5704
PIN NAME
C5703
0.1UF
10%
2 16V
X7R-CERM
402
Keys ANDed with PSOC power to isolate when PSOC is not powered.
C5701
4.7UF
73 64 63 53 48 47 46 45 44 42 25 7 6
104
20%
2 6.3V
X5R
603
72 54 53 46 7 6
BYPASS=U5701.22:19:5 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11
PP3V42_G3H
PP3V3_S4
CRITICAL
mm
VDD
10%
2 16V
X7R-CERM
402
0.1UF
U5750
C5750
PP3V3_S4
IC
USB INTERFACES TO MLB

SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
44
72 54 53 46 7 6
SLG4AP006
53 6
WS_LEFT_SHIFT_KBD
2 IN_A1
TDFN
(IPD)
3 IN_A2
OUT_A 4
WS_LEFT_SHIFT_KEY
53
OUT_B 8
WS_LEFT_OPTION_KEY
53
(IPD)
TPAD Buttons Disable
7 IN_A3_B2
(IPD)
53 6
BUTTON_DISABLE
(IPD)
D 6
PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
THRM
PAD
GND
CRITICAL
Q5701
6 IN_B1
53
WS_LEFT_OPTION_KBD
SSM6N15FEAPE
SOT563
46 45 44
IN
SMC_LID
S 1
THE TPAD BUTTONS WILL BE DISABLE

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
Pull-up in U5010.
SMC_TPAD_RST_L
CRITICAL
VDD
10%
2 16V
X7R-CERM
402
0.1UF
U5755
OUT
46
C5755
2 G
Q5701
D 3
SSM6N15FEAPE
SOT563
SLG4AP006
2 IN_A1
TDFN
5 G
(IPD)
3 IN_A2
OUT_A 4
SMC_TPAD_RST
OUT_B 8
WS_CONTROL_KEY
S 4
(IPD)
53 6
WS_CONTROL_KBD
7 IN_A3_B2
(IPD)
6 IN_B1
53
WELLSPRING 1
THRM
PAD
DRAWING NUMBER
GND
PAGE TITLE
(IPD)
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
57 OF 132
SHEET
53 OF 105
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
CRITICAL
CRITICAL
L5801
D5802
SOD-323
3.3UH-870MA
PP5V_S4_P18V5S5
PP5V_S5
R5805
2
P18V5S4_SW
PP18V5_S4_R
SWITCH_NODE=TRUE
B0520WSXG
VLF3010AT-SM-HF
VOLTAGE=5V
C5818
R5812
FB
2.2UF
10%
THRML
16V
2 X5R
PAD
603
402
25V 2
X5R
R5813
6 54
603-1
C5815
53 6
1000PF
53 6
5%
2 25V
NP0-C0G
402
SW
1%
1/16W
MF-LF
2 402
R5811
100K
1%
1/16W
MF-LF
2 402
54 6
R5800
71.5K
GND
10%
16V
X7R-CERM 2
Z2_BOOST_EN
CRITICAL
C5817
PGND
0.1UF
CTRL
1UF
55 50 49 48 32 31 30 29 25 24 18 8 7 6
104 88 73
PP3V3_S3
55560-0228
53 6
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
53
NO STUFF
PP18V5_S4
M-ST-SM
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
PP3V3_S3_TPAD
53 6
C5819
10%
QFN
DO
C5816
J5800
PP3V3_S4
72 53 46 7 6
53 6
TPS61045
NC
CRITICAL
53 6
1%
1/16W
MF-LF
2 402
P18V5S4_FB
6 54
1M
5%
50V
CERM 2
402
U5805
IPD Flex Connector
PP18V5_S4
VOLTAGE=18.5V
5%
1/16W
MF-LF
402
1
1
39PF
VIN
VOLTAGE=18.5V
PP5V_S5_P18V5S5_VIN
5%
1/16W
MF-LF
402
104 103 72 66 7
VOLTAGE=5V
R5806
10
12
11
14
13
16
15
18
17
20
19
22
21
6 54
Z2_KEY_ACT_L 6 53
Z2_RESET
6 53
PSOC_F_CS_L
6 53
PICKB_L
6 53
PSOC_MISO
6 53
PSOC_MOSI
6 53
PSOC_SCLK
6 53
SMBUS_SMC_A_S3_SDA 6
SMBUS_SMC_A_S3_SCL 6
31 45 48 55 98
31 45 48 55 98
6 Z2_CLKIN
516S0689
Keyboard Backlight Driver & Detection

104 87 73 70 69 68 65 52 47 41 22 8 7 6
105
PP5V_S0
CRITICAL
KB_BL
Keyboard Backlight Connector
L5850
B
PP3V3_S0
470K
1UF
5%
1/16W
MF-LF
402 2
BI
SMC_SYS_KBDLED
1
If LOW, keyboard backlight present

If HIGH, keyboard backlight not present
5%
1/16W
MF-LF
2 402
R5853 always stuffed, R5854 only

grounded when KB BL flex connected.
R5854
4.7K
LED 5
KB_BL
KB_BL
5%
1/16W
MF-LF
402 2
KBDLED_ANODE
R5855
U5850
NO STUFF
10
518S0691
1%
1/16W
MF-LF
2 402
KBDLED_CAP
CAP 4
THRML
GND
PAD
J5815 pin 1 is grounded

on keyboard backlight flex
DFN
10K
CRITICAL
LT3491
R58521
SMC_KDBLED_PRESENT_L
SW 3
6 CTRL
KB_BL
To detect Keyboard backlight, SMC will

tristate and read SMC_SYS_KBDLED:
F-RT-SM
6
10V 2
X5R
402-1
FF18-4A-R11AD-B-3H
VIN
10%
45
J5815
SWITCH_NODE=TRUE
1098AS-SM
KB_BL
C5850
CRITICAL
KB_BL
R58531
102 100 91 89 88 85
46 41 40 39 36 35 32 28 26 25 23 12 7 6
84 83 80 73 72 62 61 57 52 51 50 49 48
10UH-0.58A-0.35OHM
1
2
KBDLED_SW
KB_BL
1
C5855
1UF
10%
35V
2 X5R
603
(SMC_KBDLED_PRESENT_L)
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
58 OF 132
SHEET
54 OF 105
PP3V3_S3
BYPASS=U5920.14:13:8 mm
1
10UF
20%
6.3V
X5R 2
603
C5922
0.1UF
VDD
10%
6.3V
2 X5R
201
BYPASS=U5920.14:13:8 mm
R59241
NC
NC
10K
OUT
2
3 NC
U5920
LIS331DLH
CS 8
CRITICAL
SMS_INT_L
TP_SMS_INT2
R59201 R59251
VDD_IO
LGA
10
15 RESERVED
5%
1/20W
MF
201 2
46 45
C5926
14
54 50 49 48 32 31 30 29 25 24 18 8 7 6
104 88 73
11 INT1
9 INT2
SDO 7
SDA/SDI/SDO 6
SCL/SPC 4
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
SMS_I2C_SEL
R59211
PLACEMENT_NOTE=See schematic for orientation.
Desired orientation when

placed on board bottom-side (view thru top):
10K
5%
1/20W
MF
201 2
SMBUS_SMC_A_S3_SDABI
6 31 45 48 54 98
5%
1/20W
MF
201
SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R
338S0687
R5923
1
GND
5
12
13
16
NOSTUFF
R5922
1
SMBUS_SMC_A_S3_SCLIN
6 31 45 48 54 98
5%
1/20W
MF
201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
Front of system
+X
+Z (dn)
Circle indicates pin 1 location when placed

in correct orientation
PAGE TITLE
Digital Accelerometer
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
59 OF 132
SHEET
55 OF 105
C
PP3V3_S5
R6101
3.3K
5%
1/16W
MF-LF
2 402
47
IN
CRITICAL
VDD
8
72 71 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73
C6100 1
0.1UF
20%
10V
CERM 2
402
U6100
64MBIT
SPI_MLB_CLK
SCK
SOIC
SI
SPI_MLB_MOSI
IN
47
SO
SPI_MLB_MISO
OUT
47
SST25VF064C
47 19 6
IN
IN
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
NOTE: If HOLD* is asserted

ROM will ignore SPI cycles.
1
3
7
CE*
WP*
HOLD*
OMIT
VSS
4
47
SYNC_MASTER=K92_BEN
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
61 OF 132
SHEET
56 OF 105
AUDIO CODEC
APPLE P/N 353S3199

71 41 32 25 22 20 16 7
PP1V5_S0
PP5V_S0_AUDIO
PP3V3_S0
C6200 1
4.7UF
C6201
PP4V5_AUDIO_ANALOG
0.47UF
20%
4V
X5R 2
402
C6203
IN
20%
6.3V
CERM
402-LF
2.67K
1%
1/16W
MF-LF
2 402
DIGITAL MIC DATA LINE

HP AMP CNTRL
MAC SPKR AMP CNTRL
OUT
59
OUT
60 58
OUT
2.2UF
D6200
SOD-523
OUT
10UF
10%
10V 2
X5R
402
20%
2 16V
POLY-TANT
CASE-B2-SM
C6206 C6207
1UF
10%
2 10V
X5R
402-1
0.47UF
CS4206_FLYP
CS4206_FLYC
C6211
2.2UF
SENSE_A
U6200
C6212
2.2UF
CS4206_FLYN
FLYP
FLYC
FLYN
10UF
GND_AUDIO_CODEC
38
40
39
AUD_HP_PORT_L
AUD_HP_PORT_R
TP_AUD_LO2_L_P
TP_AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
31
30
32
33
AUD_LO3_L_P
AUD_LO3_L_N
AUD_LO3_R_P
AUD_LO3_R_N
MICBIAS
16
AUD_CODEC_MICBIAS
VL_IF
BITCLK
XW6206
SM
57 58 62
OUT
57 59
OUT
58 59
OUT
60
100
OUT
60 100
OUT
CS4206_VCOM
28
60 100
OUT
60
100
OUT
60 100
OUT
60 100
OUT
62
WFR SPKR AMPS (L2/R2)
XW6201
SIGNAL_MODEL=EMPTY
SM
AUD_HP_PORT_L
NC
HDA_BIT_CLK
GND_AUDIO_HPAMP
HDA_SYNC
R6201
OUT
95 16
IN
95 16
IN
61
IN
HDA_SDIN0
HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN
10
95
AUD_SDI_R
8
5
5%
1/16W
MF-LF
402
11
61
OUT
AUD_SPDIF_OUT
33
47
48
CS4206_SPDIF_OUT
R6202
2
21
23
AUD_LI_L
AUD_LI_C
AUD_LI_R
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
AUD_MIC_INL_P
AUD_MIC_INL_N
AUD_MIC_INR_P
AUD_MIC_INR_N
VREF+_ADC
27
SDI
SDO
RESET*
SPDIF_IN
SPDIF_OUT
CS4206_VREF_ADC
NC
DMIC_SCL
R62031
5%
1/16W
MF-LF
402
22
CODEC_DMIC_CLK
AUD_HP_PORT_L_P
60
AUD_HP_PORT_L_N
60
XW6202
SM
1
IN
58
IN
58
IN
58
IN
62 100
IN
62 100
IN
62 100
IN
62 100
INTERNAL MIC INPUT
61
DIGITAL MIC CLOCK LINE
CRITICAL
NOSTUFF
0
AUD_DMIC_CLK
OUT
CRITICAL
C6213 1
10%
20V 2
TANT
CASE-R-HF
20%
2 16V
POLY-TANT
CASE-B2-SM
1UF
R6204
33
5%
1/16W
MF-LF
402
DGND THRM_PAD AGND
EXTERNAL MIC INPUT
R6205
100K
1%
1/16W
MF-LF
402 2
SYNC
95 16
22
LINEIN_L+
LINEIN_CLINEIN_R+
IN
LFE SPKR AMP (FC/LFE)
59 57
VCOM
1
GND_AUDIO_HPAMP
AUD_INT_HP_REF
35
34
36
37
26
IN
57 58
20%
10V
2 X5R
805
VL_HD
49
95 16
IN
IN
C6208
59 57
95 16
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
25
46
13
45
43
42
20%
6.3V
2 CERM
402-LF
AUD_SENSE_A
10%
10V 2
X5R
402
AUD_GPIO_3
IN
14
15
44
41
12
20%
6.3V
CERM 2
402-LF
62
CS4206_FP
CS4206_FN
2
60
IN
PLACE XW6206 BETWEEN

PIN 39 & THERMAL PAD
VD VA_REF VA_HP VA
VBIAS_DAC
CRITICAL HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206B
HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
29
AUD_DMIC_SDA1
AUD_GPIO_1
AUD_GPIO_2
BAT54XV2T1
WIN SPKR AMP CNTRL
VBIAS_DAC
20%
6.3V
CERM
402-LF
24
1 C6210
2.2UF
R6200
1
C6204 C6205
0.47UF
59 57
C6209 1
1
10%
10V 2
X5R
402
20%
16V 2
POLY-TANT
CASE-B2-SM
GND_AUDIO_HPAMP
PP4V5_AUDIO_ANALOG
0.47UF
10UF
59 57
8 57
CRITICAL
10%
2 10V
X5R
402
C6202 1
58 57
IN
C6214
10UF
5%
1/16W
MF-LF
2 402
62 58 57
GND_AUDIO_CODEC
B
GND_AUDIO_HPAMP
57 59
VOLTAGE=0V
DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
AUDIO
4.5V REGULATOR
APPLE P/N 353S2234
L6251
FERR-220-OHM
1
PP5V_AUDIO_HPAMP 59
VOLTAGE=5V
0402
L6250
U6201
FERR-220-OHM
PP5V_S0_AUDIO
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
1K
VOLTAGE=5V
0402
R6250
C6251 1
1UF
C6250
C6252
0.01UF
MAX8840_BP
0.001UF
10%
10V 2
X5R
402
0.1UF
10%
16V
2 X5R
402-1
NC 5
57 58
VOLTAGE=4.5V
C6253
BP 4
3 SHDN*
GND
PP4V5_AUDIO_ANALOG
CRITICAL
AUD_REG_SHDN_L
5%
1/16W
MF-LF
402
MAX8840-4.5V
UDFN
1 IN
OUT 6
AUD_4V5_REG_IN
57 8
10%
2 50V
CERM
402
10%
16V
CERM
402
C6254
1UF
10%
10V
X5R 2
402
XW6200
SM
1
SYNC_MASTER=K92_KAVITHA
GND_AUDIO_CODEC
57 58 62
AUDIO:CODEC
DRAWING NUMBER
XW6251
SM
1
PAGE TITLE
VOLTAGE=0V
GND_AUDIO_HPAMP
Apple Inc.
57 59
VOLTAGE=0V

SIZE
REVISION
BRANCH
PAGE
62 OF 132
SHEET
57 OF 105
CODEC Nom SE RIN = 20K OHMS

FC = 5 HZ Max
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
CRITICAL
C6300
R6300
61
IN
AUD_LI_INL
3.3UF
7.87K2
AUD_LI_LF
1%
1/16W
MF-LF
402
MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=.2MM
AUD_LI_L
MIN_LINE_WIDTH=0.3MM OUT
57
10%
16V
TANT
SMA-HF1
NOSTUFF
R6301
21.5K
C6301
820PF
1%
1/16W
MF-LF
402 2
10%
2 50V
CERM
402
CRITICAL
C6302
61
IN
3.3UF
AUD_LI_GND
AUD_LI_C
MIN_LINE_WIDTH=0.3MM OUT
1
R6303
10
1%
1/16W
MF-LF
2 402
NOSTUFF
R63051
21.5K
62 58 57
IN
57
10%
16V
TANT
SMA-HF1
GND_AUDIO_CODEC
C6304
820PF
1%
1/16W
MF-LF
4022
10%
50V
2 CERM
402
CRITICAL
C6303
R6306
61
IN
7.87K2
AUD_LI_INR
3.3UF
AUD_LI_RF
MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=.2MM
1%
1/16W
MF-LF
402
AUD_LI_R
OUT
57
10%
16V
TANT
SMA-HF1
SE-TO-DIFF CONVERTER
CRITICAL
C6353
R6353
3.3UF
59 57
AUD_HP_PORT_R
AUD_SE_DIFF_IN
21K
R6354
AUD_SE_DIFF_IN_R 1 21K 2
1%
1/16W
MF-LF
402
10%
16V
TANT
SMA-HF1
1%
1/16W
MF-LF
402
AUD_GPIO_2
IN
57 60
B4
V-
C3
C4
U6350
C2
AUD_LO1_R_P
OUT
C1
UCSP
V+
MAX4253
B1
CRITICAL
60 100
R6355
2.21K2
1%
1/16W
MF-LF
402
R6357
AUD_SE_DIFF_P_INV
2.21K2
1%
1/16W
MF-LF
402
R6358
2.21K2
1%
1/16W
MF-LF
402
R6356
AUD_SE_DIFF_N_INV
2.21K2
1%
1/16W
MF-LF
402
57
PP4V5_AUDIO_ANALOG
R63501
B1
21K
C6350 1
4.7UF
20%
6.3V 2
X5R
402
C6351
R6351
CRITICAL
CRITICAL
1
A3
SYNC_MASTER=K92_AUDIO
MAX4253
U6350
AUD_SE_DIFF_VBIAS
1%
1/16W
MF-LF
402 2
V+
0.47UF
10%
2 10V
X5R
402
21K
62 58 57
A2
1%
1/16W
MF-LF
402 2
UCSP
A1
OUT
AUDIO: LINE IN
60 100
A4
DRAWING NUMBER
VB4
Apple Inc.
C6352
3.3UF
10%
2 16V
TANT
SMA-HF1
SIZE
D
REVISION

GND_AUDIO_CODEC
PAGE TITLE
AUD_LO1_R_N
BRANCH
PAGE
63 OF 132
SHEET
58 OF 105
HEADPHONE AMPLIFIER (AK4201)

APN:353S2347
VOLTAGE GAIN:1.53
D
PLACE C6500 & C6501 NEAR PVDD PIN (5)

PLACE C6503 NEAR AVDD PIN (3)
0.1UF
C6500
10UF
C6501
0.001UF
20%
10V 2
X5R
805
10%
2 50V
CERM
402
AVDD
10%
16V 2
X5R
402-1
C6503
PVDD
57
PP5V_AUDIO_HPAMP
U6500
AK4201EU
USON
IN
59
IN
AUD_HPAMP_INL_M
AUD_HPAMP_INR_M
LIN
RIN
AUD_GPIO_1
AUD_HPAMP_MUTE_L
R65001
100K
5%
1/16W
MF-LF
402 2
59 61
OUT
59 61
IN
59 61
C6505
1UF
10%
2 10V
X5R
402
AK4201_CP
AUD_HPAMP_OUTR
R65161
CRITICAL
1
C6504
1UF
10%
2 10V
X5R
402
57
OUT
CRITICAL
THRM
PAD
5%
1/16W
MF-LF
402
59 61
AK4201_PVEE
IN
OUT
AK4201_CN
PVEE 10
4 VSS1
9
VSS2
13
57
CN 6
CP 7
PDN*
R6501
0
AUD_HPAMP_OUTL
LOUT 2
11
EXT_HP_AMP
CRITICAL ROUT
59
1
12
R6526
21K
21K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
L6535
FERR-220-OHM-2.5A
1
GND_AUDIO_HPAMP
2
0603
AUD_LO_GND_R
VOLTAGE=0V
R6531
13.7K
1%
1/16W
MF-LF
2 402
AK4201_VSS2
XW6501
SM
R6530
21K
AUD_LO_FDBK
AUD_LO_GND_R
1%
1/16W
MF-LF
402
1ST ORDER DAC FILTER
LP:42.10 KHZ
57
IN
AUD_HP_PORT_L
R6510
R6511
13.7K2
1%
1/16W
MF-LF
402
21K
AUD_HPAMP_OUTL
59 61
1%
1/16W
MF-LF
402
CRITICAL
C6511
180PF
59
OUT
AUD_HPAMP_INL_M
5%
50V
CERM
402
CRITICAL
C6521
180PF
59
OUT
AUD_HPAMP_INR_M
5%
50V
CERM
402
PAGE TITLE
58 57
IN
AUD_HP_PORT_R
R6520
R6521
13.7K2
1%
1/16W
MF-LF
402
21K
AUDIO: HEADPHONE OUT

AUD_HPAMP_OUTR
DRAWING NUMBER
Apple Inc.
REVISION
SIZE
59 61
1%
1/16W
MF-LF
402
BRANCH
PAGE
65 OF 132
SHEET
59 OF 105
5X MONO SPEAKER AMPLIFIERS (SSM2375)

APN: 353S2958
GAIN = +3 DB (BR, FL, FR, LFE), +9 DB (BL)
FC (SPEAKERS BL/BR) = ~737 HZ
FC (SPEAKERS FL/FR/LFE) = ~90 HZ
PLACE C6611/C6612 CLOSE TO PVDD PIN
PP5V_S0_AUDIO_AMP_L
CRITICAL
L6610
IN
C6613
FERR-1000-OHM
0.0027UF
SPKRAMP_BL_IN_L_P
1
0402
57
VDD
U6610
SSM2375
CRITICAL
L6611
C6614
FERR-1000-OHM
0.0027UF
AUD_HP_PORT_L_N 1
2 SPKRAMP_BL_IN_L_N 1
2
IN
0402
10%
50V
CERM
402
L6601
AUD_GPIO_2
1
2
0402
L6601 SHOULD BRIDGE SPLIT BETWEEN
GND_AUDIO_CODEC & DIGITAL GND
IN
AUD_GPIO_2_L
SSM2375BL_IN_P
100 SSM2375BL_IN_N
R6602
NOSTUFF
C6600 1
NOSTUFF
D6600
SOD-523
2
100
1UF
5%
1/16W
MF-LF
402
10%
10V
X5R 2
402
WLCSP
IN+
IN-
OUT+
OUT-
C3
B3
A2
SD*
GAIN
A3
EDGE
B2
R6600
GND
100K
5%
1/16W
MF-LF
2 402
20%
6.3V 2
POLY-TANT
2012-LLP
10%
2 16V
X5R
402-1
D
SPKRAMP_BL_OUT_P
B1
A1
C6611
0.1UF
C6612 1
47UF
CRITICAL
10%
50V
CERM
402
FERR-1000-OHM
58 57
CRITICAL
C2
AUD_HP_PORT_L_P
57
C1
60 8
BL_GAIN
SPKRAMP_BL_OUT_N
OUT
6 61
OUT
6 61
OUT
6 61
OUT
6 61
OUT
6 61
OUT
6 61
R6610
47K
5%
1/16W
MF-LF
4022
BAT54XV2T1
AUD_SPKRAMP_MAC_SHDN_L
PLACE C6625 CLOSE TO VDD PIN
PP5V_S0_AUDIO_AMP_L
CRITICAL
L6620
AUD_LO3_L_P
100 57
IN
0402
AUD_LO3_L_N
100 57
IN
100
SSM2375FL_IN_P
100 SSM2375FL_IN_N
C3
B3
A2
SD*
GAIN
A3
EDGE
B2
C6621
0.1UF
10%
2 16V
X5R
402-1
SPKRAMP_FL_OUT_P
C
TP_FL_GAIN
SPKRAMP_FL_OUT_N
GND
5%
1/16W
MF-LF
402 2
CRITICAL
L6631
C6634 Spk amp placed on the top side(flipped from K17)
FERR-1000-OHM
0.0027UF To prevent criss cross routes, the N and P are swapped
1
2 SPKRAMP_BR_IN_L_N
1
2
IN
on the input and output
VDD
U6630
SSM2375
WLCSP
CRITICAL
C6633
FERR-1000-OHM
0.0027UF
1
2 SPKRAMP_BR_IN_L_P
1
2
0402
SSM2375BR_IN_N
100 SSM2375BR_IN_P
100
10%
50V
CERM
402
AUD_SPKRAMP_MAC_SHDN_L
C6631
0.1UF
C6632 1
20%
6.3V 2
POLY-TANT
2012-LLP
10%
2 16V
X5R
402-1
47UF
CRITICAL
10%
50V
CERM
402
L6630
AUD_LO1_R_P
CRITICAL
C2
IN
SPKRAMP_BR_OUT_N
B1
A1
IN+
IN-
OUT+
OUT-
C3
B3
A2
SD*
GAIN
A3
EDGE
B2
TP_BR_GAIN
SPKRAMP_BR_OUT_P
GND
C1
60
OUT+
OUT-
100K
0402
100 58
IN+
IN-
PP5V_S0_AUDIO_AMP_R
AUD_LO1_R_N
100 58
WLCSP
B1
A1
R66011
AUD_SPKRAMP_WIN_SHDN_L
60 8
20%
6.3V 2
TANT
CASE-AL1
VDD
0402
L6602 SHOULD BRIDGE SPLIT BETWEEN
GND_AUDIO_CODEC & DIGITAL GND
60
100UF
U6620
SSM2375
10%
25V
X7R
0402
FERR-1000-OHM
AUD_GPIO_3
C6622 1
CRITICAL
CRITICAL
L6621
C6624
FERR-1000-OHM
0.022UF
1
2 SPKRAMP_FL_IN_L_N
1
2
0402
IN
CRITICAL
10%
25V
X7R
0402
L6602
57
C6623
FERR-1000-OHM
0.022UF
1
2 SPKRAMP_FL_IN_L_P
1
2
C2
60 8
C1
60
B
L6641
AUD_LO3_R_N
100 57
IN
FERR-1000-OHM
1
2 SPKRAMP_FR_IN_L_N
0402
100 57
IN
FERR-1000-OHM
100
SPKRAMP_FR_IN_L_P
1
2
C6642 1
20%
6.3V 2
TANT
CASE-AL1
VDD
C6643
SSM2375FR_IN_N
100 SSM2375FR_IN_P
0.022UF
1
100UF
CRITICAL
100
10%
25V
X7R
0402
CRITICAL
U6640
SSM2375
WLCSP
CRITICAL
CRITICAL
0402
B1
A1
IN+
IN-
OUT+
OUT-
C3
B3
A2
SD*
GAIN
A3
EDGE
B2
C6641
0.1UF
10%
16V
2 X5R
402-1
SPKRAMP_FR_OUT_N
OUT
6 61
SPKRAMP_FR_OUT_P
OUT
6 61
OUT
6 61
OUT
6 61
TP_FR_GAIN
GND
C1
60
Spk amp placed on the top side(flipped from K17)

To prevent criss cross routes, the N and P are swapped on the input and output
10%
25V
X7R
0402
L6640
AUD_LO3_R_P
C6644
0.022UF
C2
60 8
PP5V_S0_AUDIO_AMP_R
PP5V_S0_AUDIO_AMP_R
AUD_LO2_R_N
100 57
IN
0402
AUD_LO2_R_P
FERR-1000-OHM
100
SPKRAMP_LFE_IN_L_P
1
2
0402
C6652 1
20%
6.3V 2
TANT
CASE-AL1
VDD
0.022UF
100
100
10%
25V
X7R
0402
100UF
CRITICAL
C6653
1
CRITICAL
U6650
SSM2375
WLCSP
SSM2375LFE_IN_N
SSM2375LFE_IN_P
C6651
0.1UF
10%
16V
2 X5R
402-1
SPKRAMP_LFE_OUT_N
B1
A1
IN+
IN-
OUT+
OUT-
C3
B3
A2
SD*
GAIN
A3
EDGE
B2
SPKRAMP_LFE_OUT_P
AUDIO:SPEAKER AMP
Apple Inc.
SIZE
D
REVISION
GND
PAGE TITLE
DRAWING NUMBER
TP_LFE_GAIN
C1
60
0.022UF
amp placed on the top side(flipped from K17)

To prevent criss cross routes, the N and P are swapped on the input and output
CRITICAL
L6650
IN
C6654
10%
25V
X7R
0402
A
100 57
CRITICAL Spk
L6651
FERR-1000-OHM
1
2 SPKRAMP_LFE_IN_L_N
C2
60 8
BRANCH
PAGE
66 OF 132
SHEET
60 OF 105
MIC CONNECTORS: single anlg mic + 1 dig mic
AUDIO JACK 1 LO/HP JACK, SPDIF TX
CRITICAL
L6700
FERR-1000-OHM
1
AUD_CONNJ1_SLEEVE2
HS_MIC_HI
OUT
62
AUD_J1_SLEEVEDET_R
OUT
62
M-RT-SM
4
10K
BI_MIC_N
100 62
OUT
62
OUT
100 62
OUT
5% 1/16W
MF-LF 402
L6702
PP3V3_S0
BI_MIC_SHIELD
LEFT
RIGHT
GROUND
62
AUD_J1_TIPDET_R
OUT
62
APN: 518S0521
L6704CRITICAL
FERR-220-OHM
6
5
2
1
3
4
AUD_CONNJ1_TIP
CRITICAL
AUD_HPAMP_OUTL
BI
59
57
AUD_HPAMP_OUTR
BI
OUT
AUD_DMIC_CLK
L6784
CRITICAL
FERR-1200-OHM-200MA
1
2
HS_MIC_LO
57
OUT
OUT
AUD_DMIC_SDA1
AUD_CONNJ1_SLEEVE
62
DX6706
ESDALC5-1BM2
CRITICAL
CRITICAL
DZ6700
DZ6702
6.8V-100PF
SOD882
10%
2 10V
X5R
402
3
4
AUD_LO_GND_R
OUT
59
IN
57
PP3V3_S0
2
0402
SPEAKER CONNECTORS
APN: 518S0521
OMIT_TABLE
CRITICAL
1UF
L6785
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
AUD_SPDIF_OUT
C6700
0603
C
1
AUD_DMIC_CLK_BK
AUD_DMIC_SDA_BK
AUD_DMIC_PWR_BK
600-OHM-300MA
L6707CRITICAL
FERR-220-OHM-2.5A
2
0402
0402
600-OHM-300MA
L6706
10
11
12
13
M-RT-SM
5
2
0402
59
0402
7
8
9
78171-0004
600-OHM-300MA
L6705CRITICAL
FERR-220-OHM
AUD_CONNJ1_RING
J6783
L6783
0402
POF
SHELL
OUT
0402
OPERATING VOLTAGE 3.3
SHIELD
PINS
AUDIO
A - VIN
B - VCC
C - GND
AUD_J1_PERIPHDET_R
FERR-1000-OHM
AUD_CONNJ1_TIPDET
F-RT-TH
SWITCH
L6703
CRITICAL
J6700
MICROPHONE
0402
SPDIF-TX-K20
DETECT FOR PT
BI_MIC_P
FERR-1000-OHM
APN: 514-0632
CRITICAL
402
CRITICAL
DZ6704
6.8V-100PF
402
CRITICAL
J6781
XW6701
SM
6.8V-100PF
402
DZ6701
78171-0004
M-RT-SM
5
CRITICAL
CRITICAL
DZ6703
DZ6705
6.8V-100PF
6.8V-100PF
6.8V-100PF
402
402
402
XW6702
SM
60 6
IN
60 6
IN
60 6
IN
60 6
IN
1
61 8
SPKRAMP_FL_OUT_P
SPKRAMP_FL_OUT_N
SPKRAMP_BL_OUT_P
SPKRAMP_BL_OUT_N
1
2
3
4
NOSTUFF
C6783
VOLTAGE=0V
PART NUMBER
377S0112
102 100 91
61 57 54 52 51 50
28 26 25 23 12 7 6
49 48 46 41 40 39 36 35 32
89 88 85 84 83 80 73 72 62
78171-0003
0402
R6701
AUD_CONNJ1_SLEEVEDET
102
84 83 80 73 72
50 49 48 46 41
26 25 23 12 7 6
40 39 36 35 32 28
62 61 57 54 52 51
100 91 89 88 85
J6780
APN: 518S0520
QTY
DESCRIPTION
EMC supressor
REFERENCE DES
CRITICAL
BOM OPTION
100PF
5%
50V
NOSTUFF CERM
NOSTUFF
C6781
100PF
DX6706
C6782
NOSTUFF
1
C6784
100PF
402
5%
2 50V
CERM
402
100PF
5%
50V
CERM 2
402
5%
50V
2 CERM
402
PP3V3_S0
AUDIO JACK 2 LINE IN JACK, SPDIF RX
APN: 514-0633
FERR-1000-OHM
AUD_CONNJ2_TIPDET
SPDIF-RX-K20
F-RT-TH
DETECT FOR PT
SWITCH
LEFT
RIGHT
GROUND
62
J6782
78171-6006
M-RT-SM
2
AUD_LI_INL
BI
58
0402
60 6
IN
L6753
60 6
IN
60 6
IN
60 6
IN
0402
60 6
IN
L6754
60 6
IN
FERR-1000-OHM
AUD_CONNJ2_RING
6
7
8
AUD_LI_INR
BI
58
SPKRAMP_FR_OUT_P
SPKRAMP_FR_OUT_N
SPKRAMP_BR_OUT_P
SPKRAMP_BR_OUT_N
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
1
2
3
4
5
6
600-OHM-300MA
AUD_CONNJ2_SLEEVE
9
10
11
12
AUD_LI_GND
OUT
58
0402
R6755
AUD_J2_OPT_OUT
10
AUD_SPDIF_IN
OUT
57
5%
1/16W
MF-LF
402
C6750
1UF
10%
2 10V
X5R
402
CRITICAL
DZ6753
ESDALC5-1BM2
CRITICAL
DZ6750
ESDALC5-1BM2
SOD882
CRITICAL
DZ6752
6.8V-100PF
SOD882
1
402
CRITICAL
DZ6751
1
2
PAGE TITLE
AUDIO: JACKS
8 61
6.8V-100PF
402
DRAWING NUMBER
R6750
1

SIZE
D
REVISION
5%
1/16W
MF-LF
402
Apple Inc.
RETURN FOR HF NOISE
B
CRITICAL
OUT
FERR-1000-OHM
AUD_CONNJ2_TIP
POF
SHIELD
PINS
AUD_J2_TIPDET_R
L6752
OPERATING VOLTAGE 3.3
SHELL
2
0402
5
2
1
3
4
AUDIO
A - VDD
B - GND
C - VOUT
APN: 518S0672
L6751
CRITICAL
J6750
BRANCH
PAGE
67 OF 132
SHEET
61 OF 105
"MIKEY"/EXTERNAL MICROPHONE
APN 353S2640
CODEC OUTPUT SIGNAL PATHS
L6880
PIN COMPLEX
0X09 (9,A)
0X09 (9,V23)
0X0B (11)
0X0A (10,D)
0x10 (16)
MAC OS SHDN
N/A
GPIO_2
GPIO_2
GPIO_2
N/A
WIN SHDN
N/A
N/A
GPIO_3
GPIO_3
N/A
FUNCTION
LINE IN
SPDIF IN
INTERNAL MIC
EXTERNAL MIC
PP3V3_S0
CONVERTER
0X05 (5)
0X07 (7)
0X06 (6)
0X06 (6)
PIN COMPLEX
VREF
0X12 (12,C)
N/A
0x0F (15)
N/A
0X0D (13,B,RIGHT)
MICBIAS (80%)
0X0D (13,V22,B,LEFT)
MIKEY
DET ASSIGNMENT
0X12 (C)
N/A
N/A
MIKEY
48 41 32 30 28 26 23 16 6
95 89
IN
BI
SMBUS_PCH_CLK
OUT
AUD_I2C_INT_L
AUD_SENSE_A
62
PP3V3_S0_AUDIO_F
IN
R6801
AUD_OUTJACK_INSERT_L
270K
5%
1/16W
MF-LF
2 402
AUD_PORTA_DET_L NC
Q6800
Q6801
IN
AUD_J1_TIPDET_R
47K
D 3
SSM6N15FEAPE
R6802
Q6801
WCSP
HS_SCL
C3
SCL
MICBIAS
C1
HS_MIC_BIAS
HS_SDA
B3
SDA
DETECT
B1
HS_SW_DET
HS_INT_L
D3
INT*
BYPASS
D1 HS_RX_BP
5%
1/16W
MF-LF
402
HS_RST_L
PERIPHDET_UNFILT
A3
ENABLE
A1
HDET
B2
CS
R6880
100K
5%
1/16W
MF-LF
2 402
GND_AUDIO_CODEC
5 G
1
1
1
R6804
220K
62 61
AUD_J1_SLEEVEDET_R
IN
5%
1/16W
MF-LF
2 402
AUD_PORTB_DET_L NC
5%
1/16W
MF-LF
2 402
D 6
2 G
S 4
C6884
S 1
OUT
AUD_MIC_INL_P
HS_MIC_HI_R
R68831
CRITICAL
C6885
62 61
2 G
C6886
2.2K 2
5%
1/16W
MF-LF
402
100 57
OUT
AUD_MIC_INL_N
XW6800
SM
S 1
62 58 57
GND_AUDIO_CODEC
INTERNAL MICROPHONE
R6855
AUD_CODEC_MICBIAS
IN
2.2K 2
INT_MIC_BIAS
CRITICAL
5%
1/16W
MF-LF
402
PP3V3_S0_AUDIO_F
R6850
20%
TANT-POLY
2012-LLP
0.47UF
100 57
OUT
AUD_MIC_INR_P
AUD_INJACK_INSERT_L NC
61 100
B
C6852
C6851
R6852
100K
5%
1/16W
MF-LF
2 402
10%
25V
X7R 2
402
CRITICAL
0.47UF
AUD_J2_DET_RC
5%
1/16W
MF-LF
402
0.0082UF
D 3
R6812
47K
BI_MIC_P
2
10%
10V
X5R
402
SOD-VESM-HF
Q6802
SSM3K15FV
1%
1/16W
MF-LF
2 402
C6850
10K
5%
1/16W
MF-LF
2 402
3.40K
CRITICAL
1%
1/16W
MF-LF
402 2
270K
AUD_J2_TIPDET_R
C6854
10UF
GND_AUDIO_CODEC
R6813
R6811
1 G
C6811
100 57
S 2
OUT
AUD_MIC_INR_N
BI_MIC_N
61 100
10%
10V
X5R
402
0.1UF
10V
2 20%
CERM 402
62 58 57
2 16V
IN
61
61
IN
C6887
62 58 57
HS_MIC_LO
5%
2 50V
CERM
402
AUD_SENSE_A
62
61
15PF
10%
2 25V
X7R
402
PORT C DETECT (LINE IN)

OUT
IN
10%
10V
X5R
402
57
62 57
0.0082UF
5%
1/16W
MF-LF
402 2
HS_MIC_HI
NOSTUFF
10%
2 16V
CERM
402
GND_AUDIO_CODEC
5%
1/16W
MF-LF
2 402
0.47UF
AUD_J1_SLEEVEDET_R
SOT563
0.01UF
62 58 57
100K
C6802
2.2K
R6885
0.47UF
SSM6N15FEAPE
R6882
SOT563
100 57
D 6
5%
1/16W
MF-LF
2 402
CRITICAL
5 G
Q6800
20%
2 6.3V
TANT
603-HF
1K
AUD_J1_SLEEVEDET_INV
5%
1/16W
MF-LF
402
10%
25V
2 X7R
402
R6881
10%
10V
X5R
402
100K 2
4.7UF
GND_AUDIO_CODEC
PP3V3_S0_AUDIO_F
C6883
R6884
R6803
62
0.01UF
0.1UF
10V
C6882
NOSTUFF
S 4
C6801
CRITICAL
1
AUD_J1_DET_RC
D
KEEP DET TRACE AS SHORT AS POSS
CD3282A1
1%
1/16W
MF-LF
2 402
2 20%
CERM 402
62 58 57
CRITICAL
SSM6N15FEAPE
SOT563
5%
1/16W
MF-LF
402
0.001UF
10%
50V
2 CERM
402
D 3
SSM6N15FEAPE
SOT563
61
62 58 57
C6881
AVDD
20.0K
1%
1/16W
MF-LF
2 402
U6880
5%
1/16W
MF-LF
402
1
2
5%
1/16W
MF-LF
402
R6805
39.2K
20%
6.3V
X5R 2
603
R6893
R6894
R6806
AUD_IPHS_SWITCH_EN
1
5%
1/16W
MF-LF
402
PORT B DETECT
(SPDIF DELEGATE)
1
1
10UF
R6891
R6892
18
C6880
5%
1/16W
MF-LF
402
SMBUS_PCH_DATA
62 61
OUT
AUD_J1_PERIPHDET_R
62 57
CRITICAL
10K
1%
1/16W
MF-LF
4022
R6890
PP3V3_S0_HS_RX
2
0402
R68861
23 19
PORT A DETECT
(LINE OUT)
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
89 48 41 32 30 28 26 23 16 6
95
CODEC INPUT SIGNAL PATHS
VOLTAGE=3.3V
FERR-1000-OHM
DET ASSIGNMENT
0X09 (A)
N/A
N/A
N/A
0X0D (B)
A2
CONVERTER
0X02 (2)
0X02 (2)
0X04 (4)
0X03 (3)
0X08 (8)
D2 AGND
VOLUME/MUTE
0X02 (2)
0X02 (2)
0X04 (4)
0X03 (3)
N/A
C2 DGND
FUNCTION
HP/LINE OUT
SPEAKERS BL/BR
SPEAKERS FL/FR
SPEAKER LFE
SPDIF OUT
R6851
3.40K
GND_AUDIO_CODEC
1%
1/16W
MF-LF
2 402
EXTRACTION NOTIFICATION CKT

62
IN
XW6850
SM
PP3V3_S0_AUDIO_F
62 58 57
GND_AUDIO_CODEC
INT_MIC_RET
R6861
220K
5%
1/16W
MF-LF
2 402
R6862
XW6851
SM
100K
PLACE L6800/C6800 CLOSE TO Q6800/01/02
Q6803
L6800
PP3V3_S0
PP3V3_S0_AUDIO_F
0402
C6800
VOLTAGE=3.3V
62
R6860
62 61
1
AUD_J1_PERIPHDET_R
0.1UF
15K
PERIPHDET_FILT
5 G
Q6803
S 4
D 6
2 AUD_IP_PERIPHERAL_DET OUT
18
AUDIO: JACK TRANSLATORS
SOT563
DRAWING NUMBER
C6860
0.1UF
Apple Inc.
S 1

GND_AUDIO_CODEC
SIZE
D
REVISION
AUD_J1_PERIPHDET_INV
20%
2 10V
CERM
402
62 58 57
PAGE TITLE
SSM6N15FEAPE
2 G
GND_AUDIO_CODEC
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10%
2 16V
X5R
402-1
61
R6863
AUD_PERIPH_DET_R 1
SOT563
2
1
62 58 57
D 3
SSM6N15FEAPE
FERR-1000-OHM
102 100 91 89 88 85 84 83
41 40 39 36 35 32 28 26 25 23 12 7 6
80 73 72 62 61 57 54 52 51 50 49 48 46
BI_MIC_SHIELD
5%
1/16W
MF-LF
2 402
BRANCH
PAGE
68 OF 132
SHEET
62 OF 105
MagSafe DC Power Jack

CRITICAL
F6905
PPDCIN_G3H
6AMP-24V
CRITICAL
J6900
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
78048-0573
1206-1
73 64 63 53 48 47 46 45 44 42 25 7 6
104
M-RT-SM
1
PWR
PWR
GND
GND
SIG
PP3V42_G3H
C6905
C6908
20%
50V
CERM
603
SMC_BC_ACOK_BUF
1
1
R6929
VCC
2.0K
U6900
5%
1/16W
MF-LF
402
RCLAMP2402B
SC-75
NC
MAX9940
SC70-5
ADAPTER_SENSE
SMC_BC_ACOK
IN
45 46 49 64
Y
1
SYS_ONEWIRE
INT 4
EXT
D6900
1
20%
10V
CERM
402
U6901
CRITICAL
NO STUFF
0.1UF
CRITICAL
TC7SZ08AFEAPE 5
SOT665
0.01UF
2
1-Wire OverVoltage & ESD Protection
6 7 49 63 64
45
BI
NC
GND
CRITICAL
NC
3.425V "G3Hot" Supply
CRITICAL
D6990
Supply needs to guarantee 3.31V delivered to SMC VRef generator
BAT30CWFILM
SOT-323
1
P3V42G3H_REF3
PPDCIN_G3H
47
PPDCIN_S5_P3V42G3H 2
VOLTAGE=18.5V
1%
1/3W
MF
805
C6995 1
0.1UF
R6995
1M
C6990
VIN 7
64 63 49 7 6
PPVIN_G3H_P3V42G3H
VOLTAGE=18.5V
R6990
5%
1/16W
MF-LF
2 402
4.7UF
10%
35V
X5R-CERM 2
0805
P3V42G3H_TON
3 TON
4 EN
P3V42G3H_FB
C6991
NC
1 REF
10%
25V 2
X5R
402
PM6640
DFN
CRITICAL
CRITICAL
33UH-20%-0.44A-0.455OHM
L6995
SW 6
THRM
GND PAD
5
1UF
BYP 9
U6990
8 VCC
2 FB
20%
10V
CERM 2
402
REF3 10
PPBUS_G3H
P3V42G3H_SW
353S2776
PP3V42_G3H
C6994
6 7 25 42 44 45 46 47 48 53 63 64 73 104
2
Vout = 3.425
D52LC-SM
SWITCH_NODE=TRUE DIDT=TRUE
11
90 64 50 49 39 35 8 7 6
300mA max output
f = 470 kHz
0.1UF
10%
16V
X5R 2
402-1
C6999
22UF
20%
2 6.3V
X5R-CERM1
0603
518-0375
CRITICAL
BATTERY CONNECTOR
J6950
BAT-K90-K91-K92
M-RT-TH
BIL Connector
1
2
6
7
SMBUS_SMC_BSA_SCL
6 45 48 63 64 98
FF18-5A-R11AD-B-3H
6 SYS_DETECT_L
F-RT-SM
SMBUS_SMC_BSA_SDA
D6950
8
9
C6950
10
11
10%
25V
X5R
402
C6960
10%
25V
X5R
603-1
6 7 25 42 44 45 46 47 48 53 63 64 73 104
RCLAMP2402B
R6950
SC-75
1UF
2
PP3V42_G3H
6
45 48 63 64 98
64 6 PPVBAT_G3H_CONN
0.1UF
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
CRITICAL
J6995
518S0720
10K
5%
1/16W
MF-LF
402
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_L
IN
BI
OUT
6 45 48 63 64 98
6 45 48 63 64 98
6 45 46
5
2
P1
P2
P3
P4
P5
P6
P7
P8
P9
12
C6955
0.001UF
13
2
C6953
47PF
10%
50V
CERM
402
5%
50V
CERM
402
SYNC_MASTER=K92_CHANG
CRITICAL
C6952
C6954
47PF
5%
50V
CERM
402
DC-In & Battery Connectors
0.001UF
10%
50V
CERM
402
PAGE TITLE
1
DRAWING NUMBER
2
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
69 OF 132
SHEET
63 OF 105
CRITICAL
Q7080
IRF9395TRPBF
DIRECTFET-MC
2
1
9
8
5
4
NC
Reverse-Current Protection
10%
25V
402
1%
1/16W
MF-LF
402
100K
5%
1/16W
MF-LF
2 402
CHGR_AGATE_DIV
CHGR_SGATE_DIV
1
R7081
R7086
62K
332K
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
CRITICAL
D7005
(CHGR_AGATE)
BAT30CWFILM
SOT-323
1
(CHGR_SGATE)
R7005
CHGR_DCIN_D_R
20
R7021
(CHGR_DCIN)
Divider sets ACIN threshold at 13.55V
BI
IN
CHGR_ACIN
R7011
9.31K
R7015
98
330K
98
5%
1/16W
MF-LF
2 402
CHGR_VCOMP_R
C7015 1
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
C7050
1UF
10%
16V
2 X5R
402
20%
2 25V
POLY-TANT
CASE-D2-SM
10%
2 25V
X5R
402
CHGR_DCIN
26
1
28 98
27 98
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
25
24
23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
21
CHGR_LGATE
GATE_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
CHGR_BGATE
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK
OUT
50
OUT
50
OUT
45 46 49 63
CRITICAL
D
1
C7025
RJK0332DPB-01
LFPAK-SM
0.22UF
DIDT=TRUE
L7030
1 2 3
4.7UH-10.2A
C7037
0.001UF
10%
2 50V
X7R
402
10%
25V
2 X5R
603-1
NO STUFF
F7041
8AMP-24V
PPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
CRITICAL
1
RJK0305DPB
NO STUFF
1
CRITICAL
10%
2 50V
CERM
402
1 2 3
(GND)
1%
1W
MF
0612
R7051
R7052
(CHGR_CSO_P)
(CHGR_CSO_N)
(PPVBAT_G3H_CHGR_R)
2.2
100 50
100 50
CRITICAL
Q7055
2
4
1
3
SI7137DP
SO-8
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
C7055 1
C7056 1
C7057 1
10%
25V
X5R 2
603-1
10%
16V 2
X5R
402-1
10%
16V
CERM 2
402
1UF
470PF
0.001UF
0.005
CHGR_VNEG_R
C7016
10%
2 50V
X7R
402
2
1206
R7050
10%
2 50V
CERM
402
20%
POLY-TANT
CASE-D2-SM
22UF
C7039
C7045
C7040
2 25V
470PF
XW7000
SM
DIDT=TRUE
Q7035
6 7 8 35 39 49 50 63 90
CRITICAL
CHGR_PHASE_RC
CRITICAL
PPBUS_G3H
2
1206
180
353S2929
TO SYSTEM
F7040
8AMP-24V
FDA1254F-SM
5%
1/10W
MF-LF
603 2
LFPAK-HF
CRITICAL
3
R70391
C7036
1%
1/16W
MF-LF
402 2
1UF
10%
25V
2 X5R
603-1
20%
2 25V
POLY-TANT
CASE-D2-SM
CRITICAL
220PF
3.01K
C7035
1UF
22UF
Max Current = 8A
(L7030 limit)
f = 400 kHz
Q7030
10%
10V
2 CERM
402
10%
50V
X7R-CERM 2
402
R70161
C7031
5
2
16
9
36V/V BMON 15
(OD) ACOK 14
29
1%
1/16W
MF-LF
2 402
U7000
(AGND)
THRM_PAD
C7021
CRITICAL
1
TO/FROM BATTERY
0.1UF
45 6
63
73
22UF
PPVBAT_G3H_CONN
5
IN
C7030
1%
1/16W
MF-LF
2 402
45 6
63
CRITICAL
1
0.01uF
VOLTAGE=12.6V
6 63
5% 48
1/16W98
MF-LF48
402 98
PPDCIN_G3H_CHGR
VOLTAGE=18.5V
30.1K
CHGR_RST_L
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
CHGR_VFRQ
CHGR_CELL
4 2 0612
VDDP
VHST CRITICAL DCIN

SMB_RST_N
SGATE
SCL
AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
3 ACIN
UGATE
5 ICOMP
PHASE
7 VCOMP
LGATE
8 VNEG
18 CSOP
BGATE
17 CSON
20V/V AMON
ISL6259
0.5%
1W
MF-LF
CHGR_CSI_R_N
0.1UF
10%
25V 2
X5R
402
PGND
SMC_RESET_L
0.020
2 3
VDD
12
13
11
10
4
6
R7020
20
5%
1/16W
MF-LF
2 402
0.1UF
10%
10V 2
X5R
402
100K
64
C7022 1
1UF
R7002
GND_CHGR_AGND
IN
C7001 1
22
R7010
VOLTAGE=5.1V
5%
1/16W
MF-LF
402
R7000
0
100
10
3 1
CHGR_CSI_R_P
5%
1/16W
MF-LF
402
PP5V1_CHGR_VDDP
19
1%
1/16W
MF-LF
402 2
4.7
10%
10V
X5R 2
402
1K
NO STUFF
1UF
R70121
VOLTAGE=5.1V
PP3V42_G3H
C7002
R7022
1
R7001
PP5V1_CHGR_VDD
73 63 53 48 47 46 45 44 42 25 7 6
104
CRITICAL
100
C7020
10%
10V
2 CERM
402
30mA max load
5%
1/16W
MF-LF
402
0.047UF
Input impedance of ~40K meets

sparkitecture requirements
10
5%
1/16W
MF-LF
402
ACIN pin threshold is 3.2V, +/- 50mV
R7080
R7085
470K
0.1UF
2 X5R
C7085
PPDCIN_G3H_INRUSH
VOLTAGE=18.5V
PPDCIN_G3H
Inrush Limiter
FROM ADAPTER
63 49 7 6
NC
10
7
NC
NC
CHGR_CSO_R_P
5% 1/16W MF-LF 402
CHGR_CSO_R_N
5% 1/16W MF-LF 402
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
C7042
C7011 1
0.068UF
0.01UF
10%
2 10V
CERM
402
10%
16V
CERM 2
402
C7000
1UF
10%
2 10V
X5R
402-1
C7005 1
C7026 1
0.22UF
0.001UF
20%
25V 2
X5R
603
64
10%
50V
CERM 2
402
GND_CHGR_AGND
VOLTAGE=0V
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER
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SIZE
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REVISION

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SHEET
64 OF 105
70 69 68 67 50 7
104 87 73 70 69 68 54 52 47 41 22 8 7 6
105
PP5V_S0
PLACE_NEAR=Q7100.2:1.5mm
VCCSAS0_BOOT_RC
R71011
C7101
20%
2 10V
X5R
603
5%
1/16W
MF-LF
402 2
R7130
19
20
DIDT=TRUE
ISL95870A
73
CRITICAL
UGATE
OMIT_TABLE
10 FB
CPU_VCCSASENSE
VCCSAS0_SREF
R7147
113K
1%
1/16W
MF-LF
2 402
73
OUT
12 VO
VCCSAS0_OCSET
11 OCSET
14
VCCSAS0_RTN
VCCSAS0_FSEL 13
C7103 1
0.022UF
10%
16V
CERM-X5R 2
402
C7105
1000PF
5%
2 25V
NP0-C0G
402
LGATE 1
GATE_NODE=TRUE
DIDT=TRUE
C7122
1000PF
5%
2 25V
NP0-C0G
402
CRITICAL
CRITICAL
Q7100
SIZ700DT
0.001
L7100
1%
1W
MF-1
0612
1.0UH-7.7A
VCCSAS0_LL
SWITCH_NODE=TRUE
DIDT=TRUE
R7140
CRITICAL
POWERPAIR-6X3.7
PPVCCSA_S0_REG_R
1
MIN_LINE_WIDTH=0.6 mm 3
VOLTAGE=1.05V
FDV0630H-SM
PPVCCSA_S0_CPU
2
4
7 12 15
6A Max Output
f = 300 kHz
PGOOD
VCCSAS0_DRVL
RTN
VCCSAS0_SET0
8 SET0
VCCSAS0_SET1
9 SET1
GATE_NODE=TRUE
DIDT=TRUE
FSEL
R7148
6 VID0
XW7101
SM
1%
1/16W
MF-LF
2 402
C7102
2.2UF
10%
2 16V
X5R
603
R71031
5 VID1
0
5%
1/16W
MF-LF
402 2
GND
PGND
R7141
12
IN
100 49
VCCSAS0_CS_P
100 49
VCCSAS0_CS_N
1K
PLACE_NEAR=C1763.2:3mm
1%
1/16W
MF-LF
402 2
C7140
1000PF
2
10%
16V
X7R-CERM 2
402
2
1
140K
1
17
PHASE 16
SREF
VCCSAS0_VO
PVCCSA_PGOOD
BOOT 18
VCCSAS0_DRVH
IN
IN
15 EN
12
PVCCSA_EN
0.1UF
10%
16V
X5R-CERM 2
0805
VCCSAS0_VBST
U7100
UTQFN
C7121 1
10UF
10%
2 10V
CERM
402
5%
1/10W
MF-LF
603 2
PVCC
C7130
C7120
10%
16V
X5R-CERM 2
0805
0.22UF
VCC
CRITICAL
10UF
PP5V_S0_VCCSAS0_VCC
C7119
10UF
2.2
VOLTAGE=5V
CRITICAL
DIDT=TRUE
CPU_VCCSA_VID<1>
5%
25V
NP0-C0G
402
R7149
47.5K
1%
1/16W
MF-LF
2 402
R7142
1K
OCP = R7141 x 8.5uA / R7140

OCP = 8.5A
1%
1/16W
MF-LF
2 402
(VCCSAS0_OCSET)
(VCCSAS0_VO)
XW7100
SM
VCCSAS0_AGND
VOLTAGE=0V
PART NUMBER
353S3074
VID1
VID0
QTY
1
DESCRIPTION
IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P
REFERENCE DES
CRITICAL
U7100
CRITICAL
BOM OPTION
Voltage
0.9V
0.8V
PAGE TITLE
System Agent Supply

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
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SHEET
65 OF 105
CRITICAL
C7240 1
C7242 1
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
C7241
1UF
68UF
0.001UF
10%
2 25V
X5R
603-1
20%
16V 2
POLY-TANT
CASE-D2E-SM
C7200
10%
2 50V
X7R
402
1UF
10%
25V
X5R 2
603-1
2.2UH-22A-5.8M-OHM
1 VIN
10%
2 50V
X7R
402
20%
10V
X5R 2
805
20%
6.3V 2
POLY-TANT
CASE-D3L-SM1
DIDT=TRUE
P5VS3_VFB1_R
2
XW7220
SM
PGND
1%
1/16W
MF-LF
2 402
mm
mm
mm
mm
mm
mm
GATE_NODE=TRUE
DIDT=TRUE
P5VS3_LL
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
P5VS3_CSP1
P5VS3_CSN1
0.1UF
P5VS3_SNUBR
10%
16V
X5R
402-1
NO STUFF
C7299 1
10%
50V
CERM 2
402
R7249
5%
1/16W
MF-LF
2 402
5.11K2
R7256
9.09K
45 42 29 17
73
1
1
XW7221
SM
R7247
0.0033UF
P5VS3_MODE
P5VS3_VFB1
P5VS3_COMP1
OUT
PM_SLP_S4_L
P5VS3_PGOOD
1%
1/16W
MF-LF
402
NO STUFF
1
R7237
20.0K
1%
1/16W
MF-LF
2 402
P5VS3_CSP1_R
R7236
13
0.22UF
VREF2
22
VREG3
29
31 VBST1
1 DRVH1
30 DRVL1
QFN
VBST2 26
DRVH2 24
SW2 25
DRVL2 27
CSP2 18
CSN2 17
11 MODE
9 VFB1
10 COMP1
RF 3
VFB2 16
COMP2 15
4 EN1
5 PGOOD1
EN2 21
PGOOD2 20
SMC_PM_G2_EN
P3V3S5_DRVH
DIDT=TRUE
P3V3S5_LL
DIDT=TRUE
P3V3S5_DRVL
DIDT=TRUE
P3V3S5_CSP2
P3V3S5_CSN2
10K
1%
1/16W
MF-LF
2 402
P5VS3_COMP1_R
C7237
47PF
5%
50V
CERM 2
402
R7221
10K
5%
1/16W
MF-LF
2 402
2 WPAK2
0.001UF
IN
OUT
NO STUFF
6
10
P3V3S5_SNUBR
DIDT=TRUE
NO STUFF
10%
50V
2 X7R
402
1.07K2
1%
1/16W
MF-LF
402
20.0K
1%
1/16W
MF-LF
402 2
C7298
0.001UF
R7239
4700PF
5%
1/10W
MF-LF
603 2
3 4 5
R7246
1%
1/16W
MF-LF
402 2
1
C7238
R72981
249K
45 73
R7216
6.65K
XW7260
SM
1%
1/16W
MF-LF
2 402
CRITICAL
1
C7290
10UF
C7292
330UF
20%
6.3V
2 X5R
603
20%
2 6.3V
POLY-TANT
CASE-D3L-SM1
XW7262
SM
1
P3V3S5_VFB2_R
2
XW7261
SM
R72601
23.2K
1%
1/16W
MF-LF
402 2
P3V3S5_CSP2_R
10%
100V 2
CERM
402
10%
50V 2
X7R
402
10%
25V
X5R
402
R72061
73
4700PF
C7272
0.001UF
1
0.1UF
1
7 104
2.2UH-14A
IHLP2525CZ-SM1
C7288
C7236
(P5VP3V3_VREF2)
C7283
10%
2 50V
X7R
402
Vout = 3.3V
10A MAX OUTPUT
f = 400 kHZ
L7260
P3V3S5_TG
P3V3S5_COMP2_R
10%
2 100V
CERM
402
10%
2 25V
X5R
603-1
45 73
NO STUFF
R7238
1UF
CRITICAL
RJK0214DPA
10%
50V
X7R 2
603-1
R7263
IN
Q7260
0.1UF
THRM_PAD
1
C7281
CRITICAL
C7264 1
P3V3S5_RF
P3V3S5_VFB2
P3V3S5_COMP2
10K
1%
1/16W
MF-LF
402 2
DIDT=TRUE
GATE_NODE=TRUE
GATE_NODE=TRUE
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
P3V3S5_VBST
DIDT=TRUE
P3V3S5_EN
S5_PWRGD
PP3V3_S5_ISNS_R
2.2UF
20%
10V
2 X5R-CERM
402
10%
10V
CERM 2
402
EN 12
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
C7203
U7201
7 CSP1
8 CSN1
GND
1%
1/16W
MF-LF
402 2
IN
73
CRITICAL
32 SW1
P5VS3_DRVL
C7218
DIDT=TRUE
40.2K
P5VS3_VBST
DIDT=TRUE
P5VS3_DRVH
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
BG 5
R7299
1
5%
1/16W
MF-LF
402 2
TGR 4
NO STUFF
5%
1/10W
MF-LF
2 603
5%
1/16W
MF-LF
2 402
4.7
P5VS3_TG
6 SKIPSEL1
19 SKIPSEL2
14 OCSEL
R72441
6 VSW
7
8
XW7222
SM
R7220
TG 3
10UF
C7250 1
330UF
P5VS3_VSW
CRITICAL
C7252 1
SON5X6
R7248
0.1UF
CSD58864Q5D
0.001UF
10%
50V
2 X7R
603-1
Q7220
PIMB104E2R2MS-SM
C7271
C7224
C7282 1
20%
16V 2
POLY-TANT
CASE-D2E-SM
68UF
10UF
C7201 1
33
CRITICAL
28
L7220
NO STUFF
TPS51980
VREG5
CRITICAL
VIN
2
1
23
PP5V_S3_ISNS_R
CRITICAL
C7280 1
20%
6.3V
2 X5R
603
P5VP3V3_VREF2
V5SW
104 66 7
7 54 72 103 104
Vout = 5V
100mA MAX OUTPUT
1 C7205
P5VP3V3_VREG3
Vout = 5.0V
14.4A MAX OUTPUT
f = 400 kHZ
CRITICAL
PP5V_S5
C7270
CRITICAL
PP5V_S3_ISNS_R
104 66 7
50 7
C7239
47PF
5%
50V
2 CERM
402
R72611
10K
(P5VP3V3_VREF2)
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
72 OF 132
SHEET
66 OF 105
70 69 68 65 50 7
CRITICAL
CRITICAL
C7330 1
C7331 1
72 67 29 28 26 7
104 82 72 46 44 43 42 31 29 7 6
10%
2 25V
X5R
603-1
20%
20%
16V
16V
POLY-TANT 2
POLY-TANT 2
CASE-D2E-SM
CASE-D2E-SM
PP1V5_S3
PP5V_S3
C7301
C7332
1UF
68UF
68UF
C7333
0.001UF
10%
2 50V
X7R
402
C7334
1UF
10%
25V
603-1
2 X5R
10UF
20%
10V 2
X5R
603
C7300 1
10UF
R7330
1
(DDRREG_DRVH)
20%
10V 2
X5R
603
4.7
DDRREG_DRVH_R
5%
1/16W
MF-LF
402
C7325
VLDOIN
IN
MEMVTT_EN
DDRREG_EN
DDRREG_1V8_VREF
C7315
0.1UF
1
1
10%
16V 2
X5R
402
U7300
(VTT Enable) 17 S3
(VDDQ/VTTREF Enable) 16 S5
R7315
30
20.0K
DDRREG_FB
TPS51916
6 VREF
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
CRITICAL
8 REFIN
1%
1/16W
MF-LF
2 402
C7316
0.01UF
10%
2 16V
CERM
R7317 1R7318
200K
1%
1/16W
MF-LF
2 402
402
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
3 TG
OUT
PP0V75_S0_DDRVTT
XW7360
SM
1
DDRREG_VTTSNS
6
PPVTTDDR_S3
10mA max load
CRITICAL
1
20%
6.3V 2
X5R
603
PP1V5_S3
2 0612
20%
MF-1
1W
1%
C7340
270UF
20%
2 2V
TANT
CASE-B4-SM
C7345
C7341 1
20%
2V 2
TANT
CASE-B4-SM
20%
2 6.3V
X5R
603
270UF
2 6.3V
X5R
C7360, C7361 close
C7361
PPDDR_S3_REG_R
CRITICAL
CRITICAL
10UF
PGND
CRITICAL
1
49 100
VOLTAGE=1.5V
FDU1040D-SM
DIDT=TRUE
10UF
C7350
SWITCH_NODE=TRUE
5 BG
(DDRREG_DRVL)
C7360
XW7300
SM
1.0UH-21A
DDRREG_VSW
VTT THRM
GND PAD
CRITICAL
VSW 6
7
8
L7330
91
OUT
C
VIN 1
DDRREG_VDDQSNS
47.5K
1%
1/16W
MF-LF
2 402
SON5X6
4 TGR
(DDRREG_LL)
DIDT=TRUE
TP_DDRREG_PGOOD
ISNS_1V5_S3_N
CSD58864Q5D
10%
50V
X7R
603-1
DDRREG_DRVL
30
10
100K
GATE_NODE=TRUE
DDRREG_LL
49 100
Q7330
PGND GND
R7316
DDRREG_DRVH
11
20
9
3
1
VTTREF 5 7
QFN
DDRREG_MODE 19 MODE
DDRREG_TRIP 18 TRIP
1%
1/16W
MF-LF
2 402
IN
DDRREG_VBST
21
73
29 8
VBST 15
DRVH 14
SW 13
OUT
CRITICAL
0.1UF
12 V5IN
ISNS_1V5_S3_P
0.001
C7346 R7350
0.001UF
10%
2 50V
X7R
402
10UF
7 26 28 29 67 72
Vout = 1.5V
18A max output
(Q7335 limit)
f = 400 kHz
CRITICAL
2
XW7301
SM
1
603
to memory
(DDRREG_VDDQSNS)
0.22UF
10%
10V
CERM 2
402
GND_DDRREG_SGND
VOLTAGE=0V
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

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SHEET
67 OF 105
PP5V_S0
6 7 8 22 41 47 52 54 65 69 70 73 87 104
105
R7401
PP5V_S0_CPUIMVP_VCC
10
VOLTAGE=5V
5%
1/16W
MF-LF
402
PP1V05_S0
102 73 70 45 39 35 23 14 13 12 10 9 7
105 104
R7480
20%
10V
X5R-CERM 2
402
20%
2 10V
X5R-CERM
402
130
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
VDDA
VDDB
VCC
R7406
1
U7400
MAX15092GTL
69
OUT
69 68
92 46 10
5.76K
1%
1/16W
MF-LF
2 402
IN
92 12
IN
92 12
IN
5.76K
1%
1/16W
MF-LF
2 402
OUT
R7464
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
R7462
215K
1%
1/16W
MF-LF
2 402
BSTA1
DHA1
CRITICALLXA1
DLA1
POKA
CSPA1
POKB
CPUIMVP_BOOT1
CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1_P
EN
CPUIMVP_ISUM
CPUIMVP_ISUM_N
CPUIMVP_FBA
CPUIMVP_NTC
CPUIMVP_NTCG
THERMA
THERMB
CPUIMVP_SLEW
SR
CRITICAL
R7469
R7467
100KOHM
100KOHM
0402
0402
2
R7465
200K
1%
1/16W
MF-LF
2 402
IMAXA
IMAXB
R7460
215K
1%
1/16W
MF-LF
2 402
R7463
137K
1%
1/16W
MF-LF
2 402
CPUIMVP_ISUM2_P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2
CSPA2
BSTA2
DHA2
LXA2
DLA2
CRITICAL
CSPAAVE
69
CSNA
FBA
VDIO
CLK
ALERT*
CPUIMVP_IMAXA
CPUIMVP_IMAXB
1
NOSTUFF
NONE
NONE
NONE
2 402
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD
CPUIMVP_VR_ON
OMIT
R7466
OUT
91
CSPA3
VRHOT*
BSTB
DHB
LXB
DLB
CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G
CSPB1
CSNB
FBB
CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N
CPUIMVP_FBB
OUT
69
OUT
69
OUT
69
OUT
69
1%
1/16W
MF-LF
402
R7407
1
C7408
150PF
69
C7404
2200PF
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
SIGNAL_MODEL=EMPTY
1
C7405
2200PF
C7406
2200PF
5%
10V
2 CERM
0402
69
IN
50 69
300
CPUIMVP_ISNS3_P
IN
50 69
R7410
470PF
1
10%
50V
CERM
402
5%
1/16W
MF-LF
402
NO STUFF
R7409
40.2K2
1%
1/16W
MF-LF
68
402
CPUIMVP_ISUM3_P
69
SIGNAL_MODEL=EMPTY
68
OUT
69
OUT
69
C7407
0.001UF
R7461
NO STUFF
XW7400
SM
1%
1/16W
MF-LF
2 402
CPUIMVP_ISNS2_P
5%
1/16W
MF-LF
402
5%
10V
2 CERM
0402
SIGNAL_MODEL=EMPTY
OUT
C7409
SIGNAL_MODEL=EMPTY
50 69 100
R7408
CPUIMVP_ISUM_R
5%
50V
CERM
402
5%
2 10V
CERM
0402
68
IN
5%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
OUT
300
CPUIMVP_ISNS1_P
10%
2 50V
CERM
402
137K
5%
1/16W
MF-LF
402
90.9K2
1
CPUIMVP_TON
TON
300
R7402
THRM
PAD
R7468
92 12
91
CPUIMVP_ISUM3_P
CPU_PROCHOT_L
GNDSA
IN
OUT
CPUIMVP_PWM3
QFN
DRVPWMA
GNDSB
73
7 50 65 67 69 70
C7403
2.2UF
20%
2 10V
X5R-CERM
402
2.2UF
54.9
2.2UF
C7401 1
R74791
C7402
C7418
100PF
5%
50V
2 CERM
402
NO STUFF
C7419
100PF
5%
50V
2 CERM
402
NO STUFF
NO STUFF
C7414
100PF
5%
50V
2 CERM
402
C7415
100PF
5%
50V
2 CERM
402
NO STUFF
NO STUFF
1
C7416
100PF
SIGNAL_MODEL=EMPTY
C7417
100PF
5%
50V
2 CERM
402
5%
50V
2 CERM
402
GND_CPUIMVP_SGND
VOLTAGE=0V
PLACE_NEAR=Q7510.1:1mm
C7440
SIGNAL_MODEL=EMPTY
1000PF
5%
25V
2 NP0-C0G
402
SIGNAL_MODEL=EMPTY
R7440
CPU_AXG_SENSE_R
10
1000PF
5%
25V
2 NP0-C0G
402
12 92
R7412
68
CPUIMVP_FBA
12.7K2
R7441
CPU_VCCSENSE_R
OMIT
C7442
NOSTUFF
NONE
2 NONE
NONE
402
OMIT
C7443
10
5%
1/16W
MF-LF
402
CPU_VCCSENSE_N
IN
5%
25V
2 NP0-C0G
402
R7413 SIGNAL_MODEL=EMPTY
CPUIMVP_FBA_R
12 92
10
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
IN
5%
1/16W
MF-LF
402
C7441
C7412
1000PF
CPU_AXG_SENSE_N
CPU_VCCSENSE_P
IN
12 92
CPU_AXG_SENSE_P IN
12 92
5%
1/16W
MF-LF
402
C7422
SIGNAL_MODEL=EMPTY
1000PF
SIGNAL_MODEL=EMPTY
NOSTUFF
SIGNAL_MODEL=EMPTY
NONE
2 NONE
NONE
402
68
CPUIMVP_FBB
R7422
8.06K2
5%
25V
NP0-C0G 2
402
CPUIMVP_FBB_R
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
R7423
10
5%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
74 OF 132
SHEET
68 OF 105
8
70 69 68 67 65 50 7
THESE TWO CAPS ARE FOR EMC
CRITICAL
1
6
376S0872
PHASE 1
DIRECTFET-MA
68
IN
68
IN
CPUIMVP_UGATE1
68
IN
10%
10V
402
GATE_NODE=TRUE
SWITCH_NODE=TRUE
CPUIMVP_PH1_SNUB
CRITICAL
100
50
DIRECTFET-MX
10.2
1%
1/16W
MF-LF
376S0930
68
IN
68
IN
CPUIMVP_UGATE2
68
IN
2 402
68 69
NOSTUFF
68
C7571
0.22UF
10%
10V
402
2 6
SWITCH_NODE=TRUE
68 50
1
3
C7529
0.001UF
10%
50V
2 X7R
402
0.001UF
10%
50V
402
2 X7R
CPUIMVP_ISNS2_P
R7524
DIRECTFET-MX
2 50V
CERM
402
1%
1/16W
MF-LF
2 402
DIDT=TRUE
NOSTUFF
Q7525
10.2
1%
1/16W
MF-LF
402 2
CPUIMVP_PH2_SNUB
CPUIMVP_ISUM_N
C7522
68 69
NOSTUFF
1
C7572
330PF
10%
50V
402
2 CERM
376S0930
CPUIMVP_ISUM2_P
CPUIMVP_ISUM1_P
PP5V_S0
CRITICAL
Q7530
IRF6710
376S0772
PHASE 3
S1
D
CPUIMVP_BOOT3_RC
20%
2 16V
POLY-TANT
CASE-D2E-SM
10%
2 16V
X5R
402
R7547
10K
5%
1/16W
MF-LF
2 402
VDD
R7531
68
IN
TQFN
PWN
CRITICAL
DH 8
68 50
DIDT=TRUE
GATE_NODE=TRUE
2 6
CPUIMVP_LGATE3
10%
2 50V
X7R
402
C7539
0.001UF
10%
2 50V
X7R
PPVCORE_S0_CPU
6 7 12 14 49 69 105
10.2
1%
1/16W
MF-LF
2 402
CPUIMVP_ISUM_N
C7532
68 69
NOSTUFF
2 50V
CERM
402
C7573
330PF
10%
50V
402
2 CERM
CPUIMVP_ISUM3_P
CRITICAL
C7561
68UF
70 69 68 67 65 50 7
402
R7534
DIDT=TRUE
NOSTUFF
1
DIRECTFET-MX
376S0930
0.001UF
1%
1/16W
MF-LF
402 2
CPUIMVP_PH3_SNUB
S
3
C7538
CPUIMVP_ISNS3_N
50
IRF6798MTRPBF 0.001UF
10%
DIDT=TRUE
GATE_NODE=TRUE
2
4
46.4
Q7535
SWITCH_NODE=TRUE
1
3
R75331
CRITICAL
1%
1W
MF
0612
CPUIMVP_ISNS3_P
2.2
DIDT=TRUE
THRM
PAD
9
PIMA104E-SM
5%
1/10W
MF-LF
603 2
CPUIMVP_PHASE3
R7530
152S1019
R7532
DIDT=TRUE
DL 4
GND
NOSTUFF
10%
2 10V
CERM
402
1UF
0.00075
PPVCORE_S0_CPU_PH3_L
0.22UF
C7537
10UF
0.36UH-20%-40A-0.00075OHM
1
2 PPVCORE_S0_CPU_PH3
C7531
C7536
10%
10%
10%
16V
16V
2 16V
X5R-CERM 2 X5R-CERM 2 X5R
0805
0805
402
CRITICAL
CPUIMVP_UGATE3
LX 7
10UF
L7530
CPUIMVP_BOOT3
BST 1
SKIP*
5%
1/16W
MF-LF
402 2
MAX17491
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
SWITCH_NODE=TRUE
U7541
CPUIMVP_PWM3 2
CPUIMVP_SKIP 6
68UF
C7535
CRITICAL
1UF
C7534
CRITICAL
1
DIDT=TRUE
C7541
C7533
CRITICAL
1
68UF
104 87 73 70 68 65 54 52 47 41 22 8 7 6
105
68
68
CRITICAL
6 7 12 14 49
69 105
CPUIMVP_ISNS2_N
50
46.4
PPVCORE_S0_CPU
2
4
R75231
10%
2 50V
CERM
402
1%
1W
MF
0612
10%
DIDT=TRUE
GATE_NODE=TRUE
PIMA104E-SM
C7528
CRITICAL
152S1019
CRITICAL
D
DIDT=TRUE
0.00075
2.2
GATE_NODE=TRUE
1UF
R7520
CRITICAL
5%
1/10W
MF-LF
603 2
DIDT=TRUE
C7527
10UF
L7520
R75221
2 CERM
C7526
10%
10%
10%
16V
16V
2 16V
0805
0805
402
0.36UH-20%-40A-0.00075OHM
NOSTUFF
CPUIMVP_LGATE2
IN
330PF
DIRECTFET-MA
C7521
CPUIMVP_PHASE2
10UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
IRF6723M2DPBF
S
DIDT=TRUE
CPUIMVP_ISUM_N
C7512
2 50V
CERM
402
CPUIMVP_BOOT2
C7524
CRITICAL
1
C7525
PPVCORE_S0_CPU_PH2_L
1
R7521
CPUIMVP_ISNS1_N
CRITICAL
1
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
Q7510
5%
1/16W
MF-LF
402 2
R7514
1%
1/16W
MF-LF
402 2
C7523
DIDT=TRUE
PPVCORE_S0_CPU
CRITICAL
1
68UF
CRITICAL
12 14 49 69 105
6
7
DIDT=TRUE
NOSTUFF
1
1
3
10%
DIDT=TRUE
GATE_NODE=TRUE
2
4
46.4
6 7
376S0872
PHASE 2
10%
50V
2 X7R
402
R75131
Q7515
CPUIMVP_LGATE1
IN
D
DIDT=TRUE
0.001UF
10%
50V
2 X7R
402
CPUIMVP_BOOT2_RC
1%
1W
MF
0612
CPUIMVP_ISNS1_P
5%
1/10W
MF-LF
603 2
DIDT=TRUE
100 68 50
2.2
CPUIMVP_PHASE1
0.001UF
C7519
0.00075
152S1019
R75121
2 CERM
C7518
CRITICAL
PIMA104E-SM
NOSTUFF
DIDT=TRUE
68
C7511
1UF
R7510
L7510
0.22UF
5%
1/16W
MF-LF
402 2
C7517
10UF
PPVCORE_S0_CPU_PH1_L 1
R7511
CRITICAL
1
C7516
10%
10%
10%
16V
16V
2 16V
402
0805
0805
0.36UH-20%-40A-0.00075OHM
4
1
CPUIMVP_BOOT1
10UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
CRITICAL
DIDT=TRUE
C7514
C7515
IRF6723M2DPBF
CRITICAL
1
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
Q7510
CPUIMVP_BOOT1_RC
C7513
68UF
CRITICAL
CRITICAL
1
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
C7562
CRITICAL
1
68UF
C7563
68UF
20%
20%
2 16V
2 16V
POLY-TANT
POLY-TANT
CASE-D2E-SM
CASE-D2E-SM
CRITICAL
1
C7564
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
68
CRITICAL
1
C7565
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
C7566
CRITICAL
1
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
C7567
68UF
CRITICAL
1
C7568
68UF
20%
20%
2 16V
2 16V
POLY-TANT
POLY-TANT
CASE-D2E-SM
CASE-D2E-SM
CRITICAL
1
C7569
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
C7553
68UF
AXG PHASE
20%
2 16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
C7554
68UF
CRITICAL
1
C7555
10UF
CRITICAL
1
C7556
10UF
C7557
1UF
68
IN
CPUIMVP_BOOT1G
C7551
R7555
68
68
IN
IN
CPUIMVP_UGATE1G
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_PHASE1G
68
IN
5%
1/16W
MF-LF
402
SON5X6
CPUIMVP_UGATE1G_R
DIDT=TRUE
GATE_NODE=TRUE
Additonal Input Bulk Caps
0.001UF
10%
2 50V
X7R
402
5 BG
0.00075
L7550
0.36UH-20%-40A-0.00075OHM
1
2 PPVCORE_S0_AXG_L2
CPUIMVP_VSWG
PIMA104E-SM
4
152S1019
NOSTUFF
SWITCH_NODE=TRUE 1
100 50 CPUIMVP_ISNS1G_P
R7552
2.2
1
5%
1/10W
MF-LF
2 603
PGND
376S0906
R7553
46.4
1%
1/16W
MF-LF
402 2
CPUIMVP_AXG_SNUB
DIDT=TRUE
SWITCH_NODE=TRUE
NOSTUFF
1
PPVCORE_S0_AXG
1
3
7 12 13 15 49
CPUIMVP_ISNS1G_N
100 50
R7554
10.2
1%
1/16W
MF-LF
2 402
CPUIMVP_ISUMG_N
0.001UF
DIDT=TRUE
GATE_NODE=TRUE
1%
1W
MF
0612
DIDT=TRUE
C7552
10%
2 50V
CERM
402
CPUIMVP_LGATE1G
C7559
R7550
CRITICAL
VIN 1
VSW 6
7
8
4 TGR
10%
10V
CERM 2
402
DIDT=TRUE
4.7
0.22UF
3 TG
CPUIMVP_BOOT1G_R
DIDT=TRUE
5%
1/16W
MF-LF
402
CRITICAL
Q7550
CSD58864Q5D
C7558
10%
2 50V
X7R
402
CRITICAL
R7556
0.001UF
10%
10%
10%
20%
16V
16V
2 16V
2 16V
POLY-TANT
402
0805
0805
CASE-D2E-SM
68
NOSTUFF
1
CPU IMVP7 & AXG VCore Output
330PF
10%
DRAWING NUMBER
2 50V
CERM
Apple Inc.
402
CPUIMVP_ISUMG_P
SIZE
D
REVISION
R
68

PAGE TITLE
C7574
BRANCH
PAGE
75 OF 132
SHEET
69 OF 105
CPU VCCIO (1.05V S0) Regulator
69 68 67 65 50 7
104 87 73 69 68 65 54 52 47 41 22 8 7 6
105
PP5V_S0
CPUVCCIOS0_BOOT_RC
1
R76011
20%
2 10V
X5R
603
5%
1/10W
MF-LF
603 2
92 12
CPU_VCCIOSENSE_N
1%
1/16W
MF-LF
402 2
SIGNAL_MODE=EMPTY
R7644
73
<Ra>SIGNAL_MODE=EMPTY
73
CPUVCCIOS0_EN
IN
OUT
2.74K
1%
1/16W
MF-LF
402 2
R7645
2.74K
1%
1/16W
MF-LF
2 402
C7602 1
2.2UF
<Rb>
C7604
10%
16V 2
X5R
603
47PF
5%
50V
CERM 2
402
C7605
47PF
5%
2 50V
CERM
402
PHASE 10
CPUVCCIOS0_LL
VO
LGATE 15
CPUVCCIOS0_VO
CRITICAL
CPUVCCIOS0_OCSET
OCSET
CPUVCCIOS0_PGOOD
PGOOD
RJK0365DPA-01
WPAK
CRITICAL
0.001
L7630
0.68UH-22A-2.4MOHM
1
2
PPCPUVCCIO_S0_REG_R 1
SWITCH_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_DRVL
FSEL
R7603
R7640
CRITICAL
1 2 3
VOLTAGE=1.05V
PIMB104T-SM
GND
PGND
GATE_NODE=TRUE
DIDT=TRUE
1%
1W
MF-1
0612
PP1V05_S0
2
4
NO STUFF
CRITICAL
C7649
20%
2V
TANT
CASE-B4-SM
C7623 1
1000PF
RJK0208DPA
5%
25V
NP0-C0G 2
402
WPAK
0.047UF
C7648
R7641
XW7600
SM
1
Vout = 1.05V
21A Max Output
f = 300 kHz
270UF
1 2 3
C7603
CPUVCCIOS0_AGND
102 104
35 39 45
7 9 10 12
13 14 23
68 73
105
NO STUFF
CRITICAL
5%
1/16W
MF-LF
2 402
10%
2 16V
X7R
402
270UF
PLACE_NEAR=L7630.2:1.5mm
CRITICAL
Q7635
RTN
Q7630
5%
2 25V
NP0-C0G
402
PLACE_NEAR=Q7630.1:1.5mm
CPUVCCIOS0_DRVH
SREF
CPUVCCIOS0_SREF
BOOT 12
C7622
1000PF
68UF
CRITICAL
UGATE 11
FB
1UF
GATE_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_FB
CPUVCCIOS0_FSEL
UTQFN
EN
CPUVCCIOS0_RTN
R76051
C7630
10%
2 16V
X5R
402
C7621 1
20%
20%
16V 2
16V 2
POLY-TANT
POLY-TANT
CASE-D2E-SM
CASE-D2E-SM
DIDT=TRUE
ISL95870
1%
1/16W
MF-LF
2 402
R76301
CPUVCCIOS0_VBST
U7600
3.01K
16
3.01K
PVCC
R76041
2.2
VCC
CRITICAL
C7620 1
68UF
5%
1/10W
MF-LF
603 2
PP5V_S0_CPUVCCIOS0_VCC
VOLTAGE=5V
14
CPU_VCCIOSENSE_P
13
92 12
CRITICAL
DIDT=TRUE
10UF
2.2
C7601
100 49
CPUVCCIOS0_CS_P
100 49
CPUVCCIOS0_CS_N
20%
2V
TANT
CASE-B4-SM
3.01K
1%
1/16W
MF-LF
402 2
VOLTAGE=0V
C7640
1000PF
2
5%
25V
NP0-C0G
402
R7642
3.01K
1%
1/16W
MF-LF
2 402
(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640

OCP = 25.6A
Vout = 0.5V * (1 + Ra / Rb)
PAGE TITLE
CPU VCCIO (1.05V) Power Supply

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
76 OF 132
SHEET
70 OF 105
104 102 100 91 86 83

23 22 20 19 17 7 6
73 72 71 56 48 46 29 25 24
1.8V S0 Regulator
PP3V3_S5
22UF
5%
25V
NP0-C0G 2
402
20%
6.3V 2
CERM
805
CRITICAL
152S1302
VDD
1
VIN 2
C7720 1
1000PF
CRITICAL
C7724
L7720
1.0UH-7A
U7720
PIMB053T-SM
ISL8014A
73
73
IN
P1V8S0_EN
OUT
P1V8S0_PGOOD
QFN
5 EN
7 PG
P1V8S0_SW
LX 14
LX 15
CRITICAL
17 THRM_PAD
11
12 PGND
9
10 SGND
PP1V8_S0
2
CRITICAL
1
P1V8S0_FB
VFB 8
4 SYNCH
SWITCH_NODE=TRUE
DIDT=TRUE
16
6
NC
13
C7723
47PF
R7720
NC
NC
NC
113K
C7721
22UF
5%
50V
2 CERM
402
20%
6.3V
2 CERM
805
6 7 14 20 25 72 88 102
Vout = 1.794V
Max Current = 4A
Freq = 1 MHz
1%
1/16W
MF-LF
402 2
1.05V S5 LDO
<Ra>
Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in S5.

Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
CRITICAL
R77211
C7722 1
90.9K
CRITICAL
XDP_PCH
22UF
1%
1/16W
MF-LF
402 2
20%
6.3V
CERM 2
805
<Rb>
U7740
73 72 46 22 20 19 18 17 16 7
TPS720105
SON
PP3V3_SUS
PP1V05_SUS
4 BIAS
Vout = 0.8V * (1 + Ra / Rb)
3 EN
NC 2
XDP_PCH
C7740 1
THRM
PAD
7
GND
5
1UF
10%
6.3V 2
CERM
402
7 23
Vout = 1.05V
Max Current = 0.35A
OUT 1
6 IN
NC
XDP_PCH
1
C7741
2.2UF
10%
2 6.3V
X5R
402
1.5V S0 Regulator
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
PP3V3_S5
CRITICAL
1
C7750
22UF
VIN
U7710
ISL8009B
20%
6.3V
CERM
805
CRITICAL
L7770
2.2UH-3.25A
DFN
73
73
IN
P1V5S0_EN
OUT
P1V5S0_PGOOD
EN
CRITICAL
LX
POR
VFB
SKIP
RSI
GND
7
1V5_S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
PP1V5_S0
Vout = 1.508V
IHLP1616BZ-SM
1
C7776
5%
50V
CERM
402
THRM_PAD
9
Max Current = 0.8A
R7780
100K
47PF
353S2535
7 16 20 22 25 32 41 57
2
2
Freq = 1.6MHZ
1%
1/16W
MF-LF
402
CRITICAL
<Ra>
1V5_S0_FB
C7771
22UF
R7781
20%
6.3V
CERM
805
CAESAR IV 1.2V INT.VR CMPTS
113K
CRITICAL
1%
1/16W
MF-LF
402
L7730
4.7UH-0.8A
<Rb>
73 36 25 7
PP3V3_ENET
ENET_SR_LX
1
2
PCAA031B-SM
Vout = 0.8V * (1 + Ra / Rb)

1
C7737
4.7UF
20%
2 6.3V
X5R
402
C7738
0.1UF
10%
2 16V
X5R
402
PP1V2_ENET
PP1V2_ENET
104 102 100 91 86 83

24 23 22 20 19 17 7 6
73 72 71 56 48 46 29 25
1.2V S0 (GMUX) Regulator
PP3V3_S5
C7760
10UF
20%
C7764
2 4V
X5R
402
16V
X5R
402
R7760
CRITICAL
152S0771
CRITICAL
U7760
2.2UH-1.2A
SC194A
PCAA031B-SM
1 NO STUFF
5%
1/16W
MF-LF
402
73
IN
4 EN
P1V2S0_EN
P1V2S0_SYNC_PWM
R7761
LX 10
353S2719
VOUT 5
P1V2S0_SW
PP1V2_S0
SWITCH_NODE=TRUE
DIDT=TRUE
3 SYNC/PWM
CRITICAL
XW7761
SM
P1V2S0_FB
7 VID1
C7736
0.1UF
10%
2 16V
X5R
402
PLACE_NEAR=L7760.2:1MM
2 MODE
PAGE TITLE
Misc Power Supplies

DRAWING NUMBER
20%
6.3V
CERM
805
Apple Inc.
THRM
PAD

SIZE
D
REVISION
11
PGND
GND
C7761
6 7 88
Vout = 1.2V
MAX CURRENT = 0.7A
FREQ = 1MHZ
22UF
2
2
5%
1/16W
MF-LF
402
7 36 71
L7760
6 VID0
1
7 36 71
MLP10
1 VIN
C7735
10UF
20%
0.1UF
10%
4V
X5R
402
CRITICAL
CRITICAL
1
36
VOLTAGE=1.2V
SWITCH_NODE=TRUE
DIDT=TRUE
BRANCH
PAGE
77 OF 132
SHEET
71 OF 105
2
3.3V_SUS FET
CRITICAL
Q7820
R7803
0
3.3V Standby(S4) FET
SIA427DJ
PP3V3_S5
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
SC70-6L
5%
1/16W
MF-LF
402
PP3V3_SUS
7 16 17 18 19 20 22 46 71 73
CRITICAL
NO STUFF
C7800
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
5 mA ?(EDP)
73 72
IN
PM_SUS_EN
3.3V S3 FET
SSM6N15FEAPE
SOT563
2 G
73
IN
10%
16V
X5R
402
PP5V_S5_P5VSUSFET_R
Q7842
SSM3K15FV
P3V3S3_EN_L
S 1
0.01UF
P3V3S3_SS
5%
1/16W
MF-LF
402
C7810
47K
D 3
73 72
IN
5%
1/16W
MF-LF
402
10%
16V
X5R
402
2
P5VSUS_EN_L
S 2
10%
16V
CERM
402
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
3 A (EDP)
3.3K
C7840
0.01UF
P5VSUS_SS
5%
1/16W
MF-LF
402
10%
16V
CERM
402
3.3V S0 FET
5%
1/16W
MF-LF
402
X5R
IN
PM_SLP_S3_R_L
6
8
SC70-6L
PP1V5_S3RS0
1 2 3
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
7 100 104
PP3V3_S5
91
MOSFET
SI7108DN
CHANNEL
N-TYPE
1UF
10%
10V
X5R
402
Q7872
6 mOhm @4.5V
LOADING
5 A (EDP)
SSM3K15FV
PP3V3_S0
91 88
D 3
13
P1V8GPU_EN
PP3V3_S0
20%
10V
CERM
402
R_BLEED
EN
EN_POL_CTRL
GPUFET_C_SR
DRAIN
16
17
C_DELAY
NO STUFF
NC
1 G
GND
0.11A (EDP)
S 2
4
5
9
10
11
12
PWRPK-1212-8
7 104
PP5V_S0_ISNS_R
D
104 82 67 46 44 43 42 31 29 7 6
PP5V_S3
5.0V S0 FET
18 mOhm @4.5V
LOADING
R7862
2.4A (EDP)
C7861
220K
5%
1/16W
MF-LF
402
PP1V8_S0
input side
R7860
10K
P5V0S0_EN_L
R7843
THRM
PAD
104 103 72 66 54 7
PP5V_S5
P-TYPE
RDS(ON)
5.5 MOHM @4.5V
LOADING
8 A (EDP)
C7860
0.01UF
P5V0S0_SS
10%
16V
CERM
402
SYNC_MASTER=K91_MLB
Power FETs
72
73 72 49
IN
DRAWING NUMBER
PM_SLP_S3_R_L
Apple Inc.
SIZE
D
REVISION

U7880 default Turn on delay EN--> on is 200~650us.
PAGE TITLE
2.2UF
20%
10V
X5R-CERM
402
20V/12V
NO STUFF
SI7615DN
CHANNEL
VOLTAGE=5.0V
1
C7843
10%
16V
X5R
402
MOSFET
SOD-VESM-HF
PP5V_S5_P5VSUSFET_R
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
Q7865
SSM3K15FV
0.033UF
6 7 14 20 25 71 88 102
14
18
PP1V8_S0GPU_ISNS_R
Q7860
SI7615DN
5.0V S0 FET
3
N-TYPE
103
6 7 72
NO STUFF
LOADING
CRITICAL
5V_SUS FET input filter
1000PF
5%
25V
NP0-C0G
402
CHANNEL
C_SR
C7882
NCP4543
19
0.1UF
SOURCE
CRITICAL
15
GPUFET_C_DELAY
1
6
7
8
MOSFET
RDS(ON)
QFN
C7881
26 mOhm @1.8V
10%
16V
CERM
402
VCC
PP1V8_S0GPU_ISNS_R
load side
IN
1.8V GPU FET
353S3093
U7880
91
0.01UF
P3V3GPU_SS
P-TYPE 8V/5V
RDS(ON)
P3V3GPU_EN
NCP4543IMN5RG-A
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
IN
1K
SiA427
CHANNEL
0.1UF
103 72 7 6
6 7 75 79 80 82 84
MOSFET
C7870
5%
1/16W
MF-LF
402
SOD-VESM-HF
1.8V GPU FET
R7870
P3V3GPU_EN_L
RDS(ON)
5%
1/16W
MF-LF
402
1.5V S3/S0 FET

TP_P1V5S3RS0_RAMP_DONEOUT
20%
10V
CERM
402
PP3V3_S0GPU
3.3V S0 GPU FET

C7871
R7872 1
51K
PLACE_NEAR=U7880.2:2.54mm
SIA427DJ
THRM
PAD
GND
C7880
Q7870
PWRPK-1212-8-HF
5%
1/16W
MF-LF
402
5.6 A (EDP)
CRITICAL
3.3V S0 GPU FET
SI7108DN
P1V5S3RS0FET_GATE_R
PG
402
Q7801
7 P1V5S3RS0FET_GATE1
5.5 mOhm @4.5V
LOADING
1UF
P-TYPE 20V/12V
RDS(ON)
10%
16V
CERM
402
SHDN*
R7801
0
SI7615DN
CHANNEL
CRITICAL
D 5
P3V3S0_SS
5%
1/16W
MF-LF
402
TDFN
CRITICAL
C7802 1
102 100 91 89 88 85 84 83
46 41 40 39 36 35 32 28 26 25 23 12 7 6
80 73 72 62 61 57 54 52 51 50 49 48
0.01UF
MOSFET
C7830
R7830
U7801
ON
3.3V S0 FET
402
APN 376S0651
NO STUFF
X5R
10%
16V
VCC
10%
10V
47K
33K
C
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
PP3V3_S0
IN
C7831
P3V3S0_EN_L
5
73 72 49
P1V5CPU_EN
2 mA (EDP)
Q7830
0.033UF
SLG5AP020
29
29 mOhm @4.5V
LOADING
SOT563
P-TYPE 12V
RDS(ON)
Q7812
SSM6N15FEAPE
20%
10V
CERM
402
SiA413
CHANNEL
CRITICAL
PP3V3_S5
R7832 1
PP1V5_S3
0.1UF
MOSFET
SI7615DN
PP5V_S5
C7801
7 22
PWRPK-1212-8
1.5V S3/S0 FET

67 29 28 26 7
PP5V_SUS
5V SUS FET
R7840
1
PM_SUS_EN
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
104 103 72 66 54 7
100? mA (EDP)
0.033UF
220K
7 104
3.3V S3 FET
R7810
P3V3S3_EN
PP3V3_S3_ISNS_R
C7841
R7842 1
SOD-VESM-HF
26 mOhm @1.8V
LOADING
SC70-6L
C7811
4 7
5%
1/16W
MF-LF
402
RDS(ON)
CRITICAL
CRITICAL
0.033UF
100K
P-TYPE 8V/5V
SIA413DJ
72
R7812
D 6
SiA427
CHANNEL
Q7840
SC70-6L
Q7812
5V_SUS FET
SIA427DJ
10%
16V
CERM
402
Q7810
PP3V3_S5
0.01UF
P3V3SUS_SS
5%
1/16W
MF-LF
402
0.01UF
P3V3S3_S4
10%
16V
CERM
402
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
S 4
12K
5%
1/16W
MF-LF
402
CHANNEL
5 G
C7820
R7820
P3V3SUS_EN_L
5.1K
P3V3S4_EN_L
SiA427
3.3V SUS FET

MOSFET
MOSFET
4 7
IN
R7800
P3V3_S4_EN
10%
16V
X5R
402
NO STUFF
5%
1/16W
MF-LF
402
SOT563
SOT563
10%
16V
X5R
402
0.033UF
100K
SSM6N15FEAPE
5%
1/16W
MF-LF
402
0.033UF
220K
SSM6N15FEAPE
73
C7809
R7802 1
6
6 7 46 53 54
3.3V Standby FET
376S0945
Q7802
D 3
Q7802
PP3V3_S4
SC70-6L
NO STUFF
SIA427DJ
NO STUFF
C7821
R7822 1
PP3V3_S5
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
Q7800 NO STUFF
BRANCH
PAGE
78 OF 132
SHEET
72 OF 105
State
S5 Rail Enables & PGOOD
SMC_PM_G2_ENABLE
Sleep (S3)
Deep Sleep (S4)
73 66 45
OUT
73 66 45
IN
R7940
SMC_PM_G2_EN
SMC_PM_G2_EN
MAKE_BASE=TRUE
100
Deep Sleep (S5)
73 66
P3V3S5_EN
P3V3S5_EN
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
Battery Off (G3Hot)
66 73
PM_SLP_S5_L
Run (S0)
PM_SLP_S4_L
PM_SLP_S3_L
3.3V,5V S3 ENABLE
73 66 45 42 29 17
IN
(PM_SLP_S4_L)
PM_SLP_S4_L
PM_SLP_S4_L OUT
MAKE_BASE=TRUE
R7911
PM_SLP_S4_L:100K pull down in PCH page
5.1K
1
R7913
3.3K
R7912
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PLACE_NEAR=U7300.16:6mm 1
5%
1/16W
MF-LF
402
TPAD_VBUS_EN
73 72
P3V3S3_EN
P3V3S3_EN
OUT
72
73
DDRREG_EN
OUT
67
73
MAKE_BASE=TRUE
73 67
0.0033UF
10%
2 50V
CERM
402
PP3V42_G3H
48 47 46 45 44 42 25 7 6
104 73 64 63 53
C7910
NO STUFF
3.3V/5.0V S4 ENABLE
R7941
DDRREG_EN
MAKE_BASE=TRUE
NO STUFF
1
C7912
0.47UF
1
53
OUT
C7942
66 73
17 29
42 45
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
100K
5%
1/16W
MF-LF
402 2
NO STUFF
R7916
S5_PWRGD (old name RSMRST_PWRGD)-->SMC
SMC-->PM_DSW_PWRGD
OUT
MAKE_BASE=TRUE
45 17
45 66
73
PM_SLP_S5_L
IN
73
2 72 P3V3_S4_EN
5%
1/16W
MF-LF
402
P3V3_S4_EN
OUT
72 73
MAKE_BASE=TRUE
S0 ENABLE
PLACE_NEAR=U1800.G18:5mm
R7978
PM_SLP_S5_L:100K pull down on PCH page

PM_SLP_S3_L
73 45 29 17 6
IN
PP3V3_S5
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
PM_SLP_S3_L:100K pull down in PCH page
NO STUFF
5%
1/16W
MF-LF
402
CPUIMVP_VR_ON
68
OUT
20%
10V
CERM 2
402
5%
1/16W
MF-LF
402
73 70
CPUVCCIOS0_PGOOD
PM_PECI_PWRGD
45
OUT
53
6445
4742
7 6
4625
6344
48
73
104
73 72
PM_SUS_EN
PM_SUS_EN
PM_SUS_EN
72 73
R7931
73 70
72 73
5%
1/16W
MF-LF
402
73 65
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
ALL_SYS_PWRGD
23 45 73 88 91
VMON_Q2_BASE
5%
1/16W
MF-LF
402
R7952
7.15K
Q1
R7954
PP1V5_S3RS0_CPUDDR 1
1K
5%
1/16W
MF-LF
402
PP1V5_S3RS0
Q2
NC
5%
1/16W
MF-LF
402
72 71 46 22 20 19 18 17 16 7
73
353S2809
S0PGD_BJT_GND_R
100
10K
1%
1/16W
MF-LF
402 2
R7972
6.04K
1%
1/16W
MF-LF
402 2
VMON_PP5V_DIV
100
ISL88042IRTEZ
TDFN
3 V2MON
(IPU)
MR*
CRITICAL
100
P5VS3_PGOOD
SOT23-6
MR* 3
PM_RSMRST_L
IN
NC
OUT
Q7922
100
PP3V3_ENET 7
54 50 49 48 32 31 30 29 25 24 18 8 7 6
104 88 55
PP3V3_S3
R79211
C7921
5%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
R7922
1
C7922
0.01UF
100K 2
P3V3ENET_SS
10%
16V
CERM
402
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up
on open-drain AP_PWR_EN signal.
Q7921
SSM3K15FV
25 36 71
0.033UF
10K
D 3
SOD-VESM-HF
PM_WLAN_EN_L
R7966
1
100
73 45 29 17 6
IN
PM_SLP_S3_L
100
SMC_S4_WAKESRC_EN
MAKE_BASE=TRUE
SMC_S4_WAKESRC_ENOUT
Q7925
45 46 73 86
S 2
IN
WOL_EN
SOT-363
5
Q7925
S
G
31
OUT
2N7002DW-X-G
2N7002DW-X-G
SOT-363
2
AP_PWR_EN
IN
18 31
S
1
4
2N7002DW-X-G
6
SOT-363
46 45 17
OUT
23 45 73 88 91
IN
SMC_ADAPTER_EN
S
1
SYNC_MASTER=K92_YUAN
PAGE TITLE
NO STUFF
R79291
5%
1/16W
MF-LF
402
(AC_EN_L)
AC_EN_L
Q7920
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
Power Control 1/ENABLE
Q7920
2N7002DW-X-G
DRAWING NUMBER
SOT-363
5
(PM_SLP_S3_L)
Apple Inc.
SIZE
D
REVISION

3
86 73 46 45
R7964
1
SOT-23-HF
PM_RSMRST_L goes to U1800.C21
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
NTR4101P
R7962
0.47UF
10%
6.3V
CERM-X5R
402
17
5%
1/16W
MF-LF
402 2
5 V3MON
VMON_PP1V5_DIV
S0PGOOD_ISL
R79611S0PGOOD_ISL
VMON_PP1V05_DIV 6 V4MON
RST* 8
S0PGOOD_ISL
1
15.0K
R7971
1%
S0PGOOD_ISL
GND THRM_PAD
10K
1/16W
R79731
330 2
MF-LF
1%
1
ALL_SYS_PWRGD
15.0K
402 2
1/16W
353S2310
1%
MF-LF
ALL_SYS_PWRGD_R
5%
402
1/16W
2
MF-LF
402
0.47UF
2
3.3V ENET FET
19
IN
PVCCSA_PGOOD
C7931
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R7963
65
C7986
5%
1/16W
MF-LF
402
IN
VDD
U7960
C7988
5%
1/16W
MF-LF
402
R7968
1
CPUVCCIOS0_PGOOD
7
1/16W
MF-LF
402 2
10%
6.3V
2 CERM-X5R
402
10%
6.3V
CERM-X5R
402
PM_SLP_S3_ENET
R7965
73 70
C7985
1UF
0.47UF
10%
6.3V
CERM-X5R
402
CRITICAL
RESET* 1
10K
PP3V3_S0
C7981
ENET Enable Generation
R79671
P1V5S0_PGOOD
IN
PP3V3_S0
P1V8S0_PGOOD
66
C7987
65 73
S 2
5%
1/16W
MF-LF
402 2
NO STUFF
P1V5S0_PGOOD from U7710
PP5V_S0
S0PGOOD_ISL S0PGOOD_ISL
PP1V5_S3RS0_CPUDDR
C7960 1
PP1V05_S0
S0PGOOD_ISL
1
0.1uF
R7960 S0PGOOD_ISL
20%
10V
1
6.04K
R7970 S0PGOOD_ISL
CERM 2
1%
402
1
5%
1/16W
MF-LF
402 2
Version in development)
71
100K
0.001UF
R79571
IN
OUT
7 16 17 18 19 20 22 46 71 72 73
20%
2 50V
CERM
402
Worst-Case Thresholds:
71
70 73
R79331
GND
S0 Rail PGOOD Circuitry
102 100 91 89 88 85 84
104
46 41 40 39 36 35 32 28 26 25 23 12 7 6
68
83 80 73 72 62 61 57 54 52 51 50 49 48
47
6
22
54
7029 15 13 10 7
104 73
U7930
Sus_PGOOD_CT 4 CT
VMON_Q4_BASE
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
105
69
52
8 7
41
65
87
20%
10V
CERM 2
402
TPS3808G33DBVRG4
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
Thresholds:
(ISL
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
5 SENSE
PP3V3_SUS
PP1V05_S0
1K
PP3V3_SUS
VDD
R7955
1
0.1uF
CRITICAL
Q4
CPUVCCIOS0_EN OUT
C7930
CRITICAL
71 73
VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency
1
No stuff C7931, 12ms

Min delay time
U7930 Sense input
threhold is 3.07V
ASMCC0179
Q3
71 73
OUT
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
DFN2015H4-8
NC
VMON_Q3_BASE
OUT
P1V2S0_EN
71 73
PP3V3_S5
Q7950
5
1%
1/16W
MF-LF
2 402
P1V5S0_EN
PVCCSA_EN
0.47UF
D 3
R7953
1K
PVCCSA_EN
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
64
SOD-VESM-HF
3.3V SUS Detect
S0PGD_C
VMON_3V3_DIV 1
OUT
5%
1/16W
MF-LF
402
15.0K
P1V8S0_EN
MAKE_BASE=TRUE
SSM3K15FV
CPUVCCIOS0_EN
MAKE_BASE=TRUE
100K
Q7931
R7951
45 39 35 23 14 13 12 10 9 7
105 104 102 73 70 68
150K
104 73 29 15 13 10 7
S0 Rail PGOOD (BJT Version)
R7956
49 72 73
MAKE_BASE=TRUE
R7917
1
P1V5S0_EN
73 71
MAKE_BASE=TRUE
GND
PP3V3_S5
P1V8S0_EN
P1V2S0_EN
73 71
CHGR_VFRQ OUT
PP3V3_S0
OUT
PP3V42_G3H
MAKE_BASE=TRUE
NO STUFF
102 100 91 89
104
80 73 72 6271 56 48 46 29 25 24 23 22 20 19 17 7 6
51 50 49 48
102 100 91 86 83 73 72
36 35 32 28
7 6
26 25 23 12
46 41 40 39
61 57 54 52
88 85 84 83
49 72 73
PM_SLP_S3_R_L
5%
1/16W
MF-LF
402
73
71
5%
1/16W
MF-LF
402
49 72 73
OUT
MAKE_BASE=TRUE
Y 4
PM_SLP_SUS_L:100K pull down on PCH page

PM_SLP_SUS_L
17
IN
R7975
5.1K
5%
1/16W
MF-LF
402
OUT
PM_SLP_S3_R_L
CHGR VFRQ Generation
PM_SLP_S3_R_L
R7986
10K
5%
1/16W
MF-LF
402
U7940
74AUP1G3208
SOT891
1 A
SMC_BATLOW_L:100K pull up on SMC page

SMC_BATLOW_L
46 45
IN
R7976
5%
1/16W
MF-LF
402
R7988
20K
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
VCC
R7985
20K
5%
1/16W
MF-LF
402
ALL_SYS_PWRGD
R7981
33K
0.1uF
91 88 73 45 23
R7987
C7940
PM_SLP_S3_R_L
MAKE_BASE=TRUE
1
R7974
73 72 49
5%
1/16W
MF-LF
402
3.3V/5.0V Sus ENABLE

CPUVCORE ENABLE
(PM_SLP_S3_R_L)
100 2
S5_PWRGD
S5_PWRGD
73 66 45
BRANCH
PAGE
79 OF 132
SHEET
73 OF 105
Page Notes
- =PP1V2_GPU_PEX_PLLXVDD
- =PP1V2_GPU_PEX_IOVDDQ
- =PP1V2_GPU_PEX_IOVDD
(NONE)
(NONE)
D
92 8
92 8
92 8
92 8
92 8
92 8
92 8
92 8
92 8
92 8
IN
PEG_R2D_C_P<0>
C8020
0.1UF
PEG_R2D_C_N<0>
C8021
0.1UF
PEG_R2D_C_P<1>
0.1UF
IN
C8022
C8023
0.1UF
IN
PEG_R2D_C_N<1>
IN
PEG_R2D_C_P<2>
IN
IN
IN
IN
PEG_R2D_C_N<2>
C8024
C8025
0.1UF
0.1UF
PEG_R2D_C_P<3>
C8026
0.1UF
PEG_R2D_C_N<3>
C8027
0.1UF
1
1
1
1
1
1
IN
PEG_R2D_C_P<4>
C8028
0.1UF
C8029
0.1UF
IN
PEG_R2D_C_N<4>
PEG_R2D_C_P<5>
C8030
0.1UF
IN
92 8
IN
PEG_R2D_C_N<5>
C8031
0.1UF
IN
PEG_R2D_C_P<6>
C8032
0.1UF
92 8
IN
PEG_R2D_C_N<6>
C8033
0.1UF
IN
PEG_R2D_C_P<7>
C8034
0.1UF
92 8
IN
PEG_R2D_C_N<7>
C8035
0.1UF
92 8
92 8
1
1
1
1
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<0>
PEG_R2D_N<0>
74 92
74 92
92 74
92 74
PEG_D2R_C_P<0>
C8055
PEG_D2R_C_N<0>
C8056
0.1UF
0.1UF
0.1UF
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<1>
74 92
92 74
PEG_D2R_C_P<1>
C8057
PEG_R2D_N<1>
74 92
92 74
PEG_D2R_C_N<1>
C8058
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<2>
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<3>
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_N<2>
PEG_R2D_N<3>
PEG_R2D_P<4>
PEG_R2D_N<4>
74 92
74 92
74 92
74 92
74 92
74 92
92 74
92 74
92 74
92 74
0.1UF
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
C8059
C8060
0.1UF
0.1UF
PEG_D2R_C_P<3>
C8061
0.1UF
PEG_D2R_C_N<3>
C8062
0.1UF
1
1
1
1
PEG_D2R_C_P<4>
C8063
C8064
0.1UF
92 74
PEG_D2R_C_N<4>
PEG_D2R_C_P<5>
C8065
0.1UF
PEG_R2D_N<5>
74 92
92 74
PEG_D2R_C_N<5>
C8066
0.1UF
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<6>
92 74
PEG_D2R_C_P<6>
C8067
0.1UF
74 92
PEG_R2D_N<6>
74 92
92 74
PEG_D2R_C_N<6>
C8068
0.1UF
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_R2D_P<7>
92 74
PEG_D2R_C_P<7>
C8069
0.1UF
74 92
PEG_R2D_N<7>
92 74
PEG_D2R_C_N<7>
C8070
0.1UF
74 92
92 74
PEG_D2R_P<0>
PEG_D2R_N<0>
92 74
OUT
OUT
8 92
92 74
92 74
8 92
92 74
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<1>
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<2>
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<3>
OUT
8 92
OUT
8 92
92 74
92 74
PEG_D2R_N<1>
92 74
PEG_D2R_N<2>
OUT
8 92
92 74
92 74
OUT
92 74
92 74
OUT
OUT
1
1
1
1
92 74
8 92
IN
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
(1 OF 9)
PCIE
PCIE_TX1P W33
PCIE_TX1N W32
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
PCIE_TX2P U33
PCIE_TX2N U32
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
PCIE_TX3P U30
PCIE_TX3N U29
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
PCIE_TX4P T33
PCIE_TX4N T32
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
PEG_R2D_P<5>
PEG_R2D_N<5>
T35 PCIE_RX5P
R36 PCIE_RX5N
PCIE_TX5P T30
PCIE_TX5N T29
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_R2D_P<6>
PEG_R2D_N<6>
R38 PCIE_RX6P
P37 PCIE_RX6N
PCIE_TX6P P33
PCIE_TX6N P32
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_R2D_P<7>
PEG_R2D_N<7>
P35 PCIE_RX7P
N36 PCIE_RX7N
PCIE_TX7P P30
PCIE_TX7N P29
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
N38 PCIE_RX8P
M37 PCIE_RX8N
PCIE_TX8P N33
PCIE_TX8N N32
NC
NC
PCIE_TX9P N30
PCIE_TX9N N29
NC
NC
PEG_R2D_P<1>
PEG_R2D_N<1>
Y35 PCIE_RX1P
W36 PCIE_RX1N
PEG_R2D_P<2>
PEG_R2D_N<2>
W38 PCIE_RX2P
V37 PCIE_RX2N
PEG_R2D_P<3>
PEG_R2D_N<3>
V35 PCIE_RX3P
U36 PCIE_RX3N
PEG_R2D_P<4>
PEG_R2D_N<4>
U38 PCIE_RX4P
T37 PCIE_RX4N
U8000
OMIT
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<4>
PEG_D2R_N<4>
OUT
8 92
NC
NC
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<5>
OUT
8 92
NC
NC
M35 PCIE_RX9P
L36 PCIE_RX9N
PEG_D2R_N<5>
OUT
8 92
NC
NC
L38 PCIE_RX10P
K37 PCIE_RX10N
PCIE_TX10P L33
PCIE_TX10N L32
NC
NC
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<6>
OUT
8 92
K35 PCIE_RX11P
J36 PCIE_RX11N
PCIE_TX11P L30
PCIE_TX11N L29
PEG_D2R_N<6>
NC
NC
NC
NC
OUT
8 92
PCIE_TX12P K33
PCIE_TX12N K32
2
10%6.3VX5R 201
2
10%6.3VX5R 201
PEG_D2R_P<7>
NC
NC
J38 PCIE_RX12P
H37 PCIE_RX12N
NC
NC
OUT
8 92
PEG_D2R_N<7>
PCIE_TX13P J33
PCIE_TX13N J32
8 92
NC
NC
H35 PCIE_RX13P
G36 PCIE_RX13N
OUT
NC
NC
NC
NC
G38 PCIE_RX14P
F37 PCIE_RX14N
PCIE_TX14P K30
PCIE_TX14N K29
NC
NC
NC
NC
F35 PCIE_RX15P
E37 PCIE_RX15N
PCIE_TX15P H33
PCIE_TX15N H32
NC
NC
OUT
8 92
92 74
95 16
IN
95 16
IN
NOSTUFF
91 88 87 82 8
PCIE_TX0P Y33
PCIE_TX0N Y32
AA38 PCIE_RX0P
Y37 PCIE_RX0N
PM_ALL_GPU_PGOOD
R8003
0
5%
1/16W
MF-LF
402
2
88 8
IN
EG_RESET_L
74 92
74 92
74 92
74 92
74 92
74 92
74 92
74 92
74 92
74 92
74 92
R8000
PEG_CLK100M_P
PEG_CLK100M_N
AB35 PCIE_REFCLKP
AA36 PCIE_REFCLKN
GPU_PWRGOOD
AH16 PWRGOOD
GPU_RESET_R_L
PCIE_CALRP Y30
PCIE_CALRN Y29
R8004
74 92
74 92
74 92
74 92
PEG_CALRP
PEG_CALRN
AA30 PERST*
R80011
R8002
2.0K
5%
1/16W
MF-LF
402
10K
1.27K
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
74 92
8 92
92 74
PEG_D2R_N<3>
FCBGA
PEG_R2D_P<0>
PEG_R2D_N<0>
8 92
92 74
92 74
PEG_R2D_P<5>
2
10%6.3VX5R 201
2
10%6.3VX5R 201
92 74
0.1UF
2
10%6.3VX5R 201
2
10%6.3VX5R 201
74 92
WHISTLER
40NM-ES
92 8
103 81 79 75 7
1%
1/16W
MF-LF
2 402
PP1V0_S0GPU
SYNC_MASTER=K91_MLB
PAGE TITLE
Whistler PCI-E
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
80 OF 132
SHEET
74 OF 105
1
Page Notes
CRITICAL
L8150
120OHM-0.3A
C8100
10UF
20%
2 10V
X5R
603
C8101
10UF
C8102
10UF
20%
2 10V
X5R
603
C8103
10UF
20%
2 10V
X5R
603
20%
2 10V
X5R
603
103 81 79 75 7 6
C8104
10UF
20%
2 10V
X5R
603
D
1
C8105
1UF
10%
2 25V
X5R
402
C8115
0.1UF
10%
6.3V
2 X5R
201
C8106
1UF
10%
2 25V
X5R
402
C8107
0.1UF
10%
6.3V
2 X5R
201
C8108
C8117
0.1UF
10%
6.3V
2 X5R
201
1UF
10%
2 25V
X5R
402
10%
2 25V
X5R
402
C8116
1UF
C8109
10%
2 25V
X5R
402
C8118
0.1UF
10%
6.3V
2 X5R
201
1UF
C8110
10%
2 25V
X5R
402
C8119
0.1UF
10%
6.3V
2 X5R
201
1UF
C8120
0.1UF
10%
6.3V
2 X5R
201
C8111
1UF
10%
2 25V
X5R
402
C8112
0.1UF
10%
6.3V
2 X5R
201
C8113
C8122
0.1UF
10%
6.3V
2 X5R
201
1UF
10%
2 25V
X5R
402
10%
2 25V
X5R
402
C8121
1UF
C8123
0.1UF
10%
6.3V
2 X5R
201
C8114
1UF
10%
2 25V
X5R
402
C8124
0.1UF
10%
6.3V
2 X5R
201
L8120
120OHM-0.3A
103 81 79 75 7 6
PP1V8_S0GPU
PP1V8_GPU_VDD_CT
CRITICAL
C8125
10UF
C8126
1UF
10%
25V
2 X5R
402
20%
10V
2 X5R
603
219mA
VOLTAGE=1.8V
0402
C8127
1UF
10%
25V
2 X5R
402
C8128
1UF
10%
25V
2 X5R
402
C8129
0.1UF
10%
6.3V
2 X5R
201
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K8
K11
K13
L7
L12
L16
L21
L23
L26
M11
N11
P7
R11
U7
U11
Y7
Y11
VDDR1_AC7
VDDR1_AD11
VDDR1_AF7
VDDR1_AG10
VDDR1_AJ7
VDDR1_AK8
VDDR1_AL9
VDDR1_G11
VDDR1_G14
VDDR1_G17
VDDR1_G20
VDDR1_G23
VDDR1_G26
VDDR1_G29
VDDR1_H10
VDDR1_J7
VDDR1_J9
VDDR1_K8
VDDR1_K11
VDDR1_K13
VDDR1_L7
VDDR1_L12
VDDR1_L16
VDDR1_L21
VDDR1_L23
VDDR1_L26
VDDR1_M11
VDDR1_N11
VDDR1_P7
VDDR1_R11
VDDR1_U7
VDDR1_U11
VDDR1_Y7
VDDR1_Y11
AF26
AF27
AG26
AG27
VDD_CT_AF26
VDD_CT_AF27
VDD_CT_AG26
VDD_CT_AG27
10UF
1UF
20%
10V
2 X5R
603
75
C8131
C8132
84 82 80 79 72 7 6
PP3V3_S0GPU
0.1UF
10%
25V
2 X5R
402
60 mA
10%
6.3V
2 X5R
201
AF23
AF24
AG23
AG24
VDDR3_AF23
VDDR3_AF24
VDDR3_AG23
VDDR3_AG24
GND_GPU_PLL
C8133
10UF
20%
2 10V
X5R
603
C8134
1UF
10%
2 25V
X5R
402
C8135
1UF
10%
2 25V
X5R
402
C8136
1UF
10%
2 25V
X5R
402
AF13
AF15
AG13
AG15
VDDR4_AF13
VDDR4_AF15
VDDR4_AG13
VDDR4_AG15
CRITICAL
L8131
470OHM-1A-150MOHM
103 81 79 75 7 6
PP1V8_S0GPU
PP1V8_GPU_MEM_PLL
VOLTAGE=1.8V
0603
1
C8137
10UF
20%
2 10V
X5R
603
75
PP1V8_GPU_VDDR4
TBD mA
C8138
1UF
10%
2 25V
X5R
402
C8139
1UF
10%
2 25V
X5R
402
C8140
0.1UF
10%
2 6.3V
X5R
201
C8141
CRITICAL
NC
NC
M20 NC/VDDRHA
M21 NC/VSSRHA
NC
NC
U12 NC/VSSRHB
V12 NC/VDDRHB
150mA
L8132
PP1V8_S0GPU
PP1V8_GPU_PLL
H7 MPV18_H7
H8 MPV18_H8
C8142
10UF
20%
2 10V
X5R
603
XW8100
SM
1
75mA
VOLTAGE=1.8V
75
0402
C8143
1UF
10%
2 25V
X5R
402
C8144
75
0.1UF
PP1V0_GPU_PLL
PP1V8_S0GPU
10%
2 6.3V
X5R
201
AN10 SPVSS
GPU_VDD_SENSE
82
OUT
82
OUT
CRITICAL
GPU_GND_SENSE
PP1V8_GPU_PCIE_VDDR
AF28 FB_VDDC
NC
VOLTAGE=0V
504mA
VOLTAGE=1.8V
0603
1
C8145
10UF
20%
10V
2 X5R
603
PP1V0_S0GPU
AN9 SPV10
GND_GPU_PLL
FERR-220-OHM-2A
103 81 79 75 7 6
AM10 SPV18
120mA
L8140
C8146
1UF
10%
25V
2 X5R
402
C8147
1UF
10%
25V
2 X5R
402
C8148
1UF
10%
25V
2 X5R
402
C8149
0.1UF
10%
6.3V
2 X5R
201
C8150
0.1UF
10%
6.3V
2 X5R
201
7 74 75 79 81 103
L8155
FERR-120-OHM-3A
1
PP1V0_GPU_PCIE_VDDC
CRITICAL
C8151
10UF
20%
10V
2 X5R
603
1920mA
VOLTAGE=1V
0603
1
C8152
1UF
10%
25V
2 X5R
402
C8153
1UF
10%
25V
2 X5R
402
C8154
1UF
10%
25V
2 X5R
402
C8155
1UF
10%
25V
2 X5R
402
VDDR4_AD12
VDDR4_AF11
VDDR4_AF12
VDDR4_AG11
0.1UF
10%
2 6.3V
X5R
201
120OHM-0.3A
103 81 79 75 7 6
AD12
AF11
AF12
AG11
C8156
1UF
10%
25V
2 X5R
402
C8157
1UF
10%
25V
2 X5R
402
C8158
1UF
10%
25V
2 X5R
402
AG28 FB_VDDCI
AH29 FB_GND
AA31
AA32
AA33
AA34
AB37
V28
W29
W30
Y31
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
PCIE_VDDR_AA31
PCIE_VDDR_AA32
PCIE_VDDR_AA33
PCIE_VDDR_AA34
PCIE_VDDR_AB37
PCIE_VDDR_V28
PCIE_VDDR_W29
PCIE_VDDR_W30
PCIE_VDDR_Y31
PCIE_VDDC_G30
PCIE_VDDC_G31
PCIE_VDDC_H29
PCIE_VDDC_H30
PCIE_VDDC_J29
PCIE_VDDC_J30
PCIE_VDDC_L28
PCIE_VDDC_M28
PCIE_VDDC_N28
PCIE_VDDC_R28
PCIE_VDDC_T28
PCIE_VDDC_U28
ISOLATED CORE I/O
C8130
C81C1
0.1UF
10%
6.3V
2 X5R
201
10%
2 25V
X5R
402
82 49 7 6
PLL
C81C0
1UF
OMIT
LEVEL
TRNSL
VOLTAGE=1V

(NONE)
(NONE)
I/O
PP1V0_GPU_PLL
2
0603
0402
=PPVCORE_GPU
=PP1V5R1V35_GPU_FB_VDDR1
=PP1V8_GPU_VDD_CT
=PP1V0_GPU_PLL
=PP3V3_GPU_VDDR3
=PP3V3_GPU_VDDR4
=PP1V8_GPU_MEM_PLL
=PP1V8_GPU_PLL
=PP1V8_GPU_PCIE_VDDR
=PP1V8_GPU_PCIE_VDDC
VOLT
SENSE
VOLTAGE=1.8V
(7 OF 9)
PCIE
PP1V0_S0GPU
PP1V8_GPU_VDDR4
FCBGA
L8130
103 81 79 75 74 7
U8000
CRITICAL
470OHM-1A-150MOHM
PP1V8_S0GPU
WHISTLER
40NM-ES
MEM I/O
TBD mA
CORE
103 78 77 76 7
VDDC_AA15
VDDC_AA17
VDDC_AA20
VDDC_AA22
VDDC_AA24
VDDC_AA27
VDDC_AB16
VDDC_AB18
VDDC_AB21
VDDC_AB23
VDDC_AB26
VDDC_AB28
VDDC_AC17
VDDC_AC20
VDDC_AC22
VDDC_AC24
VDDC_AC27
VDDC_AD18
VDDC_AD21
VDDC_AD23
VDDC_AD26
VDDC_AF17
VDDC_AF20
VDDC_AF22
VDDC_AG16
VDDC_AG18
VDDC_AG21
VDDC_AH22
VDDC_AH27
VDDC_AH28
VDDC_M26
VDDC_N24
BIF_VDDC_N27
VDDC_R18
VDDC_R21
VDDC_R23
VDDC_R26
VDDC_T17
VDDC_T20
VDDC_T22
VDDC_T24
BIF_VDDC_T27
VDDC_U16
VDDC_U18
VDDC_U21
VDDC_U23
VDDC_U26
VDDC_V17
VDDC_V20
VDDC_V22
VDDC_V24
VDDC_V27
VDDC_Y16
VDDC_Y18
VDDC_Y21
VDDC_Y23
VDDC_Y26
VDDC_Y28
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
VDDCI_AA13
VDDCI_AB13
VDDCI_AC12
VDDCI_AC15
VDDCI_AD13
VDDCI_AD16
VDDCI_M15
VDDCI_M16
VDDCI_M18
VDDCI_M23
VDDCI_N13
VDDCI_N15
VDDCI_N17
VDDCI_N20
VDDCI_N22
VDDCI_R12
VDDCI_R13
VDDCI_R16
VDDCI_T12
VDDCI_T15
VDDCI_V15
VDDCI_Y13
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
C8160
1UF
10%
25V
2 X5R
402
C8170
C8161
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
PPVCORE_GPU
C8171
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8162
C8172
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8163
C8173
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8164
C8174
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8165
C8175
1UF
C8167
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8166
C8176
1UF
10%
25V
2 X5R
402
C8168
1UF
10%
25V
2 X5R
402
10%
25V
2 X5R
402
C8177
1UF
10%
25V
2 X5R
402
C8178
1UF
10%
25V
2 X5R
402
1UF
10%
25V
2 X5R
402
C8169
C8179
1UF
10%
25V
2 X5R
402
C
1
C8180
1UF
10%
2 25V
X5R
402
C8190
10UF
20%
10V
2 X5R
603
C8181
1UF
10%
2 25V
X5R
402
C8191
10UF
20%
10V
2 X5R
603
C8182
1UF
10%
2 25V
X5R
402
C8192
10UF
20%
10V
2 X5R
603
C8183
1UF
10%
2 25V
X5R
402
C8193
10UF
20%
10V
2 X5R
603
C8184
1UF
10%
2 25V
X5R
402
C8194
10UF
20%
10V
2 X5R
603
C8185
1UF
10%
2 25V
X5R
402
C8195
10UF
20%
10V
2 X5R
603
C8186
1UF
C8187
1UF
10%
2 25V
X5R
402
C8196
10UF
20%
10V
2 X5R
603
C8188
1UF
10%
2 25V
X5R
402
10%
2 25V
X5R
402
C8197
10UF
20%
10V
2 X5R
603
C8198
10UF
20%
10V
2 X5R
603
C8189
1UF
10%
2 25V
X5R
402
C8199
10UF
20%
10V
2 X5R
603
C81A0
1UF
10%
2 25V
X5R
402
C81B0
10UF
20%
10V
2 X5R
603
C81A1
1UF
10%
2 25V
X5R
402
C81B1
10UF
20%
10V
2 X5R
603
C81A2
1UF
10%
2 25V
X5R
402
C81A3
1UF
10%
2 25V
X5R
402
C81A4
1UF
10%
2 25V
X5R
402
C81A5
1UF
10%
2 25V
X5R
402
C81A6
1UF
C81A7
1UF
10%
2 25V
X5R
402
10%
2 25V
X5R
402
C81A8
1UF
10%
2 25V
X5R
402
C81A9
1UF
10%
2 25V
X5R
402
C81B2
10UF
20%
10V
2 X5R
603
SYNC_MASTER=K92_BEN
PAGE TITLE
Whistler CORE/FB POWER

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
81 OF 132
SHEET
75 OF 105
1
Page Notes
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
99 77
BI
76
76
243
402 1% 1/16W MF-LF
R8211 1
243
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
FB_A_VREFD
FB_A_VREFS
L18
L20
MVREFDA
MVREFSA
L27
N12
AG12
7 75 76 77 78
103
FB_CALRN0
FB_CALRN1
FB_CALRN2
M27
M12
AH12
402 1% 1/16W MF-LF
R8212 1
243
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
FB_A1_DQ<0>
FB_A1_DQ<1>
FB_A1_DQ<2>
FB_A1_DQ<3>
FB_A1_DQ<4>
FB_A1_DQ<5>
FB_A1_DQ<6>
FB_A1_DQ<7>
FB_A1_DQ<8>
FB_A1_DQ<9>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<12>
FB_A1_DQ<13>
FB_A1_DQ<14>
FB_A1_DQ<15>
FB_A1_DQ<16>
FB_A1_DQ<17>
FB_A1_DQ<18>
FB_A1_DQ<19>
FB_A1_DQ<20>
FB_A1_DQ<21>
FB_A1_DQ<22>
FB_A1_DQ<23>
FB_A1_DQ<24>
FB_A1_DQ<25>
FB_A1_DQ<26>
FB_A1_DQ<27>
FB_A1_DQ<28>
FB_A1_DQ<29>
FB_A1_DQ<30>
FB_A1_DQ<31>
R8210 1
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<2>
FB_A0_DQ<3>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<7>
FB_A0_DQ<8>
FB_A0_DQ<9>
FB_A0_DQ<10>
FB_A0_DQ<11>
FB_A0_DQ<12>
FB_A0_DQ<13>
FB_A0_DQ<14>
FB_A0_DQ<15>
FB_A0_DQ<16>
FB_A0_DQ<17>
FB_A0_DQ<18>
FB_A0_DQ<19>
FB_A0_DQ<20>
FB_A0_DQ<21>
FB_A0_DQ<22>
FB_A0_DQ<23>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<26>
FB_A0_DQ<27>
FB_A0_DQ<28>
FB_A0_DQ<29>
FB_A0_DQ<30>
FB_A0_DQ<31>
MAA0_0/MMA_0
MAA0_1/MMA_1
MAA0_2/MMA_2
MAA0_3/MMA_3
MAA0_4/MMA_4
MAA0_5/MMA_5
MAA0_6/MMA_6
MAA0_7/MMA_7
G24
J23
H24
J24
H26
J26
H21
G21
MAA1_0/MMA_8
MAA1_1/MMA_9
MAA1_2/MMA_10
MAA1_3/MMA_11
MAA1_4/MMA_12
MAA1_5/MMA_13_BA2
MAA1_6/MMA_14_BA0
MAA1_7/MMA_A15_BA1
H19
H20
L13
G16
J16
H16
J17
H17
U8000
WHISTLER
40NM-ES
FCBGA
(4 OF 9)
MEM INTERFACE A
OMIT
FB_A0_A<0>
FB_A0_A<1>
FB_A0_A<2>
FB_A0_A<3>
FB_A0_A<4>
FB_A0_A<5>
FB_A0_A<6>
FB_A0_A<7>
FB_A1_A<0>
FB_A1_A<1>
FB_A1_A<2>
FB_A1_A<3>
FB_A1_A<4>
FB_A1_A<5>
FB_A1_A<6>
FB_A1_A<7>
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
99 78
BI
99 78
BI
OUT
77 99
OUT
77 99
OUT
77 99
OUT
77 99
OUT
77 99
OUT
77 99
OUT
77 99
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
77 99
OUT
WCKA0_0/DQMA_0 A32
C32
WCKA0_0*/DQMA_1
FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>
BI
77 99
99 78
BI
BI
77 99
99 78
BI
WCKA0_1/DQMA_2 D23
E22
WCKA0_1*/DQMA_3
FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>
99 78
77 99
BI
BI
BI
77 99
WCKA1_0/DQMA_4 C14
A14
WCKA1_0*/DQMA_5
FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>
WCKA1_1/DQMA_6 E10
D9
WCKA1_1*/DQMA_7
EDCA0_0/QSA_0/RDQSA_0
DDBIA0_0/QSA_0B/WDQSA_0
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>
C34
D29
D25
E20
FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>
E16
E12
J10
D7
FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>
A34
E30
E26
C20
FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>
C16
C12
J11
F8
FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>
ADBIA0/ODTA0 J21
ADBIA1/ODTA1 G19
BI
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
99 78
BI
99 78
BI
99 78
BI
77 99
BI
77 99
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
99 78
BI
BI
77 99
BI
77 99
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
99 78
BI
BI
77 99
BI
77 99
BI
77 99
BI
77 99
99 78
BI
99 78
BI
99 78
BI
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
BI
77 99
99 78
BI
99 78
77 99
BI
BI
BI
77 99
99 78
BI
99 78
BI
CLKA0 H27
CLKA0* G27
FB_A0_CLK_P
FB_A0_CLK_N
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
CLKA1 J14
CLKA1* H14
FB_A1_CLK_P
FB_A1_CLK_N
99 78
77 99
BI
OUT
OUT
77 99
99 78
BI
99 78
BI
RASA0* K23
RASA1* K19
FB_A0_RAS_L
FB_A1_RAS_L
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
CASA0* K20
CASA1* K17
FB_A0_CAS_L
FB_A1_CAS_L
99 78
77 99
BI
OUT
OUT
77 99
CSA0_0* K24
CSA0_1* K27
CSA1_0* M13
CSA1_1* K16
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
FB_A0_ABI_L
FB_A1_ABI_L
99 78
FB_A0_CS_L
OUT
77 99
NC
FB_A1_CS_L
OUT
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
99 78
BI
77 99
NC
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
FB_B1_DQ<0>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<5>
FB_B1_DQ<6>
FB_B1_DQ<7>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<18>
FB_B1_DQ<19>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<22>
FB_B1_DQ<23>
FB_B1_DQ<24>
FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<30>
FB_B1_DQ<31>
CKEA0 K21
CKEA1 J20
FB_A0_CKE_L
FB_A1_CKE_L
OUT
77 99
99 78
BI
OUT
77 99
99 78
BI
WEA0* K26
WEA1* L15
FB_A0_WE_L
FB_A1_WE_L
OUT
77 99
76
OUT
77 99
76
MAA0_8 H23
MAA1_8 J19
FB_A0_A<8>
FB_A1_A<8>
OUT
77 99
OUT
77 99
R82501
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<12>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<18>
FB_B0_DQ<19>
FB_B0_DQ<20>
FB_B0_DQ<21>
FB_B0_DQ<22>
FB_B0_DQ<23>
FB_B0_DQ<24>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<28>
FB_B0_DQ<29>
FB_B0_DQ<30>
FB_B0_DQ<31>
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
FB_B_VREFD
FB_B_VREFS
Y12 MVREFDB
AA12 MVREFSB
GPU_TEST_EN
AD28 TESTEN
GPU_CLK_TEST_P
GPU_CLK_TEST_N
AK10 CLKTESTA
AL10 CLKTESTB
243
243
R8215 1
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
FB_B1_A<0>
FB_B1_A<1>
FB_B1_A<2>
FB_B1_A<3>
FB_B1_A<4>
FB_B1_A<5>
FB_B1_A<6>
FB_B1_A<7>
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
(NONE)
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
OUT
78 99
78 99
WCKB0_1/DQMB_2 T3
WCKB0_1*/DQMB_3 T5
FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
BI
78 99
BI
78 99
WCKB1_0/DQMB_4 AE4
WCKB1_0*/DQMB_5 AF5
FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>
BI
78 99
BI
78 99
WCKB1_1/DQMB_6 AK6
WCKB1_1*/DQMB_7 AK5
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
BI
78 99
F6
K3
P3
V5
FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>
EDCB1_0/QSB_4/RDQSB_4
AB5
AH1
AJ9
AM5
FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>
DDBIB0_0/QSB_0B/WDQSB_0
G7
K1
P1
W4
FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>
AC4
AH3
AJ8
AM3
FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>
FB_B0_ABI_L
FB_B1_ABI_L
FB_B0_CLK_P
FB_B0_CLK_N
OUT
78 99
OUT
78 99
CLKB1 AD8
CLKB1* AD7
FB_B1_CLK_P
FB_B1_CLK_N
OUT
78 99
OUT
78 99
RASB0* T10
RASB1* Y10
FB_B0_RAS_L
FB_B1_RAS_L
OUT
78 99
OUT
78 99
CASB0* W10
CASB1* AA10
FB_B0_CAS_L
FB_B1_CAS_L
OUT
78 99
OUT
78 99
FB_B0_CS_L
OUT
78 99
FB_B1_CS_L
OUT
78 99
NC
CSB1_0* AD10
CSB1_1* AC10
NC
CKEB0 U10
CKEB1 AA11
FB_B0_CKE_L
FB_B1_CKE_L
OUT
78 99
OUT
78 99
WEB0* N10
WEB1* AB11
FB_B0_WE_L
FB_B1_WE_L
OUT
78 99
OUT
78 99
FB_B0_A<8>
FB_B1_A<8>
OUT
78 99
OUT
78 99
R8200
PLACE_NEAR=U8000.L20:2.54MM
40.2
100
1
R8201
100
1%
1/16W
MF-LF
2 402
C8200
1%
1/16W
MF-LF
2 402
103 78 77 76 75 7
R8205
C8201
0.1UF
100
1%
1/16W
MF-LF
2 402
51.1
1%
1/16W
MF-LF
402 2
10
R82601
C8252
5%
1/16W
MF-LF
402 2
10%
16V
2 X5R
402-1
R8262
FB_RESET_RC_L
51
FB_RESET_L
C8260
120PF
GPU_CLK_TEST_RC_N
1
R8252
51.1
NOSTUFF
1%
1/16W
MF-LF
2 402
R8206
C8202
0.1UF
10%
2 16V
X5R
402-1
40.2
1%
1/16W
MF-LF
402
PLACE_NEAR=U8000.AA12:2.54MM 2
FB_B_VREFS
PLACE_NEAR=U8000.AA12:2.54MM
R8207
10%
16V
2 X5R
402-1
100
1%
1/16W
MF-LF
2 402
10%
16V
2 X5R
402-1
SYNC_MASTER=K18_MLB
76
PAGE TITLE
PLACE_NEAR=U8000.AA12:2.54MM
1
0.1UF
Whistler FRAME BUFFER I/F
C8203
DRAWING NUMBER
0.1UF
10%
16V
2 X5R
402-1
Apple Inc.
SIZE
D
REVISION
77 78 99
5%
50V
2 CERM
402

OUT
5%
1/16W
MF-LF
402
1
5.1K
0.1UF
5%
1/16W
MF-LF
402
1
76
PLACE_NEAR=U8000.Y12:2.54MM
1
76
R8203
76
NOSTUFF
FB_B_VREFD
FB_A_VREFD
1%
1/16W
MF-LF
2 402
FB_A_VREFS
1%
1/16W
MF-LF
2 402
R82511
40.2
40.2
NOSTUFF
1
GPU_CLK_TEST_RC_P
R8204
R8202
GPU_FB_RESET_L
1
78 99
BI
CLKB0 L9
CLKB0* L8
CSB0_0* P10
CSB0_1* L10
R8261
1%
1/16W
MF-LF
2 402
(NONE)
78 99
DRAM_RST AH11
10%
16V 2
X5R
402-1
BI
MAB0_8 T8
MAB1_8 W8
0.1UF
103 78 77 76 75 7
- =PP1V5R1V35_FB_REF
BI
NOSTUFF
103 78 77 76 75 7
- =PP1V5R1V35_FB_CAL
FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>
ADBIB0/ODTB0 T7
ADBIB1/ODTB1 W7
C8251
FB_CALRP0
FB_CALRP1
FB_CALRP2
WCKB0_0/DQMB_0 H3
WCKB0_0*/DQMB_1 H1
5%
1/16W
MF-LF
402 2
402 1% 1/16W MF-LF
77 76 75 7
103 78
OMIT
FB_B0_A<0>
FB_B0_A<1>
FB_B0_A<2>
FB_B0_A<3>
FB_B0_A<4>
FB_B0_A<5>
FB_B0_A<6>
FB_B0_A<7>
10K
MEM_CALRP0
MEM_CALRP1
MEM_CALRP2
402 1% 1/16W MF-LF
243
(5 OF 9)
MEM INTERFACE B
P8
T9
P9
N7
N8
N9
U9
U8
402 1% 1/16W MF-LF
R8214 1
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
FCBGA
DQB1_0/DQB32
DQB1_1/DQB33
DQB1_2/DQB34
DQB1_3/DQB35
DQB1_4/DQB36
DQB1_5/DQB37
DQB1_6/DQB38
DQB1_7/DQB39
DQB1_8/DQB40
DQB1_9/DQB41
DQB1_10/DQB42
DQB1_11/DQB43
DQB1_12/DQB44
DQB1_13/DQB45
DQB1_14/DQB46
DQB1_15/DQB47
DQB1_16/DQB48
DQB1_17/DQB49
DQB1_18/DQB50
DQB1_19/DQB51
DQB1_20/DQB52
DQB1_21/DQB53
DQB1_22/DQB54
DQB1_23/DQB55
DQB1_24/DQB56
DQB1_25/DQB57
DQB1_26/DQB58
DQB1_27/DQB59
DQB1_28/DQB60
DQB1_29/DQB61
DQB1_30/DQB62
DQB1_31/DQB63
402 1% 1/16W MF-LF
R8213 1
U8000
WHISTLER
40NM-ES
BRANCH
PAGE
82 OF 132
SHEET
76 OF 105
Page Notes
(NONE)
(NONE)
99 76
IN
99 76
IN
99 76
99 76
IN
IN
R8401 1R8402
60.4
1%
1/16W
MF-LF
2 402
99 76
IN
99 76
IN
60.4
1%
1/16W
MF-LF
2 402
99 76
IN
99 76
IN
99 76
IN
99 76
IN
99 76
99 76
IN
IN
99 76
IN
99 76
IN
99 76
IN
R8400
1%
1/20W
MF
201 2
H11
K10
K11
H10
FB_A0_A<2>
FB_A0_A<5>
FB_A0_A<4>
FB_A0_A<3>
BA0/A2
BA1/A5
BA2/A4
BA3/A3
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
OMIT
R84041
R84031
120
99 78 77 76
IN
120
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
99 76
99 76
BI
BI
99 76
BI
99 76
99 76
IN
99 76
99 76
99 76
99 76
BI
IN
IN
IN
IN
FB_A0_A<7>
FB_A0_A<1>
FB_A0_A<0>
FB_A0_A<6>
FB_A0_CKE_L
K4
H5
H4
K5
J3
FB_A0_CLK_P
FB_A0_CLK_N
FB_A0_CS_L
FB_A0_WE_L
FB_A0_CAS_L
FB_A0_RAS_L
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
FB_RESET_L
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_A0_ABI_L
C2
C13
R13
R2
FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<3>
FB_A0_EDC<2>
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>
P4 WCK23
P5 WCK23*
FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>
U8400
32MX32-1.25GHZ-MFL
NC
BGA
H5GQ1H24AFR-T2C
C8400
4.7UF
20%
2 6.3V
X5R
402
C8403
4.7UF
20%
6.3V
2 X5R
402
C8406
1UF
10%
6.3V
2 CERM-X5R
402
C8410
1UF
10%
6.3V
2 CERM-X5R
402
C8414
1UF
10%
2 6.3V
CERM-X5R
402
C8418
0.1UF
10%
6.3V
2 X5R
201
C8422
0.1UF
10%
2 6.3V
X5R
201
C8401
4.7UF
20%
2 6.3V
X5R
402
C8404
4.7UF
20%
6.3V
2 X5R
402
C8407
1UF
10%
6.3V
2 CERM-X5R
402
C8411
1UF
10%
6.3V
2 CERM-X5R
402
C8415
1UF
10%
2 6.3V
CERM-X5R
402
C8419
0.1UF
10%
6.3V
2 X5R
201
C8423
0.1UF
10%
2 6.3V
X5R
201
C8402
20%
2 6.3V
X5R
402
C8405
4.7UF
20%
6.3V
2 X5R
402
C8408
1UF
10%
6.3V
2 CERM-X5R
402
C8412
1UF
10%
6.3V
2 CERM-X5R
402
C8416
0.1UF
10%
2 6.3V
X5R
201
C8420
0.1UF
10%
6.3V
2 X5R
201
C8424
0.1UF
10%
2 6.3V
X5R
201
77
77
77
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
4.7UF
D2
D13
P13
P2
FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<3>
FB_A0_DBI_L<2>
BI
76 99
BI
76 99
BI
76 99
BI
C8409
1UF
10%
6.3V
2 CERM-X5R
402
C8413
1UF
10%
6.3V
2 CERM-X5R
402
C8417
0.1UF
10%
2 6.3V
X5R
201
C8421
0.1UF
10%
6.3V
2 X5R
201
C8425
0.1UF
10%
2 6.3V
X5R
201
FB_A0_VREFC
FB_A0_VREFD1
FB_A0_VREFD2
(2 OF 2)
OMIT
VDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
A5
J5
U5
FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<2>
FB_A0_DQ<3>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<7>
FB_A0_DQ<8>
FB_A0_DQ<9>
FB_A0_DQ<10>
FB_A0_DQ<11>
FB_A0_DQ<14>
FB_A0_DQ<13>
FB_A0_DQ<12>
FB_A0_DQ<15>
FB_A0_DQ<31>
FB_A0_DQ<30>
FB_A0_DQ<29>
FB_A0_DQ<28>
FB_A0_DQ<26>
FB_A0_DQ<27>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<20>
FB_A0_DQ<23>
FB_A0_DQ<21>
FB_A0_DQ<22>
FB_A0_DQ<17>
FB_A0_DQ<18>
FB_A0_DQ<16>
FB_A0_DQ<19>
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
R8451 1R8452
60.4
1%
1/16W
MF-LF
2 402
NC
FB_A0_A<8>
VSSQ
99 76
IN
1%
1/16W
MF-LF
2 402
77
120
1%
1/20W
MF
201 2
R8454
R84531
120
10%
6.3V
2 CERM-X5R
402
C8450
C8453
1%
1/16W
MF-LF
2 402
20%
2 6.3V
X5R
402
C8431
C8451
4.7UF
20%
2 6.3V
X5R
402
4.7UF
5.49K
10%
2 6.3V
CERM-X5R
402
C8454
4.7UF
20%
2 6.3V
X5R
402
4.7UF
20%
2 6.3V
X5R
402
C8452
C8455
4.7UF
20%
2 6.3V
X5R
402
C8456
C8457
1UF
10%
6.3V
2 CERM-X5R
402
C8458
1UF
10%
6.3V
2 CERM-X5R
402
C8459
1UF
10%
6.3V
2 CERM-X5R
402
1
2.37K
1%
1/16W
MF-LF
2 402
77
C8432
C8460
1UF
1UF
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
R8433
5.49K
1%
1/16W
MF-LF
2 402
C8461
1UF
10%
6.3V
2 CERM-X5R
402
C8464
10%
6.3V
2 CERM-X5R
402
1UF
10%
6.3V
2 CERM-X5R
402
C8468
0.1UF
10%
2 6.3V
X5R
201
76 75 7
103 78 77
R8434
2.37K
1%
1/16W
MF-LF
2 402
C8462
1UF
10%
6.3V
2 CERM-X5R
402
C8463
1UF
10%
6.3V
2 CERM-X5R
402
1%
1/16W
MF-LF
2 402
1UF
10%
6.3V
2 CERM-X5R
402
C8469
0.1UF
10%
2 6.3V
X5R
201
C8466
0.1UF
10%
6.3V
2 X5R
201
C8470
0.1UF
10%
2 6.3V
X5R
201
C8472
0.1UF
C8473
0.1UF
10%
6.3V
2 X5R
201
C8474
0.1UF
10%
6.3V
2 X5R
201
C8467
0.1UF
10%
6.3V
2 X5R
201
C8471
0.1UF
10%
2 6.3V
X5R
201
C8475
0.1UF
10%
6.3V
2 X5R
201
C8435
1UF
10%
6.3V
2 CERM-X5R
402
77
77
77
1UF
10%
6.3V
2 CERM-X5R
402
FB_A0_VREFD2
5.49K
C8465
C8434
10%
6.3V
2 X5R
201
R8435
1UF
C8433
77
FB_A0_VREFD1
1
IN
IN
99 76
IN
99 76
IN
99 76
IN
99 76
IN
99 78 77 76
99 76
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
76 75 7
103 78 77
R8432
99 76
99 76
1%
1/20W
MF
201 2
1UF
IN
IN
120
1%
1/20W
MF
201 2
20%
2 6.3V
X5R
402
FB_A0_VREFC
R8431
IN
99 76
IN
99 76
BI
99 76
BI
99 76
BI
99 76
BI
99 76
IN
99 76
IN
99 76
IN
99 76
IN
K4
H5
H4
K5
J3
FB_A1_CLK_P
FB_A1_CLK_N
FB_A1_CS_L
FB_A1_WE_L
FB_A1_CAS_L
FB_A1_RAS_L
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
FB_RESET_L
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
(1 OF 2)
OMIT
DBI0*
DBI1*
DBI2*
DBI3*
D2
D13
P13
P2
FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FB_A1_DQ<1>
FB_A1_DQ<0>
FB_A1_DQ<3>
FB_A1_DQ<2>
FB_A1_DQ<4>
FB_A1_DQ<6>
FB_A1_DQ<5>
FB_A1_DQ<7>
FB_A1_DQ<9>
FB_A1_DQ<8>
FB_A1_DQ<11>
FB_A1_DQ<10>
FB_A1_DQ<12>
FB_A1_DQ<13>
FB_A1_DQ<14>
FB_A1_DQ<15>
FB_A1_DQ<21>
FB_A1_DQ<22>
FB_A1_DQ<23>
FB_A1_DQ<20>
FB_A1_DQ<18>
FB_A1_DQ<19>
FB_A1_DQ<17>
FB_A1_DQ<16>
FB_A1_DQ<31>
FB_A1_DQ<30>
FB_A1_DQ<28>
FB_A1_DQ<29>
FB_A1_DQ<25>
FB_A1_DQ<27>
FB_A1_DQ<24>
FB_A1_DQ<26>
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_A1_ABI_L
C2
C13
R13
R2
FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>
FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
P4 WCK23
P5 WCK23*
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>
NC
BGA
H5GQ1H24AFR-T2C
4.7UF
C8430
1UF
IN
99 76
76 99
10%
6.3V
2 CERM-X5R
402
VDDQ
IN
1%
1/16W
MF-LF
2 402
99 76
FB_A1_A<7>
FB_A1_A<1>
FB_A1_A<0>
FB_A1_A<6>
FB_A1_CKE_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
32MX32-1.25GHZ-MFL
IN
1
1
IN
NC
76 75 7
103 78 77
2.37K
IN
99 76
H11
K10
K11
H10
FB_A1_A<2>
FB_A1_A<5>
FB_A1_A<4>
FB_A1_A<3>
U8450
103 78 77 76 75 7
R8430
IN
99 76
R84501
1UF
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
99 76
60.4
1
IN
99 76
J14 VREFC
A10
U10 VREFD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
99 76
76 99
103 78 77 76 75 7
120
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
103 78
75 7
77 76
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
78 77 76 75 7
103
U8450
U8400
FB_A1_VREFC
FB_A1_VREFD1
FB_A1_VREFD2
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
(2 OF 2)
OMIT
VDD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A5
J5
U5
76 75 7
103 78 77
2.37K
1%
1/16W
MF-LF
2 402
77
FB_A1_A<8>
FB_A1_VREFC
1%
1/16W
MF-LF
2 402
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
IN
76 99
R8484
2.37K
C8484
1UF
1%
1/16W
MF-LF
2 402
77
5.49K
76 99
BI
C8480
10%
6.3V
2 CERM-X5R
402
R8481
76 99
BI
1UF
76 99
BI
NC
103 78 77 76 75 7
R8480
NC
BI
10%
6.3V
2 CERM-X5R
402
FB_A1_VREFD2
1
R8485
C8481
5.49K
1UF
C8485
1UF
1%
1/16W
MF-LF
2 402
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
VDDQ
VSSQ
J14 VREFC
A10
U10 VREFD
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
76 75 7
103 78 77
R8482
2.37K
1%
1/16W
MF-LF
2 402
77
C8482
1UF
10%
6.3V
2 CERM-X5R
402
FB_A1_VREFD1
1
R8483
5.49K
1%
1/16W
MF-LF
2 402
C8483
1UF
10%
6.3V
2 CERM-X5R
402
SYNC_MASTER=K91_YUN
PAGE TITLE
GDDR5 Frame Buffer A

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
84 OF 132
SHEET
77 OF 105
Page Notes
(NONE)
(NONE)
99 76
IN
99 76
IN
99 76
99 76
IN
IN
R8501 1R8502
60.4
1%
1/16W
MF-LF
2 402
99 76
IN
99 76
IN
60.4
1%
1/16W
MF-LF
2 402
99 76
IN
99 76
IN
99 76
IN
99 76
IN
99 76
99 76
IN
IN
99 76
IN
99 76
IN
99 76
IN
R8500
1%
1/20W
MF
201 2
H11
K10
K11
H10
FB_B0_A<2>
FB_B0_A<5>
FB_B0_A<4>
FB_B0_A<3>
BA0/A2
BA1/A5
BA2/A4
BA3/A3
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
OMIT
R85041
R85031
120
99 78 77 76
IN
120
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
99 76
99 76
BI
BI
99 76
BI
99 76
99 76
IN
99 76
99 76
99 76
99 76
BI
IN
IN
IN
IN
FB_B0_A<7>
FB_B0_A<1>
FB_B0_A<0>
FB_B0_A<6>
FB_B0_CKE_L
K4
H5
H4
K5
J3
FB_B0_CLK_P
FB_B0_CLK_N
FB_B0_CS_L
FB_B0_WE_L
FB_B0_CAS_L
FB_B0_RAS_L
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
FB_RESET_L
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_B0_ABI_L
C2
C13
R13
R2
FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<3>
FB_B0_EDC<2>
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>
P4 WCK23
P5 WCK23*
FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
U8500
32MX32-1.25GHZ-MFL
NC
BGA
H5GQ1H24AFR-T2C
C8500
4.7UF
20%
2 6.3V
X5R
402
C8503
4.7UF
20%
6.3V
2 X5R
402
C8506
1UF
10%
6.3V
2 CERM-X5R
402
C8510
1UF
10%
6.3V
2 CERM-X5R
402
C8514
1UF
10%
2 6.3V
CERM-X5R
402
C8518
0.1UF
10%
6.3V
2 X5R
201
C8522
0.1UF
10%
2 6.3V
X5R
201
C8501
4.7UF
20%
2 6.3V
X5R
402
C8504
4.7UF
20%
6.3V
2 X5R
402
C8507
1UF
10%
6.3V
2 CERM-X5R
402
C8511
1UF
10%
6.3V
2 CERM-X5R
402
C8515
1UF
10%
2 6.3V
CERM-X5R
402
C8519
0.1UF
10%
6.3V
2 X5R
201
C8523
0.1UF
10%
2 6.3V
X5R
201
C8502
20%
2 6.3V
X5R
402
C8505
4.7UF
20%
6.3V
2 X5R
402
C8508
1UF
10%
6.3V
2 CERM-X5R
402
C8512
1UF
10%
6.3V
2 CERM-X5R
402
C8516
0.1UF
10%
2 6.3V
X5R
201
C8520
0.1UF
10%
6.3V
2 X5R
201
C8524
0.1UF
10%
2 6.3V
X5R
201
78
78
78
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
4.7UF
D2
D13
P13
P2
FB_B0_DBI_L<0>BI
FB_B0_DBI_L<1>BI
FB_B0_DBI_L<3>BI
FB_B0_DBI_L<2>BI
C8509
1UF
10%
6.3V
2 CERM-X5R
402
C8513
1UF
10%
6.3V
2 CERM-X5R
402
C8517
0.1UF
10%
2 6.3V
X5R
201
C8521
0.1UF
10%
6.3V
2 X5R
201
C8525
0.1UF
10%
2 6.3V
X5R
201
FB_B0_VREFC
FB_B0_VREFD1
FB_B0_VREFD2
(2 OF 2)
OMIT
VDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
A5
J5
U5
FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<12>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<31>
FB_B0_DQ<30>
FB_B0_DQ<29>
FB_B0_DQ<28>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<24>
FB_B0_DQ<23>
FB_B0_DQ<22>
FB_B0_DQ<19>
FB_B0_DQ<21>
FB_B0_DQ<20>
FB_B0_DQ<18>
FB_B0_DQ<17>
FB_B0_DQ<16>
NC
FB_B0_A<8>
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
R8551 1R8552
60.4
1%
1/16W
MF-LF
2 402
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
120
1%
1/20W
MF
201 2
VSSQ
99 76
IN
1%
1/16W
MF-LF
2 402
78
10%
6.3V
2 CERM-X5R
402
R8554
R85531
120
C8550
C8553
1%
1/16W
MF-LF
2 402
20%
2 6.3V
X5R
402
C8531
C8551
4.7UF
20%
2 6.3V
X5R
402
4.7UF
10%
2 6.3V
CERM-X5R
402
C8554
4.7UF
20%
2 6.3V
X5R
402
4.7UF
20%
2 6.3V
X5R
402
C8552
C8555
4.7UF
20%
2 6.3V
X5R
402
C8556
C8557
1UF
10%
6.3V
2 CERM-X5R
402
C8558
1UF
10%
6.3V
2 CERM-X5R
402
C8559
1UF
10%
6.3V
2 CERM-X5R
402
1
2.37K
1%
1/16W
MF-LF
2 402
78
C8532
C8560
1UF
1UF
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
R8533
5.49K
1%
1/16W
MF-LF
2 402
C8561
1UF
10%
6.3V
2 CERM-X5R
402
C8564
10%
6.3V
2 CERM-X5R
402
1UF
10%
6.3V
2 CERM-X5R
402
C8568
0.1UF
10%
2 6.3V
X5R
201
76 75 7
103 78 77
R8534
2.37K
1%
1/16W
MF-LF
2 402
C8562
1UF
10%
6.3V
2 CERM-X5R
402
C8563
1UF
10%
6.3V
2 CERM-X5R
402
1%
1/16W
MF-LF
2 402
1UF
10%
6.3V
2 CERM-X5R
402
C8569
0.1UF
10%
2 6.3V
X5R
201
C8566
0.1UF
10%
6.3V
2 X5R
201
C8570
0.1UF
10%
2 6.3V
X5R
201
C8572
0.1UF
C8573
0.1UF
10%
6.3V
2 X5R
201
C8574
0.1UF
10%
6.3V
2 X5R
201
C8567
0.1UF
10%
6.3V
2 X5R
201
C8571
0.1UF
10%
2 6.3V
X5R
201
C8575
0.1UF
10%
6.3V
2 X5R
201
C8535
1UF
10%
6.3V
2 CERM-X5R
402
78
78
78
1UF
10%
6.3V
2 CERM-X5R
402
FB_B0_VREFD2
5.49K
C8565
C8534
10%
6.3V
2 X5R
201
R8535
1UF
C8533
78
FB_B0_VREFD1
1
IN
99 76
IN
99 76
IN
99 76
IN
99 76
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
76 75 7
103 78 77
R8532
IN
99 76
99 78 77 76
1%
1/20W
MF
201 2
1UF
IN
99 76
IN
120
1%
1/20W
MF
201 2
5.49K
99 76
IN
99 76
BI
99 76
BI
99 76
BI
99 76
BI
99 76
IN
99 76
IN
99 76
IN
99 76
IN
K4
H5
H4
K5
J3
FB_B1_CLK_P
FB_B1_CLK_N
FB_B1_CS_L
FB_B1_WE_L
FB_B1_CAS_L
FB_B1_RAS_L
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
FB_RESET_L
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
(1 OF 2)
OMIT
DBI0*
DBI1*
DBI2*
DBI3*
D2
D13
P13
P2
FB_B1_DBI_L<0>BI
FB_B1_DBI_L<1>BI
FB_B1_DBI_L<2>BI
FB_B1_DBI_L<3>BI
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FB_B1_DQ<0>
FB_B1_DQ<3>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<6>
FB_B1_DQ<5>
FB_B1_DQ<7>
FB_B1_DQ<4>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<23>
FB_B1_DQ<22>
FB_B1_DQ<21>
FB_B1_DQ<20>
FB_B1_DQ<19>
FB_B1_DQ<18>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<31>
FB_B1_DQ<26>
FB_B1_DQ<30>
FB_B1_DQ<29>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<24>
FB_B1_DQ<25>
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_B1_ABI_L
C2
C13
R13
R2
FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>
FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
P4 WCK23
P5 WCK23*
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>
NC
BGA
H5GQ1H24AFR-T2C
20%
2 6.3V
X5R
402
FB_B0_VREFC
R8531
IN
76 99
4.7UF
C8530
1UF
IN
99 76
FB_B1_A<7>
FB_B1_A<1>
FB_B1_A<0>
FB_B1_A<6>
FB_B1_CKE_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
32MX32-1.25GHZ-MFL
IN
10%
6.3V
2 CERM-X5R
402
VDDQ
IN
1%
1/16W
MF-LF
2 402
IN
99 76
R85501
1UF
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
99 76
60.4
99 76
7878
1
1
IN
NC
76 75 7
103 78 77
2.37K
IN
99 76
H11
K10
K11
H10
FB_B1_A<2>
FB_B1_A<5>
FB_B1_A<4>
FB_B1_A<3>
U8550
103 78 77 76 75 7
R8530
IN
99 76
76 99
1
IN
99 76
76 99
J14 VREFC
A10
U10 VREFD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
99 76
76 99
103 78 77 76 75 7
120
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
103 78
75 7
77 76
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
78 77 76 75 7
103
U8550
U8500
FB_B1_VREFC
FB_B1_VREFD1
FB_B1_VREFD2
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
(2 OF 2)
OMIT
VDD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A5
J5
U5
76 75 7
103 78 77
2.37K
1%
1/16W
MF-LF
2 402
78
FB_B1_A<8>
FB_B1_VREFC
1%
1/16W
MF-LF
2 402
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
BI
76 99
IN
76 99
R8584
2.37K
C8584
1UF
1%
1/16W
MF-LF
2 402
78
5.49K
76 99
C8580
10%
6.3V
2 CERM-X5R
402
R8581
76 99
1UF
76 99
NC
103 78 77 76 75 7
R8580
NC
76 99
10%
6.3V
2 CERM-X5R
402
FB_B1_VREFD2
1
R8585
C8581
5.49K
1UF
C8585
1UF
1%
1/16W
MF-LF
2 402
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
VDDQ
VSSQ
J14 VREFC
A10
U10 VREFD
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
76 75 7
103 78 77
R8582
2.37K
1%
1/16W
MF-LF
2 402
78
C8582
1UF
10%
6.3V
2 CERM-X5R
402
FB_B1_VREFD1
1
R8583
5.49K
1%
1/16W
MF-LF
2 402
C8583
1UF
10%
6.3V
2 CERM-X5R
402
SYNC_MASTER=K91_YUN
PAGE TITLE
GDDR5 Frame Buffer B

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
85 OF 132
SHEET
78 OF 105

(NONE)
(NONE)
6
6
NOTE:
AMD STRAPS FOR IDENTIFYING VRAM VENDOR & SIZE FOR WHISTLER
6
6
K92 Samsung 1G - NOSTUFF R8613, NOSTUFF R8612, STUFF R8611

K92 Hynix 1G
- STUFF R8613, NOSTUFF R8612, STUFF R8611
6
6
6
6
6
6
6
6
6
6
84 82 80 79 75 72 7 6
PP3V3_S0GPU
6
6
6
R8600
R8601
4.7K
AR1 DVPCLK
TP_DVPCLK
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
DVPDATA<0>
DVPDATA<1>
DVPDATA<2>
DVPDATA<3>
TP_DVPDATA<4>
TP_DVPDATA<5>
TP_DVPDATA<6>
TP_DVPDATA<7>
TP_DVPDATA<8>
TP_DVPDATA<9>
TP_DVPDATA<10>
TP_DVPDATA<11>
TP_DVPDATA<12>
TP_DVPDATA<13>
TP_DVPDATA<14>
TP_DVPDATA<15>
TP_DVPDATA<16>
TP_DVPDATA<17>
TP_DVPDATA<18>
TP_DVPDATA<19>
TP_DVPDATA<20>
TP_DVPDATA<21>
TP_DVPDATA<22>
TP_DVPDATA<23>
4.7K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
NC
NC
80
80
80
80
80
80
82 80
88 80
80
80
80
80
80
80
80
82 80
103 81 79 75 7 6
PP1V8_S0GPU
82 80
80
R8602
80
499
80
1%
1/16W
MF-LF
402 2
82 80
87 80
80
80
C8600 1 R8603
249
0.1UF
10%
16V
X5R 2
402-1
80 6
1%
1/16W
MF-LF
402 2
80
80
80
80
80
80
80
CRITICAL
80
L8600
80
470OHM-1A-150MOHM
81 79 75 7 6
103
PP1V8_S0GPU
VOLTAGE=1.8V
80
80
VOLTAGE=1.8V
0603
1
C8601
10UF
20%
10V
2 X5R
603
C8602
1UF
10%
25V
2 X5R
402
10%
16V
2 X5R
402-1
L8601
AM23
AN23
AK23
AL24
AM24
JTAG_TRST*
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
NC_GPU_GENERICA
NC_GPU_GENERICB
NC_GPU_GENERICC
DP_CA_DET_EG_R
NC_GPU_GENERICE
NC_GPU_GENERICF
NC_GPU_GENERICG
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
DP_EG_HPD
AK24 HPD1
C8604
20%
2 10V
X5R
603
C8605
1UF
10%
2 25V
X5R
402
PP1V8_GPU_DPLL
(GND_GPU_DPLL)
125mA
C8606
IN
GPU_CLK27M
AW34 XO_IN
99 80
IN
GPU_CLK100M
AW35 XO_IN2
100 51
IN
VOLTAGE=1.8V
0402
1
XW8601
SM
1
C8607
10UF
20%
10V
2 X5R
603
C8608
1UF
10%
25V
2 X5R
402
100 51
OUT
PP1V8_GPU_TSVDD
(GND_GPU_TSVSS)
20mA
NC
AK32 TS_FDO
NC
AL31 TSA/NC
AJ32 TSVDD
AJ33 TSVSS
0.1UF
10%
16V
2 X5R
402-1
85 99
TX1P_DPA1P AU26
TX1M_DPA1N AV25
DP_EXTA_ML_C_P<1>
DP_EXTA_ML_C_N<1>
OUT
85 99
OUT
85 99
TX2P_DPA0P AT27
TX2M_DPA0N AR26
DP_EXTA_ML_C_P<0>
DP_EXTA_ML_C_N<0>
OUT
85 99
OUT
85 99
TXCBP_DPB3P AR30
TXCBM_DPB3N AT29
OUT
6 33 97
OUT
6 33 97
TX3P_DPB2P AV31
TX3M_DPB2N AU30
OUT
6 33 97
OUT
6 33 97
TX4P_DPB1P AR32
TX4M_DPB1N AT31
OUT
6 33 97
OUT
6 33 97
TX5P_DPB0P AT33
TX5M_DPB0N AU32
OUT
6 33 97
OUT
6 33 97
TXCCP_DPC3P AU14
TXCCM_DPC3N AV13
OUT
6 33 97
OUT
6 33 97
TX0P_DPC2P AT15
TX0M_DPC2N AR14
OUT
6 33 97
OUT
6 33 97
TX1P_DPC1P AU16
TX1M_DPC1N AV15
OUT
6 33 97
OUT
6 33 97
TX2P_DPC0P AT17
TX2M_DPC0N AR16
OUT
6 33 97
OUT
6 33 97
TXCDP_DPD3P AU20
TXCDM_DPD3N AT19
NC
NC
TX3P_DPD2P AT21
TX3M_DPD2N AR20
NC
NC
TX4P_DPD1P AU22
TX4M_DPD1N AV21
NC
NC
TX5P_DPD0P AT23
TX5M_DPD0N AR22
NC
NC
R AD39
R* AD37
NC
NC
G AE36
G* AD35
NC
NC
B AF37
B* AE38
NC
NC
HSYNC AC36
VSYNC AC38
R86041
R8605
10K
5%
1/16W
MF-LF
402 2
PP1V8_S0GPU
5%
1/16W
MF-LF
2 402
6 7 75 79 81 103
VARY_BL AK27
DIGON AJ27
U8000
FCBGA
(3 OF 9)
NC
NC
G2/NC AD30
G2*/NC AD31
NC
NC
B2/NC AF30
B2*/NC AF31
NC
NC
C/NC AC32
Y/NC AD32
COMP/NC AF32
NC
NC
NC
H2SYNC/GENLK_CLK AD29
V2SYNC/GENLK_VSYNC AC29
NC
NC
VDD2DI/NC AG31
VSS2DI/NC AG32
NC
NC
A2VDD/NC AG33
NC
A2VDDQ/NC AD33
NC
XW8602
SM
GND_GPU_TVSSQ
NC VOLTAGE=0V
DP_EG_DDC_CLK
DP_EG_DDC_DATA
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_B_CLK_N
OUT
80 88
R8606
80
10K
80
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
OUT
88 99
OUT
88 99
TXOUT_U1P_DPF1P AH35
TXOUT_U1N_DPF1N AJ36
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
OUT
88 99
OUT
88 99
TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
OUT
88 99
TXOUT_U3P AF35
TXOUT_U3N AG36
TXCLK_LP_DPE3P AP34
TXCLK_LN_DPE3N AR34
OUT
NC_LVDS_EG_B_DATA_P<3>
NC_LVDS_EG_B_DATA_N<3>
80 99
OUT
88 99
OUT
88 99
TXOUT_L0P_DPE2P AW37
TXOUT_L0N_DPE2N AU35
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
OUT
88 99
OUT
88 99
TXOUT_L1P_DPE1P AR37
TXOUT_L1N_DPE1N AU39
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
OUT
88 99
OUT
88 99
TXOUT_L2P_DPE0P AP35
TXOUT_L2N_DPE0N AR35
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
OUT
88 99
NC_LVDS_EG_A_DATA_P<3>
NC_LVDS_EG_A_DATA_N<3>
88 99
80 99
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
OUT
5%
1/16W
MF-LF
2 402
88 99
80 99
80 99
80 84
80 84
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
BI
84 99
BI
84 99
AUX2P AN20
AUX2N AM20
BI
6 33 97
BI
6 33 97
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
BI
6 33 97
BI
6 33 97
AUX1P AM27
AUX1N AL27
TXCLK_UP_DPF3P AK35
TXCLK_UN_DPF3N AL36
TXOUT_L3P AN36
TXOUT_L3N AP37
OUT
LVDS_EG_BLK_PWM
EG_LCD_PWR_EN
LVDS CNTL
OMIT
BI
NC
NC
SYNC_MASTER=K92_SUMA
PAGE TITLE
Whistler LVDS/DP/GPIO
NC
NC
DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
10K
DRAWING NUMBER
LVDS_EG_DDC_CLK
LVDS_EG_DDC_DATA
OUT
BI
84
Apple Inc.
84
SIZE
D
REVISION
NC
NC

NC
NC
VOLTAGE=0V
NC
R2/NC AC30
R2*/NC AC31
DDCCLK_AUX4P AL29
DDCDATA_AUX4N AM29
PP3V3_S0GPU
6 7 72 75 79 80 82 84
Straps for audio on DP and HDMI
VDD1DI AC33
VSS1DI AC34
DDC2CLK AM19
DDC2DATA AL19
GPU_AUD_1
GPU_AUD_0
AVDD AD34
AVSSQ AE34
DDCCLK_AUX7P AK30
DDCDATA_AUX7N AK29
GND_GPU_TSVSS
85 99
OUT
DDC6CLK AJ30
DDC6DATA AJ31
C8609
OUT
DDC1CLK AM26
DDC1DATA AN26
AF29 DPLUS
AG29 DMINUS
GPU_TDIODE_P
GPU_TDIODE_N
L8602
AV33 XTALIN
AU34 XTALOUT
99 80
0.1UF
10%
2 16V
X5R
402-1
GND_GPU_DPLL
85 99
DP_EXTA_ML_C_P<2>
DP_EXTA_ML_C_N<2>
R2SET/NC AA29
AN31 DPLL_VDDC
NC
NC
VOLTAGE=0V
PP1V8_S0GPU
OUT
TX0P_DPA2P AT25
TX0M_DPA2N AR24
RSET AB34
AM32 DPLL_PVDD
AN32 DPLL_PVSS
75mA
120OHM-0.3A
81 79 75 7 6
103
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS*
GPIO_23_CLKREQ*
AH13 VREFG
GPU_VREFG
PP1V0_GPU_DPLL
10UF
TP_GPU_JTAG_TRST_L
TP_GPU_JTAG_TDI
TP_GPU_JTAG_TCK
TP_GPU_JTAG_TMS
TP_GPU_JTAG_TDO
VOLTAGE=1V
1
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
2
0603
XW8600
SM
GPU_PCIE_TX_PWR
GPU_GPIO_TX_DEEMP
GPU_PCIE_GEN2
GPU_SMB_DAT
GPU_SMB_CLK
GPU_AC_BATT
GPU_VCORE_VID0
EG_BKLT_EN
GPU_ROM_SO
GPU_ROM_SI
GPU_ROM_SCLK
GPU_CONFIG_0
GPU_CONFIG_1
GPU_CONFIG_2
DP_T29SNK0_HPD_GPU
GPU_VCORE_VID1
GPU_VCORE_VID2
SMC_GFX_THROTTLE_R_L
DP_T29SNK1_HPD_GPU
SMC_GFX_OVERTEMP_R_L
GPU_VCORE_VID3
FBVDD_ALTVO
GPU_ROM_CS_L
PEX_CLKREQ_L_R
OUT
85 99
A2VSSQ/TSVSSQ AF33
0.1UF
470OHM-1A-150MOHM
PP1V0_S0GPU
AJ21 SWAPLOCKA
AK21 SWAPLOCKB
C8603
CRITICAL
103
74 7
81 75
84 80
OMIT
AK26 SCL
AJ26 SDA
GPU_I2C_SCL
GPU_I2C_SDA
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DP_EXTA_ML_C_P<3>
DP_EXTA_ML_C_N<3>
LVTMDP
DPA
TXCAP_DPA3P AU24
TXCAM_DPA3N AV23
WHISTLER
40NM-ES
- =PP1V0_GPU_TS
5%
1/16W
MF-LF
402 2
DPB
- =PP1V0_GPU_DPLL
5%
1/16W
MF-LF
402 2
10K
FCBGA
(2 OF 9)
MULTI GFX
- =PP1V8_GPU_DPLL
10K
TP_DVPCNTL<0>
TP_DVPCNTL<1>
TP_DVPCNTL<2>
DPC
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
R8613
R86121
10K
10K
- =PP1V8_GPU_VREFG
U8000
WHISTLER
40NM-ES
PLL/CLK
R8610
- =PP3V3_GPU_I2C
NOSTUFF
AP8 DVPCNTL_0
AW8 DVPCNTL_1
AR3 DVPCNTL_2
I2C
R8611
VRAM_HYNIX
DPD
AR8 DVPCNTL_MVP_0
AU8 DVPCNTL_MVP_1
DAC1
OMIT
TP_DVPCNTL_M<0>
TP_DVPCNTL_M<1>
GPIO
DDC/AUX
Page Notes
PP1V8_S0GPU
DAC2
7
81 79 75 7 6
103
THERMAL
BRANCH
PAGE
86 OF 132
SHEET
79 OF 105
1
Unused signals
Native Func
GP
80 79
GPU_PCIE_TX_PWR
80 79
GP
GPU_GPIO_TX_DEEMP
T29 HPD GPU isolation
Native Func
GPIOs
GPU_PCIE_TX_PWR
GP
GPU_VCORE_VID2
82 80 79
79 80
80 79
GP
79 80
80 79
GP
DP_T29SNK1_HPD_GPU
79 80
80 79
GP
79 80
82 80 79
MAKE_BASE=TRUE
GP
80 79
GPU_SMB_DAT
GP
80 79
GPU_SMB_CLK
GP
80 79
GPU_AC_BATT
GP
GPU_VCORE_VID0
GP
80 79
82 80 79
GPU_SMB_CLK
MAKE_BASE=TRUE
GPU_AC_BATT
79 80
MAKE_BASE=TRUE
GPU_VCORE_VID0
GPU_ROM_SO
GP
80 79
GPU_ROM_SI
GP
80 79
EG_BKLT_EN
MAKE_BASE=TRUE
GPU_ROM_SO
MAKE_BASE=TRUE
GPU_ROM_SI
MAKE_BASE=TRUE
80 79
GPU_ROM_SCLK
GP
GPU_CONFIG_0
GP
80 79
GPU_CONFIG_1
GP
80 79
GPU_CONFIG_2
GP
80 79
80 79
DP_T29SNK0_HPD_GPU
GP
GPU_ROM_SCLK
MAKE_BASE=TRUE
GPU_CONFIG_0
MAKE_BASE=TRUE
GPU_CONFIG_1
MAKE_BASE=TRUE
GPU_CONFIG_2
MAKE_BASE=TRUE
DP_T29SNK0_HPD_GPU
MAKE_BASE=TRUE
GP
GPU_VCORE_VID1
87 80 79
80 79
79 80 82
MAKE_BASE=TRUE
GP
82 80 79
GPU_SMB_DAT
MAKE_BASE=TRUE
EG_BKLT_EN
C8741
79 80
MAKE_BASE=TRUE
GPU_PCIE_GEN2
MAKE_BASE=TRUE
88 80 79
79 80 82
MAKE_BASE=TRUE
GPU_GPIO_TX_DEEMP
MAKE_BASE=TRUE
GPU_PCIE_GEN2
100 102
50 51 52 54 57 61 62 72
6 7 12 23 25 26 28 32
35 36 39 40 41 46 48 49
73 80 83 84 85 88 89 91
PP3V3_S0
GPU_VCORE_VID2
79 80
GPU_VCORE_VID1
GPU_ROM_CS_L
GP
84 33
GPU_VCORE_VID3
FBVDD_ALTVO
80 79
NC_GPU_GENERICA
GP
79 80
GPU_ROM_CS_L
80 79
NC_GPU_GENERICB
GP
79 80
79 80
80 79
NC_GPU_GENERICC
80 79
DP_CA_DET_EG_R
GP
79 80
80 79
NC_GPU_GENERICE
GP
79 80
80 79
NC_GPU_GENERICF
GP
79 80
GP
80 79
NC_GPU_GENERICG
DP_EG_HPD
GP
79 80
NC_GPU_GENERICB
PP3V3_S0
79 80
NC_GPU_GENERICE
NO_TEST=TRUE
84 82 80 79 75 72 7 6
79 80
TP_GPU_JTAG_TRST_L
TP_GPU_JTAG_TRST_L
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
99 80 79
99 80 79
99 80 79
99 80 79
MAKE_BASE=TRUE
80 79
GPU_GPIO_TX_DEEMP
80 79
GPU_PCIE_GEN2
NOSTUFF
R87011
10K
MAKE_BASE=TRUE
10K
U8741Y 3
6
DP_T29SNK1_HPD
DP_T29SNK1_HPD_GPU
79 80
ISOLATION Rs for GPU Int Temp Sense
08
NOSTUFF
R8780
GPU_SMB_DAT
GPU_SMB_CLK
80 79
GPU_AC_BATT
1%
1/16W
MF-LF
402 2
NOSTUFF
R87041
10K
1%
1/16W
MF-LF
402 2
10K
88 80 79
EG_BKLT_EN
80 79
GPU_ROM_SO
80 79
GPU_ROM_SI
NOSTUFF
R87071
10K
1%
1/16W
MF-LF
402 2
NOSTUFF
80 79
R87051
GPU_ROM_SI
80 79
GPU_ROM_SCLK
80 79
GPU_CONFIG_0
10K
1%
1/16W
MF-LF
402 2
U8701
GPU_ROM_SCLK_R
6 C
M25P10A
GPU_ROM_CS_L_R
1 S*
33
GPU_ROM_WP_L
NO STUFF
R8722
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
OMIT_TABLE
7 HOLD*
THRM
VSS
PAD
4
9
GPU_ROM_SO 79
VOLTAGE=3.3V
80
C8702
C8703
0.1UF
GPU_ROM:YES
CRITICAL
3 W*
PP3V3_GPU_OSC_100M
2
0402
5%
1/16W
MF-LF
402
UFDFPN8
33
GPU Reference Clocks
0.1UF
10%
16V 2
X5R
402-1
10%
2 16V
X5R
402-1
? BOM OPTION NEED CONFIRMATION HERE!
R8730
CRITICAL
CRITICAL
C8700 1
GPU_CLK100M
OUT
79 99
GPU_CLK27M
OUT
79 99
R8731
GPU_CLK27M_R
5%
1/16W
MF-LF
402
SSEL0 7
SSEL1 3
30PF
5%
50V
CERM 2
402
PP3V3_S0GPU
C8701
5%
50V
2 CERM
402
NOSTUFF
NO STUFF
NO STUFF
1
1
10K
R8750
1%
1/16W
MF-LF
402 2
NOSTUFF
NOSTUFF
R87131
R87141
10K
30PF
5%
1/16W
MF-LF
402
TDFN
1 XIN/CLKIN
SSCLK 5
10 XOUT
REFCLK 9
Y8700
SM-2.5X2.0MM
R87111
R87121
1%
1/16W
MF-LF
402 2
U8700
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
10K
GPU_ROM:YES
10K
GPU_CLK100M_R
SL16010DC
1%
1/16W
MF-LF
402 2
2.2K
5%
1/16W
MF-LF
402 2
84 79
80 79
5%
1/16W
MF-LF
402
R8708
84 17 8
87 80 79
33
GPU_ROM_SO_R
Q2
VOLTAGE=3.3V
L8702
R8726
R8724
NOSTUFF 1
IN
GPU_CONFIG_1
1%
1/16W
MF-LF
402 2
120OHM-0.3A
GPU_ROM:YES
8
VCC
5 D
GPU_ROM_CS_L
84 79
5%
1/16W
MF-LF
402 2
PP3V3_S0
1%
1/16W
MF-LF
402 2
80 79
5%
1/16W
MF-LF
402 2
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
R87101
84 17 8
R8751
2.2K
5%
1/16W
MF-LF
402 2
R87521 R87531
4.7K
5%
1/16W
MF-LF
402
4.7K
5%
1/16W
MF-LF
402
84 82 80 79 75 72 7 6
PP3V3_S0GPU
NO STUFF
R87961 R87971
DP_EG_DDC_CLK
BI
DP_EG_DDC_DATA
IN
DP_IG_DDC_CLK
BI
DP_IG_DDC_DATA
2.2K
5%
1/16W
MF-LF
402
2
80 79
80 79
80 79
DP_CA_DET_EG_R
R8791
PEX_CLKREQ_L_R
R8795
2.2K
5%
1/16W
MF-LF
402
80 79
DP_CA_DET_EG
5%
PEX_CLKREQ_L
5%
IN
1/16W MF-LF 402

1/16W MF-LF 402
OUT
88
8 88
R8798
R8799
10K
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
1%
1/16W
MF-LF
402 2
GPU_CONFIG_2
SMC_GFX_OVERTEMP_L
OUT
45
SMC_GFX_THROTTLE_L
IN
45
EG_LCD_PWR_EN
OUT
79 88
EG_BKLT_EN
OUT
79 80 88
FBVDD_ALTVO
OUT
79 80 87
SYNC_MASTER=K91_MLB
FBVDD_ALTVO
PAGE TITLE
PEX_CLKREQ_L_R
R8793
R8794
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
Whistler GPIOs & STRAPs
R8792
10K
10K
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION
6 31 45 48
51 98
PP3V3_GPU_OSC_27M
2
0402
20%
2 10V
CERM
402
GPU_ROM_SI_R
GPU_ROM_SCLK
84 82 80 79 75 72 7 6
80 79
10K
C8721
0.1UF
R87201 R87211
5%
1/16W
MF-LF
402
GPU_ROM:YES
10K
1%
1/16W
MF-LF
402 2
33
PP3V3_S0GPU
2 4
10K
SMBUS_SMC_0_S0_SCL
120OHM-0.3A
84 82 80 79 75 72 7 6
NOSTUFF
L8703
PP3V3_S0GPU
27MHZ-15PPM-18PF
R87091
6 31 45 48
51 98
NOSTUFF
GPU_ROM:YES
1%
1/16W
MF-LF
402 2
SMBUS_SMC_0_S0_SDA
5%
1/16W
MF-LF
402
R8725
NOSTUFF
1%
1/16W
MF-LF
402 2
GPU_ROM:YES
R87061
R8781
80 79
GPU_SMB_CLK
80 79
GPU_SMB_DAT
80 79
99
79
80
SOT833
79 80 84
10K
80 79
80 79
NO_TEST=TRUE
84 85 88 89 91 100 102
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
R87021
GPU_ROM:YES GPU_ROM:YES
1%
1/16W
MF-LF
402 2
99
79
80
5%
1/16W
MF-LF
402
R8723
R8703
8 74LVC2G08GT
79 80
NO_TEST=TRUE
DP_EG_HPD
MAKE_BASE=TRUE
84 82 80 79 75 72 7 6
NOSTUFF 1
99
79
80
NO_TEST=TRUE
VDD1 4
VDD2 8
GPU_PCIE_TX_PWR
99
79
80
11 THM
PAD
80 79
NO_TEST=TRUE
MAKE_BASE=TRUE
6 VSS1
2 VSS2
79 80
79 80
NO_TEST=TRUE
MAKE_BASE=TRUE
80 79
1%
1/16W
MF-LF
402 2
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_B_CLK_N
NO_TEST=TRUE
PP3V3_S0GPU
10K
79 80
6 79
80
NO_TEST=TRUE
MAKE_BASE=TRUE
R8700
79 80
TP_GPU_JTAG_TMS
Config Straps
NOSTUFF 1
TP_GPU_JTAG_TDO
TP_GPU_JTAG_TMS
MAKE_BASE=TRUE
PP3V3_S0GPU
NO_TEST=TRUE
NC_GPU_GENERICG
84 33
84 82 80 79 75 72 7 6
79 80
79 80
NC_GPU_GENERICF
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
79 80
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
DP_CA_DET_EG_R
MAKE_BASE=TRUE
R8741
79 80
TP_GPU_JTAG_TDO
80 79
NO_TEST=TRUE
NC_GPU_GENERICC
MAKE_BASE=TRUE
NO_TEST=TRUE
79 80
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
80
80 79
79 80
NC_GPU_GENERICA
MAKE_BASE=TRUE
DP_T29SNK0_HPD_GPU 79
08
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
PP3V3_GPU_VDD33_R
MAKE_BASE=TRUE
GP
80 79 6
U8741Y 7
2
79 80
PEX_CLKREQ_L_R
MAKE_BASE=TRUE
79 80 87
MAKE_BASE=TRUE
GP
DP_T29SNK0_HPD
79 80 82
MAKE_BASE=TRUE
PEX_CLKREQ_L_R
84 80 79
CRITICAL
79 80
TP_GPU_JTAG_TCK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
80 79
20%
2 10V
CERM
402
74LVC2G08GT
8
SOT833
79 80
MAKE_BASE=TRUE
80 79
79 80 82
MAKE_BASE=TRUE
FBVDD_ALTVO
GP
80 79
0.1UF
MAKE_BASE=TRUE
GP
79 80 88
79 80
DP_T29SNK1_HPD_GPU
MAKE_BASE=TRUE
GPU_VCORE_VID3
TP_GPU_JTAG_TCK
80 79
GPIOs
BRANCH
PAGE
87 OF 132
SHEET
80 OF 105
1
Page Notes
81
81
PP1V8_GPU_DP_CD
PP1V0_GPU_DP_CD
AP20
AP21
DPCD/DPC_VDD18_AP20
DPCD/DPC_VDD18_AP21
AP13
AT13
DPCD/DPC_VDD10_AP13
DPCD/DPC_VDD10_AT13
AN17
AP16
AP17
AW14
AW16
DP/DPC_VSSR_AN17
DP/DPC_VSSR_AP16
DP/DPC_VSSR_AP17
DP/DPC_VSSR_AW14
DP/DPC_VSSR_AW16
U8000
FCBGA
DPAB/DPA_VDD18_AN24 AN24
DPAB/DPA_VDD18_AP24 AP24
PP1V8_GPU_DP_AB
PP1V0_GPU_DP_AB

81
- =PP1V8_GPU_DP_AB
- =PP1V8_GPU_DP_CD
WHISTLER
(6 OF 9)
40NM-ES
OMIT
DP/DPA_VSSR_AN27
DP/DPA_VSSR_AP27
DP/DPA_VSSR_AP28
DP/DPA_VSSR_AW24
DP/DPA_VSSR_AW26
- =PP1V8_GPU_DP_EF
81
- =PP1V0_GPU_DP_AB
- =PP1V0_GPU_DP_CD
AN27
AP27
AP28
AW24
AW26
- =PP1V0_GPU_DP_EF
(NONE)
AN19
AP18
AP19
AW20
AW22
DP/DPD_VSSR_AN19
DP/DPD_VSSR_AP18
DP/DPD_VSSR_AP19
DP/DPD_VSSR_AW20
DP/DPD_VSSR_AW22
AW18
DPCD_CALR
R8802
150
GPU_DP_CD_CALR
1%
1/16W
MF-LF
402
81
81
81
81
PP1V8_GPU_DP_EF
PP1V0_GPU_DP_EF
150
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
AN29
AP29
AP30
AW30
AW32
R8800
GPU_DP_AB_CALR
DPEF/DPE_VDD18_AH34
DPEF/DPE_VDD18_AJ34
DPAB_VDD18/DPA_PVDD_AU28 AU28
DP_VSSR/DPA_PVSS_AV27 AV27
PP1V8_GPU_DP_AB
AL33
AM33
DPEF/DPE_VDD10_AL33
DPEF/DPE_VDD10_AM33
DPAB_VDD18/DPB_PVDD_AV29 AV29
DP_VSSR/DPB_PVSS_AR28 AR28
PP1V8_GPU_DP_AB
DPCD_VDD18/DPC_PVDD_AU18 AU18
DP_VSSR/DPC_PVSS_AV17 AV17
PP1V8_GPU_DP_CD
DPCD_VDD18/DPD_PVDD_AV19 AV19
DP_VSSR/DPD_PVSS_AR18 AR18
PP1V8_GPU_DP_CD
AN34
AP39
AR39
AU37
DP/DPE_VSSR_AN34
DP/DPE_VSSR_AP39
DP/DPE_VSSR_AR39
DP/DPE_VSSR_AU37
PP1V8_GPU_DP_EF
AF34
AG34
DPEF/DPF_VDD18_AF34
DPEF/DPF_VDD18_AG34
DPEF_VDD18/DPE_PVDD_AM37 AM37
DP_VSSR/DPE_PVSS_AN38 AN38
PP1V8_GPU_DP_EF
PP1V0_GPU_DP_EF
AK33
AK34
DPEF/DPF_VDD10_AK33
DPEF/DPF_VDD10_AK34
DPEF_VDD18/DPF_PVDD_AL38 AL38
DP_VSSR/DPF_PVSS_AM35 AM35
PP1V8_GPU_DP_EF
AF39
AH39
AK39
AL34
AM34
DP/DPF_VSSR_AF39
DP/DPF_VSSR_AH39
DP/DPF_VSSR_AK39
DP/DPF_VSSR_AL34
DP/DPF_VSSR_AM34
AM39
DPEF_CALR
GPU_DP_EF_CALR
DP/DPB_VSSR_AN29
DP/DPB_VSSR_AP29
DP/DPB_VSSR_AP30
DP/DPB_VSSR_AW30
DP/DPB_VSSR_AW32
81
AH34
AJ34
R8801
1
PP1V0_GPU_DP_AB
DPAB_CALR AW28
DP E/F PWR
DPAB/DPB_VDD10_AN33 AN33
DPAB/DPB_VDD10_AP33 AP33
(NONE)
81
81
150
1%
1/16W
MF-LF
402
81
81
81
81
81
1%
1/16W
MF-LF
402
L8801
L8800
300mA
PP1V8_GPU_DP_AB
470OHM-1A-150MOHM
PP1V8_S0GPU
C8800
10UF
C8801
1UF
20%
10V
2 X5R
603
10%
25V
2 X5R
402
C8812
10UF
20%
2 10V
X5R
603
C8813
1UF
C8803
10UF
20%
2 10V
X5R
603
C8804
103 81 79 75 74 7
PP1V0_S0GPU
81
10%
2 25V
X5R
402
10%
2 25V
X5R
402
C8806
10UF
20%
2 10V
X5R
603
C8807
1UF
10%
2 25V
X5R
402
C8815
10UF
20%
10V
2 X5R
603
C8816
1UF
10%
25V
2 X5R
402
L8803
81 103 81 79 75 74 7
0.1UF
10%
2 16V
X5R
402-1
81
C8817
0.1UF
10%
16V
2 X5R
402-1
220mA
PP1V0_GPU_DP_EF
470OHM-1A-150MOHM
PP1V0_S0GPU
81
AF21
AG2
AG6
AG9
AG17
AG20
AG22
AH21
AJ2
AJ6
AJ10
AJ11
AJ28
AK7
AK11
AK31
AL2
AL6
AL8
AL11
AL14
AL17
AL20
AL23
AL26
AL32
AM9
AM11
AM31
AN2
AN6
AN8
AN11
AN30
AP7
AP9
AP11
AR5
B7
B9
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
C1
C39
E5
E35
F7
F9
F11
F13
F15
F17
F19
F21
F23
F25
F27
F29
VOLTAGE=1V
1
VOLTAGE=1.8V
0603
C8814
300mA
PP1V8_GPU_DP_EF
A39 VSS_MECH_A39
AW1 VSS_MECH_AW1
AW39 VSS_MECH_AW39
OMIT
A3
A37
AA2
AA6
AA16
AA18
AA21
AA23
AA26
AA28
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC2
AC6
AC11
AC13
AC16
AC18
AC21
AC23
AC26
AC28
AD9
AD15
AD17
AD20
AD22
AD24
AD27
AE2
AE6
AF10
AF16
AF18
C8805
220mA
PP1V0_GPU_DP_CD
0603
10%
2 16V
X5R
402-1
L8802
1UF
470OHM-1A-150MOHM
0.1UF
470OHM-1A-150MOHM
103 81 79 75 7 6
VOLTAGE=1.8V
PCIE_VSS_G33
PCIE_VSS_G34
PCIE_VSS_H31
PCIE_VSS_H34
PCIE_VSS_H39
PCIE_VSS_J31
PCIE_VSS_J34
PCIE_VSS_K31
PCIE_VSS_K34
PCIE_VSS_K39
PCIE_VSS_L31
PCIE_VSS_L34
PCIE_VSS_M34
PCIE_VSS_M39
PCIE_VSS_N31
PCIE_VSS_N34
PCIE_VSS_P31
PCIE_VSS_P34
PCIE_VSS_P39
PCIE_VSS_R34
PCIE_VSS_T31
PCIE_VSS_T34
PCIE_VSS_T39
PCIE_VSS_U31
PCIE_VSS_U34
PCIE_VSS_V34
PCIE_VSS_V39
PCIE_VSS_W31
PCIE_VSS_W34
PCIE_VSS_Y34
PCIE_VSS_Y39
(8 OF 9)
GND_A3
GND_A37
GND_AA2
GND_AA6
GND_AA16
GND_AA18
GND_AA21
GND_AA23
GND_AA26
GND_AA28
GND_AB12
GND_AB15
GND_AB17
GND_AB20
GND_AB22
GND_AB24
GND_AB27
GND_AC2
GND_AC6
GND_AC11
GND_AC13
GND_AC16
GND_AC18
GND_AC21
GND_AC23
GND_AC26
GND_AC28
GND_AD9
GND_AD15
GND_AD17
GND_AD20
GND_AD22
GND_AD24
GND_AD27
GND_AE2
GND_AE6
GND_AF10
GND_AF16
GND_AF18
VOLTAGE=1V
L8805
2
0603
C8802
300mA
PP1V8_GPU_DP_CD
0603
PP1V8_S0GPU
10%
16V
2 X5R
402-1
L8804
PP1V8_S0GPU
PP1V0_S0GPU
0.1UF
470OHM-1A-150MOHM
103 81 79 75 7 6
103 81 79 75 74 7
81
VOLTAGE=1.8V
0603
220mA
PP1V0_GPU_DP_AB
470OHM-1A-150MOHM
PCIE_VSS_AB39
PCIE_VSS_E39
PCIE_VSS_F34 U8000
FCBGA
PCIE_VSS_F39
81
VOLTAGE=1V
0603
C8808
0.1UF
C8809
10UF
10%
2 16V
X5R
402-1
20%
2 10V
X5R
603
C8810
1UF
10%
2 25V
X5R
402
C8811
GND_AF21
GND_AG2
GND_AG6
GND_AG9
GND_AG17
GND_AG20
GND_AG22
GND_AH21
GND_AJ2
GND_AJ6
GND_AJ10
GND_AJ11
GND_AJ28
GND_AK7
GND_AK11
GND_AK31
GND_AL2
GND_AL6
GND_AL8
GND_AL11
GND_AL14
GND_AL17
GND_AL20
GND_AL23
GND_AL26
GND_AL32
GND_AM9
GND_AM11
GND_AM31
GND_AN2
GND_AN6
GND_AN8
GND_AN11
GND_AN30
GND_AP7
GND_AP9
GND_AP11
GND_AR5
GND_B7
GND_B9
GND_B11
GND_B13
GND_B15
GND_B17
GND_B19
GND_B21
GND_B23
GND_B25
GND_B27
GND_B29
GND_B31
GND_B33
GND_C1
GND_C39
GND_E5
GND_E35
GND_F7
GND_F9
GND_F11
GND_F13
GND_F15
GND_F17
GND_F19
GND_F21
GND_F23
GND_F25
GND_F27
GND_F29
U8000
FCBGA
(9 OF 9)
40NM-ES
DPCD/DPD_VDD10_AP14
DPCD/DPD_VDD10_AP15
PP1V8_GPU_DP_AB
WHISTLER
AP14
AP15
WHISTLER
40NM-ES
PP1V0_GPU_DP_CD
DP A/B PWR
DPCD/DPD_VDD18_AP22
DPCD/DPD_VDD18_AP23
DP C/D PWR
AP22
AP23
DP OLL POWER
81
81
103 81 79 75 7 6
PP1V8_GPU_DP_CD
OMIT
GND_F31
GND_F33
GND_G2
GND_G6
GND_H9
GND_J2
GND_J6
GND_J8
GND_J27
GND_K7
GND_K14
GND_L2
GND_L6
GND_L11
GND_L17
GND_L22
GND_L24
GND_M17
GND_M22
GND_M24
GND_N2
GND_N6
GND_N16
GND_N18
GND_N21
GND_N23
GND_N26
GND_R2
GND_R6
GND_R15
GND_R17
GND_R20
GND_R22
GND_R24
GND_R27
GND_T11
GND_T13
GND_T16
GND_T18
GND_T21
GND_T23
GND_T26
GND_U2
GND_U6
NC/GND
GND_U15
GND_U17
GND_U20
GND_U22
GND_U24
GND_U27
GND_V11
NC/GND
GND_V16
GND_V18
GND_V21
GND_V23
GND_V26
GND_W2
GND_W6
GND_Y15
GND_Y17
GND_Y20
GND_Y22
GND_Y24
GND_Y27
GND/PX_EN
F31
F33
G2
G6
H9
J2
J6
J8
J27
K7
K14
L2
L6
L11
L17
L22
L24
M17
M22
M24
N2
N6
N16
N18
N21
N23
N26
R2
R6
R15
R17
R20
R22
R24
R27
T11
T13
T16
T18
T21
T23
T26
U2
U6
U13
U15
U17
U20
U22
U24
U27
V11
V13
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
AL21
NC
0.1UF
10%
2 16V
X5R
402-1
SYNC_MASTER=K92_BEN
PAGE TITLE
Whistler DP PWR/GNDs
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
88 OF 132
SHEET
81 OF 105
8
67 46 44
29 7 6
43 42 31
104 72
6
5
GPU VCore Regulator
VOLTAGE=5V
C8902 1
10
0.01uF
87 50 7
10%
2 16V
CERM
402
CRITICAL
20%
16V
POLY-TANT 2
CASE-D2E-SM
PP5V_S3_GFXIMVP6_VDD
1
16
1uF
VDD
R8905
2
GFXIMVP6_RBIAS
49
91 88 87 74 8
OUT
82
82
R8910
82
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
82
82
91 88
IN
R8924
100
1%
1/16W
MF-LF
402 2
VOLTAGE=0V
20
C8920
14
UGATE
18
BOOT
17
28
31
23
24
25
26
27
29
30
32
C8923
Q8950
RJK0365DPA-02
SOFT
WPAK
GFXIMVP6_BOOT
CRITICAL
C8956 1
1 2 3
0.22UF
IMON
10%
16V 2
X7R
603
PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE
PHASE
1%
1W
MF-1
0612
0.56UH-31A
1
PPVCORE_GPU_REG_R
FDU1040D-SM
SWITCH_NODE=TRUE
DIDT=TRUE
Vout = 0.75V - 0.90V
0.001
L8920
GFXIMVP6_PHASE
19
R8940
CRITICAL
VOLTAGE=1.2V
2
4
PPVCORE_GPU
1
3
C8966 1
C8969 1
LGATE
GFXIMVP6_LGATE
21
GATE_NODE=TRUE
CRITICAL
RJK0208DPA
20%
6.3V 2
X5R
603
WPAK
C8967
10%
6.3V
2 X5R-CERM
603
8
9
VSEN
RTN
C8942 1
20%
6.3V 2
X5R
603
10UF
10%
50V 2
X7R
402
Q8951
10UF
C8968 1
0.001UF
330UF
20%
2.0V
POLY-TANT 2 3
D2T-SM2
C8965
CRITICAL
10UF
20%
2 6.3V
X5R
603
6 7 49 75 82
30A max output

(L8920 limit)
CRITICAL
C8943
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
1 2 3
C8921 1
10%
50V
CERM 2
402
GFXIMVP6_VW
R89091
7.15K
C8950
330PF
GFXIMVP6_COMP_RC
1
R8950
150K
VW
C8922
R89031
10%
2 50V
X7R
402
1K
GFXIMVP6_COMP
1
COMP
VO
OCSET
10%
2 50V
CERM
402
ISP
ISN
R8953
ICOMP
VDIFF
PGND
VSS
VID4
1%
1/16W
MF-LF
402
THRM_PAD
VID2
VID1
0
VID0
1
0.74675V
K18
Balanced
5%
50V 2
COG
402
0.82400V
K18
0.90125V
Max perf
K18
C8971
1
68PF
1
(PPVCORE_GPU_REG)
1%
1/16W
MF-LF
2 402
GPU VCore Setpoints not up-to-date!
5%
50V
CERM
402-1
C8972 1
0.001UF
10%
50V
CERM 2
402
VOLTAGE=0V
XW8900
SM
PP3V3_S0GPU
C8906 1
9.09K
GND_GFXIMVP6_AGND
84 82 80 79 75 72 7 6
Max Batt
R8901
GFXIMVP6_DROOP
353S2289
VID3
9.76K
10
Voltage
330PF
GFXIMVP6_DFB
R8902
GFXIMVP6_VDIFF
10%
25V
CERM
402
1%
1/16W
MF-LF
402
11
1%
1/16W
MF-LF
2 402
20
13
GPU VCore Setpoints
7.32K2
33
C8951
0.0068UF
2
GFXIMVP6_VDIFF_RC 1
R8900
GFXIMVP6_OCSET
3.01K
15
1%
1/16W
MF-LF
402
2
FB
150
GFXIMVP6_VO
12
GFXIMVP6_VSUM
GFXIMVP6_FB
R8951
1%
1/16W
MF-LF
402 2
C8952
330PF
1%
1/16W
MF-LF
2 402
GFXIMVP6_PHASE_VSUM
10%
2 50V
CERM
402
0.001UF
1%
1/16W
MF-LF
402 2
10%
50V
CERM
402
C8953
680pF
CRITICAL
GFXIMVP6_UGATE
DIDT=TRUE
GFXIMVP6_IMON
QFN
10%
2 50V
CERM
402
(GFXIMVP6_AGND)
5%
1/16W
MF-LF
402
GFXIMVP6_VIN
0.001UF 0.001UF
10%
2 50V
CERM
402
100
VIN
R8925
1%
1/16W
MF-LF
402
GFXIMVP6_SOFT
GFXIMVP6_VSEN_P
GFXIMVP6_VSEN_N
0.001UF
R8908
1
U8900
5%
1/16W
MF-LF
402
GPU_GND_SENSE
1K
5%
1/16W
MF-LF
402 2
4.7UF
R8920
1
R89301
DIDT=TRUE
GPU_VDD_SENSE
20%
2 16V
POLY-TANT
CASE-D2E-SM
10%
2 50V
X7R
402
PVCC
ISL6263C
PM_ALL_GPU_PGOOD
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
GPUVCORE_EN
GFXIMVP6_AF_EN
GFXIMVP6_FDE
OUT
PP3V3_S0GPU
10K
RBIAS
0.033UF
10%
16V
X5R
402
R89071
C8904
2
VOLTAGE=1.25V
C8931
68UF
0.001UF
10%
25V 2
X5R
603-1
CRITICAL
150K 1
1%
1/16W
MF-LF
402
20
C8934
C8901
10%
2 10V
X5R
402
PPVCORE_GPU
CRITICAL
1
1UF
X5R
603-1
VOLTAGE=5V
1%
1/16W
MF-LF
402
C8932
1UF
10% C8933 1
2 25V
C8930 1
68UF
22
75
C8903
2.2UF
R8904
75
PP5V_S3_GFXIMVP6_PVCC
20%
10V
X5R-CERM 2
402
82 75 49 7 6
R8911
PP5V_S3
5%
1/16W
MF-LF
402
84
79 75 72 7 6
82 80
K92 Default Vcore Setpoints
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
GPUVID_1P11V
GPUVID4_0,GPUVID3_0,GPUVID2_1,GPUVID1_1,GPUVID0_1
TABLE_BOMGROUP_ITEM
R8990
80 79
IN
GPU_VCORE_VID0
5%
1/16W
MF-LF
402
GPUVID0_1
GPUVID1_1
GPUVID2_1
GPUVID3_1
GPUVID4_1
R89871
R89841
R89821
R89951
R89911
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2.2K
2.2K
2.2K
2.2K
2.2K
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
R8993
80 79
IN
GPU_VCORE_VID1
5%
1/16W
MF-LF
402
80 79
IN
82
82
82
82
GPUVID0_0
GPUVID1_0
GPUVID2_0
GPUVID3_0
GPUVID4_0
R89881
R89851
R89831
R89961
R89921
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2.2K
5%
1/16W
MF-LF
402
2.2K
2.2K
2.2K
GPU (Whistler) CORE SUPPLY

DRAWING NUMBER
Apple Inc.
2.2K
80 79
IN
GPU_VCORE_VID3

5%
1/16W
MF-LF
402
SIZE
D
REVISION
R8998
0
PAGE TITLE
R8994
GPU_VCORE_VID2
82
BRANCH
PAGE
89 OF 132
SHEET
82 OF 105
D
88
IN
LCD_PWR_EN
R9094 1
10K
LCD (LVDS) INTERFACE
5%
1/16W
MF-LF
402 2
CRITICAL
U9000
FPF1009
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 73 72
PP3V3_S5
ON
VIN_1
VOUT_1
VIN_2
VOUT_2
GND
1
C9009
0.1UF
CRITICAL
MFET-2X2
L9000
FERR-250-OHM
PP3V3_SW_LCD_UF
VOLTAGE=3.3V
THRM
PAD
C9011
0.1UF
10%
16V
X5R
402-1
C9001
C9012
10UF
10%
16V
X5R
402-1
2
SM
C9002
0.1UF
0.001UF
10%
16V
X5R
402-1
10%
50V
X7R
402
20%
6.3V
X5R
603
CRITICAL
J9000
20474-040E-11
F-RT-SM
41
102 100 91 89 88 85
46 41 40 39 36 35 32 28 26 25 23 12 7 6
84 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
42
100K pull-ups are for

no-panel case (development).
Panel has 2K pull-ups
84 6
84 6
R9010
R9011
100K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PP3V3_SW_LCD
VOLTAGE=3.3V
3
4
NC
LVDS_DDC_CLK
LVDS_DDC_DATA
6
7
99 84 6
C9010
99 84 6
8
9
0.001UF
10%
50V
X7R
402
10
99 84 6
99 84 6
11
12
CRITICAL
13
L9010
90-OHM-100MA
99 84 6
DLP11S
SYM_VER-1
99 84
LVDS_CONN_A_CLK_N
99 84 6
LVDS_CONN_A_CLK_P
14
15
16
99 6
99 84
99 6
1
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
17
18
19
Place close to the connector
99 84 6
99 84 6
20
21
22
99 84 6
99 84 6
23
24
CRITICAL
25
L9011
90-OHM-100MA
DLP11S
99 84 6
SYM_VER-1
99 84 6
99 84
LVDS_CONN_B_CLK_N
99 84
LVDS_CONN_B_CLK_P
26
27
28
89 6
Place close to the connector
89 6
89 6
89 6
89 6
89 6
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
99 6
29
99 6
30
31
32
33
34
35
518S0651
36
NC
37
38
39
103 89 6
PPVOUT_S0_LCDBKLT
40
C9008
43
1000PF
44
10%
100V
X7R
603
SYNC_MASTER=K17_MLB
PAGE TITLE
LVDS Display Connector

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
90 OF 132
SHEET
83 OF 105
102 100 91 89 88 85 84 83 80 73
39 36 35 32 28 26 25 23 12 7 6
72 62 61 57 54 52 51 50 49 48 46 41 40
All emulated LVDS outputs require this termination
R92021
R9220
1
357
LVDS_CONN_A_CLK_P
OUT
5%
1/16W
MF-LF
402 2
1%
1/20W
MF
201
C9220
0.1UF
10K
83 99
20%
2 10V
CERM
402
18
IN
LVDS_A_CLK_P
PP3V3_S0
PLACE_NEAR=U9600.A6:7mm
99 88
DP AUX, DDC, & HPD muxing to IG/EG
LVDS Transmitter Termination

D
C9230
0.1UF
20%
2 10V
CERM
402
VDD
U9220
R9222
99 88
IN
LVDS_A_CLK_N
357
99 88
IN
LVDS_CONN_A_CLK_N
1%
1/20W
MF
201
IN
LVDS_A_DATA_N<0>
IN
LVDS_A_DATA_P<1>
357
OUT
6 83 99
R9227
1
357
1%
1/20W
MF
201
357
OUT
OUT
99 88
IN
IN
80 17 8
IN
80 17 8
BI
80 79
IN
80 79
BI
14
13
DAUX2+
DAUX2-
DP_IG_DDC_CLK
DP_IG_DDC_DATA
12
11
DDC_CLK1
DDC_DAT1
DP_EG_DDC_CLK
DP_EG_DDC_DATA
DDC_CLK2
DDC_DAT2
DP_IG_HPD
10
HPD_1
OUT
DP_EG_HPD
HPD_2
GPU_SEL
100K
88
IN
DP_MUX_SEL_EG
IN
DP_MUX_EN
15
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
20
AUX+
AUX-
CRITICAL
DDC_CLK
DDC_DAT
HPDIN
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
OUT
BI
85 99
BI
85 99
OUT
BI
85
85
T29/DP HOT PLUG IN
(DP_EXTA_HPD)
T29_DP_HPD:MUX_GMUX
R9206
XSD*
DP_EXTA_HPD
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
GND
102 100 91 89 88 85 84 83 80 73
40 39 36 35 32 28 26 25 23 12 7 6
72 62 61 57 54 52 51 50 49 48 46 41
6 83 99
PP3V3_S0
T29_DP_HPD:ALL_OR
1%
1/20W
MF
201
99 88
BI
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
OUT
5%
1/16W
MF-LF
402 2
99 79
DAUX1+
DAUX1-
17 8
100K
BI
17
16
19
LVDS_A_DATA_N<1>
99 79
88
R9232
357
BI
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
80 79
R92041 R92051
201
PLACE_NEAR=U9600.C10:7mm
BI
94 17 8
6 83 99
1%
PLACE_NEAR=U9600.A9:7mm 1/20W
MF
94 17 8
6 83 99
1%
1/20W
MF
201
R9230
99 88
BGA
83 99
R9225
LVDS_A_DATA_P<0>
99 88
CBTL03062
OUT
C9210 1
R9235
LVDS_A_DATA_P<2>
357
OUT
6 83 99
1%
1/20W
MF
201
80
CRITICAL T29_DP_HPD:ALL_OR
8
74LVC2G32GT
5
33 DP_T29SNK0_HPD
SOT833
A
80 33
DP_T29SNK1_HPD
U9210Y
0.1UF
20%
10V
CERM 2
402
T29_HOTPLUG_DET_OR
LVDS_A_DATA_N<2>
IN
LVDS_B_CLK_N
IN
357
LVDS_CONN_B_CLK_N
LVDS_B_DATA_P<0>
IN
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
99 88
IN
LVDS_B_DATA_N<1>
357
IN
OUT
83 99
357
Q9280
SSM3K15FV
SOD-VESM-HF
OUT
6 83 99
85 46
357
OUT
6 83 99
OUT
6 83 99
1%
1/20W
MF
201
82 80 79 75 72 7 6
357
LVDS_B_DATA_P<2>
OUT
6 83 99
OUT
6 83 99
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
357
IN
LVDS_B_DATA_N<2>
5%
1/16W
MF-LF
402 2
C9270
357
R92721
DP_A_EXT_HPD
R9281
100K
5%
1/16W
MF-LF
402
20%
10V
CERM 2
402
OUT
6 83 99
VCC
88
IN
LVDS_DDC_SEL_EG
13
88
IN
LVDS_DDC_SEL_IG
1%
1/20W
MF
201
12
U9270
QFN1
C1
C2
C3
C4
R9271
20K
5%
1/16W
MF-LF
2 402
R9273
20K
5%
1/16W
MF-LF
402 2
14
20K
0.1UF
1%
1/20W
MF
201
R9257
99 88
20K
PP3V3_S0
R9255
IN
T29_DP_HPD:MCU_GMUX
PP3V3_S0GPU
R92701
R9252
1
102
51 52 54 57 61 62 72 73
6 7 12 23 25 26 28 32 35
36 39 40 41 46 48 49 50
80 83 84 85 88 89 91 100
LVDS DDC MUX
1%
1/20W
MF
201
1%
1/20W
MF
201
99 88
5%
1/16W
MF-LF
2 402
LVDS_EG_DDC_CLK
IN
79
LVDS_IG_DDC_CLK
LVDS_DDC_CLK
IN
18
OUT
A1 2
B1
A2 3
B2
8
LVDS_EG_DDC_DATA
11
LVDS_IG_DDC_DATA
LVDS_DDC_DATA
A3 9
B3
6 83
SYNC_MASTER=K92_YUN
PAGE TITLE
BI
Muxed Graphics Support
79
DRAWING NUMBER
A4 10
B4
GND THRM
CRITICAL
7
15
BI
18
BI
6 83
Apple Inc.
SIZE
D
REVISION

88
R9247
1
OUT
T29_DP_HPD:MCU_GMUX
1%
1/20W
MF
201
R9250
99 88
DP_HOTPLUG_DET
R9245
IN
SOT833
7
U9210Y
83 99
PP3V3_S0
99 88
OUT
R9242
1%
1/20W
MF
201
99 88
LVDS_CONN_B_CLK_P
IN
G 1
99 88
85
1%
1/20W
MF
201
(DP_EXTA_HPD)
T29_DP_HPD:ALL_OR
74LVC2G32GT
LVDS_B_CLK_P
6 83 99
IN
8
OUT
99 88
1%
1/20W
MF
201
R9240
357
IN
357
SN74LV4066A
99 88
R9237
BRANCH
PAGE
92 OF 132
SHEET
84 OF 105
3
8 6
IN
C9300
DP_EXTA_ML_C_P<0>
99 79
IN
C9301
DP_EXTA_ML_C_N<0>
IN
C9302
DP_EXTA_ML_C_P<1>
IN
C9303
DP_EXTA_ML_C_N<1>
IN
C9304
DP_EXTA_ML_C_P<2>
IN
C9305
DP_EXTA_ML_C_N<2>
IN
DP_EXTA_ML_C_P<3>
C9306
99 79
IN
DP_EXTA_ML_C_N<3>
C9307
BI
C9308
BI
C9309
DP_EXTA_AUXCH_C_N
0.47UF
C9371 1
IN
DP_EXTA_ML_N<2>
L9372
97 33 6
IN
T29_R2D_C_N<0>
T29_R2D_C_P<0>
85
16V
402
(C9372.2)
10%
X5R
DP_EXTA_ML_N<3>
85
16V
402
R9309
10%
X5R
8 6
DP_EXTA_AUXCH_N
16V
402
R9308
OUT
97 33 6
OUT
(All 4 Ls)
8 6
T29_D2R_N<1>
T29_D2R_P<1>
97 33 6
IN
97 33 6
IN
0.47UF
L9382
T29_R2D_C_N<1>
T29_R2D_C_P<1>
1.0NH+/-0.1NH
L9383
R9354
5%
MF
30
(C9383.2)
2
0201-1
2
0201-1
8 6
A1
0
0
1
1
A0
0
1
0
1
20%
2 10V
CERM
402
1
1
20%
2 10V
CERM
402
R9351
5%
MF
30
85 6
Note: Other Parade

devices use 96/B6,
so only 94/B4 are
used for this part.
85
85 6
85
85 6
NO STUFF
1
R9311
1K
5%
1/16W
MF-LF
402 2
85
R9310
1K
5%
1/16W
MF-LF
2 402
84
IN
84
BI
85
85
R9312
84
1K
OUT
5%
1/16W
MF-LF
2 402
IN
48
BI
B
23 16
IN
R9318
0
5%
1/16W
MF-LF
402 1
R9319
4.99K
1%
1/16W
MF-LF
2 402
OUT_D3P
OUT_D3N
23
22
14 IN_SCL
13 IN_SDA
AC_AUXP
AC_AUXN
20
19
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
R9352
97
97
C9363
DP_SDRVA_ML_C_P<1>
DP_SDRVA_ML_C_N<1>
97
97
97
1
1
0.1uF
C9367
DP_SDRVA_ML_C_P<3>
DP_SDRVA_ML_C_N<3>
0.1uF
C9366
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
0.1uF
2
10%
X5R
2
10%
X5R
2
10%
X5R
2
10%
X5R
16V
402
I2C_DPSDRVA_SCL
I2C_DPSDRVA_SDA
11
DPSDRVA_CEXT
C9319
DP_AUXCH_ISOL
39 AUXDDC_OFF (IPD)
0.1uF
C9368
85 88
0.1uF
2
10%
X5R
2
10%
X5R
22
20%
2 10V
CERM
402
OUT
33
OUT
OUT
T29_MCU_INT_L
86
86 85
use PCIe WAKE#

PCIE_WAKE_L
OMIT
OUT
R93301
18
IN
OUT
10
11
12
13
14
15
51
5%
1/16W
MF-LF
2 402
C9331
SWCLK
0
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
1 402
IN
86
IN
86
85
86 85
10K
T29_A_HV_EN
OUT
DP_SDRVA_ML_N<1>
DP_SDRVA_ML_P<1>
27
26
DIN1_1+
DIN1_1-
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
19
18
AUX1+
AUX1-
DP_SDRVA_HPD
17
HPD_1
5%
1/16W
MF-LF
2 402
201 MF
5% 1/20W
R9363
2
51
201 MF
DP_A_BIAS_P_0
5%
1
1/20W
R9367
2
51
201 MF
5% 1/20W
23
22
DIN2_1+
DIN2_1-
T29_D2R1_BIASP
T29_D2R1_BIASN
15
14
AUX2+
AUX2-
13
HPD_2
10
32
11
GPU_SEL
AUX_SEL
NC
DP_A_PWRDWN
T29_A_BIAS
P2R = Plug to Receptacle

R2P = Receptacle to Plug
IN
R9336
10K
R9339
20%
402
5%
1/16W
MF-LF
2 402
U9390
CBTL04DP081
HVQFN
DOUT_0+ 1
DOUT_0- 2
T29DPA_ML_N<3>
T29DPA_ML_P<3>
T29: Unused
OUT
6 86 97
6 86 97
BI
T29DPA_ML_N<1>
BI 6 86 97
T29DPA_ML_P<1>
OUT 6 86 97
T29: LSX_A_R2P/P2R (P/N)
OMIT_TABLE
AUX+ 6
AUX- 7
DP_A_EXT_AUXCH_P BI
DP_A_EXT_AUXCH_N BI
T29: RX_1 Bias Sink
HPD_IN 8
DP_A_EXT_HPD
IN
86 97
86 97
46 84 85
R9398
100K
5%
1/16W
MF-LF
2 402
LO=Port A
HI=Port B
THMPAD GND
SIGNAL_MODEL=T29DP_MUX
U9390 BOM table in csa 5!!!
Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

Display can detect host T29 support using I2C
pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sinks
detection of DP Source.
SYNC_MASTER=K91_MLB
PAGE TITLE
DRAWING NUMBER
1M
5%
1/16W
MF-LF
2 402
Apple Inc.
SIZE
D
REVISION
5%
1/16W
MF-LF
2 402

C9391
2 10V
CERM
DisplayPort/T29 A MUXing
33
0.1UF
20%
2 10V
CERM
402
100K
VDD
DOUT_1+ 4
DOUT_1- 5
DIN2_0+
DIN2_0-
C9390
0.1UF
CRITICAL
(T29_A_LSX_P2R)
(T29_A_LSX_R2P)
35 86
T29_A_UC_ADDR
R9330 provides pads for programming/debug of MCU, please make accessible.
If project has space for 10-pin programming header it should be used.
DIN1_0+
DIN1_0-
5%
1/16W
MF-LF
402
85
46 84 85
SWDIO
DP_SDRVA_ML_N<3>
DP_SDRVA_ML_P<3>
31
30
R9334
1K
VOLTAGE=3.3V
R9399
CBTL04DP081 (353S3151) and

PI3vEDP212 (353S3055) are
footprint-compatible parts with
similar pinouts. NXP uses pin
10 for ML and HPD, Pericom uses
pin 10 for ML and pin 11 for HPD.
5%
1/16W
MF-LF
402 2
I2C Addr:
0x26/0x27 (Wr/Rd)
R9335
DP_A_BIAS
NC
1K
85
51
DP_A_BIAS_P_22
VOLTAGE=3.3V
R9397
10K
20%
2 10V
CERM
402
1/20W
201
1/20W
201
8 6
R9338
0.1UF
T29_A_LSX_P2R
T29_A_LSX_R2P
T29_LSEO<1>
R9366
PP3V3_SW_DPAPWR
86 85
Must be 3.3V DP A port power
R9393
T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
T29_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD
16
17
18
19
20
PIO0_6/SCK
PIO1_6/RXD 23
PIO0_7/CTS#
PIO1_7/TXD 24
PIO1_8/CT16B1_CAP0 6
PIO0_8/MISO/CT16B0_MAT0
PIO0_9/MOSI/CT16B0_MAT1
SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD)
R/PIO0_11/AD0 (OD)
THRM
XTALIN 4
VSS
PAD
3
32 31 25 17 6
BI
HVQFN25
1 RESET#/PIO0_0
R/PIO1_0/AD1
2 PIO0_1/CLKOUT
R/PIO1_1/AD2
7 PIO0_2/SSEL/CT16B0_CAP0
R/PIO1_2/AD3
(IPU) SWDIO/PIO1_3/AD4
8 PIO0_4/SCL (OD)
PIO1_4/AD5/WAKEUP
9 PIO0_5/SDA (OD)
5%
MF
5%
MF
51
201 MF 5% 1/20W
VOLTAGE=3.3V
86 97
DP/T29 A Low-Speed MUX
1K
25
33
I2C_T29_SCL
I2C_T29_SDA
T29DPA_HPD
T29_A_BIAS
T29_LSOE<0>
T29_LSOE<1>
97 48 33
=T29_WAKE_L:
T29_LSEO<0>
DP_A_BIAS_N_2
1/20W
2018 6 DP_A_BIAS_N_0
U9359
74LVC1G04DBDCK
97
5%
1/16W
MF-LF
402 1
OMIT_TABLE
1.5K
CRITICAL
5
2
Must be 3.3V DP A port power

5
IN
5%
MF
1.5K
86 97
OUT
R9362
DP Path Biasing
R9361 1.5K 1
2
5% 1/20W
MF
201
R9360 1.5K 1
2
R9365
R9364
6 86 97
OUT
8 6
16V
402
R9396
21
IN
97 6
6 86 97
IN
R9384
R9385
VOLTAGE=3.3V
6.3V
201
VDD
(D9382/D9383)
DP_SDRVA_ML_P<2>
DP_SDRVA_ML_N<2>
97
5%
1/16W
MF-LF
402 2
0.1UF
IN
GND_VOID=TRUE (D9382/D9383)
GND_VOID=TRUE (D9361.2)
GND_VOID=TRUE
1.5K 1
2
GND_VOID=TRUE
5% 1/20W
201
1.5K 1
2 MF
5% 1/20W
MF
201
SIGNAL_MODEL=T29PIN
CKPLUS_WAIVE=NdifPr_badTerm
25
T29_A_RSVD_N
24
T29_A_RSVD_P
U9330
33
97 6
16V
402
LPC1112A
97 48 33
6.3V
201
C9330
TSLP-2-7
8 6
97
(D9360/D9361)
97
1/20W
201
1/20W
201
SIGNAL_MODEL=EMPTY
97
51
CRITICAL
DP_A_CA_DET
97 6
D9361
DP_SDRVA_ML_P<0>
DP_SDRVA_ML_N<0>
97
THMPAD
PP3V3_SW_DPAPWR
5%
MF
5%
MF
(D9360.2)
R93921
GND
34 PD (IPD)
86 85
88 85
97 6
TSLP-2-7
TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 Ds)
6.3V
201
2
20%
X5R
2
20%
X5R
D
1
T29: TX_1
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
BAR90-02LRH
GND_VOID=TRUE
TSLP-2-7
D9383
R9383
20%
6.3V
CERM 2
402-LF
PS8301 has internal

~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).
2.2UF
12 REXT
D9382
5% 1/20W
MF 201
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U9310.11:2 mm
DPSDRVA_REXT
DP_A_PWRDWN
1.5K
6.3V
201
86 97
GND_VOID=TRUE
R9374 1.5K
R9375 1.5K
GND_VOID=TRUE
BAR90-02LRH
GND_VOID=TRUE
DP_A_PWRDWN
Port A MCU
85
2
20%
X5R
2
20%
X5R
86 97
OUT
(D9372/D9373)
(D9365.2)
16V
402
C9369
CEXT
97 6
BAR90-02LRH
T29_R2D_P<1>
T29_R2D_N<1>
97 6
IC supports input
high while Vcc = 0V.
(DP_SDRVA_HPD)
IN
6 86 97
SC70
31
DP_A_CA_DET
R9382
1
2
D9360
5% 1/20W
MF 201
SIGNAL_MODEL=EMPTY
10% 6.3V
CERM-X5R
402
2
(IPD) OUT_HPD
32
GND_VOID=TRUE
GND_VOID=TRUE
D9372/D9373: SIGNAL_MODEL=T29PIN
D9364/D9365: SIGNAL_MODEL=EMPTY
PP3V3_S0
85
3 IN_HPD
CA_DET
1.5K
16V
402
(DP_SDRVA_AUXCH_P)
(DP_SDRVA_AUXCH_N)
38 SCL_CTL
37 SDA_CTL
102 100 91 89 88 85 84 83
41 40 39 36 35 32 28 26 25 23 12 7 6
80 73 72 62 61 57 54 52 51 50 49 48 46
16V
402
18
17
36 I2C_ADDR0 (IPD)
35 I2C_ADDR1 (IPD)
6 86 97
IN
OUT
T29_D2R_C_P<1>
T29_D2R_C_N<1>
GND_VOID=TRUE
10%
16V
X5R 2
402
0.1uF
C9362
DP_SDRVA_ML_C_P<2>
DP_SDRVA_ML_C_N<2>
97
D9365
TSLP-2-7
4V
20%
CERM-X5R-1
2
201
DP_SDRVA_ML_C_P<0>
DP_SDRVA_ML_C_N<0>
OUT_AUXP_SCL
OUT_AUXN_SDA
DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1
C9361
TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 Ds)
0.1UF
16 IN_AUXP
15 IN_AUXN
26 I2C_CTL_EN (IPU)
0.22UF
C9359
AUXCH Snoop Port,

used by PS8301
during training.
DP_EXTA_HPD
DP_A_PWRDWN_R
SDRV_PD
28
27
OUT_D1P
OUT_D1N
9 IN_D3P
10 IN_D3N
DP_EXTA_ML_P<3>
DP_EXTA_ML_N<3>
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
30
29
OUT_D0P
OUT_D0N
25
24
7 IN_D2P
8 IN_D2N
5%
1/20W
MF
2 201
OUT_D2P
OUT_D2N
DP_EXTA_ML_P<2>
DP_EXTA_ML_N<2>
DPSDRVA_I2C_CTL_EN
48
4 IN_D1P
5 IN_D1N
DP_EXTA_ML_P<1>
DP_EXTA_ML_N<1>
DP_SDRVA_ML_R_P<2>
DP_SDRVA_ML_R_N<2>
270
CRITICAL
C9360
VDD
1 IN_D0P
2 IN_D0N
DP_EXTA_ML_P<0>
DP_EXTA_ML_N<0>
0.22UF
QFN
85
C9365
1/20W
201
PS8301TQFN40GTR-A2
85 6
0.22UF
1/20W
201
U9310
Addr (W/R)
0x96/0x97
0xB6/0xB7
0x94/0x95
0xB4/0xB5
97 6
2
MF 201
2
97 6
C9312
0.1UF
T29 Path
Biasing
10% 6.3V
CERM-X5R
GND_VOID=TRUE 402
0.22UF
TSLP-2-7
IN
(D9364.2)
T29: TX_0
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
BAR90-02LRH
R9373
GND_VOID=TRUE
TSLP-2-7
D9373
5% 1/20W
MF 201
SIGNAL_MODEL=EMPTY
0.47UF
C9364
DP_SDRVA_ML_R_P<0>
DP_SDRVA_ML_R_N<0>
41
PS8301 I2C Addresses:
C9311
0.1UF
20%
6.3V 2
CERM
402-LF
5%
1/20W
MF
201 2
R9355 30
5% 1/20W
R9350 30
21
40
2.2UF
D9372
GND_VOID=TRUE
1.5K 1
2
T29_A_BIAS_R2D_N1
IN
R9353
5%
MF
C9310
C9383
(C9383.2)
2 CRITICAL
0.47UF
BAR90-02LRH
DP A Super-Driver
PP3V3_S0
6
33
100
73
50
35
6
25
41
57
85
97
BAR90-02LRH
T29_R2D_P<0>
T29_R2D_N<0>
97 6
20%
4V
CERM-X5R-1
201
GND_VOID=TRUE
C9382
T29_R2D_C_F_N<1>
T29_R2D_C_F_P<1>
1/20W
201
270
102
84 83 80
54 52 51
40 39 36
23 12 7
32 28 26
49 48 46
72 62 61
91 89 88
97
D9364
5% 1/20W
MF 201
SIGNAL_MODEL=EMPTY
97 6
0.47UF
CRITICAL
1.0NH+/-0.1NH
R9308/R9309 maintain bias on C9308/C9309

to prevent spikes when U9310 AUXDDC_OFF
transitions from high to low.
C9380 1
C9381 1
85
5%
1/16W
MF-LF
402
T29_A_BIAS_R2D_P1
IN
OVERSIZE_PAD=0.875 mm^2
(Both L 153S1376)
1/16W
402
1M
97 33 6
1.5K R9372
1
2
T29_A_BIAS_R2D_N0
IN
(C9380/C9381)
84 85 88 89 91
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 73 80 83
100 102
16V
402
10%
0.1uF
X5R
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.
PP3V3_S0
5%
1M
MF-LF
DP_EXTA_AUXCH_P 85
6 85
16V
402
10%
X5R
DP_EXTA_ML_P<3>
GND_VOID=TRUE
20%
4V
CERM-X5R-1
201
GND_VOID=TRUE
C9372
GND_VOID=TRUE
1
T29_D2R_C_P<0>
T29_D2R_C_N<0>
20%
4V
CERM-X5R-1
201
2
0.47UF
CRITICAL
1
T29 A High-Speed Signals
6.3V
1.0NH+/-0.1NH 0201-1 97 T29_R2D_C_F_N<0>
0.47UF 10%
CERM-X5R
97 T29_R2D_C_F_P<0>
402
2
1
2
C9373
L9373 1
6.3V
1.0NH+/-0.1NH 0201-1
0.47UF 10%
CERM-X5R
CRITICAL
(C9373.2) GND_VOID=TRUE 402
T29 signals are

P/N-swapped after AC
caps to improve layout.
6 85
16V
402
0.1uF
99 84
DP_EXTA_ML_P<2>
10%
X5R
85
97 33 6
16V
402
0.1uF
DP_EXTA_AUXCH_C_P
OUT
6 85
16V
402
DP_EXTA_ML_N<1>
10%
X5R
0.1uF
99 84
DP_EXTA_ML_P<1>
10%
X5R
0.1uF
99 79
97 33 6
C9370 1
(C9370/C9371)
T29_D2R_N<0>
T29_D2R_P<0>
OVERSIZE_PAD=0.875 mm^2
0.1uF
99 79
OUT
16V
402
10%
X5R
0.1uF
99 79
85
97 33 6
(Both L 153S1376)
0.1uF
99 79
DP_EXTA_ML_N<0>
10%
X5R
GND_VOID=TRUE
6 85
16V
402
0.1uF
99 79
DP_EXTA_ML_P<0>
10%
X5R
0.1uF
29
20
16
12
9
3
99 79
T29_A_BIAS_R2D_P0
IN
28
21
33
BRANCH
PAGE
93 OF 132
SHEET
85 OF 105
3.3V/HV Power MUX

D9425
R94161
C9410
470K
0.1UF
5%
1/16W
MF-LF
402 2
CRITICAL
VIN
10%
2 50V
X7R
603-1
9 CT
GND
0.1UF
R9419
249
86 85
IN
DMB53D0UV
IN
0.1UF
1
10%
6.3V
X5R
201
OUT
97 85 6
OUT
R9490
GND_VOID=TRUE
R94941
51
5%
1/20W
MF
2 201
1K
T29_A_BIAS_R
VOLTAGE=3.3V
IN
IN
OUT
5%
1/20W
MF
201 2
SIGNAL_MODEL=EMPTY
97 85 6
T29_A_BIAS_D2R_P1
97 85 6
T29_A_BIAS_D2R_N1
2.2K
SIGNAL_MODEL=EMPTY
5%
1/20W
MF
201 2
GND_VOID=TRUE
97 85 6
97 85 6
OUT
OUT
T29_D2R_C_P<1>
T29_D2R_C_N<1>
D9499
97 85
BI
BI
VOLTAGE=0V
6
8
14
R9404 GND_VOID=TRUE
OUT
T29DPA_HPD
85
OUT
T29DPA_CONFIG1_RC
85
OUT
T29DPA_CONFIG2_RC
R94521
1M
5%
1/20W
MF
201 2
97 6
GND_VOID=TRUE
97 6
16
GND_DPACONN_14
18
VOLTAGE=0V
20
BOT ROW
TOP ROW
TH PINS
SM PINS
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN
12
GND_VOID=TRUE
(Both Cs)
C9470
C9471
VOLTAGE=15V
C9499
30PF
5%
50V
2 CERM
402
C9495
3
5
GND_DPACONN_7
C9402
0.01UF
10%
50V 2
X7R
402
VOLTAGE=0V
12
C9401
12
85 97
T29DPA_ML_P<1>
T29DPA_ML_N<1>
IN
6 85 97
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
IN
85 97
IN
85 97
R9471
470K
5%
1/20W
MF
2 201
BI
6 85 97
13
T29: LSX_R2P/P2R (P/N)
15
17
19
GND_VOID=TRUE
GND_DPACONN_13
R9407
1
VOLTAGE=0V
12
GND_VOID=TRUE
(Both Cs)
5%
1/20W
MF
201
21
GND_DPACONN_19
C9472
C9473
1
2
0603
20% 4V
CERM-X5R-1
201
2
20% 4V
CERM-X5R-1
201
0.47UF
GND_VOID=TRUE
0.47UF
T29DPA_ML_P<2>
T29DPA_ML_N<2>
VOLTAGE=0V
85 97
IN
GND_VOID=TRUE
11
L9408
IN
5%
1/20W
MF
2 201
5%
1/20W
MF
201
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
20% 4V
CERM-X5R-1
201
0.47UF
470K
20% 4V
CERM-X5R-1
201
2
R9472
470K
5%
1/20W
MF
2 201
GND_VOID=TRUE
1
R9473
470K
5%
1/20W
MF
2 201
R9408
5%
1/16W
MF-LF
402
12
5%
1/20W
MF
201
0.01UF
10%
2 50V
X7R
402
470k Rs for ESD protection

on AC-coupled signals.
SYNC_MASTER=K91_MLB
1
PAGE TITLE
R9441
100K
5%
1/16W
MF-LF
2 402
DRAWING NUMBER
Apple Inc.
Sink HPD range:

High: 2.0 - 5.0V
Low: 0 - 0.8V
R9470
FERR-120-OHM-3A
R9401
0.47UF
GND_VOID=TRUE
T29: TX_1
5%
1/16W
MF-LF
402
GND_VOID=TRUE
DP Source must pull

down HPD input with
greater than or equal
to 100K (DPv1.1a).
10%
16V
2 X7R
201
5%
1/20W
MF
201
T29DPA_ML_P<0>
T29DPA_ML_N<0>
T29DPA_HPD_R
DPACONN_20_RC
1
R9402
1
1%
1/16W
MF-LF
402 2
97 6
1
0603
330PF
12
GND_VOID=TRUE R9406
97 6
L9499
T29 Dir
DSPLYPRT-M97-1
SHIELD PINS
650NH-5%-0.430MA-0.052OHM
10%
16V
X7R 2
201
12
5%
1/16W
MF-LF
402
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
CRITICAL
2
330PF
DP Dir
J9400
22
97 6
R9451 C9494 1
1M
GND_DPACONN_1
VOLTAGE=0V
97 6
0603
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
5%
1/20W
MF
2 201
L9498
650NH-5%-0.430MA-0.052OHM
5%
50V
CERM 2
402
85
3
2
GND_DPACONN_8
12
30PF
Circuit threshold range: 2.877-2.941V (2.903V nominal)
CRITICAL
10
C9498 1
12
5%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
(Both Ls)
97 85
DP Dir
R9403 GND_VOID=TRUE
GND_VOID=TRUE
SIGNAL_MODEL=T29PIN
DPAPWR_FB_DIV
R9405
T29: TX_0
5%
1/20W
MF
2 201
35 85 86
24.9K
For J9400 T29 SMT pads

(3, 5, 17 & 19):
GND_VOID=TRUE
1K
TSLP-2-7
BAR90-02LRH
CRITICAL
T29_A_HV_EN
F-RT-THSM
SIGNAL_MODEL=T29PIN
BAR90-02LRH
5%
1/16W
MF-LF
2 402
R9495
2
TSLP-2-7
5%
1/16W
MF-LF
402 2
R94361
GND_VOID=TRUE
T29DPA_ML_P<3>
T29DPA_ML_N<3>
BI
T29: Unused
DPAPWRSW_HV_DET
10K
VOLTAGE=15V
0603
BI
D9498
1K
1%
1/16W
MF-LF
402 2
R9432
220
PP3V3RHV_SW_DPAPWR
10%
50V 2
X7R
402
GND_VOID=TRUE
GND_VOID=TRUE
2.2K
R94351
5%
1/16W
MF-LF
402
R9499SIGNAL_MODEL=EMPTY
82
100K
0.01UF
5%
1/20W
MF
2 201
VOLTAGE=15V
CRITICAL
R94981
R9437
G 2
1 S
R9433
T29_D2R_C_P<0>
T29_D2R_C_N<0>
S 4
402
DPAPWRSW_ON_C
5%
1/16W
MF-LF
402
L9400
T29 Dir
97 85 6
SSM6N37FEAPE
SOT563
SOT353
4 FB
PGND
GND
2
1
DPAPWRSW_NPN_E
FERR-120-OHM-3A
C9400 1
20%
10V
2 CERM
402
ZXRE060A
1UF
10%
10V
X5R
C9435
0.1UF
0.1UF
Q9419
PP3V3RHV_SW_DPAPWR_UF
3
IN
Note: Bleeder active when

DPAPWRSW_HV_DET is
HIGH and T29_A_HV_EN
is LOW.
C9490
T29_A_BIAS
C9429
2 G
T29_A_HV_EN
5 G
R9418
SOT-563
86 85 35
5 OUT
NO STUFF
1
ZXRE060A REF range:

0.595-0.605V (0.600V nominal)
Circuit threshold range: 3.363-3.439V (3.395V nominal)
DPAPWR_BLDR_E
Q9430
SOT563
SOT363
DPAPWR_BLDR_B
1%
1/16W
MF-LF
402
6 D
SSM6N37FEAPE
20%
10V
2 CERM
402
T29_A_BIAS
MMDT3946XG
SOT-563
D 3
Q9426
DMB53D0UV
2.5V / 249 ohm = 10mA

P = ~27mW
2
FB 4
PGND
1
86 85
C9436
DPAPWRSW_HV_DET_L
Q9419
Bleeder Resistor
S 2
GND
2
20%
10V
CERM 2
402
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
Q9430
5%
1/16W
MF-LF
2 402
SOT353
100UF
20%
2 6.3V
X5R-CERM-1
603
C9426
20%
10V
CERM 2
402
C9487
U9435
4.7K
ZXRE060A
22UF
5%
1/16W
MF-LF
2 402
SOD-VESM-HF
<RLIM>
20%
2 10V
CERM
402
CRITICAL
C9480
DPAPWRSW_P3V3_ON
R9429
U9426
4.7K
5%
1/16W
MF-LF
2 402
3 CRITICAL
IN
OUT 5
0.1UF
R9430
1K
D 3
1%
1/16W
MF-LF
2 402
<RFLT>
200k / RFLT = 885mA

201k / RLIM = 935mA
CCT * 38900
CCT * 100000
1%
1/16W
MF-LF
402 2
200K
C9481
0.1UF
20%
6.3V 2
X5R
603
DPAPWRSW_HV_DET_R_L
21.5K
45 46 73
R9426
C9424
1
2
C9485
10%
6.3V
CERM-X5R
402
R94281
R9411
100K
10UF
3.3V Always
Q9415
0.47UF
DPAPWRSW_VREF
R9410
<CT>
SSM3K15FV
DPAPWR_ON_L_C
SMC_S4_WAKESRC_EN
IN
EN 4
CRITICAL
C9486 1
DPAPWRSW_P3V3_ON_L
DPAPWRSW_IFLT
IFLT 8
THRM
PAD
3 OC*
104
48 56 71 72 73
6 7 17 19 20 22
23 24 25 29 46
83 91 100 102
PP3V3_S5
IN 5
GND
2
5
13
14
TP_DPAPWRSW_FLT_L
DPAPWRSW_ILIM
T29_A_HV_EN
86 85 35
BGA
Blocking FET, off

when Source >3.4V
or HV_EN high.
MF-LF
402 2
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
STPS2L30AF
5%
1/16W
MF-LF
402 2
=
=
=
=
22
R94271
100K
10%
2 6.3V
CERM-X5R
402
IFLT
ILIM
TFLT
TSD
Q9425
SI8409DB
0.47UF
R94251
4.7K
5%
R9424 1/16W
0.1UF
16 EN*
FLT* 15
(IPU-Weak!)
6 RTRY*
ILIM 7
C9412
D9410
SM
C9411
QFN
DPAPWRSW_CT
CRITICAL
3.3V/HV MUXed
CRITICAL
VOLTAGE=15V
1
TPS2590
DPAPWRSW_HVEN_L_R
PPHV_SW_DPAPWR
U9410
10%
50V 2
X7R
603-1
1 OUT
(*) U9410 tolerance unknown
10
11
12
VOUT
Max
894mA (*)
944mA (*)
26.7ms
724ms
TPS2051B
SOT23
DFLS1100
1
2
3
4
Min
876mA
925mA
13.4ms
235ms
DP_PWR must be S4/S5 to support

wake from T29 devices.
U9480
-30V
+/-12V
-1.4V
65mOhm @ 2.5V Vgs
3.7A @ 70C
4
PP15V_T29
20V Max
17
35 8 7
Nominal
885mA
935mA
18.3ms
470ms
IFLT
ILIM
TFLT
TSD
CRITICAL
POWERDI-123
2
1
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
Port A HV Power Switch

D
Port A 3.3V Power Switch
CRITICAL
PP3V3_SW_DPAPWR
VOLTAGE=3.3V
85
SIZE
D
REVISION

BRANCH
PAGE
94 OF 132
SHEET
86 OF 105
82 50 7
CRITICAL
C9540
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
C9545
C9546
1UF
1000PF
10%
25V
X5R
603-1
5%
25V
NP0-C0G
402
CRITICAL
C9590
4.7
20%
16V
POLY-TANT
CASE-D2E-SM
PVIN_S0GPU_P1V0
C9595
C9596
1UF
68UF
R9500
1000PF
10%
25V
X5R
603-1
5%
25V
2 NP0-C0G
402
5%
1/16W
MF-LF
402
CRITICAL
CRITICAL
Q9510
C9500
SIZ700DT
1
10%
25V
X5R
805
P1V0GPU_DRVH
GATE_NODE=TRUE
DIDT=TRUE
PP5V_S0
10UF
POWERPAIR-6X3.7
C9501
2
6 7 8 22 41 47 52 54 65 68 69 70 73 104
105
1UF
10%
10V
X5R
402-1
(Internal 10-ohm path

from PVCC to VCC)
PP5V_S0GPU_P1V0P1V5_VCC
2
PCMB065T-SM
XW9515
C9516
SM
1000PF
5%
25V
NP0-C0G
402
CRITICAL
CRITICAL
6
2
P1V0GPU_VBST
17
15
DIDT=TRUE
P1V0GPU_LL
16
SWITCH_NODE=TRUE
18
DIDT=TRUE
10
C9510
14
330UF
2
20%
2 2.0V
POLY-TANT
B2-SM
P1V0GPU_VFB
P1V0GPU_TRIP
10UF
20%
6.3V
X5R
603
11
12
29
4
20
2
VIN
BOOT1
UGATE1
PHASE1
LGATE1
OUT1
EN1
BYP
FB1
ILIM1
SKIP*
EN_LDO
SECFB
TON
LDO
CRITICAL
LDOREFIN
BOOT2
U9500
UGATE2
QFN2
PHASE2
LGATE2
OUT2
EN2
REF
POK1
POK2
8.66K
1%
1/16W
MF-LF
402
<Rb>
1
R9521
21
33
P1V0S0_VSNS
P1V5FB_VBST
R9535
(=PP1V5FB_S0_REG)
27
PP2V_S0GPU_P1V5_REF
13
VOLTAGE=2V
28
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
SM
1
C9565
10UF
2
20%
6.3V
X5R
603
C9566
1000PF
5%
2 25V
NP0-C0G
402
C9580
C9585
0.1UF
20%
10V
CERM
402
10%
50V
X7R
603-1
P1V5FB_LL
<Ra>
R9563
SWITCH_NODE=TRUE
P1V5_GPU_VSNS
XW9565
SM
DIDT=TRUE
11.8K
1%
1/16W
MF-LF
402
<Rb>
R9564 1
1%
1/16W
MF-LF
402 2
Vout = 2(Req/(Ra+Req))
GPIO7
FBVDDQ
1
0
1.35V
1.503V
R9562
78.7K
35.7K
Vout = 0.7V * (1 + Ra / Rb)

(Rb should be between 10K and 100K)
0.1UF
GPU_P1V5_REFIN
P1V5FB_TRIP
130K
XW9500
CRITICAL
1
DIDT=TRUE
R9585 1
353S2312
20%
2.5V 2
POLY-TANT
CASE-B2-SM2
PWRPK-12128
GATE_NODE=TRUE
220UF
SIS426DN
P1V5FB_DRVL
PGND
75K
C9560
Q9561
C9561
0.001UF
10%
50V
CERM
402
1%
1/16W
MF-LF
402
2
CRITICAL
GPUFB_VID_L
Q9565
3
20.0K
CRITICAL
25
1
2
2
PCMB065T-SM
CRITICAL
23
7 103
Vout = 1.503V
8A MAX OUTPUT
F = 500 KHZ
DIDT=TRUE
31
L9560
26
32
1.0UH-13A-5.6MOHM
100PF
5%
50V
CERM
402
24
30
PP1V5_S0GPU_ISNS_R
CRITICAL
DIDT=TRUE
(SGND)
NO STUFF
C9520
NC
PWRPK-12128
REFIN2
ILIM2
THRM_PAD GND
<Ra>
1
R9520
10%
10V
X5R
402-1
22
f = 400 kHz
C9515
10%
50V
X7R
603-1
L9510
1
0.1UF
2.2UH-8.0A
(Q9510 limit?)
10%
10V
X5R
402-1
SIS426DN
GATE_NODE=TRUE
1UF
1UF
ISL6236
C9530
CRITICAL
C9503
C9504
19
PVCC VCC VREF3
3.5A MAX OUTPUT
P1V5FB_DRVH
VOLTAGE=5V
PP1V0_S0GPU_ISNS_R
Vout = 1.003V
Q9560
PP5V_S0GPU_VREF
DIDT=TRUE
103 7
CRITICAL
VOLTAGE=5V
P1V0GPU_DRVL
GATE_NODE=TRUE
SSM3K15FV
SOD-VESM-HF
1%
1/16W
MF-LF
402
GND_P1V0P1V5_SGND
91 88
IN
91 88 87 82 74 8
OUT
91 88 87 82 74 8
OUT
91
IN
P1V0GPU_EN
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
P1V5FB_EN
VOLTAGE=0V
FBVDD_ALTVO
IN
79 80
PAGE TITLE
1V0 GPU / 1V5 FB Power Supply

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
95 OF 132
SHEET
87 OF 105
8
85 84 83
57 54 52
41 40 39
25 23 12 7
35 32 28
50 49 48
73 72 62
100 91 89
102
80
51
36
6
26
46
61
88
R9600
PP3V3_S0
C9610
0.1UF
C9621
C9622
0.1UF
20%
2 10V
CERM
402
102 72
14 7 6
71 25 20
PP1V8_S0
C9623
0.1UF
C9624
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C9625
0.1UF
C9626
0.1UF
20%
2 10V
CERM
402
C9627
0.1UF
20%
2 10V
CERM
402
C9628
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
VOLTAGE=3.3V
C9629
94 88 18
0.1UF
94 88 18
20%
2 10V
CERM
402
94 88 18
94 88 18
L9621
94 88 18
FERR-220-OHM
PP1V8_S0_GMUX_R
5%
1/16W
MF-LF
402
C9611
0.1UF
20%
10V
2 CERM
402
C9612
0.1UF
C9613
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C9614
0.1UF
C9615
0.1UF
20%
10V
2 CERM
402
C9616
0.1UF
VOLTAGE=1.8V
VOLTAGE=3.3V
C9617
94 88 18
99 88 79
20%
2 10V
CERM
402
20%
10V
2 CERM
402
99 88 79
99 88 79
99 88 79
FERR-220-OHM
PP3V3_S0_GMUX_LRC_VCCPLL
VOLTAGE=3.3V
PP1V2_S0
1
C9600
4.7UF
C9605
C9606
0.1UF
20%
10V
2 CERM
402
C9607
0.1UF
20%
10V
2 CERM
402
C9608
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
100
100
100
100
100
100
100
100
100
100
100
100
100
100
C9609
99 88 79
99 88 79
99 88 79
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_P<2>
R9660
R9661
R9662
R9663
R9664
R9665
R9666
C9630
20%
10V
2 CERM
402
GMUX_CFG0
1%
OUT
88 84
OUT
91 88 72
OUT
91 88 82
OUT
91 88 87
OUT
91 88
OUT
16 8
OUT
80
OUT
88 83
OUT
CRITICAL
J9600
BI
95 47 45 16 6
BI
95 47 45 16 6
BI
95 47 45 16 6
BI
PP3V3_S0
JTAG_GMUX_TDO
JTAG_GMUX_TDI
JTAG_GMUX_TMS
95 47 45 16 6
73 80 83 84 85 88 89 91
6 7 12 23 25 26 28 32 35 36 39 40 41 46
48 49 50 51 52 54 57 61 62 72 95 47 25 6
100 102
88
25
88
19
18 88
BI
JTAG_ISP_TCK
8 19 23 33 88
M-RT-SM
7
GMUX_JTAG_CONN
2
3
4
5
6
R96471
10K
1%
1/20W
MF
201 2
PB26A
PB26B
K12
A4
P11
ULC_VCCPLL
LRC_VCCPLL
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
PT9B
PB27A
PB27B
PB28A
PB28B
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT28A
PT28B
PL2A
PL2B
PR2A
PR2B
PL6A
PR6A
PL6B
PR6B
PL7A
PL7B
PR7A
PR7B
PL8A
PR8A
PL8B
PL9A
PR8B
PR9A
PR9B
PL9B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL14A
PL14B
PL15A
PL15B
PL25A
PL25B
(Tie/strap low if EGPU doesnt provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
J1
GND
102 100 91 89 88 85 84 83 80
40 39 36 35 32 28 26 25 23 12 7 6
73 72 62 61 57 54 52 51 50 49 48 46 41
B5
B7
A12
C14
F13
M12
M9
M3
N5
M1
C3
F2
PT9A
BANK6
91
B1
B2
C2
D3
D1
E1
D2
E3
F1
G1
F3
G2
H2
G3
H1
H3
L1
L3
K3
L2
N1
P1
IN
PT8A
PT8B
BANK7
NO STUFF
IN
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
94 88 18
IN
GMUX_PL6A
TP_GMUX_PL6B
LVDS_IG_A_DATA_P<0>
94 88 18
IN
LVDS_IG_A_DATA_N<0>
94 88 18
IN
LVDS_IG_A_DATA_P<1>
94 88 18
IN
LVDS_IG_A_DATA_N<1>
94 88 18
IN
LVDS_IG_A_DATA_P<2>
94 88 18
IN
LVDS_IG_A_DATA_N<2>
94 88 18
IN
LVDS_IG_B_DATA_P<0>
94 88 18
IN
LVDS_IG_B_DATA_N<0>
94 88 18
IN
LVDS_IG_B_DATA_P<1>
94 88 18
IN
LVDS_IG_B_DATA_N<1>
94 88 18
IN
LVDS_IG_A_CLK_P
94 88 18
IN
LVDS_IG_A_CLK_N
94 88 18
IN
TP_LVDS_MUX_SEL_EG
8
OUT
TP_GMUX_PL14B
GMUX_RESET_L
25
IN
GMUX_VSYNC
88
PM_ALL_GPU_PGOOD
87 82 74 8
IN
PEX_CLKREQ_L
80 8
IN
94 88 18
IN
OUT
PT7B
PB14A
PB14B
PB15A (OD)
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B (OD)
PB19A
PB19B
PB20A
PB20B
BANK4
95 47 45 16 6
1909782
OUT
PB7B
BANK5
88 74 8
PP3V3_S0
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR14A
PR14B
PR24A
PR24B
A2
A3
A1
B3
C5
A5
B6
C7
A6
A7
C8
C9
A8
B9
A9
C10
B10
A10
A11
B12
B13
A13
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>
LVDS_B_DATA_P<2>
LVDS_B_DATA_N<2>
EG_PWRSEQ_EN
GMUX_DEBUG_RESET_L
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<2>
GND
GND
GND
GND
A14
B14
D12
D13
D14
E14
E12
F12
F14
G14
G12
G13
H13
H12
H14
J12
L14
M13
N14
N13
DP_A_CA_DET
DP_HOTPLUG_DET
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_IG_PANEL_PWR
EG_LCD_PWR_EN
LVDS_IG_BKL_ON
EG_BKLT_EN
18 8 7 6
104 73 55 54 50 49 48 32 31 30 29 25 24
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
R9670
JTAG_GMUX_TDI
10K
IN
IN
88
OUT
Q9605
GMUX_VSYNC
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
OUT
84 99
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
PLACE_NEAR=U9600.J12:5mm LVDS_EG_A_CLK_N
1%
1/20W
MF
201
PLACE_NEAR=U9600.D13:5mm LVDS_EG_A_DATA_N<0>
1%
1/20W
MF
201
PLACE_NEAR=U9600.E14:5mm LVDS_EG_A_DATA_N<1>
1%
1/20W
MF
201
PLACE_NEAR=U9600.F12:5mm LVDS_EG_A_DATA_N<2>
1%
EG_PWRSEQ_EN
R9684
1K
88
JTAG_GMUX_TDI
R9685
10K
88
JTAG_GMUX_TDO
R9686
10K
88
GMUX_DEBUG_RESET_L
R9680
1K
1/20W
MF
201
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_N<1>
PLACE_NEAR=U9600.H12:5mm LVDS_EG_B_DATA_N<2>
18 88 94
18 88 94
18 88 94
79 88 99
79 88 99
79 88 99
79 88 99
79 88 99
79 88 99
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
18 88 94
79 88 99
PP3V3_S0
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
88 84
DP_MUX_SEL_EG
R9681
10K
88 84
LVDS_DDC_SEL_IG
R9682
10K
88 84
LVDS_DDC_SEL_EG
R9683
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rails source is valid)
NO STUFF
88 74 8
EG_RESET_L
R9691
100K
89 88 6
LCD_BKLT_PWM
R9693
100K
5%
1/20W
MF
201
5%
1/20W
MF
201
P1V5FB1V8GPU_R_EN
91 88 87
P1V0GPU_EN
91 88 82
GPUVCORE_EN
R9674
IN
85
IN
84
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
79 88 99
IN
8 18
IN
79 80
IN
8 18
IN
79 80
R9676
4.7K
5%
1/20W
MF
2 201
1
91 88 72
88 83
R9673
P3V3GPU_EN
4.7K
5%
1/20W
MF
2 201
R9672
LCD_PWR_EN
4.7K
5%
1/20W
MF
2 201
R9671
R9678
4.7K
5%
1/20W
MF
201
4.7K
5%
1/20W
MF
2 201
GMUX_S3_PD_GND
Q9607
1
10K
1%
1/16W
MF-LF
402 2
Required Pulldowns
91 88
D 3
NO STUFF
1
SSM6N15FEAPE
R9675
SOT563
100K
5%
1/20W
MF
2201
5 G
JTAG_GMUX_TDO
88
5%
1/16W
MF-LF
2402
S 4
88
D 6
Q9605
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
88
R9605
1
1K
5%
1/16W
MF-LF
402
S 1
Graphics MUX (GMUX)
SOT563
DRAWING NUMBER
Apple Inc.
S 4
91 73 45 23
IN
S 1
33 19 8
33 19 8
ALL_SYS_PWRGD

JTAG_ISP_TDO
SIZE
D
REVISION
T29_JTAG_FET
JTAG_ISP_TDI
PAGE TITLE
D 6
SSM6N15FEAPE
D 3
2 G
MF
84 99
Q9607
1%
1/20W
MF
2 201
PP3V3_T29
1/20W
18 88 94
18 88 94
GMUX_S3_PD_EN
35 34 33 25 19 16 7
201
18 88 94
84 99
88
PP3V3_S3
NO STUFF
MF
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
R9679
PT7A
CSBGA
1/20W
1%
88
U9600
BANK0
OUT
84
PB7A
BANK1
OUT
88 84
CFG0
P2
N2
P4
N4
N3
M4
P5
M5
P6
M6
P7
M7
N7
N8
P9
N9
P10
M10
P12
P13
N12
P14
BANK2
OUT
88 84
K1
201
XP25-5
LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
P3V3GPU_EN
GPUVCORE_EN
P1V0GPU_EN
P1V5FB1V8GPU_R_EN
PEG_CLKREQ_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LPCPLUS_RESET_L
LPC_CLK33M_GMUX
GMUX_INT
BANK3
89 88 6
10K
1%
1/20W
MF
201
1%
1/20W
MF
201 2
OUT
ULC_GNDPLL
LRC_GNDPLL
10K
R9641
90 8
201
MF
NO STUFF
B4
M11
R96461
NO STUFF
MF
1/20W
Required Pullups
SILK_PART=GMUX_RST
GNDIO7
NO STUFF
VCCJ
OMIT
CRITICAL
GNDIO6
88 18
VCCAUX
TCK
TDI
TDO
TMS
TOE
GNDIO5
88
VCCIO0
88
K14
L13
K13
L12
K2
GNDIO3
GNDIO4
1%
1/20W
MF
201
JTAG_ISP_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE
GNDIO2
88 33 23 19 8
GNDIO1
1%
1/20W
MF
201 2
C11
J2
J14
M8
VCC
1
10K
GNDIO0
R9640
10K
1/20W
1%
SIGNAL_MODEL=EMPTY
20%
10V
2 CERM
402
0.1UF
PLACE_NEAR=U9600.H3:5mm
1%
PP3V3_S0
R96451
0.1UF
20%
10V
2 CERM
402
B8
C6
C12
C13
E13
M14
N10
N6
P3
M2
C1
E2
89
73
52
41
28
6
23
36
49
61
84
100
C9604
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
R9650
R9651
R9652
R9653
R9654
R9655
R9656
0.1UF
B11
C4
J3
J13
N11
P8
91
83 80
57 54
48 46
35 32
12 7
26 25
40 39
51 50
72 62
88 85
102
0.1UF
20%
4V
X5R
402
0402
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
0402
C9631
0.1UF
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
PP3V3_S0_GMUX_ULC_VCCPLL
94 88 18
L9620
71 7 6
LVDS Receiver Termination
R9610
0
PP3V3_S0_GMUX_R
1
0.1UF
20%
2 10V
CERM
402
GMUX CPLD
5%
1/16W
MF-LF
402
BRANCH
PAGE
96 OF 132
SHEET
88 OF 105
D
*L9710, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.
*PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
0.020 Ohm is place holder for 0.025 Ohm in 0612 package
OMIT
CRITICAL
PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE
R9700
0.020
1
3
PPBUS_S0_LCDBKLT_PWR
90 89
0.5%
1W
MF-LF
0612
2
4
L9710
CRITICAL
C9712
OUT
103 100
OUT
ISNS_LCDBKLT_N
VOLTAGE=8.4V
C9713
VOLTAGE=50V
1217AS-2SM
0.1UF
10UF
ISNS_LCDBKLT_P
33UH-1.8A-110MOHM
2
PPVIN_BKL 1
PPBUS_S0_LCDBKLT_PWR_SW
1
103 100
PLACE_NEAR=D9710.2:3MM
CRITICAL
C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719
C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE
POWERDI-123
1
2
CRITICAL
D9701
PPVOUT_S0_LCDBKLT
CRITICAL
DFLS260
SWITCH_NODE=TRUE
10%
2 25V
X5R
402
10%
2 25V
X5R
805
C9715
2.2UF
10%
2 100V
X7R-CERM
1210
CRITICAL CRITICAL
1
C9716
2.2UF
10%
2 100V
X7R-CERM
1210
C9718
2.2UF
10%
2 100V
X7R-CERM
1210
C9719
2.2UF
10%
2 100V
X7R-CERM
1210
6 83 103
VOLTAGE=50V
CRITICAL
1
C9717
1000PF
10%
2 100V
X7R
603
BKL_VLDO
PP3V3_S0
102 100 91 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
C9714
0.01UF
C9710
1UF
10%
2 16V
CERM
402
10%
2 25V
X5R
603-1
C9711
0.1UF
10%
2 16V
X5R
402
R97081
63.4K
1%
1/16W
MF-LF
402 2
CRITICAL
Q9701
BKL_FET_CNTL
SI7308DN
PWRPK-1212-8
23
VDDIO
22
VLDO
VIN
R97091
59.0K
1%
1/16W
MF-LF
402 2
U9701
BKL_FSET
BKL_FLT
BKL_ISET
2
5%
SMBUS_PCH_DATA
R9757
5%
NO STUFF
4 EN
BKL_FB
OUT1
12
BKL_ISEN1
OUT2
13
BKL_ISEN2
OUT3
14
BKL_ISEN3
OUT4
16
BKL_ISEN4
R9717
17
BKL_ISEN5
OUT6
18
BKL_ISEN6
VSYNC
19
BKL_VSYNC_R
10.2 2
LED_RETURN_1
0.1%
1/16W
TF
402
OUT
6 83
OUT
6 83
OUT
6 83
R9718
1
10.2 2
LED_RETURN_2
0.1%
1/16W
TF
402
C9723
0.1UF
10%
2 25V
X5R
402
R9765
R9715
100K
1%
1/16W
MF-LF
402
10K
(EEPROM should set EN_I_RES=1)
1
R9714
14.7K
LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST
R9704 SHOULD BE 47K IF RC FILTER IS USED
R9755
10K
THRM
PAD
(APN: 353S3218)
5%
1/16W
MF-LF
2 402
R9716
1%
1/16W
MF-LF
402 2
NO STUFF
OUT
6 83
R9721
10.2 2
LED_RETURN_5
0.1%
1/16W
TF
402
XW9710
SM
OUT
6 83
R9722
VOLTAGE=0V
LED_RETURN_4
C9704
BKL_SGND
10.2 2
0.1%
1/16W
TF
402
33PF
R9720
5%
2 50V
CERM
402
LED_RETURN_3
Fpwm=9.62KhZ
details in spec
10.2 2
0.1%
1/16W
TF
402
90.9K
5%
CIRCUIT 1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
I_LED=25.1ma
I_LED=369/Riset
R9704
LCD_BKLT_PWM
R9719
CRITICAL
1
1%
1/16W
MF-LF
402 2
IN
7 FAULT
1%
1/16W
MF-LF
402
88 6
TP_BKL_FAULT
BKL_SW
21
OUT5
2 PWM
BKLT_EN
24
FB
301K
11 SDA
1/16W MF-LF 402
PPBUS_S0_LCDBKLT_PWR
1
BKL_SDA
LVDS_BKL_PWM_RC
10 SCLK
1/16W MF-LF 402
R9731
90 89
3 ISET
BKL_SCL
SW
25
15 GND_L
9 GND_S
41 32 30 28 26 23 16 6
95 62 48
R9753
SMBUS_PCH_CLK
20 FILTER
1 GND_SW
41 32 30 28 26 23 16 6
95 62 48
5 FSET
LP8545SQX-EXTF
LLP1
6 GD
PLACE XW9710 AWAY FROM U9701.1 AND U9701.15
10.2 2
LED_RETURN_6
0.1%
1/16W
TF
402
OUT
6 83
PAGE TITLE
LCD Backlight Driver (LP8545)
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
R9700
CRITICAL
BOM OPTION
DRAWING NUMBER
TABLE_5_ITEM
107S0196
0.025OHM,1W,0612,MTL FILM RES
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
97 OF 132
SHEET
89 OF 105
CRITICAL
Q9806
FDC638APZ_SBMS001
CRITICAL
603-HF
VOLTAGE=10V
6
PPBUS_S0_LCDBKLT_FUSED
MOSFET
FDC638APZ
CHANNEL
P-TYPE
R9808
301K
1/16W
MF-LF
402
RDS(ON)
43 mOhm @4.5V
C9802
LOADING
0.1UF
1%
0.4 A (EDP)
3AMP-32V-467
PPBUS_G3H
64 63 50 49 39 35 8 7 6
2 5
F9800
PPBUS S0 LCDBkLT FET
SSOT6-HF
10%
16V
X5R
402-1
PBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1%
1/16W
MF-LF
402
PBUS_S0_LCDBKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
PPBUS_S0_LCDBKLT_PWR 89
VOLTAGE=10V
5
88 8
IN
LCD_BKLT_EN
BKLT_EN_L
R9840
4.7K
5%
1/16W
MF-LF
2 402
Q9807
SSM6N15FEAPE
SOT563
2
25
IN
BKLT_PLT_RST_L
SYNC_MASTER=K17_MLB
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
98 OF 132
SHEET
90 OF 105
GPU Rail Sequencing
91 88 72
P3V3GPU_EN
91 88 72
GPUVCORE_EN
91 88 82
P1V0GPU_EN
91 88 87
P3V3GPU_EN
71 56 48 46 29 25 24 23 22 20 19 17 7
104 102 100 86 83 73
91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7
83 80 73 72 62 61 57 54 52 51 50 49
102
P3V3GPU_EN
GPUVCORE_EN
GPUVCORE_EN
MAKE_BASE=TRUE
91 88 87
P1V0GPU_EN
OUT
72 88 91
OUT
82 88 91
OUT
87 88 91
P1V0GPU_EN
MAKE_BASE=TRUE
P1V5FB1V8GPU_R_EN
91 88
P1V5FB1V8GPU_R_EN
MAKE_BASE=TRUE
P1V5FB_EN
P1V5FB_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
R9932
1
91 87
91 72
P1V8GPU_EN
1
0.47UF
0.1UF
20%
2 10V
CERM
402
IN
8 74LVC2G08GT
ALL_SYS_PWRGD
SOT833
U9950Y 7
2
CPUIMVP_PGOOD
PM_S0_PGOOD
08
8 74LVC2G08GT
5
P1V8GPU_EN
OUT
U9950Y 3
6
72 91
R9962
SOT833
C9931
SYS_PWROK_R
1K
PM_PCH_SYS_PWROK
OUT
17 23
5%
1/16W
MF-LF
402
08
0.47UF
10%
6.3V
CERM-X5R
402
68
87 91
5%
1/16W
MF-LF
402
C9950
C9932
PLACE_NEAR=U1800.p12:7mm
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
OUT
IN
1K
88 73 45 23
6
48
100
R9963
5%
1/16W
MF-LF
402 2
R9931
0
6
72
PP3V3_S5
PP3V3_S0
R99501
91 88
NO STUFF
MAKE_BASE=TRUE
91 88 82
PCH S0 PWRGD
Whistler GPU requires rails to come

up in the following order:
1) GPU_3.3V
2) GPUVcore
3) GPU_1.0V
4) GPU_1.8V;GDDR5 1.5/1.35V
NO STUFF
10%
6.3V
CERM-X5R
402
SMC_DELAYED_PWRGD
NO STUFF
45 35
PLACE_NEAR=U1800.L22:5.54mm
NO STUFF
R9961
0
5%
1/16W
MF-LF
2 402
PM_PCH_PWROK
MAKE_BASE=TRUE
R9960
0
OUT
PM_PCH_PWROK
17 91
17 91
5%
1/16W
MF-LF
402
EXT GPU PWRGD Pullup
Unused PGOOD signal
PP3V3_S0
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
R99901
100K
5%
1/16W
MF-LF
4022
102 100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
NO STUFF
PLACE_NEAR=U8000.AH16:7mm
R99911
10K
91 88 87 82 74 8
IN
PM_ALL_GPU_PGOOD
91 88 87 82 74 8
IN
PM_ALL_GPU_PGOOD
91 88 87 82 74 8
IN
PM_ALL_GPU_PGOOD
5%
1/16W
MF-LF
402 2
OUT
CPUIMVP_AXG_PGOOD
IN
TP_DDRREG_PGOOD
IN
67 91
TP_P1V5S3RS0_RAMP_DONE
IN
72 91
8 74 82 87 88 91
91 67
PM_ALL_GPU_PGOOD
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
91 72
TP_P1V5S3RS0_RAMP_DONE
MAKE_BASE=TRUE
68
PAGE TITLE
Power Sequencing EG/PCH S0

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
99 OF 132
SHEET
91 OF 105
CPU Signal Constraints
CPU Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
CPU_AGTL
*
*
PCIE
PCIE
PCIE
PCIE
DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA
FDI_DATA
PCIE_85D
PCIE_85D
CPU_50S
CPU_50S
PCIE
PCIE
CPU_AGTL
CPU_AGTL
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
TOP,BOTTOM
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
CPU_VID
0.457 MM
I125
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_AGTL
PCIE
CPU_AGTL
CPU_AGTL
FDI_INT
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
XDP_CPU_PWRGOOD
XDP_BDRESET_L
XDP_PRDY_L
XDP_PREQ_l
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_CPU_PWRGD
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_CFG
CPU_CFG
CPU_CATERR_L
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_COMP
CPU_COMP
CPU_COMP
CPU_ITP
CPU_ITP
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_SM_RCOMP2
CPU_CFG<11..0>
CPU_CFG<17..16>
CPU_CATERR_L
CPU_PROC_SEL_L
TP_CPU_VTT_SELECT
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_55S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_8MIL
CPU_AGTL
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
CPU_PSI_L
PM_DPRSLPVR
CPU_PEG_COMP
CPU_PEG_RBIAS
CPU_COMP3
CPU_COMP2
CPU_COMP1
CPU_COMP0
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<3..0>
XDP_BPM_L<7..4>
XDP_CPURST_L
CPU_55S
CPU_50S
CPU_8MIL
CPU_AGTL
CPU_VID<6..0>
CPUIMVP_IMON
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
DMI_CLK100M
CPU_COMP
20 MIL
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
6 9 17
6 9 17
6 9 17
6 9 17
9 17
9 17
9 17
9 17
8 MIL
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CPU_AGTL
CPU_8MIL
DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
I126
10 16
10 16
Most CPU signals with impedance requirements are 50-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8
PCI-Express
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
9 17
10 19 45
10 17
10 17 29
23
10 23 25
10 23
10 23
PCIE_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
CLK_PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=3X_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4X_DIELECTRIC
PCIE
I124
PCIE
TOP,BOTTOM
CLK_PCIE
20 MIL
I115
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
C
XDP_CLK_CPU
XDP_CLK_CPU
XDP_CLK_PCH
XDP_CLK_PCH
XDP_CLK_ITP
XDP_CLK_ITP
PM_DPRSLPVR
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM
XDP_BPM_L
(FSB_CPURST_L)
9 23
9 23
10
10 17
8
10 46 68
10 19 23
10 19
C
10 16
10 16
16 23
16 23
23
23
10 23
10 23
10 23
10 23
10 23
10 23
10 23
23
I120
I121
I122
I123
PM_DPRSLPVR
PEG_R2D
PEG_D2R
CPU_55S
CPU_50S
CPU_50S
CPU_50S
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
GFX_VID<6..0>
GFX_DPRSLPVR
GFX_VR_EN
GFXIMVP_IMON
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CPU_50S
CPU_50S
CPU_50S
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
CPU_VID
CPU_VID
CPU_VID
PEG_R2D_P<7..0>
PEG_R2D_N<7..0>
PEG_R2D_C_P<7..0>
PEG_R2D_C_N<7..0>
PEG_D2R_P<7..0>
PEG_D2R_N<7..0>
PEG_D2R_C_P<7..0>
PEG_D2R_C_N<7..0>
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
12 68
12 68
12 70
12 70
12 68
12 68
12
12
12
12
74
74
8 74
8 74
8 74
8 74
74
74
12 68
12 68
SYNC_MASTER=K91_MLB
PAGE TITLE
CPU Constraints
12 68
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
100 OF 132
SHEET
92 OF 105
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_37S
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
MEM_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_A_CLK
MEM_A_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK
MEM_B_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
11 26
11 26
MEM_72D
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
11 26
11 26
11 26
MEM_85D
SPACING_RULE_SET
LAYER
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
WEIGHT
MEM_CLK2MEM
=4:1_SPACING
11 26
11 26
11 26
11 26
11 26
MEM_CTRL2CTRL
=3:1_SPACING
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
?
MEM_CMD2MEM
=3:1_SPACING
MEM_DATA2DATA
=1.5:1_SPACING
MEM_DATA2MEM
=3:1_SPACING
11 27
11 27
11 27
11 27
11 26 27
11 27
11 27
11 27
MEM_DQS2MEM
=3:1_SPACING
MEM_2OTHER
25 MILS
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_DQS2MEM
MEM_CTRL
MEM_2OTHER
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DQS
MEM_DQS
MEM_DQS2MEM
MEM_DATA
MEM_2OTHER
MEM_DQS
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR3:
11 26 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 28
11 28
MEM_DQS
11 27
DQ/DM signals should be matched within 0.508mm of associated DQS pair.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 27
11 27
11 27
11 27
11 27 28
11 27
11 27
11 27
SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2
11 27 28
11 27 28
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
SYNC_MASTER=K17_MLB
PAGE TITLE
Memory Constraints
11 27
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
101 OF 132
SHEET
93 OF 105
Digital Video Signal Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DP_85D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LVDS_85D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
PCH Net Properties
PHYSICAL_RULE_SET
4
NET_TYPE
PHYSICAL
SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
ISL3,ISL4,ISL9,ISL10
=4:1_SPACING
LVDS
=4:1_SPACING
DISPLAYPORT
TOP,BOTTOM
=4:1_SPACING
LVDS
TOP,BOTTOM
=4:1_SPACING
DP_AUX_CH
DP_AUX_CH
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
DP_SATA_G3_R2D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_HDD_R2D_C_P
6 16 41
SATA_HDD_R2D_C_N
6 16 41
SATA_HDD_R2D_P
6 41
SATA_HDD_R2D_N
6 41
SATA_HDD_R2D_UF_P
6 41
SATA_HDD_R2D_UF_N
6 41
SATA_HDD_R2D_RDRVR_OUT_P 6 41
SATA_HDD_R2D_RDRVR_OUT_N 6 41
SATA_HDD_R2D_RDRVR_IN_P 6 41
SATA_HDD_R2D_RDRVR_IN_N 6 41
SATA_HDD_R2D_RC_UF_P
6 41
SATA_HDD_R2D_RC_UF_N
6 41
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_HDD_D2R_P
6 16 41
SATA_HDD_D2R_N
6 16 41
SATA_HDD_D2R_RDRVR_OUT_P 6 41
SATA_HDD_D2R_RDRVR_OUT_N 6 41
SATA_HDD_D2R_RDRVR_IN_P 6 41
SATA_HDD_D2R_RDRVR_IN_N 6 41
SATA_HDD_D2R_C_P
6 41
SATA_HDD_D2R_C_N
6 41
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA
SATA
SATA
SATA
SATA
SATA
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
PCH_SATA3_ICOMP
PCH_SATA_ICOMP
SATA_50SE
SATA_37SE
SATA_ICOMP
SATA_ICOMP
PCH_SATA3COMP
PCH_SATAICOMP
USB_HUB1_UP
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
PCH_USB_RBIAS
USB_85D
USB_85D
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_RBIAS
USB
USB
USB_HUB1_UP_P
USB_HUB1_UP_N
USB_HUB2_UP_P
USB_HUB2_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
PCH_USB_RBIAS
USB_T29A_P
USB_T29A_N
8 17 84
8 17 84
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA Interface Constraints
18 88
18 88
18 88
18 88
8 18
8 18
18 88
18 88
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SATA_37SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
SATA_50SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
SATA_HDD_RDVR_R2D
DP_SATA_G3_R2D
SPACING_RULE_SET
WEIGHT
SATA
LAYER
=5:1_SPACING
SATA_ICOMP
15 MIL
SPACING_RULE_SET
LAYER
WEIGHT
=5:1_SPACING
DP_SATA_G3_R2D
SATA
TOP,BOTTOM
DP_SATA_G3_R2D
DP_SATA_G3_R2D
SATA_HDD_D2R
SATA_HDD_D2R
SATA_HDD_D2R
SATA_HDD_RDVR_D2R
USB 2.0 Interface Constraints

SATA_ODD_R2D
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

PCH_USB_RBIAS
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
USB_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=4:1_SPACING
SPACING_RULE_SET
LAYER
WEIGHT
SATA_ODD_D2R
USB
TOP,BOTTOM
=4:1_SPACING
?
SATA_ODD_D2R
USB_RBIAS
15 MIL
16 41
16 41
6 41
6 41
41
41
USB
SATA_ODD_R2D
SATA_ODD_D2R
USB_HUB2_UP
USB_EXTA
USB_EXTB
USB_EXTC
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
PCH_USB_RBIAS
USB_T29A
16 41
16 41
41
41
6 41
6 41
16
16
18 24
18 24
18 24
18 24
24 42
24 42
24 42
24 42
24 43
24 43
6 31
6 31
6 24 31
6 24 31
24 53
24 53
24 44
24 44
18
8 24
8 24
SYNC_MASTER=K92_YUN
PAGE TITLE
PCH Constraints 1
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
102 OF 132
SHEET
94 OF 105
LPC Bus Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LPC_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PCH Net Properties
PHYSICAL_RULE_SET
4
NET_TYPE
PHYSICAL
SPACING
SPACING_RULE_SET
LAYER
WEIGHT
6 MIL
LPC
CLK_LPC
8 MIL
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_50S
LPC_50S
LPC_50S
LPC
LPC
LPC
LPC_AD<3..0>
LPC_FRAME_L
LPCPLUS_RESET_L
PCH_LPC_CLK0
PCH_LPC_CLK0
PCH_LPC_CLK0
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC
CLK_LPC
CLK_LPC
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_PCH_1_CLK
SMBUS_PCH_1_DATA
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
HDA_BIT_CLK
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
SPI_CLK
SPI_CLK
SPI_MOSI
SPI_MOSI
SPI_MISO
SPI_CS0
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
PCIE_ENET_R2D
PCIE_ENET_R2D
PCIE_ENET_R2D
PCIE_ENET_R2D
PCIE_ENET_D2R
PCIE_ENET_D2R
PCIE_ENET_D2R
PCIE_ENET_D2R
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PCIE_FW_R2D
PCIE_FW_R2D
PCIE_FW_R2D
PCIE_FW_R2D
PCIE_FW_D2R
PCIE_FW_D2R
PCIE_FW_D2R
PCIE_FW_D2R
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_50S
CPU_50S
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_R2D_P<3..0>
PCIE_T29_R2D_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
PCIE_T29_D2R_C_P<3..0>
PCIE_T29_D2R_C_N<3..0>
SPACING_RULE_SET
LAYER
WEIGHT
HDA_SYNC
SMB
=2x_DIELECTRIC
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
HDA_SDOUT
HDA_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
6 16 45 47 88
6 16 45 47 88
6 25 47 88
18 25
25 45
6 25 47
6 16 23 26 28 30 32 41 48 62 89
6 16 23 26 28 30 32 41 48 62 89
16 48
16 48
16 48
16 48
16 57
16
16 57
16
16
16 57
16 57
57
16 57
16
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
HDA
SIO Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
16 47
47
16 47
47
16 47
16 47
47
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
8 MIL
SPI Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPI
8 MIL
B
I253
I254
I262
I261
PCIE_CLK100M
PCIE_CLK100M
PCIE_CLK100M_T29_
PCIE_CLK100M_T29_
I255
I257
I256
I259
PCIE_CLK100M
PCIE_CLK100M
I258
I260
PCIE_CLK100M
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_FW
PCIE_CLK100M_EXCARD
I263
I264
I265
I267
I266
I268
I270
I269
PCIE_T29_R2D
PCIE_T29_R2D
PCIE_T29_R2D
PCIE_T29_R2D
PCIE_T29_D2R
PCIE_T29_D2R
PCIE_T29_D2R
PCIE_T29_D2R
36
36
16 36
16 36
16 36
16 36
36
36
6 31
6 31
16 31
16 31
6 16 31
6 16 31
31
31
31
31
38
38
16 38
16 38
16 38
16 38
38
38
16
16
16 33
16 33
16
16
16
16
16
16 25
16 74
16 74
16 36
16 36
16 31
16 31
16 38
16 38
16 32
16 32
8 33
8 33
33
SYNC_MASTER=K91_MLB
PAGE TITLE
PCH Constraints 2
33
DRAWING NUMBER
8 33
8 33
Apple Inc.
33

R
33
SIZE
REVISION
BRANCH
PAGE
103 OF 132
SHEET
95 OF 105
CAESAR II (Ethernet) Constraints
Ethernet Net Properties

NET_TYPE
PHYSICAL
SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=3:1_SPACING
ENET_50S
ENET_50S
ENET_50S
ENET_3X
ENET_3X
ENET_3X
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
ENET_RESET_L
ENET_100D
ENET_100D
ENET_MDI
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
32 36
ENET_3X
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
36 37
36 37
CAESAR II (Ethernet PHY) Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
0.6 MM
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
FireWire Interface Constraints
FireWire Net Properties

NET_TYPE
SPACING
PHYSICAL
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
SPACING_RULE_SET
LAYER
I162
I163
WEIGHT
I164
FW_TP
=3:1_SPACING
I165
FW_P1_TPA
FW_P1_TPA
FW_P1_TPB
FW_P1_TPB
FW_110D
FW_110D
FW_110D
FW_110D
FW_TP
FW_TP
FW_TP
FW_TP
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_PORT1_TPB_N
38 40
38 40
38 40
38 40
Port 0 and 2 Not Used
SYNC_MASTER=K91_MLB
PAGE TITLE
Ethernet/FW Constraints
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
104 OF 132
SHEET
96 OF 105
DisplayPort Signal Constraints
4
T29 I2C Signal Constraints
T29_R2D0
T29_R2D0
T29_R2D1
T29_R2D1
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

T29_I2C_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=55_OHM_SE
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
T29_D2R0
T29_D2R0
T29_D2R1
T29_D2R1
T29_I2C
T29/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
D T29 SPI Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
T29_SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
NET_TYPE
SPACING
PHYSICAL
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29_R2D_P<0>
T29_R2D_N<0>
T29_R2D_P<1>
T29_R2D_N<1>
T29_R2D_C_F_P<1..0>
T29_R2D_C_F_N<1..0>
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29_D2R_C_P<1>
T29_D2R_C_N<1>
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
DP_SDRVA_ML_C_P<3..0>
DP_SDRVA_ML_C_N<3..0>
DP_SDRVA_ML_R_P<3..0>
DP_SDRVA_ML_R_N<3..0>
DP_SDRVA_ML_P<2..0:2>
DP_SDRVA_ML_N<2..0:2>
DP_SDRVA_ML_P<3..1:2>
DP_SDRVA_ML_N<3..1:2>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DPA_ML_P<3..0>
T29DPA_ML_N<3..0>
T29DPA_ML_C_P<3..0>
T29DPA_ML_C_N<3..0>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29_R2D_P<2>
T29_R2D_N<2>
T29_R2D_P<3>
T29_R2D_N<3>
T29_R2D_C_F_P<3..2>
T29_R2D_C_F_N<3..2>
T29_D2R_C_P<2>
T29_D2R_C_N<2>
T29_D2R_C_P<3>
T29_D2R_C_N<3>
T29DPB_D2R3_AUXCH_P
T29DPB_D2R3_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
DP_SDRVB_ML_C_P<3..0>
DP_SDRVB_ML_C_N<3..0>
DP_SDRVB_ML_R_P<3..0>
DP_SDRVB_ML_R_N<3..0>
DP_SDRVB_ML_P<2..0:2>
DP_SDRVB_ML_N<2..0:2>
DP_SDRVB_ML_P<3..1:2>
DP_SDRVB_ML_N<3..1:2>
DP_SDRVB_AUXCH_P
DP_SDRVB_AUXCH_N
DP_SDRVB_AUXCH_C_P
DP_SDRVB_AUXCH_C_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DPB_ML_P<3..0>
T29DPB_ML_N<3..0>
T29DPB_ML_C_P<3..0>
T29DPB_ML_C_N<3..0>
DP_B_EXT_AUXCH_P
DP_B_EXT_AUXCH_N
6 85
6 85
6 85
6 85
85
85
6 85 86
6 85 86
6 85 86
6 85 86
6 86
6 86
WEIGHT
T29_SPI
=2x_DIELECTRIC
DP_SDRVA_ML_EVEN
DP_SDRVA_ML_EVEN
DP_SDRVA_ML_ODD
DP_SDRVA_ML_ODD
DP_SDRVA_AUXCH
DP_SDRVA_AUXCH
T29/DP Connector Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
T29DP_80D
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
T29DP_100D
SPACING_RULE_SET
LAYER
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
T29DP
=5x_DIELECTRIC
T29DP
TOP,BOTTOM
=7x_DIELECTRIC
SOURCE: Bill Corneliuss T29 Routing Notes
T29_R2D2
T29_R2D2
T29_R2D3
T29_R2D3
T29_D2R2
T29_D2R2
T29_D2R3
T29_D2R3
DP_SDRVB_ML_EVEN
DP_SDRVB_ML_EVEN
DP_SDRVB_ML_ODD
DP_SDRVB_ML_ODD
DP_SDRVB_AUXCH
DP_SDRVB_AUXCH
B T29 IC Net Properties

DP_T29SNK0_ML
DP_T29SNK0_ML
DP_T29SNK0_AUXCH
DP_T29SNK0_AUXCH
DP_T29SNK1_ML
DP_T29SNK1_ML
DP_T29SNK1_AUXCH
DP_T29SNK1_AUXCH
A
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
NET_TYPE
PHYSICAL
SPACING
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_ML_P<3..0>
DP_T29SNK0_ML_N<3..0>
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_ML_P<3..0>
DP_T29SNK1_ML_N<3..0>
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
DP_85D
DP_85D
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_T29SRC_ML_C_P<3..0>
DP_T29SRC_ML_C_N<3..0>
DP_T29SRC_AUXCH_C_P
DP_T29SRC_AUXCH_C_N
T29_I2C_55S
T29_I2C_55S
T29_I2C
T29_I2C
I2C_T29_SCL
I2C_T29_SDA
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI
T29_SPI
T29_SPI
T29_SPI
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29_R2D_C_P<3..0>
T29_R2D_C_N<3..0>
T29_D2R_P<3..0>
T29_D2R_N<3..0>
6 85
6 85
6 85
6 85
6 85 97
6 85 97
85
85
85
85
85
85
6 85 86
6 85 86
85 86
85 86
85 86
85 86
Only used on dual-port hosts.

97
97
6 33 79
6 33 79
6 33
6 33
6 33 79
6 33 79
6 33
6 33
6 33 79
6 33 79
6 33
6 33
6 33 79
6 33 79
6 33
6 33
Only used on hosts supporting T29 video-in
33 48 85
SYNC_MASTER=T29_REF
33 48 85
PAGE TITLE
T29 Constraints
33
DRAWING NUMBER
Apple Inc.
33
SIZE
33
REVISION
33
BRANCH
6 8 33 85

6 8 33 85
6 8 33 85
6 8 33 85
PAGE
105 OF 132
SHEET
97 OF 105
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
SPACING
PHYSICAL
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
6 31 45 48 54 55
6 31 45 48 54 55
45 48 51
45 48 51
6 31 45 48 51 80
6 31 45 48 51 80
6 45 48 63 64
6 45 48 63 64
45 48 103 104
45 48 103 104
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
SPACING
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO_P
CHGR_CSO_N
64
64
64
64
SYNC_MASTER=K17_MLB
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
106 OF 132
SHEET
98 OF 105
GDDR5 Frame Buffer Signal Constraints
GDDR5 FB A Net Properties
GDDR5 FB B Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

GDDR5_45R50SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
12.7 MM
=STANDARD
=STANDARD
GDDR5_45SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
GDDR5_80D
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
GDDR5_CLK
=5x_DIELECTRIC
?
GDDR5_CMD
=2x_DIELECTRIC
?
GDDR5_DATA
=3x_DIELECTRIC
?
GDDR5_EDC
=7x_DIELECTRIC
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

DP_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
=3x_DIELECTRIC
I293
I294
I295
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
I296
I297
LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel.
DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm.
DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
Max length of LVDS/DisplayPort/TMDS traces: 13 inches.
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
I298
Max Length 241.3mm.
I299
I300
I301
I302
I303
I304
FB_A0_CLK
FB_A0_CLK
FB_A1_CLK
FB_A1_CLK
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_EDC0
FB_A0_EDC1
FB_A0_EDC2
FB_A0_EDC3
FB_A1_EDC0
FB_A1_EDC1
FB_A1_EDC2
FB_A1_EDC3
FB_A0_DBI_L0
FB_A0_DBI_L1
FB_A0_DBI_L2
FB_A0_DBI_L3
FB_A1_DBI_L0
FB_A1_DBI_L1
FB_A1_DBI_L2
FB_A1_DBI_L3
FB_A0_WCLK0
FB_A0_WCLK0
FB_A0_WCLK1
FB_A0_WCLK1
FB_A1_WCLK0
FB_A1_WCLK0
FB_A1_WCLK1
FB_A1_WCLK1
FB_A0_DQ_BYTE0
FB_A0_DQ_BYTE1
FB_A0_DQ_BYTE2
FB_A0_DQ_BYTE3
FB_A1_DQ_BYTE0
FB_A1_DQ_BYTE1
FB_A1_DQ_BYTE2
FB_A1_DQ_BYTE3
FB_AB_RESET
PHYSICAL
NET_TYPE
SPACING
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45R50SE
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
FB_A0_CLK_P
FB_A0_CLK_N
FB_A1_CLK_P
FB_A1_CLK_N
FB_A0_A<8..0>
FB_A1_A<8..0>
FB_A0_ABI_L
FB_A1_ABI_L
FB_A0_RAS_L
FB_A1_RAS_L
FB_A0_CAS_L
FB_A1_CAS_L
FB_A0_WE_L
FB_A1_WE_L
FB_A0_CKE_L
FB_A1_CKE_L
FB_A0_CS_L
FB_A1_CS_L
FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>
FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>
FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>
FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>
FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>
FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>
FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>
FB_A0_DQ<7..0>
FB_A0_DQ<15..8>
FB_A0_DQ<23..16>
FB_A0_DQ<31..24>
FB_A1_DQ<7..0>
FB_A1_DQ<15..8>
FB_A1_DQ<23..16>
FB_A1_DQ<31..24>
FB_RESET_L
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
I305
76 77
I306
76 77
I307
76 77
I310
76 77
I309
76 77
I308
76 77
76 77
76 77
I311
76 77
I312
76 77
I313
76 77
I316
76 77
I315
76 77
I314
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
FB_B0_CLK
FB_B0_CLK
FB_B1_CLK
FB_B1_CLK
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_EDC0
FB_B0_EDC1
FB_B0_EDC2
FB_B0_EDC3
FB_B1_EDC0
FB_B1_EDC1
FB_B1_EDC2
FB_B1_EDC3
FB_B0_DBI_L0
FB_B0_DBI_L1
FB_B0_DBI_L2
FB_B0_DBI_L3
FB_B1_DBI_L0
FB_B1_DBI_L1
FB_B1_DBI_L2
FB_B1_DBI_L3
FB_B0_WCLK0
FB_B0_WCLK0
FB_B0_WCLK1
FB_B0_WCLK1
FB_B1_WCLK0
FB_B1_WCLK0
FB_B1_WCLK1
FB_B1_WCLK1
FB_B0_DQ_BYTE0
FB_B0_DQ_BYTE1
FB_B0_DQ_BYTE2
FB_B0_DQ_BYTE3
FB_B1_DQ_BYTE0
FB_B1_DQ_BYTE1
FB_B1_DQ_BYTE2
FB_B1_DQ_BYTE3
PHYSICAL
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45R50SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
LVDS_A_CLK
LVDS_A_CLK
LVDS_A_DATA
LVDS_A_DATA
LVDS_B_CLK
LVDS_B_CLK
LVDS_B_DATA
LVDS_B_DATA
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
Whistler Net Properties

NET_TYPE
NET_TYPE
FB_B0_CLK_P
FB_B0_CLK_N
FB_B1_CLK_P
FB_B1_CLK_N
FB_B0_A<8..0>
FB_B1_A<8..0>
FB_B0_ABI_L
FB_B1_ABI_L
FB_B0_RAS_L
FB_B1_RAS_L
FB_B0_CAS_L
FB_B1_CAS_L
FB_B0_WE_L
FB_B1_WE_L
FB_B0_CKE_L
FB_B1_CKE_L
FB_B0_CS_L
FB_B1_CS_L
FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>
FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>
FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>
FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>
FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>
FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>
FB_B0_DQ<7..0>
FB_B0_DQ<15..8>
FB_B0_DQ<23..16>
FB_B0_DQ<31..24>
FB_B1_DQ<7..0>
FB_B1_DQ<15..8>
FB_B1_DQ<23..16>
FB_B1_DQ<31..24>
76 77 78
MUXGFX Net Properties

SPACING
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
PHYSICAL
SPACING
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_A_DATA_P<2..0>
LVDS_A_DATA_N<2..0>
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_B_DATA_P<2..0>
LVDS_B_DATA_N<2..0>
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_A_CLK_P
LVDS_CONN_A_CLK_N
LVDS_CONN_A_DATA_P<2..0>
LVDS_CONN_A_DATA_N<2..0>
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
LVDS_CONN_B_DATA_P<2..0>
LVDS_CONN_B_DATA_N<2..0>
84 88
84 88
84 88
84 88
84 88
84 88
84 88
84 88
6 83
6 83
6 83
PHYSICAL
GPU_CLK27M
GPU_CLK100M
LVDS_EG_A_CLK
LVDS_EG_A_CLK
LVDS_EG_A_DATA
LVDS_EG_A_DATA
LVDS_EG_A_DATA3
LVDS_EG_A_DATA3
LVDS_EG_B_DATA
LVDS_EG_B_DATA
LVDS_EG_B_DATA3
LVDS_EG_B_DATA3
CLK_SLOW_55S
CLK_SLOW_55S
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
LVDS_85D
DP_ML
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
SPACING
CLK_SLOW
CLK_SLOW
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
GPU_CLK27M
GPU_CLK100M
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P<2..0>
LVDS_EG_A_DATA_N<2..0>
LVDS_EG_B_DATA_P<2..0>
LVDS_EG_B_DATA_N<2..0>
79 80
79 80
79 88
79 88
79 88
79 88
79 80
79 80
79 88
79 88
79 80
79 80
6 83
83 84
83 84
6 83 84
DP_AUX_CH
6 83 84
83 84
DP_AUX_CH
83 84
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_EXTA_ML_C_P<3..0>
DP_EXTA_ML_C_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
79 85
79 85
84 85
84 85
79 84
79 84
6 83 84
6 83 84
SYNC_MASTER=K91_MLB
PAGE TITLE
GPU (Whistler) CONSTRAINTS

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
107 OF 132
SHEET
99 OF 105
K92 Specific Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
NET_TYPE
PHYSICAL
SPACING
NET_TYPE
SENSE_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
THERM_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
AUDIODIFF
=1:1_DIFFPAIR
ENETCONN
ENET_100D
ENETCONN
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
10 MM
0.1 MM
0.1 MM
0.1 MM
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
NET_SPACING_TYPE1
SPACING_RULE_SET
LAYER
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SENSE_DIFFPAIR
WEIGHT
CPU_COMP
SENSE
=2:1_SPACING
GND
GND_P2MM
SENSE_DIFFPAIR
CPU_VCCSENSE
THERM
=2:1_SPACING
GND
GND_P2MM
?
SENSE_DIFFPAIR
AUDIO
=2:1_SPACING
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
ENETCONN
25 MILS
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
ENET_MDI
GND
GND_P2MM
SENSE_DIFFPAIR
?
I249
SPACING_RULE_SET
LAYER
WEIGHT
GND
=STANDARD
SENSE_DIFFPAIR
I250
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
GND_P2MM
PCIE
GND
GND_P2MM
SATA
GND
GND_P2MM
I252
SENSE_DIFFPAIR
I251
I256
SENSE_DIFFPAIR
I255
SPACING_RULE_SET
LAYER
WEIGHT
I281
0.20 MM
1000
PWR_P2MM
0.20 MM
1000
USB
GND
GND_P2MM
CLK_PCIE
SB_POWER
PWR_P2MM
SENSE_DIFFPAIR
I282
GND_P2MM
I283
SENSE_DIFFPAIR
I284
I285
SENSE_DIFFPAIR
SATA
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SB_POWER
I286
PWR_P2MM
USB
MEM_CLK
GND
SB_POWER
I369
PWR_P2MM
GND_P2MM
MEM_CMD
GND
GND_P2MM
GND
GND_P2MM
MEM_DATA
GND
GND_P2MM
I372
SENSE_DIFFPAIR
I371
SENSE_DIFFPAIR
I370
MEM_CTRL
I374
SENSE_DIFFPAIR
I373
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I375
MEM_DQS
GND
GND_P2MM
SENSE_DIFFPAIR
LVDS
GND
I376
GND_P2MM
I377
SENSE_DIFFPAIR
I378
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
MEM_72D
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
10 mm
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
USB_85D
TOP
OVERRIDE
OVERRIDE
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
I385
SENSE_DIFFPAIR
I396
I398
OVERRIDE
SENSE_DIFFPAIR
I384
I395
OVERRIDE
SENSE_DIFFPAIR
I383
I386
SENSE_DIFFPAIR
I380
I382
OVERRIDE
PCIE_85D
I379
I381
OVERRIDE
VCCSAS0_CS_P
VCCSAS0_CS_N
VCCSAISNS_R_P
VCCSAISNS_R_N
ISNS_1V5_S3_R_P
ISNS_1V5_S3_R_N
CPUVCCIOS0_CS_P
CPUVCCIOS0_CS_N
CPUVCCIOISNS_R_P
CPUVCCIOISNS_R_N
GPUISENS_N
GPUISENS_P
ISNS_1V5_S3_N
ISNS_1V5_S3_P
ISNS_AIRPORT_P
ISNS_AIRPORT_N
ISNS_PP1V0_S0GPU_P
ISNS_PP1V0_S0GPU_N
ISNS_PP1V8_S0GPU_P
ISNS_PP1V8_S0GPU_N
ISNS_HDD_N
ISNS_HDD_P
ISNS_PP1V5_S0GPU_P
ISNS_PP1V5_S0GPU_N
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
ISNS_ODD_N
ISNS_ODD_P
49 65
SENSE_DIFFPAIR
I397
I400
SENSE_DIFFPAIR
SENSE_DIFFPAIR
I387
I390
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
I392
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
I389
I391
SENSE
SENSE_1TO1_55S
I399
I388
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
ISNS_HS_COMPUTING_P
ISNS_HS_COMPUTING_N
ISNS_HS_GPU_P
ISNS_HS_GPU_N
ISNS_HS_OTHER_P
ISNS_HS_OTHER_N
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N
CPUIMVP_ISNS_P
CPUIMVP_ISNS_N
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N
CPUIMVP_ISNS1G_R_P
CPUIMVP_ISNS1G_R_N
ISNS_PP1V0_S0GPU_R_P
ISNS_PP1V0_S0GPU_R_N
ISNS_AIRPORT_R_P
ISNS_AIRPORT_R_N
ISNS_HDD_R_P
ISNS_HDD_R_N
ISNS_ODD_R_P
ISNS_ODD_R_N
PCIE_EXCARD_R2D
I350
49 65
I351
49
I352
49
I354
49
I353
49
I356
49 70
I355
PCIE_EXCARD_D2R
PCIE_EXCARD_R2D
PCIE_CLK100M_EXCARD
SPACING
PHYSICAL
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CLK_PCIE_90D
CLK_PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
CLK_PCIE
CLK_PCIE
PCIE_EXCARD_R2D_P
6 32
PCIE_EXCARD_R2D_N
6 32
PCIE_EXCARD_D2R_P
6 16 32
PCIE_EXCARD_D2R_N
6 16 32
PCIE_EXCARD_R2D_C_P
16 32
PCIE_EXCARD_R2D_C_N
16 32
PCIE_CLK100M_EXCARD_CONN_P 6 32
PCIE_CLK100M_EXCARD_CONN_N 6 32
49 70
49
49
I361
49
I362
PCIE_CLK100M_AP
49
49 67
49 67
31 103
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
103
USB_85D
USB
41 103
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
31 103
103
103
103
(USB_EXTB)
41 103
103
103
I358
89 103
I357
89 103
I359
41 103
I360
41 103
I363
SPACING_RULE_SET
37
I349
0.1 MM
37
=1:1_DIFFPAIR
DIFFPAIR
ENET_100D
ENETCONN_P<3..0>
ENETCONN_N<3..0>
50
USB_EXCARD
USB_EXCARD
(USB_EXTC)
I364
50
50
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_LT1_P
USB2_LT1_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_LT2_P
USB_LT2_N
USB_EXCARD_P
USB_EXCARD_N
USB2_EXCARD_CONN_P
USB2_EXCARD_CONN_N
6 31
6 31
64
64
50 64
50 64
42
42
42
42
42
42
8 24 32
8 24 32
6 32
6 32
USB_LT3_P
USB_LT3_N
43
43
USB_TPAD_R_P
USB_TPAD_R_N
53
53
50
50
50
50 68 69
SB_POWER
50 69
SB_POWER
50
SB_POWER
50
GND
48 56 71 72 73 83 86 91 102 104
6 7 17 19 20 22 23 24 25 29 46
PP3V3_S5
PP3V3_S0
PP1V5_S3RS0
61 62 72 73 80 83 84 85 88 89
6 7 12 23 25 26 28 32 35 36 39
40 41 46 48 49 50 51 52 54 57
91 102
7 72 104
GND
50
50
50 69
50 69
50
50
NET_TYPE
50
50
PHYSICAL
SPACING
103
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
103
103
I287
SENSE_DIFFPAIR
103
I288
103
SENSE_DIFFPAIR
103
103
SENSE_DIFFPAIR
103
103
I367
SENSE_DIFFPAIR
103
I368
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
51
51
CPU_THERMD_P
CPU_THERMD_N
GPUTHMSNS_D_P
GPUTHMSNS_D_N
GPU_TDIODE_P
GPU_TDIODE_N
T29_THERMD_P
T29_THERMD_N
9 51
9 51
51
51
51 79
51 79
33 51
51
103
103
B
SENSE_DIFFPAIR
I402
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
I401
I312
AUDIO_DIFFPAIR
AUDIODIFF
I311
I314
AUDIO_DIFFPAIR
I313
I316
AUDIO_DIFFPAIR
I315
Graphics ,SATA Constraint Relaxations
I329
AUDIO_DIFFPAIR
I330
I331
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
LVDS_85D
BGA
LVDS_85D
AUDIO_DIFFPAIR
I332
TABLE_PHYSICAL_ASSIGNMENT_HEAD
I333
AUDIO_DIFFPAIR
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I334
I317
DP_85D
BGA
100_DIFF_BGA
SATA_90D
BGA
I319
100_DIFF_BGA
BGA
AUDIO_DIFFPAIR
I320
CLK_PCIE_90D
AUDIO_DIFFPAIR
I318
100_DIFF_BGA
I321
AUDIO_DIFFPAIR
I322
I340
A Memory Constraint Relaxations

LAYER
MEM_72D
BOTTOM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.127 MM
6.35 MM
DIFFPAIR NECK GAP
I338
I342
TOP
0.1 MM
6.35 MM
AUDIO_DIFFPAIR
I337
MEM_85D
AUDIO_DIFFPAIR
I336
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

PHYSICAL_RULE_SET
AUDIO_DIFFPAIR
I339
I335
AUDIO_DIFFPAIR
I341
I344
AUDIO_DIFFPAIR
I343
I346
AUDIO_DIFFPAIR
I345
I348
AUDIO_DIFFPAIR
I347
AUDIODIFF
AUDIO
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
BI_MIC_P
BI_MIC_N
AUD_LO1_R_P
AUD_LO1_R_N
AUD_LO2_R_P
AUD_LO2_R_N
AUD_LO3_R_P
AUD_LO3_R_N
AUD_LO3_L_P
AUD_LO3_L_N
AUD_MIC_INR_P
AUD_MIC_INR_N
AUD_MIC_INL_P
AUD_MIC_INL_N
SPKRAMP_BL_IN_L_P
SPKRAMP_BL_IN_L_N
SPKRAMP_FL_IN_L_P
SPKRAMP_FL_IN_L_N
SPKRAMP_BR_IN_L_P
SPKRAMP_BR_IN_L_N
SPKRAMP_FR_IN_L_P
SPKRAMP_FR_IN_L_N
SPKRAMP_LFE_IN_L_P
SPKRAMP_LFE_IN_L_N
SSM2375BL_IN_P
SSM2375BL_IN_N
SSM2375FL_IN_P
SSM2375FL_IN_N
SSM2375BR_IN_P
SSM2375BR_IN_N
SSM2375FR_IN_P
SSM2375FR_IN_N
SSM2375LFE_IN_P
SSM2375LFE_IN_N 60
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
61 62
I292
SENSE_DIFFPAIR
61 62
I291
58 60
I299
SENSE_DIFFPAIR
58 60
I300
57 60
I301
SENSE_DIFFPAIR
57 60
I302
57 60
I303
SENSE_DIFFPAIR
57 60
I304
57 60
I305
SENSE_DIFFPAIR
57 60
I306

K91 does not have
ISNS_PP3V3_S3_P
104
ISNS_PP3V3_S3_N
ISNS_PP3V3_S5_N
ISNS_PP3V3_S5_P
104
104
104
ISNS_PP5V_S3_N
ISNS_PP5V_S3_P
104
104
ISNS_PP1V05_S0PCH_N
ISNS_PP1V05_S0PCH_P
ISNS_PP5V_S0_N
ISNS_PP5V_S0_P
ISNS_CPU_DDR_N
ISNS_CPU_DDR_P
104
104
104
104
104
104
57 62
57 62
57 62
57 62
60
60
60
60
60
60
60
60
SYNC_MASTER=K91_MLB
60
PAGE TITLE
60
Project Specific Constraints
60
DRAWING NUMBER
60
60
Apple Inc.
60
SIZE
D
REVISION
R
60
60

60
60
60
BRANCH
PAGE
108 OF 132
SHEET
100 OF 105
K92 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.5.1
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
WEIGHT
DEFAULT
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
DEFAULT
0.1 MM
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
P072_SPACE
STANDARD
NET_SPACING_TYPE1
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
BGA_P2MM
=DEFAULT
P072_SPACE
0.071 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
27P4_OHM_SE
TOP,BOTTOM
0.310 MM
0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
0.250 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
37_OHM_SE
TOP,BOTTOM
0.185 MM
0.095 MM
37_OHM_SE
0.155 MM
0.090 MM
WEIGHT
2X_DIELECTRIC
SPACING_RULE_SET
LAYER
0.140 MM
3X_DIELECTRIC
0.210 MM
4X_DIELECTRIC
0.280 MM
5X_DIELECTRIC
0.350 MM
7X_DIELECTRIC
0.490 MM
SPACING_RULE_SET
LAYER
WEIGHT
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
0.15 MM
2:1_SPACING
0.2 MM
2.5:1_SPACING
0.25 MM
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
40_OHM_SE
TOP,BOTTOM
0.165 MM
0.095 MM
40_OHM_SE
0.135 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
NOTE: Based on K92 mlb stackup.
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
45_OHM_SE
TOP,BOTTOM
0.13 MM
0.13 MM
45_OHM_SE
0.099 MM
0.099 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
0.110 MM
0.095 MM
MAXIMUM NECK LENGTH
5:1_SPACING
0.5 MM
DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
50_OHM_SE
0.090 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
55_OHM_SE
TOP,BOTTOM
0.090 MM
0.090 MM
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
72_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
ISL9,ISL10
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
ISL2,ISL11
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
TOP,BOTTOM
0.175 MM
0.175 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
80_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
80_OHM_DIFF
0.105 MM
0.105 MM
0.120 MM
0.120 MM
80_OHM_DIFF
ISL2,ISL11
0.105 MM
0.105 MM
0.120 MM
0.120 MM
80_OHM_DIFF
TOP,BOTTOM
0.135 MM
0.135 MM
0.160 MM
0.160 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
85_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
85_OHM_DIFF
ISL3,ISL4
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
ISL9,ISL10
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
ISL2,ISL11
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
TOP,BOTTOM
0.125 MM
0.090 MM
0.190 MM
0.190 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL9,ISL10
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL2,ISL11
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
TOP,BOTTOM
0.115 MM
0.090 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
ISL9,ISL10
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
ISL2,ISL11
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
TOP,BOTTOM
0.089 MM
0.089 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.200 MM
0.200 MM
SYNC_MASTER=K17_MLB
PAGE TITLE
PCB Rule Definitions
DRAWING NUMBER
110_OHM_DIFF
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4
0.065 MM
0.065 MM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ISL9,ISL10
0.065 MM
0.065 MM
0.200 MM
0.200 MM
110_OHM_DIFF
ISL2,ISL11
0.065 MM
0.065 MM
0.200 MM
0.200 MM
100_DIFF_BGA
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
0.075 MM
0.075 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
0.125 MM
0.125 MM
0.075 MM
0.075 MM
0.330 MM
0.330 MM
100_DIFF_BGA
ISL9,ISL10
0.075 MM
0.075 MM
0.125 MM
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
BRANCH
TOP,BOTTOM
110_OHM_DIFF
SIZE
REVISION
110_OHM_DIFF
Apple Inc.
PHYSICAL_RULE_SET
0.125 MM

PAGE
109 OF 132
SHEET
101 OF 105
PCH "S0" Rails
73 70 68 45 39 35 23 14 13 12 10 9 7
105 104 102
PP1V05_S0
104 102 22 20 17 16
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PCH "S5" Rail
71 56 48 46 29 25 24 23 22 20 19 17 7 6
104 102 100 91 86 83 73 72
PP1V05_S0
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
7 9 10 12 13 14 23 35 39 45 68 70 73 102
104 105
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
6 7 17 19 20 22 23 24 25 29 46 48 56 71
72 73 83 86 91 100 102 104
16 17 20 22 102 104
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
PPVCCIO_S0_PCH
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
16 17 20 22 102 104
OMIT
RC100
88 72 71 25 20 14 7 6
PP1V8_S0
102 22 20 17
SHORT
NONE
NONE
NONE
603
2 PP1V8_S0_PCH
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V8_S0_PCH
PP1V8_S0_PCH
17 20 22 102
17 20 22 102
OMIT
RC101
100 91 89 88 85 84
46 41 40 39 36 35 32 28 26 25 23 12 7 6
83 80 73 72 62 61 57 54 52 51 50 49 48
PP3V3_S0
102 22 20 19 18 17 16
SHORT
NONE
NONE
NONE
603
2 PP3V3_S0_PCH
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
PP3V3_S0_PCH
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
16 17 18 19 20 22 102
SYNC_MASTER=K17_MLB
PAGE TITLE
PCH Power Aliases

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
121 OF 132
SHEET
102 OF 105
DEBUG_ADC
RD103
DEBUG_ADC
1
V+
100 89
D
100 89
5 IN-
ISNS_LCDBKLT_N
IN
DEBUG_ADC
2
4.53K
OUT 6 ISNS_LCDBKLT_IOUT 1
SC70
4 IN+
ISNS_LCDBKLT_P
IN
PLACE_NEAR=UD100.22:5mm
RD150
INA214
EDP Current: 0.715A
1M
UD120
Sense Resistor 0.025 Ohm
RD156
ADC_CH0
1%
1/16W
MF-LF
402
CD145
0.22UF
2
ADC_CH7
2
1%
1/16W
MF-LF
402
0.1UF
20%
6.3V
X5R
603
20%
10V
CERM
402
RD157
CD152
2.2UF
1%
1/16W
MF-LF
402
10%
6.3V
X5R
402
105
DIVIDER: ~ 1/22
103
22
103
23
ADC_CH0
ADC_CH1
103 ADC_CH2
103 ADC_CH3
103 ADC_CH4
103 ADC_CH5
103 ADC_CH6
103 ADC_CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
24
1
2
3
4
DVDD
PP5V_S5
7 54 66 72 103 104
10UF
RD101
QFN
DEBUG_ADC
11
10
AD0
AD1
14
SDA
SCL
17
33
15
SMBUS_SMC_MGMT_SDA
RD102
ADC_VREF
REFCOMP
ADC_REFCOMP
DEBUG_ADC
DEBUG_ADC
CD104
0.1UF
2
SMBUS_SMC_MGMT_SCL
IN
45 48 98
104
5%
1/16W
MF-LF
402
VREF
LSB: 0.001V
45 48 98
104
33
1
BI
DEBUG_ADC
ADC_SDA
ADC_SCL
16
PLACE_NEAR=U4900.F1:10mm
5%
1/16W
MF-LF
402
THRM
PAD
GND
ADC RANGE: 0V TO 4.096V
20%
6.3V
X5R
603
DEBUG_ADC
LTC2309
I2C ADDRESS: 0X10 / 0X11
CD103
UD100
DEBUG_ADC
1
DEBUG_ADC
CD102
10UF
103
20%
6.3V
X5R
402
GAIN: 100X
CD101
20%
10V
CERM
402
AVDD
226K
1
46.4K
DEBUG_ADC
GND
0.1UF
RD158
DEBUG_ADC
1
CD100
DEBUG_ADC
DEBUG_ADC
VOUT_S0_LCDBKLT_DIV
103
1%
1/16W
MF-LF
402
REF 1
DEBUG_ADC
12
DEBUG_ADC
20%
10V
CERM
402
5%
1/16W
MF-LF
402
21
VOUT_S0_LCDBKLT_XW
0.1UF
VOLTAGE=5V
25
89 83 6
DEBUG_ADC
10
PP5V_S5_DEBUG_ADC_DVDD_FILT
20
CD144
104
VOLTAGE=5V
5%
1/16W
MF-LF
402
SM
PP5V_S5_DEBUG_ADC_AVDD_FILT
13
PPVOUT_S0_LCDBKLT 1
19
DEBUG_ADC
104
XWD150
PP5V_S5
104 103 72 66 54 7
RD104
10
PP5V_S5
104 103 72 66 54 7
18
LCD BKLT Voltage Sense
LCD BKLT Current Sense
DEBUG_ADC
DEBUG_ADC
CD105
CD106
10UF
20%
10V
CERM
402
2.2UF
20%
6.3V
X5R
603
20%
6.3V
CERM
402-LF
AIRPORT Current Sense
104 103 72 66 54 7
PP5V_S5
104 103 72 66 54 7
DEBUG_ADC
1
CD130
RD130
EDP Current: 1.06A
100 31
2.61K
ISNS_AIRPORT_P
IN
100
ISNS_AIRPORT_R_P
8
THRM
2.61K
ISNS_AIRPORT_N
100
ISNS_AIRPORT_R_N
ADC_CH2
1%
1/16W
MF-LF
402
ISNS_ODD_R_P
CD131
100 41
ISNS_ODD_N
IN
GAIN: 383X
V+
100
RD155
1
226K
ISNS_ODD_IOUT
ISNS_ODD_R_N
1%
1/16W
MF-LF
402
GAIN: 226X
NOSTUFF
RD153
RD154
1M
1
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
10%
6.3V
X5R
402
DEBUG_ADC
DEBUG_ADC
1
SIGNAL_MODEL=EMPTY
CD150
103 105
2.2UF
1%
1/16W
MF-LF
402
10%
6.3V
X5R
402
ADC_CH3
VTHRM
NOSTUFF
OPA2333
DFN
1M
1M
1%
1/16W
MF-LF
402
UD140
RD152
4.42K
20%
10V
CERM
402
DEBUG_ADC
8
RD133
1M
100
DEBUG_ADC
103
DEBUG_ADC
2.2UF
DEBUG_ADC
226K
ISNS_AIRPORT_IOUT
1%
1/16W
MF-LF
402
RD132
4.42K
1%
1/16W
MF-LF
402
DEBUG_ADC
1
RD134
V-
ISNS_ODD_P
IN
DEBUG_ADC
DFN
RD131
100 41
OPA2333
DEBUG_ADC
IN
RD151
UD130
V+
100 31
DEBUG_ADC
1%
1/16W
MF-LF
402
CD151
0.1UF
DEBUG_ADC
EDP Current: 1.8A
20%
10V
CERM
402
DEBUG_ADC
DEBUG_ADC
1
0.1UF
PP5V_S5
ODD Current Sense
SIGNAL_MODEL=EMPTY
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
GPU 1.0V Current Sense

HDD Current Sense
EDP Current: 2.846A
87 7
DEBUG_ADC
IN PP1V0_S0GPU_ISNS_R
100
ISNS_PP1V0_S0GPU_P 1
4.22K
81 79 75 74 7
100
1 3
100
ISNS_PP1V0_S0GPU_N
DEBUG_ADC
4.22K
1%
1/16W
MF-LF
402
ISNS_1V0_GPU_IOUT
VTHRM
RD141
OUT PP1V0_S0GPU
RD144
DFN
V+
226K
1%
1/16W
MF-LF
402
100 41
ADC_CH4
1
2.94K
1
CD142
100 41
ISNS_HDD_N
IN
RD143
1
1%
1/16W
MF-LF
2.94K
V+
100
RD164
7
ISNS_HDD_IOUT
VTHRM
DEBUG_ADC
OPA2333
DFN
ISNS_HDD_R_N
226K
ADC_CH5
1%
1/16W
MF-LF
402
10%
6.3V
X5R
402
DEBUG_ADC
SIGNAL_MODEL=EMPTY
DEBUG_ADC
1
RD162
RD163
1M
1M
1
1%
1/16W
MF-LF
2 402
GAIN: 237X
CD140
2.2UF
GAIN: 340X
SIGNAL_MODEL=EMPTY
103
DEBUG_ADC
1%
1/16W
MF-LF
402
2 402
UD140
8
5
1%
1/16W
MF-LF
402
DEBUG_ADC
1M
ISNS_HDD_R_P
RD161
1M
100
DEBUG_ADC
402
RD142
2
1%
1/16W
MF-LF
402
103
2 X5R
DEBUG_ADC
1
RD160
ISNS_HDD_P
IN
2.2UF
10%
6.3V DEBUG_ADC
9
100

EDP Current: 1.2A
DEBUG_ADC
OPA2333
1%
1/16W
MF-LF
402
0.003
RD145
0612
MF
1W
1%
UD130
RD140
2 4
DEBUG_ADC
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
GPU 1.8V Current Sense

104 103 72 66 54 7
PP5V_S5
1
EDP Current: 2.4065A

72 7 6
IN
PP1V8_S0GPU_ISNS_R
DEBUG_ADC
UD180
RD187
RD186 1
3 ISNS_PP1V8_S0GPU_P 1
0.005
1%
1W
MF
0612
A
OUT PP1V8_S0GPU
8
2
ISNS_PP1V8_S0GPU_R_P 5
1%
1/16W
MF-LF
402
2 4
100
79 75 7 6
81
5.90K
ISNS_PP1V8_S0GPU_N 1
OPA2333
1.5V FB Current Sense
20%
10V
EDP Current: 7.8A
CERM
PLACE_NEAR=UD.23:5mm
402
7 ISNS_1V8_S0GPU_IOUT
V-
4.53K
100
ADC_CH1
MF-LF
Gain: 169x
RD180
RD189
1%
1W
MF
0612
0.22UF
20%
6.3V
DEBUG_ADC
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
78 77 76 75 7
OUT
1M
ISNS_PP1V5_S0GPU_P
UD180
8
7.68K
1
OUT
103
402
100
Gain: 130x
20%
6.3V
DEBUG_ADC
DRAWING NUMBER
Apple Inc.
X5R
RD183
1%
1/16W
MF-LF
402
DEBUG_ADC
RD184
1M
1M
1

SIGNAL_MODEL=EMPTY
2
1%
1/16W
MF-LF
402
SIZE
D
REVISION
DEBUG_ADC
0.22UF
2
DEBUG SENSORS AND ADC
CD181
402
PAGE TITLE
1
DEBUG_ADC
9
2
SIGNAL_MODEL=EMPTY
ADC_CH6
1%
MF-LF
1%
1/16W
DEBUG_ADCMF-LF
402
1%
1/16W
MF-LF
402
4.53K
ISNS_1V5_S0GPU_IOUT 1
1/16W
THRM
7.68K
1
RD185
1
V-
SIGNAL_MODEL=EMPTY
V+
RD182
OPA2333
DFN
1%
1/16W
MF-LF
402
100 ISNS_PP1V5_S0GPU_N
RD190
1
1 3
X5R
DEBUG_ADC
1M
DEBUG_ADC
DEBUG_ADC
0.002
402
PLACE_NEAR=UD.23:5mm
DEBUG_ADC
PP1V5_S0GPU_ISNS_R
103
1 CD182
402
DEBUG_ADC
1%
1/16W
MF-LF
402
OUT
1%
IN
RD181
2
1/16W
THRM
87 7
RD191
DFN
V+
RD188
5.90K
CD180
0.1UF
DEBUG_ADC
DEBUG_ADC
BRANCH
PAGE
130 OF 132
SHEET
103 OF 105
DEBUG_ADC
RD201
DEBUG_ADC
CD201
CD202
20%
6.3V
X5R
603
12
AVDD
10UF
20%
6.3V
X5R
603
23
ADC2_CH0
ADC2_CH1
104 ADC2_CH2
104 ADC2_CH3
104 ADC2_CH4
104 ADC2_CH5
104 ADC2_CH6
104 ADC2_CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
24
1
2
3
4
DVDD
DEBUG_ADC
AD0
AD1
14
15
NC
SDA
SCL
17
ADC2_SDA
ADC2_SCL
33
CRITICAL
EDP Current: 13.286A
16
SMBUS_SMC_MGMT_SDA
DEBUG_ADC
PP5V_S3
RD202
33
ADC2_VREF
REFCOMP
ADC2_REFCOMP
DEBUG_ADC
66 7
IN
ISNS_PP5V_S3_N
INA213
5 IN-
SC70
RD221
4.53K
2
OUT 6 ISNS_5V_S3_IOUT1
4 IN+
ISNS_PP5V_S3_P
REF 1
2 4
PP5V_S3_ISNS_R
ADC2_CH3
1%
1/16W
MF-LF
402
GND
OUT
104
DEBUG_ADC
1 CD221
0.22UF PLACE_NEAR=UD210.1:5mm
20%
2 6.3V
X5R
402
Gain: 50x
SMBUS_SMC_MGMT_SCL
DEBUG_ADC
CD205
0.1UF
IN
45 48 98 103
DEBUG_ADC
1
CD206
CD207
10UF
20%
10V
CERM
402
45 48 98 103
1 3
5%
1/16W
MF-LF
402
LSB: 0.001V
BI
DEBUG_ADC
UD221
CRITICAL
1%
1W
100 MF
0612
DEBUG_ADC
VREF
20
OUT
PLACE_NEAR=U4900.F1:8mm
0.1UF
20%
10V
CERM
402
V+
5%
1/16W
MF-LF
402
THRM
PAD
19
18
11
10
DEBUG_ADC
RD220
0.003
RD203
PP5V_S5
1 CD220
DEBUG_ADC
QFN
GND
ADC RANGE: 0V TO 4.096V
104 103 72 66 54 7
100
LTC2309
I2C ADDRESS: 0X32 / 0X33
7 54 66 72 103 104
72 67 46 44 43 42 31 29 7 6
82
25
22
104
CD204
20%
10V
CERM
402
UD210
104
0.1UF
PP5V_S5
5%
1/16W
MF-LF
402
DEBUG_ADC
CD203
10UF
20%
10V
CERM
402
DEBUG_ADC
DEBUG_ADC
0.1UF
2
VOLTAGE=5V
21
10
PP5V_S5_DEBUG_ADC_DVDD_FILT
103
VOLTAGE=5V
PP5V_S5_DEBUG_ADC_AVDD_FILT
5%
1/16W
MF-LF
402
2
PP5V_S3 Current Sense
13
RD204
10
103
54 7 PP5V_S5
72 66
104
DEBUG_ADC
2.2UF
20%
6.3V
X5R
603
PCH VCore Current Sense
20%
6.3V
2 CERM
104 103 72 66 54 7
PP5V_S5
DEBUG_ADC
402-LF
CD270
0.1UF
DEBUG_ADC
EDP:5A
PP5V ODD Voltage Sense

0612
MF
1W
1%
SM
1
5V_SW_ODD_XW
RD222
73 70 68 45 39 35 23 14 13 12 10 9 7
105 102
1%
1/16W
MF-LF
402
226K
ADC2_CH7
1%
1/16W
MF-LF
402
100
2.2UF
2
6.81K
ISNS_PP5V_S0_P
DEBUG_ADC
CRITICAL
UD220
4
1%
1/16W
MF-LF
402
ISNS_PP5V_S0_N
87 73 70 69 68 65 54 52 47 41 22 8 7 6
105
8.45K
ISNS_3V3_S3_R_N
UD260
GAIN: 118X
104
CD261
2.2UF
10%
6.3V
X5R
402
280K
SIGNAL_MODEL=EMPTY
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
104
CD230
2.2UF
DEBUG_ADC
OUT
GAIN: 41X
OUT
DEBUG_ADC
RD264
1
226K
ADC2_CH4
DEBUG_ADC
ADC2_CH1
DEBUG_ADC
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
280K
226K
DEBUG_ADC
1%
1/16W
MF-LF
402
RD265 PLACE_NEAR=UD210.23:5mm
ISNS_PP5V_S0_IOUT
VTHRM
RD263
ISNS_3V3_S3_IOUT
V+
ISNS_PP5V_S0_R_N
RD235
DEBUG_ADC
DFN
20%
10V
CERM
402
OPA2333
ISNS_PP5V_S0_R_P
DEBUG_ADC
1
V-
1%
1/16W
MF-LF
402
6.81K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
SC70-5
V+
DEBUG_ADC
RD262
OUT PP5V_S0
CD260
0.1UF
OPA333DCKG4
ISNS_3V3_S3_R_P 1 +
RD232
1 3
100
1 3
CD231
8.45K
DEBUG_ADC
DEBUG_ADC
0.1UF
RD231
1
OUT PP3V3_S3
X5R
402
1%
1/16W
MF-LF
402
DEBUG_ADC
ISNS_PP3V3_S3_N
20%
6.3V
RD261
IN PP5V_S0_ISNS_R
0612
MF
1W
1%
PP3V3_S3 Current Sense
100
CD271
0.22UF
104 103 72 66 54 7
DEBUG_ADC
55
8848
5029
3124
8 7 6
3018
4925
7332
54
MF-LF
DEBUG_ADC
PP5V_S5
104 103 72 66 54 7
0.005
REF
PP5V_S5
10%
6.3V PLACE_NEAR=UD210.5:8mm
X5R
402
CRITICAL 0.005
RD230
104
PP5V_S0 Current Sense
CD222
100
OUT
2 4
IN+
402
RD260
0612
MF
1W
1%
ADC2_CH5
DEBUG_ADC
1
104
DIVIDER: ~ 2/5
ISNS_PP3V3_S3_P
ISNS_PP1V05_S0PCH_P
GND
EDP Current: 9.865A
100
2
DEBUG_ADC
72 7
CRITICAL
4.53K
1
GAIN: 200X
RD223
IN PP3V3_S3_ISNS_R
ISNS_PCHCORE_IOUT
RD224
1%
1/16W
MF-LF
2 402
72 7
1/16W
PP1V05_S0
IN
RD270
OUT
SC70
DEBUG_ADC
681K
EDP:3.413A
IN-
5V_SW_ODD_DIV
DEBUG_ADC
1
CRITICAL
ISNS_PP1V05_S0PCH_N
1%
RD271 1
1M
100
0.002
DEBUG_ADC
1
DEBUG_ADC
INA210
2 4
PP5V_SW_ODD
CERM
UD275
XWD220
41 6
20%
10V
402
V+
OUT PPVCCIO_S0_PCH
102 22 20 17 16
CRITICAL
10%
6.3V
X5R
402
DEBUG_ADC
1
EDP:5.006A
RD234
1M
CPU DDR Current Sense
DEBUG_ADC
RD233
1M
1
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
100 72 7
PP1V5_S3RS0
IN
1%
1/16W
MF-LF
402
DEBUG_ADC
RD281
CRITICAL
RD280 1
3 ISNS_CPU_DDR_P
0.005
SIGNAL_MODEL=EMPTY
1%
1W
100 MF
0612
12.4K
UD260
ISNS_CPU_DDR_R_P
1%
1/16W
MF-LF
402
ISNS_CPU_DDR_N
V+
2 4
OUT PP1V5_S3RS0_CPUDDR
PP3V3_S5 Current Sense

53 48 47 46 45 44 42 25 7 6
73 64 63
THRM
CRITICAL
PP3V3_S5
RD245
0612
CERM
ISNS_PP3V3_S5_N
IN-
SC70
DEBUG_ADC
ISNS_3V3_S5_IOUT
4.53K
1
IN
OUT
IN+
REF
MF-LF
402
GND
CD241
0.22UF
X5R
402
RD226
2
1%
1/16W
MF-LF
402
ADC2_CH6
104
CD281
10%
6.3V
2 X5R
DEBUG_ADC
RD284
1
1M
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
DEBUG SENSORS AND ADC 2

DRAWING NUMBER
Apple Inc.
CD223
2.2UF
1%
1/16W
MF-LF
402
10%
6.3V
X5R
402
SIZE
D
REVISION

PAGE TITLE
104
DEBUG_ADC
1
DIVIDER: ~ .606
RD227PLACE_NEAR=UD210.4:8mm
1
1M
20%
6.3V
Gain: 100x
DEBUG_ADC
3V3_WLAN_F_DIV
DEBUG_ADC
DEBUG_ADC
1%
ISNS_PP3V3_S5_P
OUT
2.2UF
226K
104
1/16W
100
1 3
66 7
ADC2_CH2
ADC2_CH0
DEBUG_ADC
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
2 402
RD246
6
1%
1/16W
MF-LF
402
PP3V3 WLAN Voltage Sense
RD225
1%
1/16W
MF-LF
402
649K
DEBUG_ADC
OUT
0.002
CRITICAL
PP3V3_S5_ISNS_R
3V3_WLAN_F_XW
INA214
100
UD245
2 4
MF
1W
1%
PP3V3_WLAN_F1
402
V+
OUT
20%
10V
100
71
24
7 6
20
46
83
31
DEBUG_ADC
1M
SM
0.1UF
226K
402
DEBUG_ADC
1
XWD200
CD240
ISNS_CPU_DDR_R_N
RD283
DEBUG_ADC
ISNS_CPU_DDR_IOUT
GAIN: 81X
DEBUG_ADC
1
102
73 72
29 25
19 17
23 22
56 48
91 86
1%
1/16W
MF-LF
402
PP3V42_G3H
EDP Current: 9.98A
12.4K
RD285
7
V-
RD282
73 29 15 13 10 7
DEBUG_ADC
OPA2333
DFN
BRANCH
PAGE
131 OF 132
SHEET
104 OF 105
CPURIPPLE_ENG
LD300
FERR-120-OHM-0.3A
PP5V_S0
87 73 70 69 68 65 54 52 47 41 22 8 7 6
104
PP5V_S0_RMC_FLT
VOLTAGE=5V
0402
CPURIPPLE_ENG
PLACE_NEAR=RD305.1:5MM
PLACE_NEAR=CD310.1:2MM
CD310
XWD300
SM
69 49 14 12 7 6
IN
PPVCORE_S0_CPU
VOLTAGE=1.1V
CD300
10UF
1UF
PPVCORE_S0_RMC
CPURIPPLE_ENG
CPU_VCORE_C
20%
2 6.3V
CERM-X5R
0402-1
CPURIPPLE_ENG
RD306
10%
16V
X5R
402
CPURIPPLE_ENG
10.2 2
0.1%
1/16W
TF
402
RD300
PP1V05_S0
73 70 68 45 39 35 23 14 13 12 10 9 7
104 102
100
5%
1/16W
MF-LF
402
PP1V05_S0_RMC_R
CPURIPPLE_ENG
VOLTAGE=1.05V
DD300
SOD-523
1
BAT54XV2T1
CPURIPPLE_ENG
CPURIPPLE_ENG
1
CD304 1 RD301
11K
10UF
20%
6.3V
CERM-X5R 2
0402-1
0.1%
1/16W
MF
402 2
CPURIPPLE_ENG
CPURIPPLE_ENG
1
RD303
CD301
0.1UF
1.0K
10%
16V
2 X5R
402-1
0.1%
1/16W
TF
2 402
1V05_S0_RMC_DIV
CPURIPPLE_ENG
NO_TEST=TRUE
V+
CPURIPPLE_ENG
UD300
CPURIPPLE_ENG
OPA2365
DD301
SOD-523
SO-8
1
RD305
10.2 2
1
CPURIPPLE_ENG
RD3021
CPURIPPLE_ENG
CD305
0.1UF
11K
0.1%
1/16W
MF
402 2
CPURIPPLE_ENG
1
RD304
0.1%
1/16W
TF
402
COMP_CPU_VCORE_RMC
UD300
CPU_VCORE_RMC_P
NO_TEST=TRUE
CPU_VCORE_RMC_DIV
V-
NO_TEST=TRUE
OPA2365
SO-8
V+
BAT54XV2T1
VSNS_CPU_VCORE_RMC_OUT
NO_TEST=TRUE
CPU_VCORE_RMC_N
V-
NO_TEST=TRUE
1.0K
CPURIPPLE_ENG
RD320
4.53K2
ADC_CH3
1%
1/16W
MF-LF
402
OUT
103
CPURIPPLE_ENG
1
CD320
0.22UF
0.1%
1/16W
TF
2 402
10%
10V
2 CERM
402
10%
16V 2
X5R
402-1
CPURIPPLE_ENG
PLACE_NEAR=RD305.1:5MM
CPURIPPLE_ENG
RD308
RD307
1
10
1K
2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PAGE TITLE
Power Supplies BIST

DRAWING NUMBER
Apple Inc.
SIZE
D
REVISION

BRANCH
PAGE
132 OF 132
SHEET
105 OF 105

Apple Macbook Pro A1297 (K92, 820-2914)

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Functional / ICT Test

CPU DDR3 INTERFACES

CPU POWER AND GND

CPU & PCH XDP

DDR3 SO-DIMM Connector A

DDR3 Byte/Bit Swaps

DDR3 SO-DIMM Connector B

CPU Memory S3 Support

FSB/DDR3/FRAMEBUF Vref Margining

T29 Power Support

ETHERNET PHY (CAESAR IV)

FireWire LLC/PHY (FW643)

FireWire Port & PHY Power

External USB Connectors

PROJECT SPECIFIC CONNS

Front Flex Support

LPC+SPI Debug Connector

K92 SMBus Connections

Voltage & Load Side Current Sensing

High Side and CPU/AXG Current Sensing

AUDIO: HEADPHONE OUT

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

PBus Supply & Battery Charger

System Agent Supply

5V / 3.3V Power Supply

1.5V DDR3 Supply

CPU IMVP7 & AXG VCore Regulator

CPU IMVP7 & AXG VCore Output

CPU VCCIO (1.05V) Power Supply

Misc Power Supplies

Power Control 1/ENABLE

Whistler CORE/FB POWER

Whistler FRAME BUFFER I/F

GDDR5 Frame Buffer A

GDDR5 Frame Buffer B

Whistler GPIOs & STRAPs

Power Sequencing EG/PCH S0

GPU (Whistler) CONSTRAINTS

Project Specific Constraints

PCB Rule Definitions

PCH Power Aliases

DEBUG SENSORS AND ADC

DEBUG SENSORS AND ADC 2

Power Supplies BIST

GPU (Whistler) CORE SUPPLY

LVDS Display Connector

Muxed Graphics Support

1V0 GPU / 1V5 FB Power Supply

Graphics MUX (GMUX)

LCD Backlight Driver (LP8545)

LCD Backlight Support

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SATA 3.0/ 6GHZ.

FAN CONN AND CONTROL

System Block Diagram

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K92 POWER SYSTEM ARCHITECTURE

SMC AVREF SUPPLY

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