Cory Snooks

EE 330 Lab 4
9/25/2013

Using PCells to Speed up the Design Process

ABSTRACT: Parameterized Cells from the NCSU_TechLib_ami06 library were used to implement a simple three
input NOR gate. Multiple NOR gates were then used to synthesize a Boolean function. A layout view was created
and checked against the schematic to ensure correctness of the layout. A test bench was used to verify the correct
output of the NOR gate and the Boolean function.

Using Parameterized Cells (PCells)

PCells were used to make the layout view a much less difficult process to create. PCells could be
adjusted using the fingers and multiplier sections. The number of fingers expanded the number
of poly1 regions that were on the transistor and the multiplier section increased the number of
separate gate regions on the transistor. The multiplier was used to place multiple transistors in
parallel, and the fingers were used to place transistors in series.

Figure 1: The effects of fingers are seen in the pmos transistor on the left and the effects of the multiplier are seen in the nmos transistor on the
right.

Using PCells, a three input NOR gate and an inverter were created. A test bench was set up to
deliver a Vpulse for each of the three inputs with a varying pulse width that doubled for each
Vpulse. That effectively created a Boolean counter from zero to fifteen. The outputs from each
schematic were checked against a truth table for the corresponding circuit.
A new symbol for the NOR gate was created and used to implement the Boolean function
F = (A + B + C)(A + B + C)(A + B + C) . A layout view of that function was then created and
checked back against the schematic. The layout view had to be within the constraints of a total
working area of 150m2, the inputs must have been available at the left boundary of the box, the
output must have been available at the right side of the box, only two metals were to of be used,
and the Vss and Vdd bars could have only been 6 wide. Everything matched and a testbench
was used to verify the output of the circuit against a truth table for the Boolean function.

Cory Snooks
EE 330 Lab 4
9/25/2013

Figure 2: The schematic view of the Boolean function is shown above.

Figure 3: Testing of the schematic is accomplished by using Vpulse signals with varying periods for the input variables.

Cory Snooks
EE 330 Lab 4
9/25/2013

Figure 4: The Layout view of the Boolean function is shown above.

A B C F F'
0 0 0 1 1
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
Figure 5: The truth table for the Boolean function F and the equivalent NOR function F is shown above.

Conclusion:
The use of PCells made the layout view much easier to create because they cut down on design
time and mistakes. I did not entirely understand why stick diagrams were necessary before this
lab. It would be very difficult to create a layout design without having a stick diagram as a guide.
I can see how chips with any level of difficulty would take a long time to create in the layout
view just because of the positioning of the poly and metals to move the signals around. This was
a very simple schematic and it still took some thought as to how to get a connection from point A
to point B without causing any problems. I found it much easier to go back and make changes to
the schematic view than it was to make changes to the layout view when there were
discrepancies.