1022 10.23 10.24 10.25 Chop. 10 Locic GATES ‘Sketch the circuit of am JL inverter. Explain the operation of the ‘ireuit and compare it to a resistor-transistor inverter. Sketch 121 NAND and NOR gates and explain how they operate, Using illustrations, explain the construction of an JZ circuit, and discuss its advantages compared to other logic types. Compare the various types of IC logle in terms of propagation delay time, power dissipation, noise immunity, and fancout. CHAPTER ll Sampling Gates Sa INTRODUCTION ‘A sampling gate is switching cult which usually is employed to sample the omplitude of de or low-frequency signals. Sampling gate teuity com be constructed vsing diodes, bipolar transistors, or FETs. For large: signel yoltoges, odes or bipolar transistors may be salsfacory. For very srl sonals, JFETs or MOSFETs produce the best results, oe 11-1 DIODE SAMPLING GATE ‘A very simple die ante which may be applied to voltage level sampling is shown in Figure 1-1. The signal ¥, to be sampled is applied ta ie, cathode of P. The output voltage Fi derived from the eathode of Dy A Pals conro! input Fi applied vin'R, tothe anodes of D, and Dy ie Sigal source resistance is ty, and the load is R,. When the eontea Yoltage is zero or negative, diodes Dy snd D, ae reverse bined ad ¥, When the contral voltage becomes positive, Dy and D, are lorvant. biased. Then, WnVALR,am SAMPLING GATES. a 0) Vote atone sep) Sec. 11-2 BIPOLAR TRANSISTOR SERIES GATE a It is seen that the signal voltage is passed to the output terminals when {he control voltage pulses positively. The waveforms of input voltage control voltage, and output voltage are illustrated in Figure Il-\by, Tae ireut shown can éample only postive input signals. Reversing the aiodes ‘and the contol input would permit sampling of « negative signal voltage The diode sampling gate has erors due to diferences in the vollige drops across each diode, and due to diode leakage currents. Consequentiy, diode gates are applicable only where large signal amplitudes are involved ‘and where accuracy is not important. 11-2 BIPOLAR TRANSISTOR SERIES GATE ‘The circuit of « bipolar transistor series sampling gate-is shown in Figure 11-2. The low-frequency signal to be sampled is applied to the collector, ‘and the output is derived from the emitter terminal. A pulse waveform o: the base acts as a control, driving the transistor into saturation and cutofl ‘When the control voltage is positive, @, is biased on. When the control yoltage goes to zer0, Q, is of. AL transistor saturation, the output voltage is V=¥,. At cutoff, the output becomes zero. It is seen that the transister 's operating as a switch, and that the output from the gate is a series of ‘samples of the input amplitude. ‘The waveforms in Figure 11-2 wre drawn for a positive input signal if the input becomes negative, as shown in Figure 11-3), then the transistor operates in the inverted mode. The emitter terminal acts as the collector, ‘and the collector operates as the transistor emitter. This, by no means, fe «an efficent way to operate a transistor used for amplification. However’ ss & saturated switch with large base current, the transistor perfovins satisfactorily in inverted mode. To ensure that the device will switch off ‘the negative swing of the control voltage must be greater than the negative 1 ly Input (%)34 Chap. 11 SAMPLING GATES Ccltctor Emitter Saharan ts behaves as sent Scalector Contre input 14) Output (70) (©) Vottge waveforms [FOURE 11-3. Sais got wth negative sgl vlloge ond ons ianvered mode, peak of the signal voltage. For a signal with postive and negative compo- nents, the circuit waveforms are as illustrated in Figure 11-3(b). ‘The inpot signal applied to a sampling gate is frequently a very low level voltage. Since the transistor saturation voltage constitutes a loss of Signal amplitude [see Figure 11-4()), Veg (also termed the effet col, ge) must be maintained as small as possible, Reference to the transistor See.11-2 BIPOLAR TRANSISTOR SERIES GATE ms © a, on © Qo OURE 11-4. Gor sources in biplor Ronaor srs ote luirteritis in Figure 4-2 shows that forthe smallest gay c must be Eeptsmall and fy must be relatively lege For Jel ma ost, Sol me, Ragbicel Vem is 02 V. Another source of error fe the chitosan, teakage current Zyo that flows when the device is biased aff Ign eames ap Teac wtPUt voltage to develop across load resistance Rfeee Figs M-4Q)} A typical level of fgg tor a switching transistor is 50 SA at Donen in the design ofa series sampling gate, the load resistance Ry should 2c. suteted much larger than the signal source resistance 2, this wi Seid large signal curents which would eause a significant voltage drop Acrom Re: The signal current can be reduced to a minimum if I, is mando Stual (othe output current fy. The amplitude ofthe control voltage shontd be eater than the peak signal volinge. The sampling frequency (ie. the Sontrol voltage frequency) should be several times the Irequency of the signal to be sampled, EXAMPLE 11-1 ee Design a transistor series gate to sample a si 2, and a source resistance of 100 2. Also cal 1 Fesuay 414 Tyo.6 Chop. 11 SAMPLING GATES solution RD>R, Let y= 100%, =100%1009= 1040 When the ramsor is on, % yay ten Rem Ryd La Ip len 2000 The contra voltage 71> V,. Let Vin2xVin202 Vea and 13v = j3¥ $8k0 standard value) HET OSED (use ard val) Typically, Vomay"02 V, and Igo=50 nA. Ke Error due to Ve ggqy= 280% x 100% = SEF x100%= 10%, Re) 50.0Ax10K9 x 100% 100% Se0.11-9 BIPOLAR TRANSISTOR SHUNT GATE 11-3, BIPOLAR TRANSISTOR SHUNT GATE Fees stmling gate is suitable for signals having « low source Tetulance. For signals with a vey high source reatance’ the oe gate cae mea tt be much lager than, i iffielt fo hale wg on ‘ets, a shunt sampling gate is most suitable, Jo the shunt sampling gate (Figure 11-5), transistor Q, shorts the input ‘o Ground when tis switched into saturation, When Q, is nf, conwen et ‘Sigal current) Contot vote (F,) Output cuent fo) (©) Curent and voltage waveforms [MOURE 11-5. polar nonstor sunt got ond woetorms.om Chop. 11 SAMPLING GATES fe tame 88 fo = leed 2, on Az [lo “Us ~ too) 00) off |ROURE 11-6. Eror sores in biol shun gota. from the signal source to the load resistance. Therefore the shunt sampling fate essentially is current switch, whereas the series sampling gate is & oltage switch. The transistor offset voltage resulls in a load current Ferwo/R1, when the transistor ison (Figure 1-6(2)], When the device i off some ofthe signal current is lost a8 feo through the transistor [Figure 1-6(b) Ifthe input signal becomes negative, the transistor operates in the inverted mode, as in the case of the series gate. ‘The lod resistaice fora shunt sampling eate should be selected such that Zo Ry is much larger than Very. For transistor saturation and for ‘minimum Yeryag, fy can be approxiiately equal to Zo. As in the cate of the series gate, the sampling frequency should be at lesat several times the signal frequency. The transistor leakage current Jeg should be very much smaller than Zo A ee Design a transistor shunt gate to sample a signal current having & peak amplitude of 2 mA. Also, calculate the output errors due 0 Vernay and Teo: See.11-3 BIPOLAR TRANSISTOR SHUNT GATE a solution . Ie=n2mA Let ToRL=10% Vertu) 10x Fenny om To toxo2¥ “Tima 7 TKO Let Ialg=2mA Take 4V-07V : 33V Re mA 2ma 165KM (use 1.8 kA standard value) % Error cure de to Vergy “EH? Fexwwaty/ Ry ror de to Venqug™ “#880 Re 5 199% = SEXED 09% 10% 2mA Typical Joo 50.nA, Error dv to feo= “£2 100% S0nA = Tak * 100% =0.0025% eee390 Chop. 11 SAMPUNG GATES 11-4 JFET SERIES GATE A series sampling gate using an n-channel JFET is shown in Figure 11-7, ‘Note that the control voltage V goes from + V, to a negative level greater than the transistor pinchoff voltage V>. When V,=+¥,, the FET is on, When —¥,> Vp, the device is off. Note that because the drain terminal of the FET goes up to + ¥,, the gate must also go up to that level for Q, t0 be correctly biased on. A’ gate resistance R, (typically 1 MQ) is usually included to limit any gate current that might flow. The JFET can also be ‘operated in inverted mode, in which case the drain terminal acts as a soures, and the source terminal performs the function of the drain, Inverted operation of a JFET is satisfactory only if the signal level is very small. If the signal becomes large, the (inverted) gate-channel junction fo, 2 oo Inve ou) Control (¥) Pr = ag (JPET seer ete fo * Row fg hs Rog ] ey fy oss) (010 off [IOURE 11-7. Creu, wavetoms, ond wor sures for FET wis got Se. (rer Semies GATE a could become forward-biased, andthe resultant gate current would affect the drain source voltage, Field effect transistors have a dain source voltage df0p of Ip Ren ‘when biased into sattration (see Figure 11-7(6) and See. 43), Win ol ‘rain current, this drain-souree voltage drop can be much small than the Vera of & bipolar transistor. A typical valve of Re, for «switching FET is 309, although devices with Ray at low as 5 tre avaiable Fee 4 oad curent of 200 A, as ia Exasple IL-l, the typical PRY igen voltage is (200 xAX30 )=6 mV. This is only 03% of a 2 V sige compared to the 10% loss due to the Vena, of the bipolar tanseent When the JPET is bite off thee isn gic'surce leakage eurent hor which corresponds to Igo in a bipolar transistor [Figure IU NO, Then ogg constitutes an unwanted load current. Fora switching SFE Fg a be 0.2 mA or les, which is superior tothe typical 30 nA of bipolar leven The performance specification for some switching IFETs ie Gren seven Maxim Pincheff — Dramsource Gatesource Draimeorce woltage —onresinance teokage tage Vraay "Roney Joss Joc Ne ov a0 O1nA Ona 2nsas 9 78 02mA = O2na Note that the data sheet for the 21N4391 is in Appendix 1-10. EXAMPLE 11-3 A low-frequency signal with a peak amplitude of 1 V is applied to a voltage follower with a very low output resistance, The signal is to be Voltage FIOUE 11-8. FET sre gta,a0 Chap. 11 SAMPUNG GATES sampled at the output of the voltage follower and fed to a circuit with 2i~10 k@. Design a suitable FET gate cireuit and estimate the output solution The ciruit is as shown in Figure 11-8. For the 2N4391 FET, the control voltage Fi> Cray 10 V). Let YR With Q, on, ye RAR, ~— lV ~“Oa+ 10K Voston = FoR ten) =0. mAx309=3 mV Fsstom, v, amy 3a 100% 13% =0.1mA Exror due to Vp, x 100% With Q, off IeeToss70.1 0A VorlossRy =0.1nAx10KO=1 pV R, Aoss®r 5 109%, = 18 tooo OO 1-5 JFET SHUNT GATE Error due to Toss The JFET shunt sampling gate shown in Figure 11-9(a) operates in a similar way to the bipolar shunt circuit. Like the bipolar shunt gate, the aa Output a) (2) JPET shunt ante a [20 oto Vey ToRoqa Re ©) 2 on (2 of FIOURE 11-9. Cre, waveform, and ror sures for JFE sont gta. JFET shunt gate is essentially a current switch. When the FET is on, the output of the gate is shorted to ground. The output voltage at this time actually is Tp Royexy and this produces an unwanted output current (Cp Roveny/R,,) [580 Figure 11-9(b)). However, for the shunt FET gate the unwanted output is much less than the minimum possible with a bipolar iteuit. When the transistor i of, the drain-source leakage curent ooyy, diverts signal current from the load {see Figure 11-9(¢)}. Again, this uncally is less than the corresponding bipolar leakage current, EXAMPLE 11-4 $e A low-frequency current with an amplitude of 0.1 mA isto be sampled and fed to the input of a circuit with R,= 10 kO, Design a suitable FET shunt sate, and estimate the output voltage errors due to the transistormm Chop. 11 SAMPUNG GATES solution Use a 2N4391 FET, Let the control voltage be ~12 V as in Example 11-3, When 0, is on, Vo=IRocesy 0.1 mAx302=3 mv and when Q, is off, YorLR, =O mAx10kO=1¥ The error when Q, is oni given by when 0, is off 11-6 MOSFET SAMPLING GATES MOSFETs are almost ideal devices for use as sampling gates. They have the same low Rpg characteristic as JFETs, and the enhancement mode devices are normally off while the gate is at the same potential ay the Substrate. Figure 11-10(a) shows the circuit of a series sampling gate using ‘anchannel MOSFET. With the substrate at ground potential, the control voltage should go from 0 V to a positive voltage to switch the gate from off fo on. When the input signal can be either negative of positive, the substrate should be taken to a negative bias voltage and the control voltage should start at the bias level. A MOSFET shunt sampling gate is shown in Figure 11-10(b). Here, again, the substrate terminal of the FET can be taken to a negative bias voltage, and the control voltage should start at the bias level to accommodate negative signal voltages. Substrate connected nd (6) Seis — shunt ate MOURE I-10. MOSFET srnptng got16 Chop. 11 SAMPLING GATES ‘The circuit in Figure 11-10(c) is a series gate employing two MOSFETs, ‘This circuit is particularly suitable where the load has a very high input resistance. When Q, is on, the signal voltage is switched to the load, and Qs is off. When Q, is ff, the load voltage should be zero. With yon at this time, the output voltage is Corry for 21) x (Roy » for 25) ‘When typical values of 0.1 nA and 30 @ are used, the unwanted output voltage is only 3 nV. ‘One problem in using MOSFETS as sampling gates is that the control voltage (applied to the gate) must always be greater than the maximum signal level Infact, the control voltage must usually exceed the maxima signal amplitude by at least 2 Y. Since there is very litle voltage drop along the channel of the FET, both drain and source terminals are closely equal to the signal voltage level (as desired). Therefore, the channel of the device is always af the same potential as the signal, I the signal ap- roaches the level of the control voltage, there may not be sufficient ‘gate-channel bias to properly turn the device on. Thus, part of the signal may not be reproduced accurately at the output. The CMOS transmission gate overcomes this difficulty. ‘As shown in Figure 11-11, a CMOS transmission gate consists of two complementary MOSFETs connected in inverse parallel. The drain of 0, fs connected to the source terminal of Q;, and the source of Q, connected to the drain of Oy. Both substrate terminals are grounded, and cach gate has its own control voltage. Note that the control voltage waveforms in Figure 1-11 show that the ‘channel device Q, has a control voltage which goes from ground to a positive voltage level. Q,, the p-channel FET, has a control voltage that foes from ground to a negative level. Note also that the two control Waveforms are in antiphase. When Q, gate is going positive, the gate of is driven negative. This means that both devices are tumed on and off simultaneously. Both present a low resistance path from inpul to output when on, and both offer a high resistance between input and output when off. Now consider the signal and output waveforms illustrated in Figure 1-11. The input amplitude is shown as +8 V, and the control voltage on Qi kate is +8 V, while that © Qyis —8 V. During the time that the signal is positive, current can flow from input to output along both FET channels when the devices are biased on. If the positive amplitude of the signal approaches the control voltage amplitude (as illustrated), Q, tends to switch off, Because there is not sufficient gate-channel voltage difference te keep it biased on. However, Q, is not affected, because its gnte-channel ‘Sec. 11-7 OPERATIONAL AMPLIFIER SAMPLING GATE 27 CMOS transom gle and waveform, voltage dlilernce (16 V in Figure 11-1) ssl easily adequate to keep it biased on. Thus the signal carent continues to few a phaser CMOS transmission gates can be purchased as integrated circuits Usually four or more gates are contained in one IC package, 11-7 OPERATIONAL AMPLIFIER SAMPLING GATE ‘An operational amplifier connected as an inverting amplifier can be made into a sarmpling gate by installing x FET across its feedback resistor the390 Crp] Oatput ¥, FIOURE 11-12. Operation! omplifer someting poe ‘iteuit is shown in Figore 11-12. When Q, is off the output voltage is Meee 2s is on its channel resistance Ryygy isin parallel with Rp, s0 that the output becomes Since RallRocoxy€Ry (normally), v,~0 Sec. 11-7 OPERATIONAL AMPLIFIER SAMPLING GATE a As with other sampling gates, the output waveform is a series of stantaneous samples of the input. However, in this case the oulpet samples are an inverted version of the input. Also, the input corre amplified in the sampling process, depending upon the selenden of tre ratio Ra/Ry, When Q, is an n-channel JFET, as illustrated, te contey roltage should go down to a negative level equal to the FET mani Pineh-off voltage to ensure switch of, and up to ground level for samen an. [When a MOSFET is employed, the required control voltage lorie act as discussed in Sections 11-4 and 1 esause of the use of an operational amplifier, ths gate has a very low Pit impedance. Its input impedance is equal to Ry. Design procedon Jf soltage gain of 10. The maximum signal voltage is ¥;=500 enV, Select suitable resistor values and control voltage amplitude. Ako ertinn the output error due to the Riga of the FET. solution for the 7A1, Igy 500 0A tet = 100% Fagmasy = 100%500 nA =S0 KA, ¥, $00 mv Rm yA 7 HORM (standard value) Ram A, Ry 10X10 9 10049 (standard value) Noe that for a présive gain of 10, Ry and Ry would hace to be precion restos RRR, 10K for the 2N4391, Vigoas 10 V (cee AppendixMo Chop. 11 SAMPUNG GarEs voltage is, ¥,> 10 V Roxon) =302 Rocoal Ra Zero ouput= vx Soten Rs _ x 30.2100 ke 500 mv 0 RNOO KD A 5 gy Ry om he =10%500 mv av 2a enor= 15 top 03% ee 11-8 SAMPLE-AND-HOLD CIRCUIT A sample-andthold ciruit, as its name implies, samples the instantaneous ‘amplitude of a signal, and then holds the output voltage constant unl the next sampling instant The circuit, ove Fig, 11-13(2), is simply a series gate with a capacitor C; to perform the holding function. Operational ampli fiers 4, and A, are connected as voltage followers (see Section 7-7) to provide high input impedance and low output impedance. ‘The waveforms in Figure 11-13(a) illustrate the relationship between input and output. At time , the instantancous amplitude ofthe input ie, ‘The output holds at the v, level until time #5, when it jumps to the inpat amplitude 0,, Similarly, when the input is falling, the output amplitede Temains constant at ¢, from ty tof, Daring the sampling time 1, 0; ison and C; is charged via Rpg, 08 illustrated in Figure 11-13(b). Ifthe sampling time i= 4=5CR where Ris Roreny, the capacitor is charged to 0.993 of the input voltage. (This comes from Equation 2-2). Allowing the capacitor to charge to 0.993 of V, results in a 0.7% error inthe sampled amplitude, If -=7 CR, V,=0.999 V,, ie. a 0.1% During the holding time f,, C, is partially discharged by the-bias ‘current Iya flowing into A;. The FET souree-gate leakage current Jeg also Pox gre ‘ime (b) Charging crus aps al = Holding ‘ine ctor voltage (6) Ettestof Cox FROUREN-13, Sompleandteld doit,ae Chop. 11 SAMPLING GATES ‘causes some discharge of C,. However, I 22220 it can usually be neglected. The capacitance of C, is ealeulated fom the knowledge of Ips, the holding time fs, and the acceptable ene fine to Ci discharge. Alter the value of G; is established, the sampling tave ‘is calculated from C, and the acceptable charging error. One more source of error in the output voltage is the FET gate-source ‘pacitance Cs. When the control voltage om the gate goes to its lowest level Ges is changed to e,—(V,+¥,) This illustrated in Figure 11-1300), The charge on Gos is removed from Cy, and thus reduces Vo. Example 11-6 demonstrated how a sample-and-hold cireuit is designed, and how the ‘various error sources affect the accuracy of the sample. ‘normally very much less than EXAMPLE 11-6 ee A sample-and-hold circuit is to use 741 operational amplifiers and a 2N4301 FET. The signal voltage amplitude, ¥;= +1 ¥, iso be sampled pith an accuracy of approximately 0.25%. The holding time is S00 got Determine the capacitor value and the minimum sampling time. Ales calculate the eect of Cog 105 pF. solution for the 741, Fycany = 500 MA. Allow Fnjaun 10 discharge C, by 0.1% dering A¥=0.1% of LV. =Imv Text c= BX for the 2N4391, Riygq)=30 Allow another 0.1% error in V; due to the sampling time f, For 0.1% error, C Rony 177x025 wFx309 5 ws REVIEW QUESTIONS AND PROBLEMS oe For the 2N4391, Frquuy=10 ¥ —ocmnt Fara] —[ov+1¥] -uv Vesmany™ +¥e- Vs s1v-(-11v) =Rv O-CosX Vases) = 105 pFx12V =150 pc when @ is removed from Cy, charge on Cas i REVIEW QUESTIONS AND PROBLEMS etch the cet of 4 dade sampling gate. Show the volage Suvfocs expna th operation of he Cacuy and dant te 142 Repeat Problem Ifo bipolar tanior eis sampling pte ain how tipoar esr ets exmping gle fans No Gen the lput pul is alemately postive and nepalve il ‘pect o mound 114 Design bipolar tassios ote to sample signal vith