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14. (a) (i) EXPLAIN INDETAIL ABOUT PARTITION AND MUX TESTING WITH
NECESSARY EXAMPLE AND DIAGRAM. (8)
(ii) EXPLAIN THE PRINCIPLE OF SILICON DEBUG. (8)
[OR]
(b) (i) ELABORATE THE SCAN BASED TECHNIQUES. (8)
(ii) DISCUSS IN DETAIL ABOUT:
(I) PSEUDO RANDOM PATTERN GENERATOR. (4)
(II) OUTPUT RESPONSE ANALYSER.
(4)
15. (a) USING MIXED LEVEL MODE WRITE A VHDL PROGRAM FOR A
(i) COMPARATOR.
(8)
(ii) D FLIP FLOP.
(8)
[OR]
(b) WITH ALL THE THREE TYPES OF MODELING WRITE A VHDL
PROGRAM FOR A
(i) DECODER (8)
(ii) FULL ADDER. (8)
PART A:
1.
Vgs
Vgs=constant
Ids (ms)
2.
Ans : Cut-off region , linear region , saturation region .
3.
Ans :
n+
P+
P+
+ + + +
4.
Ans : Capacitance due to fringing field effects is the major component of the
overall capacitance of inter connect wires. For the final line metallization, the value of
fringing field capacitance will be the same order as that of the area capacitance.
5.
Ans : For CMOS, the area required is 533 m2 , for pseudo Nmos the area required is
288 m2.
6.
Ans : Ratioed circuits dissipate power continually in certain states and have poor
noise margin than complementary circuits.
Ratioed circuits used in situations where smaller area is needed.
7.
Ans : Temperature , large of interconneccts.
8.
Ans : Faults are modeled at transistor level. At this level only , the complete circuit
structure is known.
9.
Ans : These are having one input and more outputs
Buf
Not
Syntax :
gate type [instance na,e] (out1 , out2 , .outN , input)
eg:
buf buffer(out1 , out2 , clk)
10.
Ans : It models the delays in hardware that do not exhibit any inertial delay. It
represents pure propagation delay.