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USE ieee.std_logic_1164.all;
ENTITY soal8_30 IS
PORT( Clock
Reset
N, D
z
: IN STD_LOGIC;
: IN STD_LOGIC;
: IN STD_LOGIC;
: OUT STD_LOGIC);
END soal8_30 ;
ARCHITECTURE behavioral OF soal8_30 IS
TYPE Statetype IS (S1,S2,S3,S4,S5);
SIGNAL y : Statetype;
BEGIN
PROCESS (Reset, Clock)
BEGIN
IF Reset = '1' THEN
y<=S1;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF N = '1' THEN y<=S3;
ELSIF D = '1' THEN y<=S2;
ELSE y<=S1;
END IF;
z<='0';
WHEN S2 =>
IF N = '1' THEN y<=S4;
ELSIF D = '1' THEN y<=S5;
ELSE y<=S2;
END IF;
z<='0';
WHEN S3 =>
IF N = '1' THEN y<=S2;
ELSIF D = '1' THEN y<=S4;
ELSE y<=S3;
END IF;
z<='0';
WHEN S4 =>
y<=S1;
z<='1';
WHEN S5 =>
y<=S3;
z<='1';
END CASE;
END IF;
END PROCESS;
END behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY soal8_31 IS
PORT (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
N, D : IN STD_LOGIC;
z
: OUT STD_LOGIC);
END soal8_31;
ARCHITECTURE behavioral OF soal8_31 IS
TYPE Statetype IS (S1,S2,S3,S4,S5);
SIGNAL y_present, y_next: Statetype;
BEGIN
PROCESS (N,D,y_present)
BEGIN
CASE y_present IS
WHEN S1 =>
IF N = '1' THEN y_next<=S3;
ELSIF D = '1' THEN y_next<=S2;
ELSE y_next<=S1;
END IF;
WHEN S2 =>
IF N = '1' THEN y_next<=S4;
ELSIF D = '1' THEN y_next<=S5;
ELSE y_next<=S2;
END IF;
WHEN S3 =>
IF N = '1' THEN y_next<=S2;
ELSIF D = '1' THEN y_next<=S4;
ELSE y_next<=S3;
END IF;
WHEN S4 =>
y_next<=S1;
WHEN S5 =>
y_next<=S3;
END CASE;
END PROCESS;
PROCESS ( Clock, Reset )
BEGIN
IF Reset = '1' THEN
y_present<=S1;
ELSIF Clock'EVENT AND Clock = '1' THEN
y_present<=y_next;
END IF;
END PROCESS;
z<='1' WHEN y_present = S4 OR y_present = S5 ELSE '0';
END behavioral;
count :=0;
END IF;
END CASE;
END IF;
END PROCESS;
END behavioral;