Carnegie Mellon

Virtual Memory: Concepts

15-213: Introduc0on to Computer Systems
15th Lecture, Oct. 14, 2010

Instructors:
Randy Bryant and Dave OHallaron

Carnegie Mellon

Today

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protec;on
Address transla;on

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A System Using Physical Addressing

CPU

...

Main memory
0:
1:
Physical address 2:
3:
(PA)
4:
4
5:
6:
7:
8:
M-1:
Data word

Used in simple systems like embedded microcontrollers in

devices like cars, elevators, and digital picture frames
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A System Using Virtual Addressing

CPU Chip
CPU

Virtual address
(VA)

4100

MMU

Physical address
(PA)

...

Main memory
0:
1:
2:
3:
4:
5:
6:
7:
8:

M-1:
Data word

Used in all modern servers, desktops, and laptops

One of the great ideas in computer science
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Address Spaces

Linear address space: Ordered set of con0guous non-nega0ve integer

addresses:

{0, 1, 2, 3 }
Virtual address space: Set of N = 2n virtual addresses

{0, 1, 2, 3, , N-1}
Physical address space: Set of M = 2m physical addresses

{0, 1, 2, 3, , M-1}
Clean dis;nc;on between data (bytes) and their aVributes (addresses)
Each object can now have mul;ple addresses
Every byte in main memory:
one physical address, one (or more) virtual addresses
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Why Virtual Memory (VM)?

Uses main memory eciently

Use DRAM as a cache for the parts of a virtual address space

Simplies memory management

Each process gets the same uniform linear address space

Isolates address spaces

One process cant interfere with anothers memory
User program cannot access privileged kernel informa0on

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Today

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protec;on
Address transla;on

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VM as a Tool for Caching

Virtual memory is an array of N con;guous bytes stored

on disk.
The contents of the array on disk are cached in physical
memory (DRAM cache)
These cache blocks are called pages (size is P = 2p bytes)
Virtual memory
VP 0 Unallocated
VP 1 Cached

Physical memory

0
0

Uncached
Unallocated
Cached
Uncached
Cached
n-p
VP 2 -1 Uncached

Empty

PP 0
PP 1

Empty
Empty
M-1

PP 2m-p-1

N-1

Virtual pages (VPs)

stored on disk

Physical pages (PPs)

cached in DRAM
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DRAM Cache Organiza;on

DRAM cache organiza;on driven by the enormous miss penalty

DRAM is about 10x slower than SRAM
Disk is about 10,000x slower than DRAM

Consequences
Large page (block) size: typically 4-8 KB, some0mes 4 MB
Fully associa0ve
Any VP can be placed in any PP
Requires a large mapping func0on dierent from CPU caches
Highly sophis0cated, expensive replacement algorithms
Too complicated and open-ended to be implemented in hardware
Write-back rather than write-through

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Page Tables

A page table is an array of page table entries (PTEs) that

maps virtual pages to physical pages.
Per-process kernel data structure in DRAM
Physical page
number or
Valid disk address
PTE 0 0
null
1
1
0
1
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 4

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7

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Page Hit

Page hit: reference to VM word that is in physical memory

(DRAM cache hit)

Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
0
1
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 4

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Page Fault

Page fault: reference to VM word that is not in physical

memory (DRAM cache miss)
Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
0
1
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 4

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Handling Page Fault

Page miss causes page fault (an excep0on)

Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
0
1
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 4

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Handling Page Fault

Page miss causes page fault (an excep0on)

Page fault handler selects a vic0m to be evicted (here VP 4)

Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
0
1
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 4

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Handling Page Fault

Page miss causes page fault (an excep0on)

Page fault handler selects a vic0m to be evicted (here VP 4)

Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
1
0
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 3

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Handling Page Fault

Page miss causes page fault (an excep0on)

Page fault handler selects a vic0m to be evicted (here VP 4)
Oending instruc0on is restarted: page hit!
Virtual address

Physical page
number or
Valid disk address
PTE 0 0
null
1
1
1
0
0
0
PTE 7 1

null

Physical memory
(DRAM)
VP 1
VP 2
VP 7
VP 3

PP 0
PP 3

Virtual memory
(disk)
VP 1

Memory resident
page table
(DRAM)

VP 2
VP 3
VP 4
VP 6
VP 7
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Locality to the Rescue Again!

Virtual memory works because of locality

At any point in ;me, programs tend to access a set of ac;ve
virtual pages called the working set
Programs with beger temporal locality will have smaller working sets

If (working set size < main memory size)

Good performance for one process aier compulsory misses

If ( SUM(working set sizes) > main memory size )

Thrashing: Performance meltdown where pages are swapped (copied)

in and out con0nuously

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Today

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protec;on
Address transla;on

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VM as a Tool for Memory Management

Key idea: each process has its own virtual address space
It can view memory as a simple linear array
Mapping func0on scagers addresses through physical memory

Well chosen mappings simplify memory alloca0on and management

Virtual
Address
Space for
Process 1:

VP 1
VP 2

Address
translaHon

PP 2

...

Physical
Address
Space
(DRAM)

N-1

PP 6

Virtual
Address
Space for
Process 2:

PP 8

VP 1
VP 2

...

...

N-1

(e.g., read-only
library code)

M-1

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VM as a Tool for Memory Management

Memory alloca;on
Each virtual page can be mapped to any physical page
A virtual page can be stored in dierent physical pages at dierent 0mes

Sharing code and data among processes

Map virtual pages to the same physical page (here: PP 6)
Virtual
Address
Space for
Process 1:

VP 1
VP 2

Address
translaHon

PP 2

...

Physical
Address
Space
(DRAM)

N-1

PP 6

Virtual
Address
Space for
Process 2:

PP 8

VP 1
VP 2

...

...

N-1

(e.g., read-only
library code)

M-1

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Simplifying Linking and Loading

Kernel virtual memory

Linking

0xc0000000

Each program has similar virtual

User stack
(created at run;me)

address space

Code, stack, and shared libraries

always start at the same address

Memory
invisible to
user code
%esp
(stack
pointer)

Memory-mapped region for

shared libraries

0x40000000

Loading
execve() allocates virtual pages
for .text and .data sec0ons
= creates PTEs marked as invalid

Run-;me heap
(created by malloc)

The .text and .data sec0ons

Read/write segment
(.data, .bss)

are copied, page by page, on

demand by the virtual memory
system

Read-only segment
(.init, .text, .rodata)
0x08048000

brk

Loaded
from
the
executable
le

Unused
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Today

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protec;on
Address transla;on

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VM as a Tool for Memory Protec;on

Extend PTEs with permission bits

Page fault handler checks these before remapping
If violated, send process SIGSEGV (segmenta0on fault)

Process i:

Process j:

SUP

READ WRITE

Address

VP 0:

No

Yes

No

PP 6

VP 1:
VP 2:

No

Yes

Yes

PP 4

Yes

Yes

Yes

PP 2

SUP

READ WRITE

Physical
Address Space
PP 2
PP 4
PP 6

Address

VP 0:

No

Yes

No

PP 9

VP 1:

Yes

Yes

Yes

PP 6

VP 2:

No

Yes

Yes

PP 11

PP 8
PP 9
PP 11
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Today

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protec;on
Address transla;on

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VM Address Transla;on

Virtual Address Space

V = {0, 1, , N1}

Physical Address Space

P = {0, 1, , M1}

Address Transla;on
MAP: V P U {}
For virtual address a:

MAP(a) = a if data at virtual address a is at physical address a in P

MAP(a) = if data at virtual address a is not in physical memory
Either invalid or stored on disk

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Summary of Address Transla;on Symbols

Basic Parameters
N = 2n : Number of addresses in virtual address space
M = 2m : Number of addresses in physical address space
P = 2p : Page size (bytes)

Components of the virtual address (VA)

TLBI: TLB index

TLBT: TLB tag
VPO: Virtual page oset
VPN: Virtual page number

Components of the physical address (PA)

PPO: Physical page oset (same as VPO)

PPN: Physical page number
CO: Byte oset within cache line
CI: Cache index
CT: Cache tag
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Address Transla;on With a Page Table

Virtual address
n-1

Page table
base register
(PTBR)
Page table address
for process

p p-1

Virtual page number (VPN)

Virtual page oset (VPO)

Page table
Valid

Physical page number (PPN)

Valid bit = 0:
page not in memory
(page fault)
m-1

Physical page number (PPN)

p p-1

Physical page oset (PPO)

Physical address
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Address Transla;on: Page Hit

2
PTEA

CPU Chip
CPU

1
VA

PTE

MMU

3
PA

Cache/
Memory

4
Data
5

1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory
4) MMU sends physical address to cache/memory
5) Cache/memory sends data word to processor
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Address Transla;on: Page Fault

Excep;on
4
2
PTEA

CPU Chip
CPU

1
VA
7

Page fault handler

MMU

PTE
3

Vic;m page

Cache/
Memory

Disk
New page
6

1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory
4) Valid bit is zero, so MMU triggers page fault excep0on
5) Handler iden0es vic0m (and, if dirty, pages it out to disk)
6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restar0ng faul0ng instruc0on

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Integra;ng VM and Cache

PTE

CPU Chip
PTEA
CPU

PTE

PTEA
hit

VA

MMU

PTEA
miss

PA

PA
miss
PA
hit

Data

PTEA
PA

Memory

Data

L1
cache

VA: virtual address, PA: physical address, PTE: page table entry, PTEA = PTE address
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Speeding up Transla;on with a TLB

Page table entries (PTEs) are cached in L1 like any other

memory word
PTEs may be evicted by other data references
PTE hit s0ll requires a small L1 delay

Solu;on: TranslaHon Lookaside Buer (TLB)

Small hardware cache in MMU
Maps virtual page numbers to physical page numbers
Contains complete page table entries for small number of pages

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TLB Hit
CPU Chip

CPU

TLB
2

PTE

VPN

1
VA

MMU

PA
4

Cache/
Memory

Data
5

A TLB hit eliminates a memory access

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TLB Miss
CPU Chip

TLB
2

4
PTE

VPN

CPU

1
VA

MMU

3
PTEA
PA

Cache/
Memory

Data
6

A TLB miss incurs an addi;onal memory access (the PTE)

Fortunately, TLB misses are rare. Why?

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Mul;-Level Page Tables

Suppose:
4KB (212) page size, 48-bit address space, 8-byte PTE

Problem:
Would need a 512 GB page table!

Level 1
Table
...

248 * 2-12 * 23 = 239 bytes

Common solu;on:
Mul0-level page tables
Example: 2-level page table

Level 2
Tables

Level 1 table: each PTE points to a page table (always

memory resident)
Level 2 table: each PTE points to a page
(paged in and out like any other data)

...

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A Two-Level Page Table Hierarchy

Level 1
page table

Level 2
page tables

Virtual
memory
VP 0

PTE 0

PTE 0

PTE 1

...

PTE 2 (null)

PTE 1023

PTE 3 (null)
PTE 0

PTE 5 (null)

...

PTE 6 (null)

PTE 1023

VP 1023
VP 1024

2K allocated VM pages
for code and data

...

Gap

PTE 7 (null)

(1K - 9)
null PTEs

...

VP 2047

PTE 4 (null)

PTE 8

6K unallocated VM pages

1023 null
PTEs
PTE 1023

...

32 bit addresses, 4KB pages, 4-byte PTEs

1023
unallocated
pages
VP 9215

1023 unallocated pages

1 allocated VM page
for the stack
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Summary

Programmers view of virtual memory

Each process has its own private linear address space
Cannot be corrupted by other processes

System view of virtual memory

Uses memory eciently by caching virtual memory pages
Ecient only because of locality
Simplies memory management and programming
Simplies protec0on by providing a convenient interposi0oning point
to check permissions

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