SSD 1298

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1298
Advance Information
240 RGB x 320 TFT LCD Controller Driver
integrated Power Circuit, Gate and Source Driver
with built-in RAM
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1298
Rev 1.1
P 1/82
Mar 2008
Copyright 2008 Solomon Systech Limited
CONTENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GENERAL DESCRIPTION ......................................................................................... 5

FEATURES................................................................................................................. 6
ORDERING INFORMATION....................................................................................... 7
BLOCK DIAGRAM ..................................................................................................... 8
DIE PAD FLOOR PLAN ............................................................................................. 9
PIN DESCRIPTION................................................................................................... 19
BLOCK FUNCTION DESCRIPTION......................................................................... 24
COMMAND TABLE .................................................................................................. 28
COMMAND DESCRIPTION...................................................................................... 30
GAMMA ADJUSTMENT FUNCTION ....................................................................... 55
MAXIMUM RATINGS................................................................................................ 62
DC CHARACTERISTICS.......................................................................................... 62
AC CHARACTERISTICS.......................................................................................... 64
GDDRAM ADDRESS................................................................................................ 69
INTERFACE MAPPING ............................................................................................ 70
DISPLAY SETTING SEQUENCE ............................................................................. 73
POWER SUPPLY BLOCK DIAGRAM...................................................................... 76
SSD1298 OUTPUT VOLTAGE RELATIONSHIP ..................................................... 77
PACKAGE INFORMATION ...................................................................................... 81
Solomon Systech
Mar 2008
P 2/82
Rev 1.1
SSD1298
TABLES
Table 3-1 Ordering Information......................................................................................................... 7
Table 4-2 - SSD1298 Bump Pad Coordinate (Bump Center)............................................................. 10
Table 5-1: Power Supply Pins ............................................................................................................ 19
Table 5-2 - Interface Logic Pins ......................................................................................................... 21
Table 5-3: Mode Selection Pins.......................................................................................................... 22
Table 5-4: Driver Output Pins............................................................................................................. 23
Table 5-5: Miscellaneous Pins ............................................................................................................ 23
Table 6-1 - Data bus selection modes ................................................................................................. 25
Table 7-1 - Command Table ............................................................................................................... 28
Table 8-1 - 3-field interlace driving.................................................................................................... 34
Table 12-1 Parallel 6800 Timing Characteristics ............................................................................ 64
Table 12-2 Parallel 8080 Timing Characteristics ............................................................................ 65
Table 12-3 - Serial Timing Characteristics......................................................................................... 66
Table 12-4 - RGB Timing Characteristics .......................................................................................... 67
Table 14-1: Interface setting and data bus setting .............................................................................. 70
Table 14-2 The Function of 6800-series parallel interface.............................................................. 70
Table 14-3 The Function of 8080-series parallel interface............................................................. 71
SSD1298
Rev 1.1
P 3/82
Mar 2008
Solomon Systech
FIGURES
Figure 4-1 - SSD1298 Block Diagram Description.............................................................................. 8
Figure 6-1 Read Display Data.......................................................................................................... 24
Figure 6-2: 3-wire SPI interface (9 bits) ............................................................................................. 25
Figure 6-3: 4-wire SPI interface (8 bits) ............................................................................................. 26
Figure 8-1 - gate output timing in 3-field interlacing driving............................................................. 34
Figure 8-2 - Line Inversion AC Driver ............................................................................................... 35
Figure 8-3 OTP circuitry.................................................................................................................. 49
Figure 12-1 Parallel 6800-series Interface Timing Characteristics .................................................. 64
Figure 12-2 Parallel 8080-series Interface Timing Characteristics .................................................. 65
Figure 12-3 4 wire Serial Timing Characteristics............................................................................ 66
Figure 12-4 RGB Timing Characteristics ........................................................................................ 67
Figure 12-5 Power Up Sequence ...................................................................................................... 67
Figure 17-1: Booster Capacitors ......................................................................................................... 78
Figure 17-2 : Filtering and Charge Sharing Capacitors ...................................................................... 78
Figure 17-3 Panel Connection Example .......................................................................................... 79
Solomon Systech
Mar 2008
P 4/82
Rev 1.1
SSD1298
GENERAL DESCRIPTION
SSD1298 is an all in one TFT LCD Controller Driver that integrated the RAM, power circuits, gate driver and source
driver into a single chip. It can drive up to 262k color amorsphous TFT panel with resolution of 240 RGB x 320.
It also integrated the controller function and consists of 172,800 bytes (240 x 320 x 18 / 8) Graphic Display Data RAM
(GDDRAM) such that it interfaced with common MPU through 8-/9-/16-/18-bit 6800-series / 8080-series compatible
parallel interface or serial peripheral interface and stored the data in the GDDRAM. Auxiliary 18-/16-/6- bit video
interface (VSYNC, HSYNC, DOTCLK, OE) are integrated into SSD1298 for animation image display.
SSD1298 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver with
minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display counter
electrode. An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide
maximum flexibility and optimal display quality.
SSD1298 can be operated down to 1.4V and provide different power save modes. It is suitable for any portable batterydriven applications requiring long operation period and compact size.
SSD1298
Rev 1.1
P 5/82
Mar 2008
Solomon Systech
FEATURES
240RGBx320 single chip controller driver IC for 262k color amorphous TFT LCD
Power Supply
- VDDIO = 1.4V 3.6V (I/O Interface)
- VCIR = 2.5V 3.6V (Regulator power supply for logic circuit)
- VCI = 2.5V 3.6V (power supply for internal analog circuit)
Output Voltages
- Gate Driver:
VGH-GND = 9V ~ 18V
VGL-GND = -6 ~ -15V
VGH-VGL = 30Vp-p
- Source Driver:
Maximum of VLCD63 = 6V
Typical Source Output Voltage variation: 10 mV
- VCOM drive:
VCOMH = 3.0V ~ 5.0V
VCOML = -1.0V ~ -3.0V
Maximum of VCOMA = 6V
System Interface
- 16-/18-bit RGB interface (OE, DOTCLK, HSYNC, VSYNC, DB[17:0]
- High-speed interface by 8-/9-/16-/18-bit 6800-series / 8080-series parallel ports
- Serial Peripheral Interface (SPI)
- VSYNC interface (system interface + VSYNC)
- WSYNC interface (system interface + WSYNC)
Support low power consumption:
- Low voltage supply
- Low current sleep mode
- 8-color display mode for power saving
- Charge sharing function for step-up circuits
High-speed RAM addressing functions
- RAM write synchronization function
- Window address function
- Vertical scrolling function
- Partial display mode
Internal power supply circuit
- Voltage generator
- DC-DC converter up to 6x/-5x
Built-in internal oscillator
Internal GDDRAM capacity: 172800Byte
Support Frame and Line inversion AC drive
TFT storage capacitance: Cs on common
Support source and gate scan direction control
Programmable gamma correction curve
Built-in Non Volatile Memory for VCOM calibration Display Size: 240 RGB x 320
Support flexible arrangement of gate circuits on both sides of the glass substrate
Solomon Systech
Mar 2008
P 6/82
Rev 1.1
SSD1298
ORDERING INFORMATION
Table 3-1 Ordering Information
SSD1298
Ordering Part
Number
Source
Gate
Package Form
SSD1298Z
240 x 3 (720)
320
Gold Bump Die
Rev 1.1
P 7/82
Mar 2008
Reference
Solomon Systech
BLOCK DIAGRAM
Figure 4-1 - SSD1298 Block Diagram Description
G0 to G319
VCOM
VCI
VDDIO
VDD
regulator
circuit
Source driver
Regulator
Circuit
VCI
C1N
C1P
C2N
C2P
C3N
C3P
CXP
CXN
CYP
CYN
S0 to S719
Gamma /
Grayscale
Voltage
Generator
Switches Network
Data Latches
Regulator
Circuit
VLCD63
20
Booster
Circuit
Address
Counter
VGH
VGL
GateDriver
GDDR
AM
Timing Generation
System Interface
OSC
Solomon Systech
Mar 2008
P 8/82
VSYNC
DOTCLK
D[17:0]
DC/SDC
WR/SCL
CS
OE
PS0-3
RES
WSYNC
VSS/AVSS/
IOGND/VCH
Rev 1.1
SSD1298
DIE PAD FLOOR PLAN

Pin 1354
Pin 1
Note
(1)
Diagram showing the die face up.
(2)
Coordinates are referenced to center of the
chip.
(3)
Coordinate units and size of all alignment
marks are in um.
(4)
All alignment keys do not contain gold
15
15
25 25 25
25 25 25
15
15
Figure 4-3: Alignment Marks
40
Center:
Size:
15 25 25
25 25 15
Center:
Size:
(-10633,-141.12)
105 x 105 m2
40
(10633,-141.12)
105 x 105 m2
Die Center
Figure 4-2: Output Pad Pitch (Pad 299 - 1354)
100
25
100
21 19
20
Table 4-1: Die Information

Die Size (no scribe)
Die Thickness
Typical Bump Height
Bump Co-planarity
(within die)
Bump Size 1
Pad Pitch 1
Bump Size 2
Pad Pitch 2
2 um
50 x 80 m2 (Pin 1 298)
70 m
21 x 100 m2 (Pin 299 1354)
20 m stagger
Pin 299
Pin 298
SSD1298
21416 x 755 um2

300 25 um
15 um
Figure 4-4 - SSD1298 Pad Arrangement (Bump face up)
Rev 1.1
P 9/82
Mar 2008
Solomon Systech
Table 4-2 - SSD1298 Bump Pad Coordinate (Bump Center)

Note: IC material temperature expansion factor is 2.6ppm, customer should take into account during panel design
Pad # Pad Name
X-pos
Y-pos
Pad #
Pad Name
X-pos
Y-pos
Pad #
Pad Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
DUMMY
DUMMY
DUMMY
NC
NC
NC
VGH
VGH
VGH
VGH
VGH
VSS
VSS
VSS
DUMMY
DUMMY
DUMMY
DUMMY
NC
NC
NC
NC
PS0
PS1
PS2
PS3
DUMMY
VDDIO
DUMMY
RESB
VSYNC
HSYNC
DOTCLK
OE
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
DUMMY
VSS
NC
D7
D6
Solomon Systech
-10395.000
-10325.000
-10255.000
-10185.000
-10115.000
-10045.000
-9975.000
-9905.000
-9835.000
-9765.000
-9695.000
-9625.000
-9555.000
-9485.000
-9415.000
-9345.000
-9275.000
-9205.000
-9135.000
-9065.000
-8995.000
-8925.000
-8855.000
-8785.000
-8715.000
-8645.000
-8575.000
-8505.000
-8435.000
-8365.000
-8295.000
-8225.000
-8155.000
-8085.000
-8015.000
-7945.000
-7875.000
-7805.000
-7735.000
-7665.000
-7595.000
-7525.000
-7455.000
-7385.000
-7315.000
-7245.000
-7175.000
-7105.000
-7035.000
-6965.000
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D5
D4
D3
D2
D1
D0
SDO
SDI
RD
WR
DC
CSB
NC
VDDIO
VDDIO
WSYNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DUMMY
DUMMY
NC
NC
NC
DUMMY
TESTA
TESTB
TESTC
NC
DUMMY
NC
NC
NC
NC
IOGND
IOGND
IOGND
IOGND
IOGND
IOGND
IOGND
VDDIO
VDDIO
VDDIO
-6895.000
-6825.000
-6755.000
-6685.000
-6615.000
-6545.000
-6475.000
-6405.000
-6335.000
-6265.000
-6195.000
-6125.000
-6055.000
-5985.000
-5915.000
-5845.000
-5775.000
-5705.000
-5635.000
-5565.000
-5495.000
-5425.000
-5355.000
-5285.000
-5215.000
-5145.000
-5075.000
-5005.000
-4935.000
-4865.000
-4795.000
-4725.000
-4655.000
-4585.000
-4515.000
-4445.000
-4375.000
-4305.000
-4235.000
-4165.000
-4095.000
-4025.000
-3955.000
-3885.000
-3815.000
-3745.000
-3675.000
-3605.000
-3535.000
-3465.000
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VDDIO
VDDIO
VDDIO
VDDIO
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VCORE
VCORE
VCORE
VCORE
VCORE
VCORE
VCORE
VCORE
VCORE
VREGC
VREGC
VREGC
VREGC
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
Mar 2008 P 10/82
Rev 1.1
X-pos
Y-pos
-3395.000
-3325.000
-3255.000
-3185.000
-3115.000
-3045.000
-2975.000
-2905.000
-2835.000
-2765.000
-2695.000
-2625.000
-2555.000
-2485.000
-2415.000
-2345.000
-2275.000
-2205.000
-2135.000
-2065.000
-1995.000
-1925.000
-1855.000
-1785.000
-1715.000
-1645.000
-1575.000
-1505.000
-1435.000
-1365.000
-1295.000
-1225.000
-1155.000
-1085.000
-1015.000
-945.000
-875.000
-805.000
-735.000
-665.000
-595.000
-525.000
-455.000
-385.000
-315.000
-245.000
-175.000
-105.000
-35.000
35.000
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
SSD1298
Pad #
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Pad
X-pos
Y-pos
Pad # Pad Name
Name
VSS
105.000
-305.620
201 VCIX2G
VSS
175.000
-305.620
202 VCIX2G
VSS
245.000
-305.620
203 VCIX2
VSS
315.000
-305.620
204 VCIX2
VSS
385.000
-305.620
205 VCIX2
VSS
455.000
-305.620
206 VCIX2
VSS
525.000
-305.620
207 VCIX2
VSS
595.000
-305.620
208 VCIX2
VSS
665.000
-305.620
209 VCIX2
VSS
735.000
-305.620
210 VCI
DUMMY
805.000
-305.620
211 VCI
DUMMY
875.000
-305.620
212 VCI
DUMMY
945.000
-305.620
213 VCI
EXVR
1015.000
-305.620
214 VCI
DUMMY 1085.000
-305.620
215 VCI
DUMMY 1155.000
-305.620
216 VCI
DUMMY 1225.000
-305.620
217 VCI
DUMMY 1295.000
-305.620
218 VCIP
DUMMY 1365.000
-305.620
219 VCI
DUMMY 1435.000
-305.620
220 VCI
VCOM
1505.000
-305.620
221 VCI
VCOM
1575.000
-305.620
222 VCI
VCOM
1645.000
-305.620
223 VCI
VCOM
1715.000
-305.620
224 VCI
VCOM
1785.000
-305.620
225 VCI
VCOM
1855.000
-305.620
226 VCI
VCOMH 1925.000
-305.620
227 CYN
VCOMH 1995.000
-305.620
228 CYN
VCOMH 2065.000
-305.620
229 CYN
VCOMH 2135.000
-305.620
230 CYN
VCOMH 2205.000
-305.620
231 CYN
VCOMH 2275.000
-305.620
232 CYP
VCOML
2345.000
-305.620
233 CYP
VCOML
2415.000
-305.620
234 CYP
VCOML
2485.000
-305.620
235 CYP
VCOML
2555.000
-305.620
236 CYP
VCOML
2625.000
-305.620
237 CXN
VCOML
2695.000
-305.620
238 CXN
DUMMY 2765.000
-305.620
239 CXN
DUMMY 2835.000
-305.620
240 CXN
VLCD63 2905.000
-305.620
241 CXN
DUMMY 2975.000
-305.620
242 CXP
DUMMY 3045.000
-305.620
243 CXP
DUMMY 3115.000
-305.620
244 CXP
VCOMR
3185.000
-305.620
245 CXP
DUMMY 3255.000
-305.620
246 CXP
VCIM
3325.000
-305.620
247 DUMMY
VCIM
3395.000
-305.620
248 VGL
VCIM
3465.000
-305.620
249 VGL
VCIX2G
3535.000
-305.620
250 VGL
SSD1298
Rev 1.1
P 11/82
Mar 2008
X-pos
3605.000
3675.000
3745.000
3815.000
3885.000
3955.000
4025.000
4095.000
4165.000
4235.000
4305.000
4375.000
4445.000
4515.000
4585.000
4655.000
4725.000
4795.000
4865.000
4935.000
5005.000
5075.000
5145.000
5215.000
5285.000
5355.000
5425.000
5495.000
5565.000
5635.000
5705.000
5775.000
5845.000
5915.000
5985.000
6055.000
6125.000
6195.000
6265.000
6335.000
6405.000
6475.000
6545.000
6615.000
6685.000
6755.000
6825.000
6895.000
6965.000
7035.000
Y-pos
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
Pad #
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Pad Name X-pos

VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
DUMMY
DUMMY
DUMMY
VGH
VGH
VGH
VGH
VGH
VGH
DUMMY
C3N
C3N
C3N
DUMMY
C3P
C3P
C3P
DUMMY
C1N
C1N
C1N
C1P
C1P
C1P
C2N
C2N
C2N
C2P
C2P
C2P
CDUM1N
CDUM1N
CDUM1N
CDUM1P
CDUM1P
CDUM1P
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
7105.000
7175.000
7245.000
7315.000
7385.000
7455.000
7525.000
7595.000
7665.000
7735.000
7805.000
7875.000
7945.000
8015.000
8085.000
8155.000
8225.000
8295.000
8365.000
8435.000
8505.000
8575.000
8645.000
8715.000
8785.000
8855.000
8925.000
8995.000
9065.000
9135.000
9205.000
9275.000
9345.000
9415.000
9485.000
9555.000
9625.000
9695.000
9765.000
9835.000
9905.000
9975.000
10045.000
10115.000
10185.000
10255.000
10325.000
10395.000
10670.000
10650.000
Y-pos
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
-305.620
293.380
168.380
Solomon Systech
Pad #
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
Pad Name X-pos

Y-pos
Pad # Pad Name X-pos
DUMMY
10630.000 293.380
351 G95
9630.000
DUMMY
10610.000 168.380
352 G97
9610.000
DUMMY
10590.000 293.380
353 G99
9590.000
G1
10570.000 168.380
354 G101
9570.000
G3
10550.000 293.380
355 G103
9550.000
G5
10530.000 168.380
356 G105
9530.000
G7
10510.000 293.380
357 G107
9510.000
G9
10490.000 168.380
358 G109
9490.000
G11
10470.000 293.380
359 G111
9470.000
G13
10450.000 168.380
360 G113
9450.000
G15
10430.000 293.380
361 G115
9430.000
G17
10410.000 168.380
362 G117
9410.000
G19
10390.000 293.380
363 G119
9390.000
G21
10370.000 168.380
364 G121
9370.000
G23
10350.000 293.380
365 G123
9350.000
G25
10330.000 168.380
366 G125
9330.000
G27
10310.000 293.380
367 G127
9310.000
G29
10290.000 168.380
368 G129
9290.000
G31
10270.000 293.380
369 G131
9270.000
G33
10250.000 168.380
370 G133
9250.000
G35
10230.000 293.380
371 G135
9230.000
G37
10210.000 168.380
372 G137
9210.000
G39
10190.000 293.380
373 G139
9190.000
G41
10170.000 168.380
374 G141
9170.000
G43
10150.000 293.380
375 G143
9150.000
G45
10130.000 168.380
376 G145
9130.000
G47
10110.000 293.380
377 G147
9110.000
G49
10090.000 168.380
378 G149
9090.000
G51
10070.000 293.380
379 G151
9070.000
G53
10050.000 168.380
380 G153
9050.000
G55
10030.000 293.380
381 G155
9030.000
G57
10010.000 168.380
382 G157
9010.000
G59
9990.000 293.380
383 G159
8990.000
G61
9970.000 168.380
384 G161
8970.000
G63
9950.000 293.380
385 G163
8950.000
G65
9930.000 168.380
386 G165
8930.000
G67
9910.000 293.380
387 G167
8910.000
G69
9890.000 168.380
388 G169
8890.000
G71
9870.000 293.380
389 G171
8870.000
G73
9850.000 168.380
390 G173
8850.000
G75
9830.000 293.380
391 G175
8830.000
G77
9810.000 168.380
392 G177
8810.000
G79
9790.000 293.380
393 G179
8790.000
G81
9770.000 168.380
394 G181
8770.000
G83
9750.000 293.380
395 G183
8750.000
G85
9730.000 168.380
396 G185
8730.000
G87
9710.000 293.380
397 G187
8710.000
G89
9690.000 168.380
398 G189
8690.000
G91
9670.000 293.380
399 G191
8670.000
G93
9650.000 168.380
400 G193
8650.000
Solomon Systech
Y-pos
Pad # Pad Name
293.380
401 G195
168.380
402 G197
293.380
403 G199
168.380
404 G201
293.380
405 G203
168.380
406 G205
293.380
407 G207
168.380
408 G209
293.380
409 G211
168.380
410 G213
293.380
411 G215
168.380
412 G217
293.380
413 G219
168.380
414 G221
293.380
415 G223
168.380
416 G225
293.380
417 G227
168.380
418 G229
293.380
419 G231
168.380
420 G233
293.380
421 G235
168.380
422 G237
293.380
423 G239
168.380
424 G241
293.380
425 G243
168.380
426 G245
293.380
427 G247
168.380
428 G249
293.380
429 G251
168.380
430 G253
293.380
431 G255
168.380
432 G257
293.380
433 G259
168.380
434 G261
293.380
435 G263
168.380
436 G265
293.380
437 G267
168.380
438 G269
293.380
439 G271
168.380
440 G273
293.380
441 G275
168.380
442 G277
293.380
443 G279
168.380
444 G281
293.380
445 G283
168.380
446 G285
293.380
447 G287
168.380
448 G289
293.380
449 G291
168.380
450 G293
Mar 2008 P 12/82
X-pos
8630.000
8610.000
8590.000
8570.000
8550.000
8530.000
8510.000
8490.000
8470.000
8450.000
8430.000
8410.000
8390.000
8370.000
8350.000
8330.000
8310.000
8290.000
8270.000
8250.000
8230.000
8210.000
8190.000
8170.000
8150.000
8130.000
8110.000
8090.000
8070.000
8050.000
8030.000
8010.000
7990.000
7970.000
7950.000
7930.000
7910.000
7890.000
7870.000
7850.000
7830.000
7810.000
7790.000
7770.000
7750.000
7730.000
7710.000
7690.000
7670.000
7650.000
Rev 1.1
Y-pos
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
SSD1298
Pad #
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
Pad Name
G295
G297
G299
G301
G303
G305
G307
G309
G311
G313
G315
G317
G319
DUMMY
DUMMY
DUMMY
S719
S718
S717
S716
S715
S714
S713
S712
S711
S710
S709
S708
S707
S706
S705
S704
S703
S702
S701
S700
S699
S698
S697
S696
S695
S694
S693
S692
S691
S690
S689
S688
S687
S686
SSD1298
X-pos
Y-pos
Pad # Pad Name
7630.000 293.380
501 S685
7610.000 168.380
502 S684
7590.000 293.380
503 S683
7570.000 168.380
504 S682
7550.000 293.380
505 S681
7530.000 168.380
506 S680
7510.000 293.380
507 S679
7490.000 168.380
508 S678
7470.000 293.380
509 S677
7450.000 168.380
510 S676
7430.000 293.380
511 S675
7410.000 168.380
512 S674
7390.000 293.380
513 S673
7370.000 168.380
514 S672
7350.000 293.380
515 S671
7130.000 293.380
516 S670
7110.000 168.380
517 S669
7090.000 293.380
518 S668
7070.000 168.380
519 S667
7050.000 293.380
520 S666
7030.000 168.380
521 S665
7010.000 293.380
522 S664
6990.000 168.380
523 S663
6970.000 293.380
524 S662
6950.000 168.380
525 S661
6930.000 293.380
526 S660
6910.000 168.380
527 S659
6890.000 293.380
528 S658
6870.000 168.380
529 S657
6850.000 293.380
530 S656
6830.000 168.380
531 S655
6810.000 293.380
532 S654
6790.000 168.380
533 S653
6770.000 293.380
534 S652
6750.000 168.380
535 S651
6730.000 293.380
536 S650
6710.000 168.380
537 S649
6690.000 293.380
538 S648
6670.000 168.380
539 S647
6650.000 293.380
540 S646
6630.000 168.380
541 S645
6610.000 293.380
542 S644
6590.000 168.380
543 S643
6570.000 293.380
544 S642
6550.000 168.380
545 S641
6530.000 293.380
546 S640
6510.000 168.380
547 S639
6490.000 293.380
548 S638
6470.000 168.380
549 S637
6450.000 293.380
550 S636
Rev 1.1
P 13/82
Mar 2008
X-pos
6430.000
6410.000
6390.000
6370.000
6350.000
6330.000
6310.000
6290.000
6270.000
6250.000
6230.000
6210.000
6190.000
6170.000
6150.000
6130.000
6110.000
6090.000
6070.000
6050.000
6030.000
6010.000
5990.000
5970.000
5950.000
5930.000
5910.000
5890.000
5870.000
5850.000
5830.000
5810.000
5790.000
5770.000
5750.000
5730.000
5710.000
5690.000
5670.000
5650.000
5630.000
5610.000
5590.000
5570.000
5550.000
5530.000
5510.000
5490.000
5470.000
5450.000
Y-pos
Pad # Pad Name X-pos
168.380
551 S635
5430.000
293.380
552 S634
5410.000
168.380
553 S633
5390.000
293.380
554 S632
5370.000
168.380
555 S631
5350.000
293.380
556 S630
5330.000
168.380
557 S629
5310.000
293.380
558 S628
5290.000
168.380
559 S627
5270.000
293.380
560 S626
5250.000
168.380
561 S625
5230.000
293.380
562 S624
5210.000
168.380
563 S623
5190.000
293.380
564 S622
5170.000
168.380
565 S621
5150.000
293.380
566 S620
5130.000
168.380
567 S619
5110.000
293.380
568 S618
5090.000
168.380
569 S617
5070.000
293.380
570 S616
5050.000
168.380
571 S615
5030.000
293.380
572 S614
5010.000
168.380
573 S613
4990.000
293.380
574 S612
4970.000
168.380
575 S611
4950.000
293.380
576 S610
4930.000
168.380
577 S609
4910.000
293.380
578 S608
4890.000
168.380
579 S607
4870.000
293.380
580 S606
4850.000
168.380
581 S605
4830.000
293.380
582 S604
4810.000
168.380
583 S603
4790.000
293.380
584 S602
4770.000
168.380
585 S601
4750.000
293.380
586 S600
4730.000
168.380
587 S599
4710.000
293.380
588 S598
4690.000
168.380
589 S597
4670.000
293.380
590 S596
4650.000
168.380
591 S595
4630.000
293.380
592 S594
4610.000
168.380
593 S593
4590.000
293.380
594 S592
4570.000
168.380
595 S591
4550.000
293.380
596 S590
4530.000
168.380
597 S589
4510.000
293.380
598 S588
4490.000
168.380
599 S587
4470.000
293.380
600 S586
4450.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Solomon Systech
Pad # Pad Name

601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
S585
S584
S583
S582
S581
S580
S579
S578
S577
S576
S575
S574
S573
S572
S571
S570
S569
S568
S567
S566
S565
S564
S563
S562
S561
S560
S559
S558
S557
S556
S555
S554
S553
S552
S551
S550
S549
S548
S547
S546
S545
S544
S543
S542
S541
S540
S539
S538
S537
S536
Solomon Systech
X-pos
4430.000
4410.000
4390.000
4370.000
4350.000
4330.000
4310.000
4290.000
4270.000
4250.000
4230.000
4210.000
4190.000
4170.000
4150.000
4130.000
4110.000
4090.000
4070.000
4050.000
4030.000
4010.000
3990.000
3970.000
3950.000
3930.000
3910.000
3890.000
3870.000
3850.000
3830.000
3810.000
3790.000
3770.000
3750.000
3730.000
3710.000
3690.000
3670.000
3650.000
3630.000
3610.000
3590.000
3570.000
3550.000
3530.000
3510.000
3490.000
3470.000
3450.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
Pad
Name
S535
S534
S533
S532
S531
S530
S529
S528
S527
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
S516
S515
S514
S513
S512
S511
S510
S509
S508
S507
S506
S505
S504
S503
S502
S501
S500
S499
S498
S497
S496
S495
S494
S493
S492
S491
S490
S489
S488
S487
S486
X-pos
3430.000
3410.000
3390.000
3370.000
3350.000
3330.000
3310.000
3290.000
3270.000
3250.000
3230.000
3210.000
3190.000
3170.000
3150.000
3130.000
3110.000
3090.000
3070.000
3050.000
3030.000
3010.000
2990.000
2970.000
2950.000
2930.000
2910.000
2890.000
2870.000
2850.000
2830.000
2810.000
2790.000
2770.000
2750.000
2730.000
2710.000
2690.000
2670.000
2650.000
2630.000
2610.000
2590.000
2570.000
2550.000
2530.000
2510.000
2490.000
2470.000
2450.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
Pad
Name
S485
S484
S483
S482
S481
S480
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
S468
S467
S466
S465
S464
S463
S462
S461
S460
S459
S458
S457
S456
S455
S454
S453
S452
S451
S450
S449
S448
S447
S446
S445
S444
S443
S442
S441
S440
S439
S438
S437
S436
Mar 2008 P 14/82
X-pos
2430.000
2410.000
2390.000
2370.000
2350.000
2330.000
2310.000
2290.000
2270.000
2250.000
2230.000
2210.000
2190.000
2170.000
2150.000
2130.000
2110.000
2090.000
2070.000
2050.000
2030.000
2010.000
1990.000
1970.000
1950.000
1930.000
1910.000
1890.000
1870.000
1850.000
1830.000
1810.000
1790.000
1770.000
1750.000
1730.000
1710.000
1690.000
1670.000
1650.000
1630.000
1610.000
1590.000
1570.000
1550.000
1530.000
1510.000
1490.000
1470.000
1450.000
Rev 1.1
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
SSD1298
Pad #
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
Pad
Name
S435
S434
S433
S432
S431
S430
S429
S428
S427
S426
S425
S424
S423
S422
S421
S420
S419
S418
S417
S416
S415
S414
S413
S412
S411
S410
S409
S408
S407
S406
S405
S404
S403
S402
S401
S400
S399
S398
S397
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
SSD1298
X-pos
Y-pos
Pad #
Pad
Name
1430.000
1410.000
1390.000
1370.000
1350.000
1330.000
1310.000
1290.000
1270.000
1250.000
1230.000
1210.000
1190.000
1170.000
1150.000
1130.000
1110.000
1090.000
1070.000
1050.000
1030.000
1010.000
990.000
970.000
950.000
930.000
910.000
890.000
870.000
850.000
830.000
810.000
790.000
770.000
750.000
730.000
710.000
690.000
670.000
650.000
630.000
610.000
590.000
570.000
550.000
530.000
510.000
490.000
470.000
450.000
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
Rev 1.1
P 15/82
Mar 2008
X-pos
430.000
410.000
390.000
370.000
350.000
330.000
310.000
290.000
270.000
250.000
230.000
210.000
190.000
170.000
150.000
130.000
110.000
90.000
70.000
50.000
30.000
10.000
-10.000
-30.000
-50.000
-70.000
-90.000
-110.000
-130.000
-150.000
-170.000
-190.000
-210.000
-230.000
-250.000
-270.000
-290.000
-310.000
-330.000
-350.000
-370.000
-390.000
-410.000
-430.000
-450.000
-470.000
-490.000
-510.000
-530.000
-550.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
Pad
Name
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
X-pos
Y-pos
-570.000
-590.000
-610.000
-630.000
-650.000
-670.000
-690.000
-710.000
-730.000
-750.000
-770.000
-790.000
-810.000
-830.000
-850.000
-870.000
-890.000
-910.000
-930.000
-950.000
-970.000
-990.000
-1010.000
-1030.000
-1050.000
-1070.000
-1090.000
-1110.000
-1130.000
-1150.000
-1170.000
-1190.000
-1210.000
-1230.000
-1250.000
-1270.000
-1290.000
-1310.000
-1330.000
-1350.000
-1370.000
-1390.000
-1410.000
-1430.000
-1450.000
-1470.000
-1490.000
-1510.000
-1530.000
-1550.000
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Solomon Systech
Pad #
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
Pad
Name
X-pos
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
Solomon Systech
-1570.000
-1590.000
-1610.000
-1630.000
-1650.000
-1670.000
-1690.000
-1710.000
-1730.000
-1750.000
-1770.000
-1790.000
-1810.000
-1830.000
-1850.000
-1870.000
-1890.000
-1910.000
-1930.000
-1950.000
-1970.000
-1990.000
-2010.000
-2030.000
-2050.000
-2070.000
-2090.000
-2110.000
-2130.000
-2150.000
-2170.000
-2190.000
-2210.000
-2230.000
-2250.000
-2270.000
-2290.000
-2310.000
-2330.000
-2350.000
-2370.000
-2390.000
-2410.000
-2430.000
-2450.000
-2470.000
-2490.000
-2510.000
-2530.000
-2550.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
Pad
Name
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
X-pos
-2570.000
-2590.000
-2610.000
-2630.000
-2650.000
-2670.000
-2690.000
-2710.000
-2730.000
-2750.000
-2770.000
-2790.000
-2810.000
-2830.000
-2850.000
-2870.000
-2890.000
-2910.000
-2930.000
-2950.000
-2970.000
-2990.000
-3010.000
-3030.000
-3050.000
-3070.000
-3090.000
-3110.000
-3130.000
-3150.000
-3170.000
-3190.000
-3210.000
-3230.000
-3250.000
-3270.000
-3290.000
-3310.000
-3330.000
-3350.000
-3370.000
-3390.000
-3410.000
-3430.000
-3450.000
-3470.000
-3490.000
-3510.000
-3530.000
-3550.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
Pad
Name
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
Mar 2008 P 16/82
X-pos
-3570.000
-3590.000
-3610.000
-3630.000
-3650.000
-3670.000
-3690.000
-3710.000
-3730.000
-3750.000
-3770.000
-3790.000
-3810.000
-3830.000
-3850.000
-3870.000
-3890.000
-3910.000
-3930.000
-3950.000
-3970.000
-3990.000
-4010.000
-4030.000
-4050.000
-4070.000
-4090.000
-4110.000
-4130.000
-4150.000
-4170.000
-4190.000
-4210.000
-4230.000
-4250.000
-4270.000
-4290.000
-4310.000
-4330.000
-4350.000
-4370.000
-4390.000
-4410.000
-4430.000
-4450.000
-4470.000
-4490.000
-4510.000
-4530.000
-4550.000
Rev 1.1
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
SSD1298
Pad #
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
Pad
Name
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
SSD1298
X-pos
Y-pos
-4570.000
-4590.000
-4610.000
-4630.000
-4650.000
-4670.000
-4690.000
-4710.000
-4730.000
-4750.000
-4770.000
-4790.000
-4810.000
-4830.000
-4850.000
-4870.000
-4890.000
-4910.000
-4930.000
-4950.000
-4970.000
-4990.000
-5010.000
-5030.000
-5050.000
-5070.000
-5090.000
-5110.000
-5130.000
-5150.000
-5170.000
-5190.000
-5210.000
-5230.000
-5250.000
-5270.000
-5290.000
-5310.000
-5330.000
-5350.000
-5370.000
-5390.000
-5410.000
-5430.000
-5450.000
-5470.000
-5490.000
-5510.000
-5530.000
-5550.000
Rev 1.1
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
P 17/82
Pad #
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
Mar 2008
Pad
Name
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
X-pos
Y-pos
-5570.000 168.380
-5590.000 293.380
-5610.000 168.380
-5630.000 293.380
-5650.000 168.380
-5670.000 293.380
-5690.000 168.380
-5710.000 293.380
-5730.000 168.380
-5750.000 293.380
-5770.000 168.380
-5790.000 293.380
-5810.000 168.380
-5830.000 293.380
-5850.000 168.380
-5870.000 293.380
-5890.000 168.380
-5910.000 293.380
-5930.000 168.380
-5950.000 293.380
-5970.000 168.380
-5990.000 293.380
-6010.000 168.380
-6030.000 293.380
-6050.000 168.380
-6070.000 293.380
-6090.000 168.380
-6110.000 293.380
-6130.000 168.380
-6150.000 293.380
-6170.000 168.380
-6190.000 293.380
-6210.000 168.380
-6230.000 293.380
-6250.000 168.380
-6270.000 293.380
-6290.000 168.380
-6310.000 293.380
-6330.000 168.380
-6350.000 293.380
-6370.000 168.380
-6390.000 293.380
-6410.000 168.380
-6430.000 293.380
-6450.000 168.380
-6470.000 293.380
-6490.000 168.380
-6510.000 293.380
-6530.000 168.380
-6550.000 293.380
Pad #
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
Pad
Name
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
DUMMY
DUMMY
DUMMY
G318
G316
G314
G312
G310
G308
G306
G304
G302
G300
G298
X-pos
-6570.000
-6590.000
-6610.000
-6630.000
-6650.000
-6670.000
-6690.000
-6710.000
-6730.000
-6750.000
-6770.000
-6790.000
-6810.000
-6830.000
-6850.000
-6870.000
-6890.000
-6910.000
-6930.000
-6950.000
-6970.000
-6990.000
-7010.000
-7030.000
-7050.000
-7070.000
-7090.000
-7110.000
-7130.000
-7150.000
-7170.000
-7190.000
-7210.000
-7230.000
-7250.000
-7270.000
-7290.000
-7350.000
-7370.000
-7390.000
-7410.000
-7430.000
-7450.000
-7470.000
-7490.000
-7510.000
-7530.000
-7550.000
-7570.000
-7590.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Solomon Systech
Pad #
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
Pad
Name
X-pos
G296
G294
G292
G290
G288
G286
G284
G282
G280
G278
G276
G274
G272
G270
G268
G266
G264
G262
G260
G258
G256
G254
G252
G250
G248
G246
G244
G242
G240
G238
G236
G234
G232
G230
G228
G226
G224
G222
G220
G218
G216
G214
G212
G210
G208
G206
G204
G202
G200
G198
G196
G194
Solomon Systech
-7610.000
-7630.000
-7650.000
-7670.000
-7690.000
-7710.000
-7730.000
-7750.000
-7770.000
-7790.000
-7810.000
-7830.000
-7850.000
-7870.000
-7890.000
-7910.000
-7930.000
-7950.000
-7970.000
-7990.000
-8010.000
-8030.000
-8050.000
-8070.000
-8090.000
-8110.000
-8130.000
-8150.000
-8170.000
-8190.000
-8210.000
-8230.000
-8250.000
-8270.000
-8290.000
-8310.000
-8330.000
-8350.000
-8370.000
-8390.000
-8410.000
-8430.000
-8450.000
-8470.000
-8490.000
-8510.000
-8530.000
-8550.000
-8570.000
-8590.000
-8610.000
-8630.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
Pad
Name
G192
G190
G188
G186
G184
G182
G180
G178
G176
G174
G172
G170
G168
G166
G164
G162
G160
G158
G156
G154
G152
G150
G148
G146
G144
G142
G140
G138
G136
G134
G132
G130
G128
G126
G124
G122
G120
G118
G116
G114
G112
G110
G108
G106
G104
G102
G100
G98
G96
G94
G92
G90
X-pos
-8650.000
-8670.000
-8690.000
-8710.000
-8730.000
-8750.000
-8770.000
-8790.000
-8810.000
-8830.000
-8850.000
-8870.000
-8890.000
-8910.000
-8930.000
-8950.000
-8970.000
-8990.000
-9010.000
-9030.000
-9050.000
-9070.000
-9090.000
-9110.000
-9130.000
-9150.000
-9170.000
-9190.000
-9210.000
-9230.000
-9250.000
-9270.000
-9290.000
-9310.000
-9330.000
-9350.000
-9370.000
-9390.000
-9410.000
-9430.000
-9450.000
-9470.000
-9490.000
-9510.000
-9530.000
-9550.000
-9570.000
-9590.000
-9610.000
-9630.000
-9650.000
-9670.000
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
Pad #
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
Pad
Name
X-pos
G88
G86
G84
G82
G80
G78
G76
G74
G72
G70
G68
G66
G64
G62
G60
G58
G56
G54
G52
G50
G48
G46
G44
G42
G40
G38
G36
G34
G32
G30
G28
G26
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
G0
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
Mar 2008 P 18/82
-9690.000
-9710.000
-9730.000
-9750.000
-9770.000
-9790.000
-9810.000
-9830.000
-9850.000
-9870.000
-9890.000
-9910.000
-9930.000
-9950.000
-9970.000
-9990.000
-10010.000
-10030.000
-10050.000
-10070.000
-10090.000
-10110.000
-10130.000
-10150.000
-10170.000
-10190.000
-10210.000
-10230.000
-10250.000
-10270.000
-10290.000
-10310.000
-10330.000
-10350.000
-10370.000
-10390.000
-10410.000
-10430.000
-10450.000
-10470.000
-10490.000
-10510.000
-10530.000
-10550.000
-10570.000
-10590.000
-10610.000
-10630.000
-10650.000
-10670.000
Rev 1.1
Y-pos
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
168.380
293.380
SSD1298
PIN DESCRIPTION
Remark:
I = Input;
O = Output;
IO = Bi-directional;
P = Power;
VCC = System VDD;
GND = System VSS;
Table 5-1: Power Supply Pins

Pin Name
VSS
AVSS
IOGND
VCHS
Type
VCI
Connect
to
GND
GND
GND
AVSS
Power
Supply
Ground of
the Power
Supply
Power
Supply for
Analog
Circuits
P
VCIP
VCI
VCIM
O
VCIX2
VCIX2J
P
VCIX2G
VCOMR
VCOMH
O
VCOML
VLCD63
VGH
VGL
Stabilizing
capacitor
Stabilizing
capacitor
VCIX2 on
FPC
VCIX2 on
FPC
External
voltage
source or
Open
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
GND
CXP
CXN
CYP
CYN
C1P
C1N
C2P
C2N
C3P
Booster
capacitor
Booster
capacitor
Booster
capacitor
Booster
capacitor
CDUM1P
SSD1298
Booster
voltages
Voltage for
analog
External
Reference
Voltages for
VCOM
Signal
LCD
Driving
Voltages
External
Reference
EXVR
C3N
Function
Booster and
Stabilization
Capacitors
Booster
capacitor
Stabilizing
capacitor
Rev 1.1
Description
System ground pin of the IC.
Grounding for analog circuit.
Grounding for logic circuit.
Grounding for booster circuit.
Booster input voltage pin.
- Connect to voltage source between 2.5V to 3.6V
Voltage supply pin for analog circuit. This pin requires a
noise free path for providing accurate LCD driving
voltages.
- Connect to same source of VCI
P 19/82
Mar 2008
Negative voltage of VCI.
Equals to 2x VCI
They are the power supply used by on chip analog

blocks and VGH/VGL DC-DC.
This pin provides voltage reference for internal voltage

regulator when register VDV[4:0] of Power Control 4
set to 01111.
- Connect to an external voltage source for reference
This pin indicates a HIGH level of VCOM generated in
driving the VCOM alternation.
This pin indicates a LOW level of VCOM generated in
driving the VCOM alternation.
Open
-
This pin is the maximum source driver voltage.
A positive power output pin for gate driver and for MTP
programming
A negative power output pin for gate driver.
External reference of internal gamma resistor

- Connect to VSS
- Connect a capacitor to CXN
- Connect a capacitor to CXP
- Connect a capacitor to CYN
- Connect a capacitor to CYP
- Connect a capacitor to C1N
- Connect a capacitor to C1P
Stabilization
Capacitors
When
not in
use
-
- Connect a capacitor to CDUM1N
Solomon Systech
Pin Name
Type
CDUM1N
Connect
to
Stabilizing
capacitor
Stabilizing
capacitor
VCORE
VREGC
VCORE
VDDIO
Power
Supply
VCIR
Power
Supply
Solomon Systech
Function
When
not in
use
Open
Description
- Connect a capacitor to CDUM1P

Power for
Core Logic
Regulator
output for
logic
circuits
Power for
interface
logic pins
Power for
interface
logic pins
Open
Vdd for core use. Connect a capacitor for stabilization
Regulator output for VCORE use.
Voltage input pin for logic I/O, connect to system VDD.

- Connect to voltage source between 1.4V to 3.6V
Internal regular input for logic supply : VCIR=2.5V3.3V
Mar 2008 P 20/82
Rev 1.1
SSD1298
Table 5-2 - Interface Logic Pins

Name
Type
Connect
to
Function
Description
DC
MPU
Data or command
CSB
MPU
Chip select pin for 6800/8080/SPI interface

6800-system : E (enable signal)
8080-system : RD (read strobe signal)
Serial mode : Not used and should be connected to VDDIO or Vss
68-system : RW (indicates read cycle when High, write cycle
when Low)
80-system : WR (write strobe signal)
Serial mode : SCL (serial clock input)
RD
WR
MPU
Logic
Control
MPU
D0-D17
IO
MPU
Data bus
For parallel mode, 8/9/16/18 bit interface.

Please refer to Section 13 Interface Mapping for definition.
Unused pins should connect to VSS.
WSYNC
MPU
Logic
Control
Ram Write Synchronization output
OE
MPU
DOTCLK
MPU
HSYNC
VSYNC
I
I
MPU
MPU
RESB
MPU
SDI
MPU
SDO
MPU
SSD1298
Rev 1.1
Display
Timing
Signals
System
Reset
P 21/82
Data output pin in serial interface
Mar 2008
VDDIO
or Vss
VDDIO
or Vss
VSS
Open
Display enable pin from controller. Data will be treated as dummy

regardless the OE status during front/back porch setting at
registers R16 and R17.
Dot-clock signal and oscillator source. A non-stop external clock
must be provided to that pin even at front or black porch nondisplay period.
Line Synchronization input
Frame/Ram Write Synchronization input
System reset pin.
- An active low pulse at this pin will reset the IC, Connect to
VDDIO in normal operation
Data input pin in serial interface
Serial
interface
When
not in
use
VDDIO
or Vss
-
Vss
Vss
VSS
VSS
VSS
Open
Solomon Systech
Table 5-3: Mode Selection Pins

Name
PS[3:0]
Type
Solomon Systech
Connect
to
VDDIO or
VSS
Function
Interface
Selection
When
not in
use
Description
PS3
0
0
0
0
0
PS2
0
0
0
0
1
PS1
0
0
1
1
0
PS0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
Interface Mode
16-bit 6800 parallel interface
9-bit generic D[8:0] (262k
colour) + 3-wire SPI If 65K
color, D3 shorts to D8 internally
16-bit generic (262k colour) +
3-wire SPI
18-bit generic (262k colour) +
3-wire SPI
6-bit generic D[8:3] (262k
colour) + 3-wire SPI
18-bits 6800 parallel interface
3-wire SPI
4-wire SPI
Mar 2008 P 22/82
Rev 1.1
SSD1298
Table 5-4: Driver Output Pins

Name
Connect
to
Type
VCOM
LCD
G0-G319
LCD
Function
LCD
Driving
Signals
O
S0-S719
LCD
Description
A power supply for the TFT-display common electrode.
Gate driver output pins. These pins output VGH, VGL or VGOFFH
level.
Source driver output pins.
S(3n) : display Red if BGR = LOW, Blue if BGR = HIGH.
S(3n+1) : display Green.
S(3n+2) : display Blue if BGR = LOW, Red if BGR = HIGH.
When
not in
use
Open
Open
Open
Table 5-5: Miscellaneous Pins

Name
Type
Connect
to
Function
Description
NC
DUMMY
These pins must be left open and cannot be connected together

Floating pins and no connection inside the IC. These pins
should be open.
Test pin of the internal circuit.
- Leave this pin open and insert test point in FPC
TESTA
TESTB
TESTC
SSD1298
FPC
IO
FPC
IC
Testing
Signal
FPC
Rev 1.1
P 23/82
Mar 2008
When
not in
use
Open
Open
Open
Open
Open
Solomon Systech
6
6.1
BLOCK FUNCTION DESCRIPTION

System Interface
The System Interface unit consists of three functional blocks for driving the 6800-series parallel interface,
8080-series high speed parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral
interface. The selection of different interface is done by PS3, PS2, PS1 and PS0 pins. Please refer to the pin
descriptions on page 19.
a) MPU Parallel 6800-series Interface
The parallel Interface consists of 18 bi-directional data pins D[17:0], R / W , D/ C , E and CS . R / W
input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status
register. R / W input low indicates a write operation to Display Data RAM or Internal Command
Registers depending on the status of D/ C input. The E input serves as data latch signal (clock) when
high provided that CS is low. Please refer to Parallel Interface Timing Diagram of 6800-series
microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU,
pipeline processing is internally performed which requires the insertion of a dummy read before the
first actual display data read. This is shown in the following diagram.
R/W#(WR#)
E(RD#)
DATA BUS
N
write column address
dummy read
n+1
data read1
data read 2
n+2
data read 3
Figure 6-1 Read Display Data
b) MPU Parallel 8080-series Interface

The parallel interface consists of 18 bi-directional data pins D[17:0], RD, WR, DC and CSB. RD
input serves as data read latch signal (clock) when low provided that CSB is low. Whether reading the
display data from GDDRAM or reading the status from the status register is controlled by DC. WR
input serves as data write latch signal (clock) when low provided that CSB is low. Whether writing
the display data to the GDDRAM or writing the command to the command register is controlled by
DC. A dummy read is also required before the first actual display data read for 8080-series interface.
Please refer Figure 7-1.
c) 3-lines Serial Peripheral Interface
Solomon Systech
Mar 2008 P 24/82
Rev 1.1
SSD1298
The operation is similar to 4-lines serial peripheral interface while DC is not used. There are
altogether 9-bits will be shifted into the shift register on every ninth clock in sequence: DC bit, D7 to
D0 bit. The DC bit (first bit of the sequential data) will determine the following data byte in the shift
register is written to the Display Data RAM (DC bit = 1) or the command register (DC bit = 0).
6800 series Parallel
Interface
18/16/9/8-bits
18/16/9/8-bits
Status only
Yes
Data Read
Data Write
Command Read
Command Write
8080 series Parallel

Interface
18/16/9/8-bits
18/16/9/8-bits
Status only
Yes
MCU Serial Interface

Yes
8-bits
No
8-bits
Table 6-1 - Data bus selection modes
Figure 6-2: 3-wire SPI interface (9 bits)
Transfer
Transfer starts
Transfer starts
Transfer
CSB
SCL
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
LSB
MSB
DC
SDI
DB
7
DB
0
DC
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
LSB
MSB
DC
DB
7
DB
0
DC
Register / data
Register / data
d) 4-wire Serial Peripheral Interface (8 bits)

The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial
transfer clock line (SCL), serial input data (SDI). The serial data transfer starts at the falling edge of
CSB input and ends at the rising edge of CSB.SDC determinate the data of SDI which is register or
data.
SSD1298
Rev 1.1
P 25/82
Mar 2008
Solomon Systech
Figure 6-3: 4-wire SPI interface (8 bits)
Transfer starts
Transfer
Transfer starts
Transfer
CSB
SDC
1
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
SCK
SDI
LSB
MSB
DB
7
Register
6.2
DB
0
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
LSB
MSB
DB
7
DB
0
Data
RGB Interface
SSD1298 supports RGB interface. RGB interface unit consists of D[17:0], HSYNC, VSYNC,
DOTCLK and OE signals for display moving pictures. When the RGB interface is selected, the
display operation is synchronized with external control signals (HSYNC, VSYNC and DOTCLK).
Data is written in synchronization with the control signals when DEN is enabled for write operation
in order to avoid flicker or tearing effect while updating display data.
6.3
Address Counter (AC)

The address counter (AC) assigns address to the GDDRAM. When an address set instruction is
written into the IR, the address information is sent from the IR to the AC.
After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After
reading the data, the AC is not updated. A window address function allows for data to be written only
to a window area specified by GRAM.
6.4
Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the
RAM is 240 RGB x 320 x 18 / 8 = 172,800 bytes. For mechanical flexibility, re-mapping on both
Segment and Common outputs can be selected by software. Please refer to the command Data
Output/Scan direction for detail description.
Four pages of display data forms a RAM address block and stored in the GDDRAM. Each block will
form the fundamental units of scrolling addresses. Various types of area scrolling can be performed
by software program according to the command Set area Scroll and Set Scroll Start.
6.5
Gamma/Grayscale Voltage Generator

The grayscale voltage circuit generates a LCD driver circuit that corresponds to the grayscale levels
as specified in the grayscale gamma adjustment resister. 262,144 possible colors can be displayed
when 1 pixel = 18 bit. For details, see the gamma adjustment register.
Solomon Systech
Mar 2008 P 26/82
Rev 1.1
SSD1298
6.6
Booster and Regulator Circuit

These two functional blocks generate the voltage of VGH, VGL, VCOM levels and VLCD0~63
which are necessary for operating a TFT LCD.
6.7
Timing Generator
The timing generator generates a timing signal for the operation of internal circuit such as the internal
RAM accessing, date output timing etc.
6.8
Oscillation Circuit (OSC)

This module is an on-chip low power RC oscillator circuitry. The oscillator generates the clock for
the DC-DC voltage converter. This clock is also used in the display timing generator.
6.9
Data Latches
This block is a series of latches carrying the display signal information. These latches hold the data,
which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level.
6.10 Liquid Crystal Driver Circuit

SSD1298 consists of a 720-output source driver (S0-S719) and a 320-output gate driver (G0-G319).
The display image data is latched when 720 bits of data are inputted. The latched data control the
source driver and output drive waveforms. The gate driver for scanning gate lines outputs either VGH
or VGL level. The shift direction of 720-bit source output from the source driver can be changed by
setting the RL bit and the shift direction of gate output from the gate driver can be changed by setting
the TB bit. The scan mode by the gate driver can be changed by setting the SM bit. Sets the gate
driver pin arrangement in combination with the TB bit to select the operimal scan mode for the
module.
SSD1298
Rev 1.1
P 27/82
Mar 2008
Solomon Systech
COMMAND TABLE
Table 7-1 - Command Table
Reg#
R
SR
R00h
R01h
Register
Index
Status Read
Oscillation Start
R/W D/C IB15 IB14 IB13 IB12 IB11 IB10

0
1
0
0
0
1
(0000h)
Driver output
control
(3B3Fh)
R02h
LCD drive AC
control
R03h
R07h
R0Bh
R0Ch
IB5
IB4
IB3
IB2
IB1
IB0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
L7
L6
L5
L4
L3
L2
L1
L0
0
OSCE
N
RL
REV
GD
BGR
SM
TB
MUX8
MUX7
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
FLD
ENWS
B/C
EOR
WSMD
NW7
NW6
NW5
NW4
NW3
NW2
NW1
NW0
DCT3
DCT2
DCT1
DCT0
BT2
BT1
BT0
DC3
DC2
DC1
DC0
AP2
AP1
AP0
0
D0
(5308h)
Power control (2)
IB6
(0000h)
Frame cycle control
IB7
All GAMAS[2:0] setting

8 color (6A64h)
Display control
IB8
(0000h)
Power control (1)
IB9
(0004h)
PT1
PT0
VLE2
VLE1
SPT
GON
DTE
CM
D1
NO1
NO0
SDT1
SDT0
EQ2
EQ1
EQ0
DIV1
DIV0
SDIV
SRTN
RTN3
RTN2
RTN1
RTN0
VRC2
VRC1
VRC0
R0Dh
Power control (3)
VRH3
VRH2
VRH1
VRH0
R0Eh
Power control (4)
VCOMG
VDV4
VDV3
VDV2
VDV1
VDV0
R0Fh
Gate scan start

position
SCN8
SCN7
SCN6
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
SLP
(0000h)
R10h
R11h
R15h
Sleep mode
VS mode
DFM1
DFM0
0
0
0
0
0
0
0
0
0
0
(0001h)
Entry mode
(6830h)
Entry mode
(0000h)
Solomon Systech
Nosync
DMode
TY1
TY0
ID1
ID0
AM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Denmode WMode
Mar 2008 P 28/82
INVDOT INVDEN INVHS
Rev 1.1
INVVS
SSD1298
(continued)
Reg#
R1Eh
R22h
R23h
Register
R/W D/C IB15 IB14 IB13 IB12 IB11 IB10
R28h
R29h
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
R41h
R49h
R4Ah
R4Eh
VCM0
WMG3
WMG2
WMG1
WMG0
WMR3
WMR2
WMR1
WMR0
WMG5
WMG4
RAM write data

mask (2)
0
0
Frame Frequency
1
1
(8000h)
Data[17:0] mapping depends on the interface setting
WMB5
WMB4
WMB3
WMB2
WMB1
WMB0
OSC3
OSC2
OSC1
OSC0
VCOM OTP
(000Ah)
VCOM OTP
(80C0h)
control (1)
1
1
1
1
1
1
1
1
1
1
PKP12
PKP11
PKP10
PKP02
PKP01
PKP00
PKP32
PKP31
PKP30
PKP22
PKP21
PKP20
PKP52
PKP51
PKP50
PKP42
PKP41
PKP40
PRP12
PRP11
PRP10
PRP02
PRP01
PRP00
PKN12
PKN11
PKN10
PKN02
PKN01
PKN00
PKN32
PKN31
PKN30
PKN22
PKN21
PKN20
PKN52
PKN51
PKN50
PKN42
PKN41
PKN40
PRN12
PRN11
PRN10
PRN02
PRN01
PRN00
VRP14
VRP13
VRP12
VRP11
VRP10
VRP03
VRP02
VRP01
VRP00
control (10)
0
0
0
0
0
0
0
0
0
0
VRN14
VRN13
VRN12
VRN11
VRN10
VRN03
VRN02
VRN01
VRN00
Vertical scroll
control (1)
VL18
VL17
VL16
VL15
VL14
VL13
VL12
VL11
VL10
VL28
VL27
VL26
VL25
VL24
VL23
VL22
VL21
VL20
HEA7
HEA6
HEA5
HEA4
HEA3
HEA2
HEA1
HEA0
HSA7
HSA6
HSA5
HSA4
HSA3
HSA2
HSA1
HSA0
VSA8
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
VEA8
VEA7
VEA6
VEA5
VEA4
VEA3
VEA2
VEA1
VEA0
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
SS28
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
SE28
SE27
SE26
SE25
SE24
SE23
SE22
SE21
SE20
control (2)
control (3)
control (4)
control (5)
control (6)
control (7)
control (8)
control (9)
Vertical scroll
control (2)
Horizontal RAM
address position
Vertical RAM
address start
position
Vertical RAM
address end
position
First window start
(0000h)
First window end
(013Fh)
Second window
start
Second window end
(013Fh)
Set GDDRAM X
address counter
Set GDDRAM Y
address counter
(0000h)
Note:
IB0
VCM1
WMR4
(0000h)
R4Fh
IB1
VCM2
(0000h)
R4Bh
IB2
VCM3
WMR5
(013Fh)
R48h
IB3
VCM4
(0000h)
R46h
IB4
VCM5
(EF00h)
R45h
IB5
RAM write data

mask (1)
(0000h)
R44h
IB6
nOTP
RAM data read
RAM data write
(0000h)
R42h
IB7
(0000h)
R25h
IB8
1
1
1
(0000h)
R24h
IB9
0
0
1
Power control (5)
XAD7
XAD6
XAD5
XAD4
XAD3
XAD2
XAD1
XAD0
YAD8
YAD7
YAD6
YAD5
YAD4
YAD3
YAD2
YAD1
YAD0
In R01h, bits REV, BGR, TB, RL, CM will override the corresponding hardware pins settings.
Setting R28h as 0x0006 is required before setting R25h and R29h registers.
SSD1298
Rev 1.1
P 29/82
Mar 2008
Solomon Systech
COMMAND DESCRIPTION
Index (IR)
R/W
W
DC
0
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
ID7
IB6
ID6
IB5
ID5
IB4
ID4
IB3
ID3
IB2
ID2
IB1
ID1
IB0
ID0
The index instruction specifies the RAM control indexes (R00h to RFFh). It sets the register number in the range of
00000000 to 11111111 in binary form. But do not access to Index register and instruction bits which do not have its
own index register.
Device Code Read (R00h)

R/W
R
DC
1
IB15
1
IB14
0
IB13
0
IB12
1
IB11
1
IB10
0
IB9
0
IB8
1
IB7
1
IB6
0
IB5
0
IB4
1
IB3
1
IB2
0
IB1
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
1
If this register is read forcibly, 8999h is read.
Oscillator (R00h) (POR = 0000h)

R/W
DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB0
OSCEN
0
OSCEN: The oscillator will be turned on when OSCEN = 1, off when OSCEN = 0.
Driver Output Control (R01h) (POR = 3B3Fh)

R/W
DC
W
1
POR
IB15
0
0
IB14
RL
0
IB13
REV
1
IB12
GD
1
IB11
BGR
1
IB10
SM
0
IB9
TB
1
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
1
0
0
1
1
1
1
1
1
REV: Displays all character and graphics display sections with reversal when REV = 1. Since the grayscale level can
be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is
indicated below.
REV
0
1
RGB data
00000H
:
3FFFFH
00000H
:
3FFFFH
Source Output level

Vcom = L
V63
:
V0
V0
:
V63
Vcom = H
V0
:
V63
V63
:
V0
GD: Selects the 1st output Gate

GD = 0, G0 is 1st output Gate, Gate sequence G0, G1, G2, G3, , G318, G319
GD = 1, G1 is 1st output Gate, Gate sequence G1, G0, G3, G2, , G319, G318
BGR: Selects the order from RGB to BGR in writing 18-bit pixel data in the GDDRAM.
When BGR = 0 <R><G> color is assigned from S0.
When BGR = 1 <G><R> color is assigned from S0.
Solomon Systech
Mar 2008 P 30/82
Rev 1.1
SSD1298
SM: Change scanning order of gate driver.

SM
0
1
Gate scan squence (GD=0)

G0, G1, G2, G3G219 (left and right gate interlaced)
G0, G2, G318, G1, G3, G319
See Scan mode setting on next page.

TB: Selects the output shift direction of the gate driver.
When TB = 1, G0 shifts to G319.
When TB = 0, G319 shifts to G0.
RL: Selects the output shift direction of the source driver.
When RL = 1, S0 shifts to S719 and <R><G> color is assigned from S0.
When RL = 0, S719 shifts to S0 and <R><G> color is assigned from S719.
Set RL bit and BGR bit when changing the dot order of R, G and B. RL setting will be ignored when display with RAM
(Dmode[1:0] = 00).
MUX[8:0]: Specify number of lines for the LCD driver. MUX[8:0] settings cannot exceed 319.
Remark: When using the partial display, the output for non-display area will be minimum voltage.
SSD1298
Rev 1.1
P 31/82
Mar 2008
Solomon Systech
GD=0, G0 is the 1st gate output channel, gate output sequence is G0, G1, G2, G3, , G318, G319.
SM = 0
SM = 1
G0
G2
G4
G1
G3
G5
G0
G2
G316
G318
TB = 1
RL = 1
G1
G3
G316
G318
G317
G319
G317
G319
S0
S0
S719
G1
G3
G5
G0
G2
G4
S719
G0
G2
G316
G318
G1
G3
TB = 0
RL = 1
G316
G318
G317
G319
G317
G319
S0
S0
S719
G1
G3
G5
G0
G2
G4
S719
G0
G2
G316
G318
TB = 1
RL = 0
G1
G3
G316
G318
S0
TB = 0
RL = 0
G317
G319
G317
G319
S0
S719
G1
G3
G5
G0
G2
G4
S719
G0
G2
G316
G318
G1
G3
G316
G318
S0
Solomon Systech
G317
G319
G317
G319
S719
S0
S719
Mar 2008 P 32/82
Rev 1.1
SSD1298
GD=1, G1 is the 1st gate output channel, gate output sequence is G1, G0, G3, G2, , G319, G318.
SM = 0
SM = 1
G1
G3
G1
G3
G5
G0
G2
G4
G317
G319
TB = 1
RL = 1
G0
G2
G317
G319
G316
G318
S0
G316
G318
S0
S719
S719
G1
G3
G1
G3
G5
G0
G2
G4
G317
G319
G0
G2
TB = 0
RL = 1
G317
G319
G316
G318
S0
G316
G318
S719
S0
S719
G1
G3
G1
G3
G5
G0
G2
G4
G317
G319
TB = 1
RL = 0
G0
G2
G317
G319
G316
G318
S0
G316
G318
S0
S719
S719
G1
G3
G5
G0
G2
G4
G1
G3
G317
G319
G0
G2
TB = 0
RL = 0
G316
G318
G317
G319
S0
SSD1298
Rev 1.1
P 33/82
S719
Mar 2008
G316
G318
S0
S719
Solomon Systech
LCD-Driving-Waveform Control (R02h) (POR = 0000h)

R/W
DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12 IB11 IB10

FLD ENWS B/C
0
0
0
IB9
IB8
IB7
EOR WSMD NW7
0
0
0
IB6
NW6
0
IB5
NW5
0
IB4
NW4
0
IB3
NW3
0
IB2
NW2
0
IB1
NW1
0
IB0
NW0
0
FLD: Set display in interlace drive mode to protect from flicker. It splits one frame into 3 fields and drive.
When FLD = 1, it is 3 field driving, which also limit VBP = 1.
When FLD = 0, it is normal driving.
The following figure shows the gate selection when the 3-field invension is enabled and the output waveform of the 3field interlaced driving.
Table 8-1 - 3-field interlace driving
TB = 1
Gate
G0
G1
G2
G3
G4
G317
G318
G319
FLD = 0
X
X
X
X
X
X
X
X
X
X
X
FLD = 1
X
TB = 0
Gate
G319
G318
G317
G316
G315
G2
G1
G0
FLD = 0
X
X
X
X
X
X
X
x
X
X
X
FLD = 1
X
X
Figure 8-1 - gate output timing in 3-field interlacing driving

1 frame
Field 1
Blank period
Field 2
Field 3
Field 1
AC Polarity
G0
G1
G2
G3
G4
G5
G3n +1
G3n +2
G3n +3
Solomon Systech
Mar 2008 P 34/82
Rev 1.1
SSD1298
B/C: Select the liquid crystal drive waveform VCOM.

When B/C = 0, frame inversion of the LCD driving signal is enabled.
When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[7:0]+1.
EOR: When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for
alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven
and the N-lines.
NW[7:0]: Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). N-line is equal to
NW[7:0]+1.
Figure 8-2 - Line Inversion AC Driver
N Frame
Back porch
1
N+1 Frame
Front porch
322
335
336
Back porch
1
Front porch
3
322
335
336
Frame Inversion
320 line drive
N Frame
Back porch
1
N+1 Frame
Front porch
322
335
336
Back porch
1
Front porch
3
322
335
336
Line Inversion
320 line drive
SSD1298
Rev 1.1
P 35/82
Mar 2008
Solomon Systech
ENWS: When ENWS = 1, it enables WSYNC output pin. Mode1 or Mode2 is selected by WSMD. When ENWS =
0(POR), it disables WSYNC feature, the WSYNC output pin will be high-impedance.
WSYNC
/CS
D/C
MPU
/WR
SSD1298
D[17:0]
16
WSMD = 0 is mode1, the waveform of WSYNC output will be:
tn
tu
WSYNC
100%
Memory
Access
0%
Fast write MCU

Slow write MCU
SSD1298 displaying memory
tn is the time when there is No Update of LCD screen from on-chip ram content.
tu is the time when the LCD screen is updating based on on-chip ram content.
e.g. fosc = 510KHz, for 320mux, tn = 282us (6 lines), tu =15.06ms (320 lines)
WSMD = 1 is mode2, the waveform of WSYNC output will be:
WSYNC
0
m-1
mux line read
For fast write MCU: MCU should start to write new frame of ram data just after rising edge of long WSYNC pulse and
should be finished well before the rising edge of the next long WSYNC pulse.
e.g. 5MHz 8 bit parallel write cycle for 18 bit color depth, or 3MHz 8 bit parallel write cycle for 16 bit color depth.
For slow write MCU (Half the write speed of fast write): MCU should start to write new frame ram data after the rising
edge of the first short WSYNC pulse and must be finished within 2 frames time.
e.g. 2.5MHz 8 bit parallel write cycle for 18 bit color depth.
* Usually, mode2 is for slower MCU, while mode1 is for fast MCU.
Solomon Systech
Mar 2008 P 36/82
Rev 1.1
SSD1298
Power control 1 (R03h) (POR = 6864h)

R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11

DCT3 DCT2 DCT1 DCT0 BT2
0
1
1
0
1
IB10
BT1
0
IB9
BT0
0
IB8
0
0
IB7
DC3
0
IB6
DC2
1
IB5
DC1
1
IB4
DC0
0
IB3
AP2
0
IB2
AP1
1
IB1
AP0
0
IB0
0
0
DCT[3:0]: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
DCT3 DCT2 DCT1 DCT0
Step-up cycle
0
0
0
0
Fline 24
0
0
0
1
Fline 16
0
0
1
0
Fline 12
0
0
1
1
Fline 8
0
1
0
0
Fline 6
0
1
0
1
Fline 5
0
1
1
0
Fline 4
0
1
1
1
Fline 3
1
0
0
0
Fline 2
1
0
0
1
Fline 1
1
0
1
0
fosc / 4
1
0
1
1
fosc / 6
1
1
0
0
fosc / 8
1
1
0
1
fosc / 10
1
1
1
0
fosc / 12
1
1
1
1
fosc / 16
* Fline = Line frequency
fosc = Internal oscillator frequency (~510KHz)
BT[2:0]: Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply
voltage to be used.
BT2
0
0
0
0
1
1
1
1
SSD1298
BT1
0
0
1
1
0
0
1
1
BT0
0
1
0
1
0
1
0
1
Rev 1.1
VGH output
3 x VCIX2
3 x VCIX2
3 x VCIX2
2 x VCIX2 + VCI
2 x VCIX2 + VCI
2 x VCIX2 + VCI
2 x VCIX2
2 x VCIX2
P 37/82
Mar 2008
VGL output
-(VGH) + VCI
-(VGH) + VCIX2
-(VCIX2)
-(VGH)
-(VGH) + VCI
-(VGH) + VCix2
-(VGH)
-(VGH) + VCI
VGH booster ratio

+6
+6
+6
+5
+5
+5
+4
+4
VGL booster ratio

-5
-4
-2
-5
-4
-3
-4
-3
Solomon Systech
DC[3:0]: Set the step-up cycle of the step-up circuit for 262k-color mode (CM = VSS). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
DC3 DC2 DC1 DC0

Step-up cycle
0
0
0
0
Fline 24
0
0
0
1
Fline 16
0
0
1
0
Fline 12
0
0
1
1
Fline 8
0
1
0
0
Fline 6
0
1
0
1
Fline 5
0
1
1
0
Fline 4
0
1
1
1
Fline 3
1
0
0
0
Fline 2
1
0
0
1
Fline 1
1
0
1
0
fosc / 4
1
0
1
1
fosc / 6
1
1
0
0
fosc / 8
1
1
0
1
fosc / 10
1
1
1
0
fosc / 12
1
1
1
1
fosc / 16
* Fline = Line frequency
fosc = Internal oscillator frequency (~510KHz)
AP[2:0]: Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When
the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current
taking into account the power consumption. During times when there is no display, such as when the system is in a sleep
mode.
AP2
0
0
0
0
1
1
1
1
Solomon Systech
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Op-amp power
Least
Small
Small to medium
Medium
Medium to large
Large
Large to Maximum
Maximum
Mar 2008 P 38/82
Rev 1.1
SSD1298
Display Control (R07h) (POR = 0000h)

R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
PT1
0
IB11
PT0
0
IB10
VLE2
0
IB9
IB8
VLE1 SPT
0
0
IB7
0
0
IB6
0
0
IB5
IB4
GON DTE
0
0
IB3
CM
0
IB2
0
0
IB1
D1
0
IB0
D0
0
PT[1:0]: Normalize the source outputs when non-displayed area of the partial display is driven.
VLE[2:1]: When VLE1 = 1 or VLE2 = 1, a vertical scroll is performed in the 1st screen by taking data VL17-0 in R41h
register. When VLE1 = 1 and VLE2 = 1, a vertical scroll is performed in the 1st and 2nd screen by VL1[8:0] and VL2[8:0]
respectively.
SPT: When SPT = 1, the 2-division LCD drive is performed.
CM: 8-color mode setting.
When CM = 1, 8-color mode is selected.
When CM = 0, 8-color mode is disable.
GON: Gate off level becomes VGH when GON = 0.
DTE: When GON = 1 and DTE = 0, all gate outputs become VGL. When GON = 1 and DTE = 1, selected gate
wire becomes VGH, and non-selected gate wires become VGL.
D[1:0]: Display is on when D1 = 1 and off when D1 = 0. When off, the display data remains in the GDDRAM, and
can be displayed instantly by setting D1 = 1. When D1= 0, the display is off with all of the source outputs set to the
GND level. Because of this, the driver can control the charging current for the LCD with AC driving. When D[1:0] =
01, the internal display is performed although the display is off. When D[1:0] = 00, the internal display operation
halts and the display is off. Control the display on/off while control GON and DTE.
GON
DTE
D1
D0
0
0
1
0
0
0
0
0
0
0
1
1
Internal
Display
Operation
Halt
Operation
Operation
Operation
Operation
Source output
Gate output
GND
GND
GND
Grayscale level
output
VGH
VGH
VGOFFL
VGOFFL
Selected gate line: VGH
Non-selected gate line:
VGOFFL
Grayscale level
output
Frame Cycle Control (R0Bh) (POR = 5308h)

R/W
DC
W
1
POR
IB15
NO1
0
IB14 IB13 IB12 IB11

NO0 SDT1 SDT0
0
1
0
1
0
IB10
EQ2
0
IB9
EQ1
1
IB8
EQ0
1
IB7
DIV1
0
IB6
IB5
IB4
IB3
IB2
IB1
IB0
DIV0 SDIV SRTN RTN3 RTN2 RTN1 RTN0
0
0
0
1
0
0
0
NO[1:0]: Sets amount of non-overlap of the gate output.

NO1
0
0
1
1
NO0
0
1
0
1
1 Line period
Amount of non-overlap
reserved
1 clock cycle (POR)
2 clock cycle
3 clock cycle
1 Line period
Gn
Gn+1
SSD1298
Rev 1.1
Non-overlap period
P 39/82
Mar 2008
Solomon Systech
SDT[1:0]: Set delay amount from the gate output signal falling edge of the source outputs.
SDT1
0
0
1
1
SDT0
0
1
0
1
Delay amount of the source output

0 clock cycle
1 clock cycle (POR)
2 clock cycle
3 clock cycle
EQ[2:0]: Sets the equalizing period.

EQ2
0
0
0
0
1
1
1
1
EQ1
0
0
1
1
0
0
1
1
EQ0
0
1
0
1
0
1
0
1
1 Line period
EQ period
No EQ
2 clock cycle
3 clock cycle
4 clock cycle
5 clock cycle
6 clock cycle
7 clock cycle
8 clock cycle
1 Line period
Gn
Sn
EQ
Delay amount of
the source output
Equalizing
period
DIV[1:0]: Set the division ratio of clocks for internal operation. Internal operations are driven by clocks which
frequency is divided according to the DIV1-0 setting.
DIV1
0
0
1
1
DIV0
0
1
0
1
Division Ratio
1
2
4
8
* fosc = internal oscillator frequency, ~510kHz

SDIV: When SDIV = 1, DIV1-0 value will be count. When SDIV = 0, DIV1-0 value will be auto determined.
SRTN: When SRTN =1, RTN3-0 value will be count. When SRTN = 0, RTN3-0 value will be auto determined.
RTN[3:0]: Set the no. of clocks in each line. The total number will be the decimal value of RTN3-0 plus 16. e.g. if
RTN3-0 = 1010h, the total number of clocks in each line = 10 +16 = 26 clocks.
Solomon Systech
Mar 2008 P 40/82
Rev 1.1
SSD1298
Frame frequency calculation

For DMode[1:0] = 00
Frame _ frequency =
where
Fosc
div (rtn + 16) (mux + vbp + vfp + 3)
Fosc = internal oscillator frequency

div = Division ratio determined by DIV[1:0]
rtn = RTN[3:0]
mux = MUX[8:0]
vbp = VBP[7:0]
vfp = VFT[7:0]
for default values of SSD1298

Fosc = ~510KHz, DIV[1:0] = 00, RTN[3:0] = 8, MUX[8:0] = 319, VBP[7:0] = 3, VFP[7:0] = 1,
Frame frequency =
510 K
510 K
=
= 65 Hz
1 (8 + 16) (319 + 3 + 1 + 3) 1 24 326
Power Control 2 (R0Ch) (POR = 0004h)

R/W DC
W
1
POR
IB15 IB14
0
0
0
0
IB13
0
0
IB12 IB11
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
IB1
IB0
VRC2 VRC1 VRC0
1
0
0
VRC[2:0]: Adjust VCIX2 output voltage. The adjusted level is indicated in the chart below VRC2-0 setting.
VRC2 VRC1 VRC0
VCIX2 voltage
0
0
0
5.1V
0
0
1
5.3V
0
1
0
5.5V
0
1
1
5.7V
1
0
0
5.9V
1
0
1
6.1V
1
1
0
Reserve
1
1
1
Reserve
Note: The above setting is valid when VCI has high enough voltage supply for boosting up the required voltage.
The above setting is assumed 100% booster efficiency. Please refer to DC Characteristics for detail.
SSD1298
Rev 1.1
P 41/82
Mar 2008
Solomon Systech
Power Control 3 (R0Dh) (POR = 0009h)

R/W DC
W
1
POR*
IB15 IB14
0
0
0
0
IB13
0
0
IB12 IB11
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
IB2
IB1
IB0
VRH3 VRH2 VRH1 VRH0
1
0
0
1
VRH[3:0]: Set amplitude magnification of VLCD63. These bits amplify the VLCD63 voltage 1.78 to 3.00. times the Vref
voltage set by VRH[3:0].
VRH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VRH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VRH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VRH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VLCD63 Voltage
Vref x 2.810
Vref x 2.900
Vref x 3.000
Vref x 1.780
Vref x 1.850
Vref x 1.930
Vref x 2.020
Vref x 2.090
Vref x 2.165
Vref x 2.245
Vref x 2.335
Vref x 2.400
Vref x 2.500
Vref x 2.570
Vref x 2.645
Vref x 2.725
*Vref is the internal reference voltage equals to 2.0V.

Power Control 4 (R0Eh) (POR = 3200h)
R/W DC
W
1
POR*
IB15 IB14 IB13 IB12 IB11 IB10

IB9
IB8
0
0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0
0
0
1
1
0
0
1
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
0
0
VcomG: When VcomG = 1, it is possible to set output voltage of VcomL to any level, and the instruction (VDV4-0)
becomes available. When VcomG = 0, VcomL output is fixed to Hi-z level, VCIM output for VcomL power supply
stops, and the instruction (VDV4-0) becomes unavailable. Set VcomG according to the sequence of power supply setting
flow as it relates with power supply operating sequence.
VDV[4:0]: Set the alternating amplitudes of Vcom at the Vcom alternating drive. These bits amplify 0.6 to 1.23 times
the VLCD63 voltage. When VcomG = 0, the settings become invalid. External voltage at VcomR is referenced when
VDV = 01111.
VCOML = 0.9475*VCOMH - VCOMA
VDV4
0
0
0
VDV3
0
0
0
VDV1
0
0
1
VDV0
0
1
0
1
1
VDV2
0
0
0
:
:
:
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
:
:
:
1
1
1
0
1
1
1
0
1
Vcom Amplitude
VLCD63 x 0.60
VLCD63 x 0.63
VLCD63 x 0.66
:
Step = 0.03
:
VLCD63 x 0.99
VLCD63 x 1.02
Reference from
external variable
resistor
VLCD63 x 1.05
VLCD63 x 1.08
:
Step = 0.03
:
VLCD63 x 1.20
VLCD63 x 1.23
Reserved
Reserved
Note: Vcom amplitude < 6V
Solomon Systech
Mar 2008 P 42/82
Rev 1.1
SSD1298
Gate Scan Position (R0Fh) (POR = 0000h)

R/W DC
W
1
POR

0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0
0
0
0
0
0
0
0
0
0
SCN[8:0]: Set the scanning starting position of the gate driver. The valid range is from 0 to 319.
1st line of
data
G0
G0
1st line of
data
G29
SCN8-0
= 000000000
SCN8-0
= 000011101
G319
G319
Sleep mode (R10h) (POR = 0001h)

R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
SLP
1
SLP: Sleep mode enable bit. In the sleep mode, the internal display operations are halted except the R-C oscillator to
reduce current consumption. No change in the GDDRAM data or instructions during the sleep mode is made, although it
is retained.
When SLP = 1, the driver enters into the sleep mode.
When SLP = 0, the driver leaves the sleep mode.
Entry Mode (R11h) (POR = 6230h)

R/W DC
IB15
IB14 IB13
W
1 VSMode DFM1 DFM0
POR
0
1
1
IB12
0
0
IB11
IB10
IB9
IB8
DenMode Wmode Nosync Dmode
0
0
1
0
IB7
TY1
0
IB6
TY0
0
IB5
ID1
1
IB4
ID0
1
IB3
AM
0
IB2
0
0
IB1
0
0
IB0
0
0
VSMode: When VSMode = 1 at DMode[1:0] = 00, the frame frequency will be dependent on VSYNC.
VSYNC
/CS
D/C
MPU
/WR
SSD1298
D[17:0]
16
In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to
the internal RAM at faster than the calculated minimum speed (internal display oerpation speed + buffer), it becomes
possible to rewrite the moving picture data without flickering the display and display a moving picture via system
interface.
The display operation is performed in synchronization with the internal clock signal generated from the internal
oscillator and the VSYNC signal. The display data is written in the internal RAM so that the SSD1298 rewrites the data
only within the moving picture area and minimize the number of data transfer required for moving picture display.
Therefore, the SSD1298 can write data via VSYNC interface in high speed with low power consumption.
SSD1298
Rev 1.1
P 43/82
Mar 2008
Solomon Systech
VSYNC
RAM data
write via
system I/F
The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more
than the values calculated from the following formulas, respectively.
Fosc [ Hz ] = Frame _ frequency * ( mux + vfp + vbp + 3 ) * ( rtn + 16 ) * ( div )
240 * mux
RAMWriteSpeed (min)[ Hz ] >
1
( vbp + mux m arg ins ) * ( rtn + 16 ) *
fosc
where
Fosc = internal oscillator frequency

div = Division ratio determined by DIV[1:0]
rtn = RTN[3:0]
mux = MUX[8:0]
vbp = VBP[7:0]
vfp = VFT[7:0]
Note: When RAM write operation is not started right after the falling edge of VSYNC, the time from the falling edge of
VSYNC until the start of RAM write operation must also be taken into account.
DFM[1:0]: Set the color display mode.
DFM1
1
1
DFM0
1
0
Color mode
65k color (POR)
262k color
DenMode:
DenMode=1 : RGB interface ignore HSYNC, VSYNC pin and HBP, VBP
DenMode=0 : RGB interface control by HSYNC, VSYNC pin and HBP, VBP
When DenMode=1, Generic mode will write each input rgb pixel into RAM buffer, the window of ram buffer to
be written defined by command R44h (define X of window)m R45h (define Y start),R46 (define Y end),
whenever the input RGB dimension is larger than the defined ram window, it wont have any effect.
WMode:
WMode=1 : Write RAM from Generic RGB data (POR, if PS:00xx)
WMode=0 : Write RAM from SPI interface
Nosync:
Nosync=1 : Dmode change immediately
Nosync=0 : Dmode change Sync with on chip frame start
Dmode:
Dmode=1 : Display engine will be clocked by on chip oscillator and ignore DOTCLK pin
Dmode=0 : Display engine will be clocked by DOTCLK pin and onchip oscillator will be off (POR, if PS:00xx)
TY[1:0]: In 262k color mode, 16 bit parallel interface, there are three types of methods in writing data into the ram,
Type A, B and C are described as below.
TY1
0
0
Solomon Systech
TY0
0
1
Writing mode
Type A
Type B
Mar 2008 P 44/82
Rev 1.1
SSD1298
Interface Color mode Cycle

st
262k Type A 1
nd
2
rd
3
st
16 bit 262k Type B 1
nd
2
st
262k Type C 1
nd
2
Remark :
SSD1298
Rev 1.1
D17
R5
B5
G5
R5
x
R5
B5
D16
R4
G4
G4
R4
x
R4
G4
D15
R3
B3
G3
R3
x
R3
B3
D14
R2
B2
G2
R2
x
R2
B2
Type C
D13
R1
B1
G1
R1
x
R1
B1
Hardware pins
D12 D11 D10 D9 D8 D7
R0 x
x
G5 G4
B0 x
x
R5 R4
G0 x
x
B5 G4
R0 x
x
G5 G4
x
x
x
B5 G4
R0 x
x
G5 G4
B0 x
x
x
x
D6
G3
R3
B3
G3
B3
G3
x
D5
G2
R2
B2
G2
B2
G2
x
D4
G1
R1
B1
G1
B1
G1
x
D3 D2 D1 D0
G0 x
x
R0 x
x
B0 x
x
G0 x
x
B0 x
x
G0 x
x
x
x
x
Don't care bits

Not connected pins
P 45/82
Mar 2008
Solomon Systech
ID[1:0]: The address counter is automatically incremented by 1, after data are written to the GDDRAM when ID[1:0] =
1. The address counter is automatically decremented by 1, after data are written to the GDDRAM when ID[1:0] = 0.
The setting of incrementing or decrementing of the address counter can be made independently in each upper and lower
bit of the address. The direction of the address when data are written to the GDDRAM is set with AM bits.
AM: Set the direction in which the address counter is updated automatically after data are written to the GDDRAM.
When AM = 0, the address counter is updated in the horizontal direction. When AM = 1, the address counter is
updated in the vertical direction. When window addresses are selected, data are written to the GDDRAM area specified
by the window addresses in the manner specified with ID1-0 and AM bits.
ID[1:0]="00
Horizontal: decrement
Vertical: decrement
ID[1:0]="01
Horizontal: increment
Vertical: decrement
ID[1:0]="10
Horizontal: decrement
Vertical: increment
ID[1:0]="11
Horizontal: increment
Vertical: increment
00,00h
00,00h
00,00h
00,00h
AM="0
Horizontal
13F,EFh
00,00h
13F,EFh
13F,EFh
00,00h
00,00h
13F,EFh
00,00h
AM="1
Vertical
13F,EFh
13F,EFh
Generic Interface Control (R15h) (POR = 0000h)

R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8
W 1
0
0
0
0
0
0
0
0
POR
0
0
0
0
0
0
0
0
13F,EFh
IB7
0
0
13F,EFh
IB6 IB5 IB4 IB3

IB2
IB1
IB0
0
0
0
INVDOT INVDEN INVHS INVVS
0
0
0
0
0
0
0
INVDOT: sets the signal polarity of DOTCLK pin. When INVDOT = 0, data is latched at positive edge of DOTCLK.
When INVDOT = 1, data is latched at negative edge of DOTCLK.
INVDEN: sets the signal polarity of DEN pin. When INVDEN = 0, DEN is active high. When INVDEN = 1, DEN is
active low.
INVHS: sets the signal polarity of HSYNC pin. When INVHS = 0, HSYNC is active low. When INVHS = 1, HSYNC is
active high.
INVVS: sets the signal polarity of VSYNC pin. When INVVS = 0, VSYNC is active low. When INVVS = 1, VSYNC is
active high.
Solomon Systech
Mar 2008 P 46/82
Rev 1.1
SSD1298
Power Control 5 (R1Eh) (POR = 0029h)

R/W DC
W
1
POR*

0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
nOTP
0
IB6
0
0
IB5
IB4
IB3
IB2
IB1
IB0
VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
1
0
1
0
0
1
nOTP: nOTP equals to 0 after power on reset and VcomH voltage equals to programmed OTP value. When nOTP set
to 1, setting of VCM[5:0] becomes valid and voltage of VcomH can be adjusted.
VCM[5:0]: Set the VcomH voltage if nOTP = 1. These bits amplify the VcomH voltage 0.35 to 0.99 times the
VLCD63 voltage. Default value is 101001 when power on reset.
VCM5
0
0
VCM4
0
0
VCM3
0
0
VCM2
0
0
VCM1
0
0
VCM0
0
1
1
1
1
1
0
1
:
:
:
1
1
1
1
1
1
VcomH
VLCD63 x 0.35
VLCD63 x 0.36
:
Step = 0.01
:
VLCD63 x 0.98
VLCD63 x 0.99
Write Data to GRAM (R22h)

R/W
W
DC
1
D[17:0]
WD[17:0] mapping depends on the interface setting
WD[17:0]: Transforms all the GDDRAM data into 18-bit, and writes the data. Format for transforming data into 18-bit
depends on the interface used. SSD1298 selects the grayscale level according to the GDDRAM data. After writing data
to GDDRAM, address is automatically updated according to AM bit and ID bit. Access to GDDRAM during stand-by
mode is not available.
Read Data from GRAM (R22h)

R/W
R
DC
1
D[17:0]
RD[17:0] mapping depends on the interface setting
RD[17:0]: Read 18-bit data from the GDDRAM. When the data is read to the microcomputer, the first-word read
immediately after the GDDRAM address setting is latched from the GDDRAM to the internal read-data latch. The data
on the data bus (DB170) becomes invalid and the second-word read is normal. When bit processing, such as a logical
operation, is performed, only one read can be processed since the latched data in the first word is used.
Frame Frequency Control (R25h) (POR = 8000h)

R/W DC IB15 IB14 IB13 IB12 IB11
W
1 OSC3 OSC2 OSC1 OSC0 0
POR*
1
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
0
0
OSC[3:0]: Set the frame frequency by OSC[3:0]

OSC[3:0]
Internal Oscillator
Frequency (Hz)
Corresponding
Frame Freq (Hz)
(other registers are at
POR value)
0000
0010
0101
1000
1010
1100
1110
SSD1298
Rev 1.1
P 47/82
Mar 2008
390K
430K
470K
510K
548K
587K
626K
50
55
60
65
70
75
80
Solomon Systech
Vcom OTP (R28h R29h)

Reg# R/W
R28h W
R29h W
DC
1
1
IB15
0
1
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
1
IB6
0
1
IB5
0
0
IB4
0
0
IB3
0
0
IB2
1
0
IB1
1
0
IB0
0
0
When OTP is access, these registers must be set accordantly.

OTP programming sequence
Step
Operation
Power up the module at VCI = 2.7V, VDDIO = 1.8V.
1
Turn on the display as normal to 65k/262k color mode (displaying a test
pattern if any).
Set nOTP to 1 (R1Eh) and optimizes VcomH by adjusting VCM[5:0]
2
(R1Eh).
3
Power down the whole module.
4
Connect a supply to the module at VCI = 2.7V, VDDIO = 1.8V
Write below commands for OTP initialization and wait for 200ms for
activate the OTP :
Index
Value
R00h
0x0001
5
R28h
0x0006
R29h
0x80C0
Connect a 14.5V supply to VGH through a current limiting resistor, see
figure below.
Write the optimized value found in Step 2 to VCM[5:0] (R1Eh) and set
6
nOTP to 1.
7
Fire the OTP by write HEX code 000Ah to register R28h.
8
Wait 500ms.
OTP complete. Power down the whole module and remove 14.5V
9
supply.
Note: nOTP must set to 0 to activate the OTP effect.
Precaution:
1. All capacitors on OTP machine should be discharged completely before placing the LCD module.
2. The OTP programming voltage should not be applied when placing and removing the LCD module.
3. The OTP programming voltage should not be applied before VDDIO/VCI.
4. After OTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before
removing the LCD module.
Solomon Systech
Mar 2008 P 48/82
Rev 1.1
SSD1298
Figure 8-3 OTP circuitry
SSD1298
VGH
+C
-
Note:
GND
14.5V
R = 1K ~ 2k ohm
C = 1uF
(built-in on the module)
GND
Gamma Control (R30h to R3Bh)

Reg# R/W DC
IB15
IB14
IB13
IB12
IB11
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
VRP
14
VRN
14
VRP
13
VRN
13
IB10
PKP
12
PKP
32
PKP
52
PRP
12
PKN
12
PKN
32
PKN
52
PRN
12
VRP
12
VRN
12
IB9
PKP
11
PKP
31
PKP
51
PRP
11
PKN
11
PKN
31
PKN
51
PRN
11
VRP
11
VRN
11
IB8
PKP
10
PKP
30
PKP
50
PRP
10
PKN
10
PKN
30
PKN
50
PRN
10
VRP
10
VRN
10
IB7
IB6
IB5
IB4
IB3
VRP
03
VRN
03
IB2
PKP
02
PKP
22
PKP
42
PRP
02
PKN
02
PKN
22
PKN
42
PRN
02
VRP
02
VRN
02
IB1
PKP
01
PKP
21
PKP
41
PRP
01
PKN
01
PKN
21
PKN
41
PRN
01
VRP
01
VRN
01
IB0
PKP
00
PKP
20
PKP
40
PRP
00
PKN
00
PKN
20
PKN
40
PRN
00
VRP
00
VRN
00
Note: please refer to table 5 for POR values.

PKP[52:00]: Gamma micro adjustment register for the positive polarity output
PRP[12:00]: Gradient adjustment register for the positive polarity output
VRP[14:00]: Adjustment register for amplification adjustment of the positive polarity output
PKN[52:00]: Gamma micro adjustment register for the negative polarity output
PRN[12:00]: Gradient adjustment register for the negative polarity output
VRN[14:00]: Adjustment register for the amplification adjustment of the negative polarity output.
(For details, see the Section 11 Gamma Adjustment Function).
SSD1298
Rev 1.1
P 49/82
Mar 2008
Solomon Systech
Vertical Scroll Control (R41h-R42h) (POR =0000h)

Reg# R/W DC
W
1
R41h
POR
W
1
R42h
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VL18 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10
0
0
0
0
0
0
0
0
0
VL28 VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20
0
0
0
0
0
0
0
0
0
VL1[8:0]: Specify scroll length at the scroll display for vertical smooth scrolling. Any raster-row from the first to 320th
can be scrolled for the number of the raster-row. After 320th raster-row is displayed, the display restarts from the first
raster-row. The display-start raster-row (VL1[8:0]) is valid when VLE1 = 1 or VLE2 = 1. The raster-row display is
fixed when VLE[2:1] = 00.
VL2[8:0]: Specify scroll length at the scroll display for vertical smooth scrolling at 2nd screen. The display-start rasterrow (VL2[8:0]) is valid when VLE1 = 1 and VLE2 = 1.
Horizontal RAM address position (R44h) (POR = EF00h)

R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11 IB10 IB9

IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
HSA[7:0]/HEA[7:0]: Specify the start/end positions of the window address in the horizontal direction by an address unit.
Data are written to the GDDRAM within the area determined by the addresses specified by HEA[7:0] and HSA[7:0].
These addresses must be set before the RAM write. In setting these bits, make sure that 00h HSA[7:0] HEA[7:0]
EFh.
Vertical RAM address position (R45h-R46h)

Reg# R/W DC
W
1
R45h
POR
W
1
R46h
POR
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
0
0
0
0
0
0
0
0
0
VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
1
0
0
1
1
1
1
1
1
VSA[8:0]/VEA[8:0]: Specify the start/end positions of the window address in the vertical direction by an address unit.
Data are written to the GRAM within the area determined by the addresses specified by VEA[8:0] and VSA[8:0]. These
addresses must be set before the RAM write. In setting these bits, make sure that 00h VSA[8:0] VEA[8:0]
13Fh.
1st Screen driving position (R48h-R49h)
Reg# R/W DC
W
1
R48h
POR
W
1
R49h
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
0
0
0
0
0
0
0
0
0
SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
1
0
0
1
1
1
1
1
1
SS1[8:0]: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the set gate
driver, i.e. the first driving Gate is G0 if SS1[8:0] = 00H
SE1[8:0]: Specify the driving end position for the first screen in a line unit. The LCD driving is performed to the set gate
driver. For instance, when SS1[8:0] = 07H and SE1[8:0] = 10H are set, the LCD driving is performed from G7 to
G16, and non-selection driving is performed for G1 to G6, G17, and others. Ensure that SS1[8:0] SE1[8:0] 13FH.
Solomon Systech
Mar 2008 P 50/82
Rev 1.1
SSD1298
2nd Screen driving position (R4Ah-R4Bh)

Reg# R/W DC
W
1
R4Ah
POR
W
1
R4Bh
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
0
0
0
0
0
0
0
0
0
SE28 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
1
0
0
1
1
1
1
1
1
SS2[8:0]: Specify the driving start position for the second screen in a line unit. The LCD driving starts from the set gate
driver. The second screen is driven when SPT = 1.
SE2[8:0]: Specify the driving end position for the second screen in a line unit. The LCD driving is performed to the set
gate driver. For instance, when SPT = 1, SS2[8:0] = 20H, and SE2[8:0] = 2FH are set, the LCD driving is
performed from G32 to G47. Ensure that SS1[8:0] SE1[8:0] ; SS2[8:0] SE2[8:0] 13FH.
RAM address set (R4Eh-R4Fh)
Reg# R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9
W
1
0
0
0
0
0
0
0
R4Eh
POR
0
0
0
0
0
0
0
W
1
0
0
0
0
0
0
0
R4Fh
POR
0
0
0
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0
0
0
0
0
0
0
0
0
0
YAD8 YAD7 YAD6 YAD5 YAD4 YAD 3 YAD 2 YAD 1 YAD 0
0
0
0
0
0
0
0
0
0
XAD[7:0]: Make initial settings for the GDDRAM X address in the address counter (AC).
YAD[8:0]: Make initial settings for the GDDRAM Y address in the address counter (AC).
After GDDRAM data are written, the address counter is automatically updated according to the settings with AM, I/D
bits and setting for a new GDDRAM address is not required in the address counter. Therefore, data are written
consecutively without setting an address. The address counter is not automatically updated when data are read out from
the GDDRAM. GDDRAM address setting cannot be made during the standby mode. The address setting should be made
within the area designated with window addresses.
Optimize display performance and crosstalk mininmization (R20+R26+R27+R2E+R2F)
Reg# R/W
R20h W
R4Bh
R26h W
R27h W
R2Eh W
R2Fh W
DC
1
1
1
1
1
IB15
1
0
0
0
0
IB14
0
1
0
1
0
IB13
1
1
0
1
0
IB12
1
1
0
1
1
IB11
0
0
0
1
0
IB10
0
0
0
1
0
IB9
0
0
0
1
1
IB8
0
0
0
0
0
IB7
1
0
0
0
1
IB6
1
0
1
1
1
IB5
1
0
0
0
1
IB4
0
0
0
0
0
IB3
0
0
0
0
1
IB2
0
0
1
1
0
IB1
1
0
0
0
1
IB0
1
0
0
1
1
R20h is to adjust Internal Vcom strength

R26h is to adjust Internal Bandgap strength
R27h is to adjust Internal VCOMH/VCOML timing
R2Eh is to adjust VCOM charge sharing time
R2Fh is to adjust Ram speed
SSD1298
Rev 1.1
P 51/82
Mar 2008
Solomon Systech
Window Address Function

The window address function enables writing display data sequentially in a window address area made in the internal
GDDRAM. The window address area is made by setting the horizontal address register (start: HSA7-0, end: HEA 7-0
bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and ID[1:0] bits set the transition
direction of RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables
the SSD1298 to write data including image data sequentially without taking the data wrap position into account. The
window address area must be made within the GDDRAM address map area.
Condition:
00h HSA[7:0] HEA[7:0] EFh
00h VSA[8:0] VEA[8:0] 13Fh
AM and ID[1:0] refer to R11h
GDDRAM address map
0000h
0000h
00EFh
0000h
Window address area
120x40 at middle
0000h
013Fh
00EFh
013Fh
Window address setting area:

HSA[7:0] = 3Bh; HEA[7:0] = B3h
VSA[8:0] = 8Bh; VEA[8:0] = B3h
AM = 0 and ID[1;]] = 11
Solomon Systech
Mar 2008 P 52/82
Rev 1.1
SSD1298
Partial Display and Scrolling Function

SSD1298 support schrolling and partial display function. The SSD2220 enables to selectively drive two screens at
arbitrary positions with the screen-driving position registers (R48h to R4Bh). Only the lines required to display two
screens at arbitrary positions are selectively driven.
The first screen driving position registers (R48 and R49) specifies the start line (SS18-10) and the end line (SE18-10) for
displaying the first screen. The second screen driving position register (R4A) specifies the start line (SS28-20) and the
end line (SE28-20) for displaying the second screen. The second screen control is effective when the SPT bit is set to 1.
The total number of lines driven for displaying the first and second screens must be less than the number of lines to drive
the LCD.
Scrolling Funtion: In Full screen display, schrolling could be enabled by setting VL1[8:0]
Example Register setting
Register Value
R07h
0233h
MO=0, VLE2=0, VLE1=1, SPT=0
R48h
0000h
SS1[8:0] = 0
R49h
013Fh
SE1[8:0] = 319
R4Ah
0000h
SS2[8:0] = 0
R4Bh
013Fh
SE2[8:0] = 431
R41h
0040h
VL1[8:0] = 64
R42h
0000h
VL2[8:0] = 0
RAM Content
Remark
Enable schrolling by setting VLE1=1
Set scrolling amount
Display
ROW
0
63
64
G64
127
128
191
192
255
256
319
SSD1298
Rev 1.1
P 53/82
Mar 2008
Solomon Systech
Partial display with one window:

Example Register setting
Register Value
R07h
1833h
PT=11, VLE2=0, VLE1=0, SPT=0
R48h
0040h
SS1[8:0] = 64
R49h
007Fh
SE1[8:0] = 127
R4Ah
0000h
SS2[8:0] = 0
R4Bh
013fh
SE2[8:0] = 319
R41h
0000h
VL1[8:0] = 0
R42h
0000h
VL2[8:0] = 0
RAM Content
Remark
Set PT=11 to set non-display to display data1
Define 1st display window
Display
ROW
0
Non-display area
63
64
Display area
127
128
191
192
Non-display area
255
256
319
Solomon Systech
Mar 2008 P 54/82
Rev 1.1
SSD1298
GAMMA ADJUSTMENT FUNCTION
The SSD1298 incorporates gamma adjustment function for the 262,144-color display. Gamma adjustment is
implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle
adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid
crystal panels specification.
RGB Interface
Display Data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
PKP02 PKP01 PKP00

PKP12 PKP11 PKP10
PKP22 PKP21 PKP20
Positive
polarity
register
V0
PKP32 PKP31 PKP30

PKP42 PKP41 PKP40
8-levels
Grayscale
amplifier
PRP12 PRP11 PRP10
6-bits
6-bits
64 grayscale
Control <R>
64 grayscale
Control <G>
64 grayscale
Control 
LCD Driver
LCD Driver
LCD Driver
64 levels
PKP52 PKP51 PKP50

PRP02 PRP01 PRP00
6-bits
VRP03 VRP02 VRP01 VRP00

VRP14 VRP13 VRP12 VRP11 VRP10
V63
PKN02 PKN01 PKN00
PKN12 PKN11 PKN10
PKN22 PKN21 PKN20
Negative
polarity
register
PKN32 PKN31 PKN30
PKN42 PKN41 PKN40

PKN52 PKN51 PKN50
PRN02 PRN01 PRN00
LCD
PRN12 PRN11 PRN10

VRN03 VRN02 VRN01 VRN00
VRN14 VRN13 VRN12 VRN11 VRN10
SSD1298
Rev 1.1
P 55/82
Mar 2008
Solomon Systech
9.1
Structure of Grayscale Amplifier
Below figure indicates the structure of the grayscale amplifier. It determines 8 levels (VIN0-VIN7) by the gradient
adjuster and the micro adjustment register. Also, dividing these levels with ladder resistors generates V0 to V63.
Gradient
adjustment register
VLCD63
PRP0
3
PRP1
PKP0
Amplitude
adjustment register
Micro adjustment register
PKP1
PKP2
PKP3
PKP4
3
PKP5
VRP0
VRP1
VINP0
V0
VINP1
8 to 1
selector
V1
:
V7
VINP2
8 to 1
selector
VINP3
VINP4
8 to 1
selector
Grayscale Amplifier
8 to 1
selector
Ladder resistor
V8
V19
V20
:
V42
V43
:
V54
VINP5
8 to 1
selector
V55
:
V61
8 to 1
selector
VINP6
VINP7
*
GND
Solomon Systech
V62
V63
Individual ladder resistors are used for positive and

negative polarity.
Mar 2008 P 56/82
Rev 1.1
SSD1298
Ladder resistor for negative polarity
Ladder resistor for positive polarity

VLCD63
VRP0[3:0]
0 to 30R
VRP0
5R
4R
0 to 28R
VRHP
1R
5R
RP1
RP2
RP3
RP4
RP5
RP6
RP7
1R
16R
RP23
1R
RP24
RP25
RP26
RP27
RP28
RP29
RP30
1R
0 to 28R
VRLP
4R
5R
0 to 31R
VRP1 8R
PKP0[2:0]
KVP1
KVP2
KVP3
KVP4
KVP5 8 to 1
KVP6 selector
KVP7
KVP8
PRP0[2:0]
KVP9
RP8
KVP10
RP9
KVP11
RP10 KVP12
RP11 KVP13 8 to 1
RP12 KVP14 selector
RP13 KVP15
RP14 KVP16
RP15
RP31
RP32
RP33
RP34
RP35
RP36
RP37
RP38
VRN0[3:0]
VRN0
KVP0
RP0
RP16
RP17
RP18
RP19
RP20
RP21
RP22
5R
VINP0
VINP1
PKP1[2:0]
VINP2
PKP2[2:0]
KVP17
KVP18
KVP19
KVP20
KVP21 8 to 1
KVP22 selector
KVP23
KVP24
VINP3
PKP3[2:0]
KVP25
KVP26
KVP27
KVP28
KVP29 8 to 1
KVP30 selector
KVP31
KVP32
VINP4
PKP4[2:0]
KVP33
KVP34
KVP35
KVP36
KVP37 8 to 1
KVP38 selector
KVP39
KVP40
PRP1[2:0]
KVP41
RP38 KVP42
RP40 KVP43
RP41 KVP44
RP42 KVP45 8 to 1
RP43 KVP46 selector
RP44 KVP47
RP45 KVP48
VINP5
PKP5[2:0]
RP46
VINP6
VINP7
VRP1[4:0]
RP47
5R
4R
0 to 28R
VRHN
1R
5R
KVN0
RN0
RN1
RN2
RN3
RN4
RN5
RN6
RN7
PRN0[2:0]
KVN9
RN8 KVN10
RN9 KVN11
RN10 KVN12
RN11 KVN13 8 to 1
RN12 KVN14 selector
RN13 KVN15
RN14 KVN16
RN15
1R
RN16
RN17
RN18
RN19
RN20
RN21
RN22
16R
RN23
1R
RN24
RN25
RN26
RN27
RN28
RN29
RN30
5R
1R
0 to 28R
VRLN
4R
KVN1
KVN2
KVN3
KVN4
KVN5 8 to 1
KVN6 selector
KVN7
KVN8
RN31
RN32
RN33
RN34
RN35
RN36
RN37
RN38
PKN0[2:0]
VINN1
PKN1[2:0]
VINN2
PKN2[2:0]
KVN17
KVN18
KVN19
KVN20
KVN21 8 to 1
KVN22 selector
KVN23
KVN24
VINN3
PKN3[2:0]
KVN25
KVN26
KVN27
KVN28
KVN29 8 to 1
KVN30 selector
KVN31
KVN32
VINN4
PKN4[2:0]
KVN33
KVN34
KVN35
KVN36
KVN37 8 to 1
KVN38 selector
KVN39
KVN40
PRN1[2:0]
KVN41
RN38 KVN42
RN40 KVN43
RN41 KVN44
RN42 KVN45 8 to 1
RN43 KVN46 selector
RN44 KVN47
RN45 KVN48
5R
0 to 31R
VRN1 8R
VINN0
VINN5
PKN5[2:0]
VINN6
VINN7
VRN1[4:0]
RN47
GND
SSD1298
Rev 1.1
P 57/82
Mar 2008
Solomon Systech
9.2
Gamma Adjustment Register
This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This
register can independent set up to positive/negative polarities and there are three types of register groups to adjust
gradient, amplitude, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. (Using
the same setting for Reference-value and R.G.B.) Following graphics indicates the operation of each adjusting register.
Grayscale Number
9.2.1
Micro adjustment
Grayscale Voltage
Amplitude adjustment
Grayscale Voltage
Grayscale Voltage
Gradient adjustment
Grayscale Number
Grayscale Number
Gradient adjusting register
The gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the
grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistors in
the middle of the ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator. Also, there is an
independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive.
9.2.2
Amplitude adjusting register
The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it
controls the variable resistors in the boundary of the ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale
voltage generator. Also, there is an independent resistor on the positive/negative polarities as well as the gradientadjusting resistor.
9.2.3
Micro adjusting register
The micro-adjusting register is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it
controls each reference voltage level by the 8 to 1 selector towards the 8-level reference voltage generated from the
ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting
resistors.
Solomon Systech
Mar 2008 P 58/82
Rev 1.1
SSD1298
9.3
Ladder Resistor / 8 to 1 selector
This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable
resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. The gamma registers control the
variable resistors and 8 to 1 selector resistors.
Variable Resistor
There are 3 types of the variable resistors that are for the gradient and amplitude adjustment. The resistance is set by the
resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0 / VRP(N)1) as below.
PRP(N)[0:1]
000
001
010
011
100
101
110
111
Resistance
0R
4R
8R
12R
16R
20R
24R
28R
VRP(N)0
0000
0001
0010
Resistance
0R
2R
4R
VRP(N)1
00000
00001
00010
:
Step = 1R
:
:
Step = 2R
:
1110
1111
Resistance
0R
1R
2R
28R
30R
11110
11111
30R
31R
8 to 1 selecter
In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which are generated by the ladder resistors.
There are six types of reference voltage (VIN1 to VIN6) and totally 48 divided voltages can be selected in one ladder
resistor. Following figure explains the relationship between the micro-adjusting register and the selecting voltage.
Registor
PKP[2:0]
000
001
010
011
100
101
110
111
VINP1
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
Grayscale voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
SSD1298
Postive polarity
Selected voltage
VINP2 VINP3 VINP4
KVP9 KVP17 KVP25
KVP10 KVP18 KVP26
KVP11 KVP19 KVP27
KVP12 KVP20 KVP28
KVP13 KVP21 KVP29
KVP14 KVP22 KVP30
KVP15 KVP23 KVP31
KVP16 KVP24 KVP32
VINP5
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
VINP6
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
Formula
Grayscale voltage
VINP(N)0
V22
VINP(N)1
V23
V8+(V1-V8)*(30/48)
V24
V8+(V1-V8)*(23/48)
V25
V8+(V1-V8)*(16/48)
V26
V8+(V1-V8)*(12/48)
V27
V8+(V1-V8)*(8/48)
V28
V8+(V1-V8)*(4/48)
V29
VINP(N)2
V30
V20+(V8-V20)*(22/24)
V31
V20+(V8-V20)*(20/24)
V32
V20+(V8-V20)*(18/24)
V33
V20+(V8-V20)*(16/24)
V34
V20+(V8-V20)*(14/24)
V35
V20+(V8-V20)*(12/24)
V36
V20+(V8-V20)*(10/24)
V37
V20+(V8-V20)*(8/24)
V38
V20+(V8-V20)*(6/24)
V39
V20+(V8-V20)*(4/24)
V40
V20+(V8-V20)*(2/24)
V41
VINP(N)3
V42
V43+(V20-V43)*(22/23)
V43
Rev 1.1
P 59/82
Mar 2008
Registor
PKN[2:0]
000
001
010
011
100
101
110
111
Negative polarity
Selected voltage
VINN1 VINN2 VINN3 VINN4
KVN1 KVN9 KVN17 KVN25
Formula
Grayscale voltage
V43+(V20-V43)*(21/23)
V44
V43+(V20-V43)*(20/23)
V45
V43+(V20-V43)*(19/23)
V46
V43+(V20-V43)*(18/23)
V47
V43+(V20-V43)*(17/23)
V48
V43+(V20-V43)*(16/23)
V49
V43+(V20-V43)*(15/23)
V50
V43+(V20-V43)*(14/23)
V51
V43+(V20-V43)*(13/23)
V52
V43+(V20-V43)*(12/23)
V53
V43+(V20-V43)*(11/23)
V54
V43+(V20-V43)*(10/23)
V55
V43+(V20-V43)*(9/23)
V56
V43+(V20-V43)*(8/23)
V57
V43+(V20-V43)*(7/23)
V58
V43+(V20-V43)*(6/23)
V59
V43+(V20-V43)*(5/23)
V60
V43+(V20-V43)*(4/23)
V61
V43+(V20-V43)*(3/23)
V62
V43+(V20-V43)*(2/23)
V63
V43+(V20-V43)*(1/23)
VINP(N)4
VINN5
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
VINN6
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
Formula
V55+(V43-V55)*(22/24)
V55+(V43-V55)*(20/24)
V55+(V43-V55)*(18/24)
V55+(V43-V55)*(16/24)
V55+(V43-V55)*(14/24)
V55+(V43-V55)*(12/24)
V55+(V43-V55)*(10/24)
V55+(V43-V55)*(8/24)
V55+(V43-V55)*(6/24)
V55+(V43-V55)*(4/24)
V55+(V43-V55)*(2/24)
VINP(N)5
V62+(V55-V62)*(44/48)
V62+(V55-V62)*(40/48)
V62+(V55-V62)*(36/48)
V62+(V55-V62)*(32/48)
V62+(V55-V62)*(25/48)
V62+(V55-V62)*(18/48)
VINP(N)6
VINP(N)7
Solomon Systech
Reference voltage of positive polarity:

Reference
Formula
Micr0-adjusting rgister
-KVP0
VLCD63 - V x VRP0 / SUMRP
PKP0[2:0] = 000
KVP1
VLCD63 - V x (VRP0 + 5R) / SUMRP
PKP0[2:0] = 001
KVP2
PKP0[2:0] = 010
KVP3
PKP0[2:0] = 011
KVP4
PKP0[2:0] = 100
KVP5
PKP0[2:0] = 101
KVP6
PKP0[2:0] = 110
KVP7
PKP0[2:0] = 111
KVP8
PKP1[2:0] = 000
KVP9
VLCD63 - V x (VRP0 + 33R + VRHP) / SUMRP
PKP1[2:0] = 001
KVP10
PKP1[2:0] = 010
KVP11
PKP1[2:0] = 011
KVP12
PKP1[2:0] = 100
KVP13
PKP1[2:0] = 101
KVP14
PKP1[2:0] = 110
KVP15
PKP1[2:0] = 111
KVP16
PKP2[2:0] = 000
KVP17
PKP2[2:0] = 001
KVP18
PKP2[2:0] = 010
KVP19
PKP2[2:0] = 011
KVP20
PKP2[2:0] = 100
KVP21
PKP2[2:0] = 101
KVP22
PKP2[2:0] = 110
KVP23
PKP2[2:0] = 111
KVP24
PKP3[2:0] = 000
KVP25
PKP3[2:0] = 001
KVP26
PKP3[2:0] = 010
KVP27
PKP3[2:0] = 011
KVP28
PKP3[2:0] = 100
KVP29
PKP3[2:0] = 101
KVP30
PKP3[2:0] = 110
KVP31
PKP3[2:0] = 111
KVP32
PKP4[2:0] = 000
KVP33
PKP4[2:0] = 001
KVP34
PKP4[2:0] = 010
KVP35
PKP4[2:0] = 011
KVP36
PKP4[2:0] = 100
KVP37
PKP4[2:0] = 101
KVP38
PKP4[2:0] = 110
KVP39
PKP4[2:0] = 111
KVP40
PKP5[2:0] = 000
KVP41
VLCD63 - V x (VRP0 + 87R + VRHP + VRLP) / SUMRP
PKP5[2:0] = 001
KVP42
PKP5[2:0] = 010
KVP43
PKP5[2:0] = 011
KVP44
PKP5[2:0] = 100
KVP45
PKP5[2:0] = 101
KVP46
PKP5[2:0] = 110
KVP47
VLCD63-V x (VRP0 + 111R + VRHP + VRLP) / SUMRP
PKP5[2:0] = 111
KVP48
-KVP49
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1
V: Voltage difference between VLCD63 and of GND.
Solomon Systech
Mar 2008 P 60/82
Reference voltage
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
Rev 1.1
SSD1298
Reference voltage of negative polarity:

Reference
Formula
Micr0-adjusting rgister
-KVN0
VLCD63 - V x VRN0 / SUMRN
PKN0[2:0] = 000
KVN1
VLCD63 - V x (VRN0 + 5R) / SUMRN
PKN0[2:0] = 001
KVN2
PKN0[2:0] = 010
KVN3
PKN0[2:0] = 011
KVN4
PKN0[2:0] = 100
KVN5
PKN0[2:0] = 101
KVN6
PKN0[2:0] = 110
KVN7
PKN0[2:0] = 111
KVN8
PKN1[2:0] = 000
KVN9
VLCD63 - V x (VRN0 + 33R + VRHN) / SUMRN
PKN1[2:0] = 001
KVN10
PKN1[2:0] = 010
KVN11
PKN1[2:0] = 011
KVN12
PKN1[2:0] = 100
KVN13
PKN1[2:0] = 101
KVN14
PKN1[2:0] = 110
KVN15
PKN1[2:0] = 111
KVN16
PKN2[2:0] = 000
KVN17
PKN2[2:0] = 001
KVN18
PKN2[2:0] = 010
KVN19
PKN2[2:0] = 011
KVN20
PKN2[2:0] = 100
KVN21
PKN2[2:0] = 101
KVN22
PKN2[2:0] = 110
KVN23
PKN2[2:0] = 111
KVN24
PKN3[2:0] = 000
KVN25
PKN3[2:0] = 001
KVN26
PKN3[2:0] = 010
KVN27
PKN3[2:0] = 011
KVN28
PKN3[2:0] = 100
KVN29
PKN3[2:0] = 101
KVN30
PKN3[2:0] = 110
KVN31
PKN3[2:0] = 111
KVN32
PKN4[2:0] = 000
KVN33
PKN4[2:0] = 001
KVN34
PKN4[2:0] = 010
KVN35
PKN4[2:0] = 011
KVN36
PKN4[2:0] = 100
KVN37
PKN4[2:0] = 101
KVN38
PKN4[2:0] = 110
KVN39
PKN4[2:0] = 111
KVN40
PKN5[2:0] = 000
KVN41
VLCD63 - V x (VRN0 + 87R + VRHN + VRLN) / SUMRN
PKN5[2:0] = 001
KVN42
PKN5[2:0] = 010
KVN43
PKN5[2:0] = 011
KVN44
PKN5[2:0] = 100
KVN45
PKN5[2:0] = 101
KVN46
PKN5[2:0] = 110
KVN47
VLCD63-V x (VRN0 + 111R + VRHN + VRLN) / SUMRN
PKN5[2:0] = 111
KVN48
-KVN49
SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1
V: Voltage difference between VLCD63 and of GND.
SSD1298
Rev 1.1
P 61/82
Mar 2008
Reference voltage
VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
Solomon Systech
10 MAXIMUM RATINGS
Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDDIO
VCI
I
TA
Tstg
Parameter
Supply Voltage
Input Voltage
Current Drain Per Pin Excluding VDDIO and
VSS
Operating Temperature
Storage Temperature
Value
-0.3 to +4.0
VSS - 0.3 to 5.0
Unit
V
V
25
mA
-40 to +85
-65 to +150
o
o
C
C
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, strong electric fields, when exposed to a MOS
device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using
insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material.
All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must
not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. It is advised that proper precautions to be taken
to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VCI and Vout be
constrained to the range VSS < VDDIO VCI < VOUT. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either
VSS or VDDIO). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during
normal operation. This device is not radiation protected.
11 DC CHARACTERISTICS
DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 1.65 to 3.6V, TA = -40 to 85C)
Symbol
Parameter
VDDIO
Power supply pin of IO pins
VCIR
Regulator power supply for

logic device
Test Condition
Recommend Operating Voltage
Possible Operating Voltage
VCI
Booster Reference Supply

Voltage Range

VGH
VCIX2
VGH
VGL
VcomH
VcomL
VLCD63
VLCD63
VOH1
VOL1
VIH1
VIL1
IOH
IOL
IOZ
Gate driver High Output

Voltage Booster efficiency
VCIX2 primary booster

efficiency
Gate driver High Output
Voltage
Gate driver Low Output
Voltage
Vcom High Output Voltage
Vcom Low Output Voltage
Max. Source Voltage
Source voltage variation
Logic High Output Voltage
Logic Low Output Voltage
Logic High Input voltage
Logic Low Input voltage
Logic High Output Current
Source
Logic Low Output Current
Drain
Logic Output Tri-state Current
Drain Source
Solomon Systech
Min
Typ
Max
Unit
1.4
3.6
2.5
3.6
2.5 or
VDDIO
whichever
is higher
3.6
88
90
82
84
83
85
18
-15
-6
VCI + 0.5
-VCIM+0.5
-2
0.9* VDDIO
0
0.8*VDDIO
0
5
-1
6
2
VDDIO
0.1*VDDIO
VDDIO
0.2*VDDIO
V
V
V
%
V
V
V
V
Vout = VDDIO-0.4V
50
Vout = 0.4V
-50
-1
No panel loading; 4x or 5x
booster; ITO for CYP, CYN,
VCIX2, VCI and VCHS = 10
Ohm
No panel loading; 6x booster;
ITO for CYP, CYN, VCIX2, VCI
and VCHS = 10 Ohm
No panel loading, ITO for CYP,
CYN, VCIX2, VCI and VCHS =
10 Ohm
Iout=-100A
Iout=100A
Mar 2008 P 62/82
Rev 1.1
SSD1298
IIL/IIH
CIN
RSON
RGON
RCON
Idp(262k)
Logic Input Current

Logic Pins Input Capacitance
Source drivers output
resistance
Gate drivers output resistance
Vcom output resistance
Display current for 262k
Idp(8 color)
Display current for 8 color

mode
Islp
Sleep mode current
Vddi1o = 1.8V, Vci =

2.8V. 5x/-5x booster
ratio. Full color current
consumption, without
panel loading
Current consumption for
8 color partial display,
without panel loading
Oscillator off, no
source/gate output, Ram
read write halt. Send
command R10-0001
(sleep mode), R00-0000
(stop osc)
-1
-
1
7.5
A
pF
500
200
Ivdd
150
500
uA
Ivci
2.5
mA
Ivdd
120
500
Ivci
mA
Ivdd
30
100
Ivci
40
200
Remark: Ivci(total) = Ivci + Ivcir
SSD1298
Rev 1.1
P 63/82
Mar 2008
Solomon Systech
12 AC CHARACTERISTICS
Table 12-1 Parallel 6800 Timing Characteristics
(TA = -40 to 85C, VDDIO = 1.4V to 3.6V )
Symbol
tcycle
tcycle
tAS
tAH
tDSW
tDHW
tACC
tOH
PWCSL
PWCSH
PWCSL
PWCSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Clock Cycle Time (read cycle)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Output Hold time
Pulse width /CS low (write cycle)
Pulse width /CS high (write cycle)
Pulse width /CS low (read cycle)
Pulse width /CS high (read cycle)
Rise time
Fall time
Min
Typ
Max
100
1000
0
0
5
5
250
100
50
50
500
500
-
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tAH
R/W
tcycle
PWCSL
CS
PWCSH
tR
tF
E
tDHW
tDSW
D0~D17(WRITE)
Valid Data
tACC
D0~D17(READ)
Valid Data
tOH
Figure 12-1 Parallel 6800-series Interface Timing Characteristics
Solomon Systech
Mar 2008 P 64/82
Rev 1.1
SSD1298
Table 12-2 Parallel 8080 Timing Characteristics
(TA = -40 to 85C, VDDIO = 1.65V to 3.6V)

Symbol
tcycle
tcycle
tAS
tAH
tDSW
tDHW
tACC
tOH
PWCSL
PWCSH
PWCSL
PWCSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Clock Cycle Time (read cycle)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Output Hold time
Pulse Width /CS low (write cycle)
Pulse Width /CS high (write cycle)
Pulse Width /CS low (read cycle)
Pulse Width /CS high (read cycle)
Rise time
Fall time
Min
Typ
Max
100
1000
0
0
5
5
250
100
50
50
500
500
-
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
D/C
tAH
tAS
PWCSL
CS
tF
PWCSH
tR
tcycle
WR
RD
tDSW
D0~D17
tDHW
Valid Data
Read Cycle
D/C
tAH
tAS
PWCSL
CS
tF
PWCSH
tR
tcycle
WR
RD
tOH
tACC
D0~D17
Valid Data
Figure 12-2 Parallel 8080-series Interface Timing Characteristics
SSD1298
Rev 1.1
P 65/82
Mar 2008
Solomon Systech
Table 12-3 - Serial Timing Characteristics

(TA = -40 to 85C, VDDIO = 1.65V to 3.6V )
Symbol
tcycle
fCLK
tAS
tAH
tCSS
tCSH
tDSW
tOHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Serial Clock Cycle Time
SPI Clock tolerance = +/- 2 ppm
Register select Setup Time
Register select Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise time
Fall time
Min
Typ
Max
77
Unit
ns
13
MHz
4
5
2
10
5
10
38
38
-
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tCSS
CS
tAH
tCSH
tcycle
tCLKL
SCK
tR
tDHW
tF
tDSW
SDI
tCLKH
Valid Data
CS
SCK
D7
SDI
D6
D5
D4
D3
D2
D1
D0
Figure 12-3 4 wire Serial Timing Characteristics
Solomon Systech
Mar 2008 P 66/82
Rev 1.1
SSD1298
Table 12-4 - RGB Timing Characteristics

(TA = -40 to 85C, VDDIO = 1.65V to 3.6V )
Symbol
fDOTCLK
tDOTCLK
tVSYS
tVSYH
tHSYS
tHSYH
Parameter
DOTCLK Frequency
DOTCLK Period
Vertical Sync Setup Time
Vertical Sync Hold Time
Horizontal Sync Setup Time
Horizontal Sync Hold Time
Min
253
30
30
30
30
Typ
2.64
379
-
Max
3.95
-
tHV
Phase difference of Sync Signal Falling Edge
176
tCLK
tCKH
tDS
tDH
tRES
DOTCLK Low Period

DOTCLK High Period
Data Setup Time
Data hold Time
Reset pulse width
126
126
40
40
10
Unit
MHz
ns
ns
ns
ns
ns
tDOT
CLK
ns
ns
ns
ns
ns
Note: External clock source must be provided to DOTCLK pin of SSD1298. The driver will not operate in absence of the clocking signal.
Figure 0-4 RGB Timing Characteristics
SSD1298
Rev 1.1
P 67/82
Mar 2008
Solomon Systech
Figure 12-5 - Power Up Sequence
Solomon Systech
Mar 2008 P 68/82
Rev 1.1
SSD1298
GDDRAM ADDRESS
TB=1
G0
G1
G2
G3
G4
.
.
.
G316
G317
G318
G319
RL=1
S0
S1
S2
S3
S4
S5
S6
S7
S8
RL=0 S719 S718 S717 S716 S715 S714 S713 S712 S711
BGR=0 R
G
B
R
G
B
R
G
B
BGR=1 B
G
R
B
G
R
B
G
R
TB=0
0000H,0000H
0000H, 0001H
0000H, 0010H
G319
0001H,0000H
0001H, 0001H
0001H, 0010H
G318
0010H,0000H
0010H, 0001H
0010H, 0010H
G317
0011H,0000H
0011H, 0001H
0011H, 0010H
G316
0100H,0000H
0100H, 0001H
0100H, 0010H
G315
.
.
.
.
.
.
.
.
.
.
.
.
013CH, 0000H
013CH, 0001H
013CH, 0010H
G3
013DH, 0000H
013DH, 0001H
013DH, 0010H
G2
G1
013EH, 0000H
013EH, 0001H
013EH, 0010H
G0
013FH, 0000H
013FH, 0001H
013FH, 0010H
Horizontal address
Remark :
SSD1298
S714 S715 S716 S717 S718 S719

S5
S4
S3
S2
S1
S0
R
G
B
R
G
B
B
G
R
B
G
R
.
.
.
0000H, 00EEH
0001H, 00EEH
0010H, 00EEH
0011H, 00EEH
0100H, 00EEH
0000H, 00EFH
0001H, 00EFH
0010H, 00EFH
0011H, 00EFH
0100H, 00EFH
.
.
.
013CH, 00EEH
013DH, 00EEH
013EH, 00EEH
013FH, 00EEH
.
.
.
013CH, 00EFH
013DH, 00EFH
013EH, 00EFH
013FH, 00EFH
238
239
Vertical
address
0
1
2
3
4
.
.
.
316
317
318
319
The address is in 00xxH,0yyyH format, where yyy is the vertical address and xx is the horizontal address
Rev 1.1
P 69/82
Mar 2008
Solomon Systech
13
INTERFACE MAPPING
13.1 Interface Setting

Table 13-1: Interface setting and data bus setting
PS3 PS2 PS1 PS0 Interface Mode
0
0
0
0
1
1
1
1
13.1.1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1

Data bus input

D[17:10], D[8:1]
D[17:10]
D[17:10], D[8:1]
D[17:10]
D[17:0]
D[17:9]
D[17:0]
D[17:9]
Data bus output

D[17:10], D[8:1]
D[8:1]
D[17:10], D[8:1]
D[8:1]
D[17:0]
D[8:0]
D[17:0]
D[8:0]
6800-series System Bus Interface
E
/CS
D/C
MPU
R/W
SSD1298
D[17:0]
18/16/9/8
Table 13-2 The Function of 6800-series parallel interface

PS3 PS2 PS1 PS0
0
Interface Mode
0
Data bus
D[17:10],
D[8:1]
D[8:1]
D[17:10]
0
D[17:0]
D[8:0]
D[17:9]
R/W
D/C
/CS
Operation
Read 8-bit command
Read 8-bit parameters or status*
Write 8-bit command
Write 16-bit display data
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
* A dummy read is required before the first actual display data read
Solomon Systech
Mar 2008 P 70/82
Rev 1.1
SSD1298
13.1.2
8080-series System Bus Interface

/RD
/CS
D/C
MPU
/WR
SSD1298
D[17:0]
18/16/9/8
Table 13-3 The Function of 8080-series parallel interface

PS3 PS2 PS1 PS0
0
Interface Mode
Data bus
0
D[17:10],
D[8:1]
D[8:1]
D[17:10]
0
D[17:0]
D[8:0]
D[17:9]
/WR
/RD
D/C
/CS
Read 8-bit command
Operation
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
* A dummy read is required before the first actual display data read
SSD1298
Rev 1.1
P 71/82
Mar 2008
Solomon Systech
13.2 Mapping for Writing an Instruction
Interface
18 bits
16 bits
9 bits
8 bits
Remark :
Cycle D17
IB15
IB15
st
1
IB15
nd
2
IB7
st
1
IB15
nd
2
IB7
x
D16
IB14
IB14
IB14
IB6
IB14
IB6
D15
IB13
IB13
IB13
IB5
IB13
IB5
D14
IB12
IB12
IB12
IB4
IB12
IB4
D13
IB11
IB11
IB11
IB3
IB11
IB3
D12
IB10
IB10
IB10
IB2
IB10
IB2
Hardware pins
D10 D9 D8 D7
IB8
x
IB7 IB6
IB8
IB7 IB6
IB8
x
IB0
x
IB8
IB0
D11
IB9
IB9
IB9
IB1
IB9
IB1
D6
IB5
IB5
D5
IB4
IB4
D4
IB3
IB3
D6
G0
G3
R3
B3
G3
B3
G3
x
G0
D5
B5
G2
R2
B2
G2
B2
G2
x
B4
D3
IB2
IB2
D2
IB1
IB1
D1
IB0
IB0
D0
x
Don't care bits

Not connected pins
13.3 Mapping for Writing Pixel Data
Interface Color mode Cycle D17

18 bits
262k
R5
st
1
R5
nd
B5
2
rd
G5
3
st
262k
1
R5
16 bits
nd
x
2
st
1
R5
nd
B5
2
65k
R4
st
1
R5
9 bits
262k
nd
G2
2
st
1
R5
nd
262k
G5
2
rd
8 bits
3
B5
st
R4
1
65k
nd
G2
2
Remark :
D16
R4
R4
B4
G4
R4
x
R4
B4
R3
R4
G1
R4
G4
B4
R3
G1
D15
R3
R3
B3
G3
R3
x
R3
B3
R2
R3
G0
R3
G3
B3
R2
G0
D14
R2
R2
B2
G2
R2
x
R2
B2
R1
R2
B5
R2
G2
B2
R1
B4
D13
R1
R1
B1
G1
R1
x
R1
B1
R0
R1
B4
R1
G1
B1
R0
B3
D12
R0
R0
B0
G0
R0
x
R0
B0
G5
R0
B3
R0
G0
B0
G5
B2
D11
G5
x
x
x
x
x
x
x
G4
G5
B2
x
x
x
G4
B1
Hardware pins
D10 D9 D8 D7
G4 G3 G2 G1
x
G5 G4
x
R5 R4
x
B5 B4
x
G5 G4
x
B5 B4
x
G5 G4
x
x
x
G3
G2 G1
G4 G3
B1 B0
x
x
x
G3
B0
D4
B4
G1
R1
B1
G1
B1
G1
x
B3
D3 D2 D1 D0
B3 B2 B1 B0
G0 x
x
R0 x
x
B0 x
x
G0 x
x
B0 x
x
G0 x
x
x
x
x
B2 B1 B0
Don't care bits

Not connected pins
13.4 Mapping for Writing Pixel Data in generic mode

Interface
Color mode Cycle D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
18-bit RGB
262k
RR5 RR4 RR3 RR2 RR1 RR0 GG5 GG4 GG3 GG2 GG1 GG0 BB5 BB4 BB3 BB2 BB1 BB0
16-bit RGB
65k
RR4 RR3 RR2 RR1 RR0 RR4 GG5 GG4 GG3 GG2 GG1 GG0 BB4 BB3 BB2 BB1 BB0 BB4
9-bit RGB
262k
st
nd
BB5 BB4 BB3 BB2 BB1 BB0 GG2 GG1 GG0
st
RR5 RR4 RR3 RR2 RR1 RR0
nd
GG5 GG4 GG3 GG2 GG1 GG0
1
2
1
6-bit RGB
262k
rd
Solomon Systech
RR5 RR4 RR3 RR2 RR1 RR0 GG5 GG4 GG3
BB5 BB4 BB3 BB2 BB1 BB0
Mar 2008 P 72/82
Rev 1.1
SSD1298
14 DISPLAY SETTING SEQUENCE

14.1 Display ON Sequence
Power supply setting
Set R07h at 0021h

GON = 1
DTE = 0
D[1:0] = 01
Set R00h at 0001h
Set R07h at 0023h

GON = 1
DTE = 0
D[1:0] = 11
Set R10h at 0000h

Exit sleep mode
Wait 30ms
Set R07h at 0033h

GON = 1
DTE = 1
D[1:0] = 11
Entry Mode setting (R11h)
LCD driver AC setting (R02h)
RAM data write (R22h)
Display ON
and start to write RAM
SSD1298
Rev 1.1
P 73/82
Mar 2008
Solomon Systech
14.2 Display OFF Sequence
Display ON
Set R07h at 0000h

Halt the operation
Set R00h at 0000h

Turn off oscillator
Set R10h at 0001h

Enter sleep mode
Remove power from VCI, then remove VDDIO, VCIR
Display OFF
VGH
VCIX2
RESB
VCI
VDDIO
Note:
1. VDDIO should be the last to fall, or VCI/VDDIO could be power off at the same time
2. If OTP is active in the application, the MTP programming voltage should be turned off and capacitors at VGH
and VCIX2 discharged before VCI/VDDIO are turned off.
Solomon Systech
Mar 2008 P 74/82
Rev 1.1
SSD1298
14.3 Sleep Mode Display Sequence
Display ON
Set R10h at 0001h
Ivci = 66uA
Set R07h at 0000h
Sleeping
Release from Sleep

Set R10h at 0000h
Display ON
SSD1298
Rev 1.1
P 75/82
Mar 2008
Solomon Systech
15 POWER SUPPLY BLOCK DIAGRAM
VCOM
VCIM
VGH
VGL
VCOMH VCOML
VLCD63
VCI
Regulator Circuit &
VCOM Generator Circuit
VCIR
Source
driver
VSS/VSSRC/
AVSS/VCHS
Booster
Circuit
CDUM1P
Gamma /
Grayscale
Voltage
Generator
CDUM1N
&
CXP
CXN
VLCD63
Regulator
Circuit
Supply Voltage
Regulator
Circuit
CYP
CYN
S0 to S719
VCIX2/G/J
Switches
Network
Data
Latches
C1P
C2P
GDDRAM
Gate Driver
C2N
C3P
OSC /
Timing
Generator
C3N
Address
Counter
G0 to G319
GTESTL, GTESTR
C1N
System Interface / Control Logic
Solomon Systech
HSYNC
DOTCLK
VSYNC
D[0-17]
DC
WR
CS
OE
PS0-3
RESB
VCORE/
VREGC
WSYNC
VDDIO
Mar 2008 P 76/82
Rev 1.1
SSD1298
16 SSD1298 OUTPUT VOLTAGE RELATIONSHIP
VGH (9~18V)
VLCD63 (max 6V)

VCOMH (max 5V)
VCI (2.5~3.6V)
VCOM amplitude
(max 6V)
VSS
VCOML
VGL (-6~ -15V)
Note: VGH-VGL<30Vp-p
SSD1298
Rev 1.1
P 77/82
Mar 2008
Solomon Systech
19Application Circuit
Figure 16-1: Booster Capacitors
CYP
CYN
CXP
CXN
C1P
C1N
C2P
C2N
C3P
C3N
+6.3V
+
6.3V
+
6.3V
+
16V
+ 16V
-
All capacitors
0.1 ~ 0.22uF (0.22uF for better
stability)
Figure 16-2 : Filtering and Charge Sharing Capacitors
VCIX2 6.3V
VCIM 6.3V
VGH
VGL
VCI
VCIP
VCORE
VCOMH
VCOML
(VLCD63)
(CDUM1P)
(CDUM1N)
Solomon Systech
16V
16V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
+
+
+
+
+
+
+
VSS
Mandatory requirement on external components for SSD1298 is 13

capacitors.
VCIX2, VCIM, VGH, VGL, VCI, VCORE, VCOMH, VCOML
C1P/C1N, C2P/C2N, C3P/C3N, CYP/CYN, CXP/CXN
Remark:
Capacitor for VCIX2 = 2.2uF
VCI should be separated with VCIP at ITO layout to provide noise free
path.
VSS should be separated with VCHS, AVSS and VSSRC at ITO layout to
provide noise free path.
All other capacitors 1.0uF ~ 2.2uF (2.2uF is preferred for better display
quality and power consumption.)
(Optional capacitors)
VLCD63, capacitors are for stability
Capacitors on CDUM1N/CDUM1P are for power saving.
Mar 2008 P 78/82
Rev 1.1
SSD1298
Figure 16-3 Panel Connection Example
240RGB x 320 TFT Panel

(Cs on Common)
320
720
SSD1298
Rev 1.1
P 79/82
S0-S719
SSD1298
MCU interface and

control
RESB
CSB
E
DC
WR
D0-D17
External component
pins
Refer to figure 3-5
Power/Ground
VCI / VSS
AVSS /IOGND
VDDIO
G0-G319
Mar 2008
Solomon Systech
Figure 16-4 - ITO and FPC connection example

Operating conditions:
System 3.6V>System VDD>1.95V or1.65V>System VDD>1.4V
Cs on common structure is used
Color filter mapping

TFT Panel
Normal white panel is used

Suggested Panel
ITO resistnce
VPP
20
10
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
(Optional)
Test Pad: TESTA
TESTB
TESTC
10
VDDIO
VCI
5
5
10
10
10
10
10
10
10
10
5
VCI
5
20
20
20
20
20
20
20
20
20
20
20
20
20
Solomon Systech
DUMMY
DUMMY
DUMMY
DUMMY
NC
NC
NC
VGH
VGH
VGH
VGH
VGH
VSS
VSS
VSS
VDDIO
VDDIO
DUMMY
DUMMY
NC
NC
NC
NC
PS0
PS1
PS2
PS3
DUMMY
DUMMY
DUMMY
RES
VSYNC
HSYNC
DOTCLK
OE
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
DUMMY
DUMMY
NC
D7
D6
D5
D4
D3
D2
D1
D0
SDO
SDI
RD
WR
DC
CSB
NC
VDDIO
VDDIO
WSYNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DUMMY
DUMMY
NC
NC
NC
DUMMY
TESTA
TESTB
TESTC
NC
DUMMY
NC
NC
NC
NC
IOGND
IOGND
IOGND
IOGND
IOGND
IOGND
IOGND
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VCIR
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VREGC
VREGC
VREGC
VREGC
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DUMMY
DUMMY
DUMMY
EXVR
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
DUMMY
DUMMY
VLCD63
DUMMY
DUMMY
DUMMY
VCOMR
DUMMY
VCIM
VCIM
VCIM
VCIX2G
VCIX2G
VCIX2G
VCIX2
VCIX2
VCIX2
VCIX2
VCIX2
VCIX2
VCIX2
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCIP
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
CYN
CYN
CYN
CYN
CYN
CYP
CYP
CYP
CYP
CYP
CXN
CXN
CXN
CXN
CXN
CXP
CXP
CXP
CXP
CXP
DUMMY
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
DUMMY
DUMMY
DUMMY
VGH
VGH
VGH
VGH
VGH
VGH
DUMMY
C3N
C3N
C3N
DUMMY
C3P
C3P
C3P
DUMMY
C1N
C1N
C1N
C1P
C1P
C1P
C2N
C2N
C2N
C2P
C2P
C2P
CSVCMN
CSVCMN
CSVCMN
CSVCMP
CSVCMP
CSVCMP
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
G0
G4
G8
G12
G16
G20
G24
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:G308
:G312
:G316
:DUMMY
:DUMMY
S1
S3
S5
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
S715
S717
S719
DUMMY
DUMMY
DUMMY
G317
G313
G309
G9
G5
G1
DUMMY
DUMMY
Mar 2008 P 80/82
Rev 1.1
SSD1298
17 PACKAGE INFORMATION
17.1 DIE TRAY DIMENSIONS
SSD1298
Rev 1.1
P 81/82
Mar 2008
Solomon Systech
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical
parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support
or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) Restriction
of Hazardous Substance (RoHS) Directive (2002/95/EC) and China standard (SJ/T11364-2006)
with control Marking Symbol
. Hazardous Substances test report is available upon requested.
http://www.solomon-systech.com
Solomon Systech
Mar 2008 P 82/82
Rev 1.1
SSD1298

SSD 1298

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

SSD 1298

Încărcat de

Drepturi de autor:

Formate disponibile

SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

Copyright 2008 Solomon Systech Limited

GENERAL DESCRIPTION ......................................................................................... 5

Gold Bump Die

DIE PAD FLOOR PLAN

Figure 4-3: Alignment Marks

Figure 4-2: Output Pad Pitch (Pad 299 - 1354)

Table 4-1: Die Information

21416 x 755 um2

Figure 4-4 - SSD1298 Pad Arrangement (Bump face up)

Table 4-2 - SSD1298 Bump Pad Coordinate (Bump Center)

Mar 2008 P 10/82

Pad Name X-pos

Pad Name X-pos

Mar 2008 P 12/82

Pad # Pad Name

Mar 2008 P 14/82

Mar 2008 P 16/82

Mar 2008 P 18/82

Table 5-1: Power Supply Pins

Negative voltage of VCI.

They are the power supply used by on chip analog

This pin provides voltage reference for internal voltage

This pin is the maximum source driver voltage.

A negative power output pin for gate driver.

External reference of internal gamma resistor

- Connect a capacitor to CDUM1N

- Connect a capacitor to CDUM1P

Vdd for core use. Connect a capacitor for stabilization

Regulator output for VCORE use.

Voltage input pin for logic I/O, connect to system VDD.

Internal regular input for logic supply : VCIR=2.5V3.3V

Mar 2008 P 20/82

Table 5-2 - Interface Logic Pins

Chip select pin for 6800/8080/SPI interface

For parallel mode, 8/9/16/18 bit interface.

Ram Write Synchronization output

Data output pin in serial interface

Display enable pin from controller. Data will be treated as dummy

Table 5-3: Mode Selection Pins

Mar 2008 P 22/82

Table 5-4: Driver Output Pins

Table 5-5: Miscellaneous Pins

These pins must be left open and cannot be connected together

BLOCK FUNCTION DESCRIPTION

Figure 6-1 Read Display Data

b) MPU Parallel 8080-series Interface

Mar 2008 P 24/82

8080 series Parallel

MCU Serial Interface

Table 6-1 - Data bus selection modes

Figure 6-2: 3-wire SPI interface (9 bits)

d) 4-wire Serial Peripheral Interface (8 bits)

Figure 6-3: 4-wire SPI interface (8 bits)

Address Counter (AC)

Graphic Display Data RAM (GDDRAM)

Gamma/Grayscale Voltage Generator

Mar 2008 P 26/82

Booster and Regulator Circuit

Oscillation Circuit (OSC)

6.10 Liquid Crystal Driver Circuit

R/W D/C IB15 IB14 IB13 IB12 IB11 IB10