15.

16.

INTERNAL EXAMINATION III

Branch: ME VLSI Design Date Time: 8.5.15 9.30 to 12.30
Semester: II
Max. Marks: 100
Sub: CP7023Reconfigurable Computing
PART A (5*2=10)
1. Mention the various interconnecting technologies used by
FPGA.
2. What is the right device to reconfigure? Justify your answer.
3. Why does general purpose computing give slow speed of
processing?
4. Define island-style FPGA.
5. What are the techniques for DFG optimizations?
6. How is synchronous dataflow differed from dynamic
streaming dataflow?
7. Briefly explain the FPGA design flow.
8. Write down the problems present in FPGA placement.
9. What are the steps involved in structural mapping?
10. Give development flow for SOPC system.

17.

18.
19.

20.

(ii).Explain the implementation and mapping of DAA into

FPGA platform.(8)
Explain in detail about for configuration bit stream
generation.(16)
(or)
(i).Write down the word length optimization models for
fixed point computation. (8)
(ii).Write short notes about partition based placement and
analytic placement.(8)
(i).What is parametric hardware generation? Explain it. (8)
(ii).How automatic compilation is carried out for
reconfiguration.(8)
(or)
What are the functions followed by operating system for
reconfigurable computing .(16)
(i).Distinguish the performance of small scale reconfigurable
systems with reconfigurable supercomputing.(8)
(ii).What are the general purpose systems that using multiple
FPGA.(8)
(or)
(i).Explain about various configuration architectures.(8)
(ii). How reconfiguration process is managed.(8)

PART B (40)
Answer all questions
11. Explain about various types of CPLDs .(16)
(or)
12. Explain the Reconfigurable Processing Fabric Architectures.
(16)

13. Explain the CORDIC architecture(processor) and its

algorithm for FPGA computing (16)
(or)
14. (i).Draw the architecture for and explain the NIOS II
processor .(8)
Faculty in charge

HOD/ECE