10EC661

USN

Sixth Semester B.E. Degree Examination, June/July 2015

Analog and Mixed Mode VLSI Design
Time: 3 hrs.

Max. Marks:100

Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

Note: Answer any FIVE full questions, selecting

atleast TWO questions from each part.
PART A
1

a. Explain briefly about DAC specifications.

b. Explain briefly about mixed signal layout issues.

a. Explain the operation of 4 bit charge scaling DAC. Mention the method which reduces the
size of the capacitor.
(10 Marks)
b. Find the output voltage for a 3 bit pipeline DAC for 3 cases : DA = 010, DB = 100 and
DC = 101 and show that the conversion time to perform all three conversions is five clock
cycles using the pipe line approach. Assume that Vref = 6V.
(10 Marks)

a. Design a 3bit flash converter, listing the values of the voltages at each resistor tap and draw
the transfer curve for Vin = 0 to 5V. Assume Vref = 5V. construct a table listing thermometer
code, and the digital output code for Vin = 2, 3.5 and 4V.
(12 Marks)
b. Explain the working of the successive approximation ADC with the help of block diagram.

(10 Marks)
(10 Marks)

(08 Marks)

a. Explain in detail about each block of a voltage comparator.

(12 Marks)
b. Discuss general level shifting and differential to single ended and single to differential
converters.
(08 Marks)
PART B

a. What is meant by decimation? Illustrate the decimal filter with block diagram.
b. Explain the principle of interpolation with block diagrams.
c. Explain implementation of band-pass and high-pass sync filters.

a. Describe CMOS process flow with neat sketches.

(10 Marks)
b. Briefly discuss implementing capacitors and resistors in a submicron CMOS process.

(05 Marks)
(05 Marks)
(10 Marks)

(10 Marks)

a. Explain with the help of circuit diagrams, the technique of making the slow rate concern in
the design of op-amp.
(10 Marks)
b. Explain fully differential op-amp.
(10 Marks)

a. Discuss how SNR of a data converter can be improved by using averaging.

(06 Marks)
b. Explain how a simple delay element can be realized using pass-transistor and clocked
CMOS logic.
(08 Marks)
c. What is the need of biasing a push pull amplifier? Explain.
(06 Marks)

*****