FLIP-FLOP D

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flip_d is
Port ( d ,r: in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end flip_d;
architecture Behavioral of flip_d is
begin
process (clk,r)
begin
if (r='1')then
q<='0';
elsif (clk'event and clk='1') then
q<= d;
end if;
end process;
end Behavioral;

FLIP-FLOP JK

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flip_jk is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
r : in STD_LOGIC;
q : out STD_LOGIC);
end flip_jk;
architecture Behavioral of flip_jk is
begin

PROCESS(r,clk)
variable TMP: std_logic;
begin
if(r='1') then
TMP:='0';
elsif(clk='1' and clk'EVENT) then
if(j='0' and k='0')then
TMP:=TMP;
elsif(j='1' and k='1')then
TMP:= not TMP;
elsif(j='0' and k='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
q<=TMP;
end PROCESS;
end behavioral;
CONTADOR_3_BITS

FORMA 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity contador is
Port ( e: in STD_LOGIC;

clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(2downto 0));
end contador;
architecture Behavioral of contador is
signal c : std_logic_VECTOR(2 downto 0);
begin
process(e,clk)
BEGIN
IF e= '0' THEN
c <= "000";
ELSIF (clk'EVENT AND clk='0')then
c <= c +1;
END IF;
q <= c;
END PROCESS;
end Behavioral;

FORMA 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_4_bits is
Port ( enable,d : in STD_LOGIC;
clk : in STD_LOGIC;
q1,q2,q3 : out STD_LOGIC);
end contador_4_bits;

architecture Behavioral of contador_4_bits is

signal clk_1,clk_2:std_logic;
begin
D_1: entity work.flip_d
port map (
d=>d,
clk=>clk,
r=>enable,
q=>clk_1
);
q1<=clk_1;
D_2: entity work.flip_d
port map (
d=>d,
clk=>clk_1,
r=>enable,
q=>clk_2
);
q2<=clk_2;
D_3: entity work.flip_d
port map (
d=>d,
clk=>clk_2,
r=>enable,
q=>q3
);
end Behavioral;

REGISTRO DE DESPLAZAMIENTO SISO

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_std.all;

entity siso is
Port ( CLR_N : in STD_LOGIC;
CLK : in STD_LOGIC;
ingreso : in std_logic;
salida : out STD_LOGIC;
aux1 : out STD_LOGIC;
aux2 : out STD_LOGIC);
end siso;
architecture taller of siso is
signal progreso: std_logic_vector(2 downto 0);
begin

process (clr_n,clk)
begin
if (clr_n ='0') then
progreso<= "000";

elsif (clk' event and clk='1') then

progreso (2)<= ingreso;
aux1 <= progreso(2);
progreso (1)<= progreso(2);
aux2 <= progreso(1);
progreso (0)<= progreso(1);
salida <= progreso(0);
end if;
end process;
end taller;