Skup Instrukcija mikroprocesora

ATxmega

Skup Instrukcija ATxmega

Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add without Carry
ADC

Rd, Rr

Add with Carry

ADIW
SUB

Rd, K
Rd, Rr

Add Immediate to Word

Subtract without Carry

SUBI
SBC

Rd, K
Rd, Rr

Subtract Immediate
Subtract with Carry

SBCI
SBIW

Rd, K
Rd, K

Subtract Immediate with Carry

Subtract Immediate from Word

AND
ANDI

Rd, Rr
Rd, K

Logical AND
Logical AND with Immediate

OR
ORI

Rd, Rr
Rd, K

Logical OR
Logical OR with Immediate

EOR

Rd, Rr

Exclusive OR

COM
NEG

Rd
Rd

Ones Complement
Twos Complement

SBR
CBR
INC

Rd, K
Rd,K
Rd

Set Bit(s) in Register

Clear Bit(s) in Register
Increment

DEC

Rd

Decrement

TST
CLR

Rd
Rd

Test for Zero or Minus

Clear Register

SER
MUL

Rd
Rd,Rr

Set Register
Multiply Unsigned

MULS

Rd,Rr

Multiply Signed

MULSU
FMUL

Rd,Rr
Rd,Rr

Multiply Signed with Unsigned

Fractional Multiply Unsigned

FMULS
FMULSU

Rd,Rr
Rd,Rr

Fractional Multiply
Fractional Multiply Signed with

DES

Unsigned
Data Encryption

Rd Rd + Rr

Z,C,N,V,S,H

Rd Rd + Rr + C

Z,C,N,V,S,H

Rd Rd + 1:Rd + K
Rd Rd - Rr

Z,C,N,V,S
Z,C,N,V,S,H

2
1

Rd Rd - K
Rd Rd - Rr - C

Z,C,N,V,S,H
Z,C,N,V,S,H

1
1

Rd Rd - K - C
Rd + 1:Rd Rd + 1:Rd - K

Z,C,N,V,S,H
Z,C,N,V,S

1
2

Rd Rd Rr
Rd Rd K

Z,N,V,S
Z,N,V,S

1
1

Rd Rd v Rr
Rd Rd v K

Z,N,V,S
Z,N,V,S

1
1

Rd RdRr

Z,N,V,S

Rd $FF - Rd
Rd $00 - Rd

Z,C,N,V,S
Z,C,N,V,S,H

1
1

Rd Rd v K
Rd Rd ($FFh - K)
Rd Rd + 1

Z,N,V,S
Z,N,V,S
Z,N,V,S

1
1
1

Rd Rd - 1

Z,N,V,S

Rd Rd Rd
Rd RdRd

Z,N,V,S
Z,N,V,S

1
1

Rd $FF
R1:R0 Rd x Rr (UU)

None
Z,C

1
2

R1:R0 Rd x Rr (SS)

Z,C

R1:R0 Rd x Rr (SU)
R1:R0 Rd x Rr<<1 (UU)

Z,C
Z,C

2
2

Signed R1:R0 Rd x Rr<<1 (SS)

R1:R0 Rd x Rr<<1 (SU)

Z,C
Z,C

2
2

if (H = 0) then

1/2

R15:R0Encrypt(R15:R0, K)
else if (H = 1) then
R15:R0Decrypt(R15:R0, K)
Branch instructions
RJMP
k

Relative Jump

IJMP

Indirect Jump to (Z)

EIJMP

PC PC + k + 1

None

PC(15:0) Z,

None

Extended Indirect Jump to (Z)

PC(21:16) 0
PC(15:0) Z,

None

PC(21:16) EIND
PC k

None

PC PC + k + 1
PC(15:0) Z,

None
None

2/3
2/3

Extended Indirect Call to (Z)

PC(21:16) 0
PC(15:0) Z,

None

call Subroutine

PC(21:16) EIND
PC k

JMP

Jump

RCALL
ICALL

Relative Call Subroutine

Indirect Call to (Z)

EICALL
CALL

RET
RETI

Subroutine Return
Interrupt Return

None

3/4

PC STACK
PC STACK

None
I

4/5
4/5

if (Rd = Rr) PC PC + 2 or 3
Rd - Rr

None
Z,C,N,V,S,H

1/2/3
1

CPSE
CP

Rd,Rr
Rd,Rr

Compare, Skip if Equal

Compare

CPC
CPI

Rd,Rr
Rd,K

Compare with Carry

Compare with Immediate

Rd - Rr - C
Rd - K

Z,C,N,V,S,H
Z,C,N,V,S,H

1
1

SBRC
SBRS

Rr, b
Rr, b

Skip if Bit in Register Cleared

Skip if Bit in Register Set

None
None

1/2/3
1/2/3

SBIC

A, b

Skip if Bit in I/O Register

if (Rr(b) = 0) PC PC + 2 or 3
if (Rr(b) = 1) PC PC + 2 or 3

if (I/O(A,b) = 0) PC PC + 2 or 3

None

2/3/4

If (I/O(A,b) =1) PC PC + 2 or 3
if (SREG(s) = 1) then PC PC + k + 1

None
None

2/3/4
1/2

Cleared
SBIS
BRBS

A, b
s, k

Skip if Bit in I/O Register Set

Branch if Status Flag Set

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Skup Instrukcija mikroprocesora

ATxmega
BRBC
BREQ
BRNE

s, k
k
k

Branch if Status Flag Cleared

Branch if Equal
Branch if Not Equal

BRCS

Branch if Carry Set

BRCC
BRSH

k
k

Branch if Carry Cleared

Branch if Same or Higher

BRLO
BRMI

k
k

Branch if Lower
Branch if Minus

BRPL
BRGE

k
k

Branch if Plus
Branch if Greater or Equal,

BRLT

Signed
Branch if Less Than, Signed

BRHS

Branch if Half Carry Flag Set

BRHC

Branch if Half Carry Flag

if (SREG(s) = 0) then PC PC + k + 1
if (Z = 1) then PC PC + k + 1
if (Z = 0) then PC PC + k + 1

None
None
None

1/2
1/2
1/2

if (C = 1) then PC PC + k + 1

None

1/2

if (C = 0) then PC PC + k + 1
if (C = 0) then PC PC + k + 1

None
None

1/2
1/2

if (C = 1) then PC PC + k + 1
if (N = 1) then PC PC + k + 1

None
None

1/2
1/2

if (N = 0) then PC PC + k + 1
if (N V= 0) then PC PC + k + 1

None
None

1/2
1/2

if (N V= 1) then PC PC + k + 1

None

1/2

if (H = 1) then PC PC + k + 1

None

1/2

if (H = 0) then PC PC + k + 1

None

1/2

if (T = 1) then PC PC + k + 1
if (T = 0) then PC PC + k + 1

None
None

1/2
1/2

if (V = 1) then PC PC + k + 1
if (V = 0) then PC PC + k + 1

None
None

1/2
1/2

if (I = 1) then PC PC + k + 1

None

1/2

if (I = 0) then PC PC + k + 1

None

1/2

Rd Rr

Rd (k)
Rd (X)

Cleared
BRTS
BRTC

k
k

Branch if T Flag Set

Branch if T Flag Cleared

BRVS
BRVC

k
k

Branch if Overflow Flag is Set

Branch if Overflow Flag is

BRIE

Cleared
Branch if Interrupt Enabled

BRID
k
Data transfer instructions
MOV
Rd, Rr

Branch if Interrupt Disabled

MOVW
LDI

Rd, Rr
Rd, K

Copy Register Pair

Load Immediate

LDS
LD

Rd, k
Rd, X

Load Direct from data space

Load Indirect

LD

Rd, X+

Load Indirect and Post-

Copy Register

Increment
LD

Rd, -X

Load Indirect and PreDecrement

None

Rd+1:Rd Rr+1:Rr
Rd K

None
None

1
1

None
None

2
1

Rd (X),

None

None

Rd (Y)
Rd (Y)

None
None

1
1

XX+1
X X - 1,
Rd (X)

LD
LD

Rd, Y
Rd, Y+

Load Indirect
Load Indirect and Post-

LD

Rd, -Y

Increment
Load Indirect and Pre-

YY+1
Y Y 1,

None

Rd, Y+q

Decrement Y
Load Indirect with

Rd (Y)
Rd (Y + q)

None

LD

Rd, Z

Displacement
Load Indirect

Rd, Z+

Load Indirect and Post-

Rd (Z)

None

LD

None

None

Rd (Z + q)

None

(k) Rd

None

(X) Rr
(X) Rr,

None
None

1
1

LDD

Increment
LD

Rd, -Z

Load Indirect and PreDecrement

LDD

Rd, Z+q

Load Indirect with

Rd (Z),
Z Z+1

Z Z - 1,
Rd (Z)

Displacement
STS

k, Rr

Store Direct to Data Space

ST
ST

X, Rr
X+, Rr

Store Indirect
Store Indirect and Post-

ST

-X, Rr

Increment
Store Indirect and Pre-

XX+1
X X - 1,

None

ST

Y, Rr

Decrement
Store Indirect

None

ST

Y+, Rr

Store Indirect and Post-

(X) Rr
(Y) Rr

None

None

(Y + q) Rr

None

(Z) Rr

None

Increment
ST

-Y, Rr

Store Indirect and PreDecrement

STD

Y+q, Rr

Store Indirect with

(Y) Rr,
YY+1

Y Y - 1,
(Y) Rr

Displacement
ST

Z, Rr

Store Indirect

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Skup Instrukcija mikroprocesora

ATxmega
ST
ST

Z+, Rr
-Z, Rr

Store Indirect and Post-

(Z) Rr,

Increment

Z Z + 1

None

Z Z - 1

None

(Z + q) Rr

None

R0 (Z)
Rd (Z)

None
None

3
3

None

R0 (RAMPZ:Z)

None

Rd (RAMPZ:Z)

None

Extended Load Program

Rd (RAMPZ:Z),

None

Memory and Post-

ZZ+1

Increment
Store Program Memory

(RAMPZ:Z) R1:R0

None

None

Store Indirect and PreDecrement

STD

Z+q,Rr

Store Indirect with

Displacement

LPM
LPM

Rd, Z

Load Program Memory

Load Program Memory

LPM

Rd, Z+

Load Program Memory and

Post-Increment

ELPM

Extended Load Program

Rd (Z),
ZZ+1

Memory
ELPM

Rd, Z

Extended Load Program

Memory

ELPM

Rd, Z+

SPM
SPM

Z+

Store Program Memory and

(RAMPZ:Z) R1:R0,

Post-Increment

ZZ+2
Rd I/O(A)

None

None
None

1
1

Rd STACK
Temp Rd,

None
None

2
2

None

None

None

Z,C,N,V,H

Z,C,N,V

Z,C,N,V,H

Z,C,N,V

Rd(n) Rd(n+1), n=0..6

Rd(3..0) Rd(7..4)

Z,C,N,V
None

1
1

SREG(s) 1
SREG(s) 0

SREG(s)
SREG(s)

1
1

I/O(A, b) 1
I/O(A, b) 0

None
None

1
1

T Rr(b)
Rd(b) T

T
None

1
1

C 1

IN

Rd, A

by 2
In From I/O Location

OUT
PUSH

A, Rr
Rr

Out To I/O Location

Push Register on Stack

POP
XCH

Rd
Z, Rd

Pop Register from Stack

Exchange RAM location Temp

I/O(A) Rr
STACK Rr

Rd (Z),
LAS

LAC

LAT

Z, Rd

Z, Rd

Z, Rd

Load and Set RAM location

Temp Rd,

Temp

Rd (Z),

Load and Clear RAM location

(Z) Temp v (Z)

Temp Rd,

Temp

Rd (Z),

Load and Toggle RAM

location Temp

Bit and bit-test instructions

LSL
Rd

(Z) Temp

(Z) ($FFh Rd) (Z)

Temp Rd,
Rd (Z),
(Z) Temp (Z)

Logical Shift Left

Rd(n+1) Rd(n),
Rd(0) 0,

LSR

Rd

Logical Shift Right

C Rd(7)
Rd(n) Rd(n+1),
Rd(7) 0,

ROL

Rd

Rotate Left Through Carry

C Rd(0)

Rd(0) C,
Rd(n+1) Rd(n),

ROR

Rd

Rotate Right Through Carry

C Rd(7)
Rd(7) C,
Rd(n) Rd(n+1),

ASR
SWAP

Rd
Rd

Arithmetic Shift Right

Swap Nibbles

BSET
BCLR

s
s

Flag Set
Flag Clear

SBI
CBI

A, b
A, b

Set Bit in I/O Register

Clear Bit in I/O Register

BST
BLD

Rr, b
Rd, b

Bit Store from Register to T

Bit load from T to Register

SEC

Set Carry

C Rd(0)

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Skup Instrukcija mikroprocesora

ATxmega
CLC
SEN

Clear Carry
Set Negative Flag

C 0
N 1

C
N

1
1

CLN
SEZ

Clear Negative Flag

Set Zero Flag

N 0
Z 1

N
Z

1
1

CLZ
SEI

Clear Zero Flag

Global Interrupt Enable

Z 0
I 1

Z
I

1
1

CLI
SES

Global Interrupt Disable

Set Signed Test Flag

I 0
S 1

I
S

1
1

CLS
SEV

Clear Signed Test Flag

Set Twos Complement

S 0
V 1

S
V

1
1

CLV

Overflow
Clear Twos Complement

V 0

SET

Overflow
Set T in SREG

Clear T in SREG
Set Half Carry Flag in SREG

T 1

CLT
SEH

T
H

1
1

H 0

None

CLH
Clear Half Carry Flag in SREG
MCU control instructions
BREAK
Break (See specific descr. for

T 0
H 1

BREAK)
NOP
SLEEP

No Operation
Sleep (see specific descr. for

None
None

1
1

WDR

Sleep)
Watchdog Reset (see specific

None

descr. for WDR)

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