8251 Usart

24-Oct-11
8251
USART
Hardeep Singh
Lecturer/ECE
SBBSIET, Padhiana
24-Oct-11
Hardeep Singh/Lecturer/SBBSIET
Introduction
Two types of data transfer
Parallel data transfer
Serial data transfer
Types of communication
Simplex
Duplex
Half duplex
Full duplex
Serial Transmission Formats

Asynchronous data transfer
Synchronous data transfer
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Baud Rate
In serial communication the rate at which data
bits are transmitted generates a term baud rate.
Baud rate is defined as bits/second or the changes
in voltage levels/second
Baud
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BitsTransmitted
Second
8085 Serial I/O

Serial communication is useful for data
transfer between two points
SID Serial input data
This is an active high, serial input port pin, used to
accept serial 1 bit data under software control
When a RIM instruction is executed the SID pin data is
loaded in D7 of accumulator
SOD- Serial output data

This is an active high, serial output port pin, used to
transfer serial 1 bit data under software control
When a SIM instruction is executed the SOD pin is set
or reset depending on D7 and D6 bits of accumulator
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8251 USART
USART Universal Synchronous/Asynchronous
Receiver and Transmitter
It will do the job of sending data out,
accepting data bits, generation/removing
other signals check different conditions etc.
8251 will convert this parallel data into serial
stream and transmit on serial output line
And, vice versa
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8251 Functional Block Diagram
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The 8251 block diagram contains 5 functional

block
Data bus buffer
Read write control logic
Transmitter section
Receiver section
Modem control
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Data Bus Buffer

It is a tri state bi directional, buffer used to
interface data bus of 8251 to the system data
bus
The directional of data transfer through data
bus buffer is decided by RD and WR
This buffer transfers control word, status
word, data from receiver, depending on signal
given by R/W logic
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Read/Write Control Logic

This block accepts different control signals
such as RD, WR, C/D, CS, CLK and Reset from
control bus and generate control signals for
device operation
The 8251 is selected when CS=0. When CS=0 it
accepts C/D pin and decides which part to
activate
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8251 contains
a. Two data buffer registers
I. Data buffer for transmitter
II. Data buffer for reciever
b. Two control/status registers

a. Control word register
b. Status register
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Transmitter Section
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Receiver Section
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This section consists of receive buffer and receive control

blocks
The receiver section accepts serial data on Rxd pin.
The input register converts the serial data into parallel
form
In asynchronous mode it will check for making state first,
then it checks for start bit
If start bit is detected then the bits are converted to
parallel form and transfer to receiver buffer register
For asynchronous mode 8251 contains false start bit
detection circuit
When the data byte is transferred from input register to
receiver buffer register, the control logic generates a signal
RxRDY to signal CPU about availability of data byte to read
by CPU
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Modem Control
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For sending the data on long distance

telephone lines are used
The telephone lines are analog in nature so
MODEMs are used to convert digital data to
analog data
Handshake signals of MODEM
DTR Data Terminal ready
DSR Data set ready
RTS Request to send
CTS Clear to send
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Pin Diagram 8251 USART
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D0 D7: Data bus

These are 8 bit bidirectional data lines connected to
system data bus
The microprocessor uses these lines to send or
receive data from 8251
CS: Chip select

This is a chip select input signal used to select 8251
When CS=0, the 8251 is selected. If CS=1, 8251 is
not selected
CLK: Clock input

The clock frequency must be greater than 30 times
receiver and transmitter frequency
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RESET: Reset input

This pin is generally connected to reset out of
8085
This pin is used to force 8251 in idle mode i.e
reset condition
WR: Write input

This pin is an input signal used to load information
in 8251
RD: Read input

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C/D: Control/Data
This is an input pin, used to differentiate two sections control and
data section.
When C/D=1, the control section is enabled
And, when C/D-0, the data section in enabled
DSR
DTR
RTS
CTS
TxD
TxC
TxRDY
TxE
RxD
RxC
RxRDY
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SYNDET/BRKDET: Sync Detect/ Break Detect

Synchronous mode: In it the pin is used as sync detect
There are two possible conditions input and output, which
is programmed through mode word
When SYNDET is used as output it indicates that you are
using 8251 sync detect circuit
Asynchronous mode:
This pin is used to detect break
If programmed stop bits are not available for consecutive
stop bit sequences, the output of pin goes high
If RxD remains LOW for stop bits, it represents problem in
line connected between transmitter and reciever
The status of this pin is also available in status word
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8251 Control Word

8251 contains 16 bit control register divided
into two sections of 8 bits each
Mode control word
Command word register
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8251 Control Word:

Asynchronous Mode
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Mode Word Format (Asynchronous Mode)
D1 D0=00 / Synchronous mode,

D1 D0 =/ 00 /Asynchronous mode
D2 and D3 defines the length of character
D5 and D4 defines parity bit
D7 and D6 defines the number of stop bits
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Mode Word Format

The mode word format of synchronous mode
D1 D0 =00, specifies synchronous mode
The function of bits D2 to D5 are same as
synchronous mode
D7=1 it is single sync character. If D7=0 it is
double sync character
D6 defines whether SYNDET pin is used as
input or output
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8251 Control Word:

Synchronous Mode
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Command Word Format
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Command Word Format

After mode word, a command word is
programmed to control actual operation
D0 and D1 are used to enable transmitter and
receiver
D1 and D5 are used to set status of MODEM
control signals, DTR and RTS.
D3 is used to send the break character
D3 is low it will force TxD line LOW
D4 is used to reset all error flags

D6 is used to perform internal reset operation
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D7 is only used for synchronous mode

If D7=1 the receiver will enter the hunt mode
If internal SYNDET circuit is used the receiver
buffer contents are compared, after each bit
received with the programmed sync characters, till
match occurs.
When sync character match occurs, 8251 will
come out of hunt mode and starts to assemble
data bytes
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8251 Status Word
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The status register bits DSR, SYNDET, TxE,

RxRDY gives status of respective pins on 8251
TxRDY bit in status register is set if transmit
buffer is empty
Parity error
Overrun error
Framing error
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8251 Data Transfer Operations
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Asynchronous Mode Transmission
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Asynchronous Mode Reciever
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Synchronous Mode Transmission
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Synchronous Mode Reception
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8251 Interfacing in I/O mapped I/O
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24-Oct-11

Serial Transmission Formats

8085 Serial I/O

SOD- Serial output data

8251 Functional Block Diagram

The 8251 block diagram contains 5 functional

Data Bus Buffer

Read/Write Control Logic

b. Two control/status registers

This section consists of receive buffer and receive control

For sending the data on long distance

Pin Diagram 8251 USART

D0 D7: Data bus

CS: Chip select

CLK: Clock input

RESET: Reset input

WR: Write input

RD: Read input

SYNDET/BRKDET: Sync Detect/ Break Detect

8251 Control Word

8251 Control Word:

Mode Word Format (Asynchronous Mode)

D1 D0=00 / Synchronous mode,

Mode Word Format

8251 Control Word:

Command Word Format

Command Word Format

D4 is used to reset all error flags

D7 is only used for synchronous mode

8251 Status Word

The status register bits DSR, SYNDET, TxE,

8251 Data Transfer Operations

Asynchronous Mode Transmission

Asynchronous Mode Reciever

Synchronous Mode Transmission

Synchronous Mode Reception

8251 Interfacing in I/O mapped I/O

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