Thosiba 670 D - LA-6054P

A
Compal confidential
Hamburg 10ADG
NALAE LA-6054P Schematics Document

Mobile AMD S1G4/ RS880M / SB820M
3
2009-02-04 Rev. 0.2
Compal Secret Data
Security Classification
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
Wednesday, May 19, 2010

E
of
52
Compal Confidential
Thermal Sensor
ADM1032ARMZ
Model Name : NALAE
Fan Control
page 7
page 5
AMD S1G4 CPU
Memory BUS(DDRIII)
Dual Channel
uFCPGA-638 Package
1.5V DDRIII 1066/1333MHZ
File Name : LA-6054P
200pin DDRIII-SO-DIMM X2
page 9,10
BANK 0, 1, 2, 3
page 5,6,7,8
Hyper Transport Link 2.6GHz

16X16
PCIeMini Card WLAN

PCIe Port 2
CRT
USB Port 8
AMD
page 17
LCD Conn.
RS880M
Madison & Park
page 18
page 28
PCIe 4x
1.5V 2.5GHz(250MB/s)
Page 35,36,37,38,39
40,41,42,43
HDMI Conn.
page 19
page 11,12,13,14,15
RTL 8105E 10/100

2
A-Link Express II
4X PCI-E
SATA port 0
USB/B
USB port 0,1
5V 1.5GHz(150MB/s)
AMD
Card Reader
USB port 5
page 28
SATA port 1
page 27
BT conn
Int. Camera
USB port 6
USB port 9
page 28
5V 1.5GHz(150MB/s)
SB820M
USB
RJ45
page 26
PCIe port 3
page 26
SATA HDD
page 25
SATA ODD
page 25
5V 480MHz
SATA port 3
5V 1.5GHz(150MB/s)
page 18
eSATA
USB port 2
page 25
5V 480MHz
page 20,21,22,23,24
3
Clock Generator
SLG8SP626
HD Audio
page 16
3.3V 24.576MHz/48Mhz
LPC BUS
RTC CKT.
3.3V 33 MHz
ODD/B
Debug Port
Power On/Off CKT.
ALC259Q
page 32
ENE KB926 D3
page 32
Power/B
page 29
page 31
page 33
page 33
Audio & USB/B

DC/DC Interface CKT.
page 34
HDA Codec
MDC 1.5 Conn

page 25
page 20
Int.
MIC CONN
page 18
SPI ROM
Int.KBD
page 33
page 32
page 32
MIC CONN
page 30
HP CONN
page 30
SPK CONN
page 30
LED/B
page 33
Power Circuit DC/DC

4
page 44,45,46.47
48,49,50,51
Touch Pad/B
page 33
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
E
of
52
DESIGN CURRENT 0.1A
+3VL
+5VL
DESIGN CURRENT 0.1A
B+
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.7A
RT8205EGQW
DESIGN CURRENT 5A
+3VALW
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 2A
+5VS
SUSP
N-CHANNEL
SI4800
SUSP#
DESIGN CURRENT 2.5A
+1.8VS
MP2121DQ
WOL_EN#
DESIGN CURRENT 330mA
+3V_LAN
P-CHANNEL
AO3413
SUSP
DESIGN CURRENT 1.5A
N-CHANNEL
DESIGN CURRENT 1A
P-CHANNEL
AO3413
BT_PWR#
NALAE Hamburg AMD DIS
+3VS
VGA_ENVDD
SI4800
+LCD_VDD
+BT_VCC
P-CHANNEL
AO3413
+2.5VS
APL5508
POK
RT8209BGQW
DESIGN CURRENT 12A
+1.1VALW
DESIGN CURRENT 3.5A
+1.1VS
VLDT_EN#
N-CHANNEL
IRF8113
VLDT_EN#
DESIGN CURRENT 6A
N-CHANNEL
+NB_CORE
IRF8113
VR_ON
DESIGN CURRENT 36A
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A
ISL6265A
+CPU_CORE_0
DESIGN CURRENT 4A
+VDDNB
SYSON
RT8209BGQW
DESIGN CURRENT 11A
+1.5V
SUSP
N-CHANNEL
IRF8113
DESIGN CURRENT 5A
+1.5VS
DESIGN CURRENT 1A
+0.75VS
DESIGN CURRENT 1.5A
+1.05VS
DESIGN CURRENT 2.5A
+1.0VS
SUSP
APL5331KAC
VR_ON#
APL5331KAC
SUSP#
APL5930KAI
SUSP#
A
DESIGN CURRENT 20A
Ipeak = 20A, Imax = 14A, Iocp_min = 20.14A
APW7138NITRL
Compal Secret Data
2008-09-25
Issued Date
+VGA_CORE
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

1
of
52
Symbol Note :
Voltage Rails
: Digital Ground
O : ON
X : OFF
GPU
: Analog Ground
Manhattan
+5VS
1
+3VS
power
plane
CPU
M96/M92
+2.5VS
NB
VGA
SB
S1G4
RS880M
MADISON
S1G4
RS880M
PARK
S1G4
RS880M
M96
S1G4
RS880M
M92
Comment
SB820M Madison@ or PARK@

SB820M +4PCS or 8PCS
SB820M M9X@+M96@ or M92@
SB820M +4PCS or 8PCS
+1.8VS
+1.5VS
State
B+
+3VL
+5VALW
+5VL
+1.1VALW
+1.05VS
+1.5V
+3VALW
Platform
@ : just reserve , no build
+1.1VS
CPU
Danube
NB
S1G4
+0.75VS
VGA
RS880M
SB
NA
Comment
SB820M
+VGA_CORE
+RTCVCC
+VDDNB
+CPU_CORE
+NB_CORE
BTO (Build-To-Order)
Function
S0
Description
S1
Explain
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
BLUE TOOTH
BTO
Option Table
HDMI
(B)
(Y)
BT@
H@
SMBUS Control Table

SOURCE
I2C / SMBUS ADDRESSING
CPU
THERMAL
SENSOR
EC_SMB_CK1
DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
1010000X
EC_SMB_CK2
DDR SO-DIMM 1
A2
1010001X
EC_SMB_DA2
CLOCK GENERATOR (EXT.)
D2
11010010
I2C_CLK
EC_SMB_DA1
DDC_CLK0
DDC_DATA0
SCL0
EC SM Bus2 address
SDA0
Device
HEX
Address
Device
Smart Battery
16H
0001 011X b
ADI1032-1 CPU 98H
1001 100X b
HDMI-CEC
34H
0011 010X b
ADI1032-2 VGA 9AH
1001 101X b
HEX
Address
SCL1
SDA1
KB926
SODIMM
I / II
CLK
GEN
WLAN
LCD
DDC
ROM
HDMI
DDC
ROM
KB926
RS880M
I2C_DATA
EC SM Bus1 address
BATT
RS880M
SB820
SB820
EC KB926D3
EC KB926D4
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
+1.1VS
250 mil
1
VLDT CAP.
1
C1
10U_0805_10V4Z
Near CPU Socket

1
C2
10U_0805_10V4Z
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
<11> H_CADIP[0..15]
<11> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
H_CADOP[0..15]
<11>
H_CADON[0..15]
<11>
+1.1VS
+1.1VS
JCPUA
VLDT=500mA
< From NB >
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
+VLDT_B 1
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
C7
2 10U_0805_10V4Z
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
< To NB >
<11>
<11>
<11>
<11>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<11>
<11>
<11>
<11>
FOX_PZ6382A-284S-41F_Champlian
< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS
1A
+FAN1
C1119
<30> EN_DFAN1
2
+3VS
10U_0805_10V4Z
+FAN1
10U_0805_10V4Z
U31
1
2
3
4
EN
VIN
VOUT
VSET
GND
GND
GND
GND
C1121
8
7
6
5
1000P_0402_25V8J
1
2
3
1
2
3
4
5
GND
GND
JFAN
C1120
R795
10K_0402_5%
2
@ ACES_85204-0300N
FAN_SPEED1 <30>
2
APL5607KI-TRG_SO8
C1122
@
1
Compal Secret Data
2008-09-25
Issued Date
0.01U_0402_25V7K
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
< DDR2 VREF is 0.5 ratio >
< Processor DDR3 Memory Interface >
+1.5V
R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1%
< From/To SO_DIMMB >
+MCH_REF
1
R2
1
C9
0.1U_0402_16V7K
C8
1000P_0402_25V8J
1K_0402_1%
+1.05VS
+1.05VS
JCPUB
Place them close to CPU within 1"
+1.5V
R4 1
R5 1
2 39.2_0402_1%
2 39.2_0402_1%
<9> MEM_MA_RST#
<9> DDR_A_ODT0
< To SO_DIMMA > <9> DDR_A_ODT1
< To SO_DIMMA >
<9> DDR_CS0_DIMMA#
<9> DDR_CS1_DIMMA#
<9> DDR_CKE0_DIMMA
< To SO_DIMMA > <9> DDR_CKE1_DIMMA

<9> DDR_A_CLK0
<9> DDR_A_CLK#0
MEM_P
MEM_N
<9> DDR_A_CLK1
<9> DDR_A_CLK#1
<9> DDR_A_BS#0
< To SO_DIMMA > <9> DDR_A_BS#1

<9> DDR_A_BS#2
< To SO_DIMMA >
<9> DDR_A_RAS#
<9> DDR_A_CAS#
<9> DDR_A_WE#
AF10
AE10
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
W10
AC10
AB10
AA10
A10
Y10
VTT_SENSE
MEMVREF
W17
+MCH_REF
MB_RESET_L
B18
MB0_ODT0
MB0_ODT1
MB1_ODT0
W26
W23
Y26
DDR_B_ODT0
DDR_B_ODT1
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
V26
W25
U22
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
MB_CKE0
MB_CKE1
J25
H26
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
P22
R22
A17
A18
AF18
AF17
R26
R25
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
MEM_MA_RST#
H16
MA_RESET_L
DDR_A_ODT0
DDR_A_ODT1
T19
V22
U21
V19
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
DDR_CS0_DIMMA# T20
DDR_CS1_DIMMA# U19
U20
V20
DDR_CKE0_DIMMA J22
DDR_CKE1_DIMMA J20
DDR_A_CLK0
DDR_A_CLK#0
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
< VTT regulator voltage >
MEM_MB_RST#
DDR_A_CLK1
DDR_A_CLK#1
N19
N20
E16
F16
Y16
AA16
P19
P20
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
< To SO_DIMMA >
< To SO_DIMMA > <9> DDR_A_MA[15..0]
D10
C10
B10
AD10
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
PAD
T1
MEM_MB_RST# <10>
DDR_B_ODT0 <10>
DDR_B_ODT1 <10>
< To SO_DIMMB >
DDR_CS0_DIMMB# <10>
DDR_CS1_DIMMB# <10><
To SO_DIMMB >
DDR_CKE0_DIMMB <10>
DDR_CKE1_DIMMB <10><
To SO_DIMMB >
DDR_B_CLK0 <10>
DDR_B_CLK#0 <10>
< To SO_DIMMB >

DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_B_MA[15..0] <10>
<10> DDR_B_DM[7..0]
< To SO_DIMMB >
DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>
< To SO_DIMMB >
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>
< To SO_DIMMB >
< To SO_DIMMB >
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
< From/To SO_DIMMB >
DDR_A_D[63..0]
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<9>
< From/To SO_DIMMA >
DDR_A_DM[7..0]
<9>
< To SO_DIMMA >
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
< From/To SO_DIMMA >
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
JCPUD
+1.5V
+2.5VDDA
+2.5VS
+2.5VDDA
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
VDDA=300mA
L1 1
2 FBM_L11_201209_300L_0805
1
1
C12
C13
+2.5VDDA
1
C14
LDT_RST#
H_PWRGD
LDT_STOP#
+ C11
@
2
4.7U_0805_10V4Z
150U_B2_6.3VM_R45M
3300P_0402_50V7-K
0.22U_0603_16V4Z
T2
+1.5V
+1.5V
< 200-MHz PLL Reference Clock >

1
C16
2 3900P_0402_50V7K
+1.1VS
CPU_CLKIN_SC_P
1
<19> CLK_CPU_BCLK
R10
C15
2 3900P_0402_50V7K
<19> CLK_CPU_BCLK#
Address:100_1100
R15
R16
1
1
1
1
2
2 1K_0402_5%
1K_0402_5%
2 44.2_0402_1%
2 44.2_0402_1%
CPU_HTREF0
CPU_HTREF1
<49> CPU_VDD0_RUN_FB_H
<49> CPU_VDD0_RUN_FB_L
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
169_0402_1%
R12
R14
CPU_CLKIN_SC_N
Place close to CPU wihtin 1.5"
R27
2 510_0402_5% CPU_TEST25L
R29
1 1K_0402_5%
CPU_TEST12
R30
1 1K_0402_5%
CPU_TEST18
R31
1 1K_0402_5%
CPU_TEST19
R32
1 1K_0402_5%
CPU_TEST20
R33
1 1K_0402_5%
CPU_TEST21
R34
1 1K_0402_5%
CPU_TEST22
R265 2
1 1K_0402_5%
CPU_TEST23
R35
1 1K_0402_5%
CPU_TEST24
R28
R6
P6
HT_REF0
HT_REF1
F6
E6
H6
G6
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
TEST18
TEST19
TEST28_H
TEST28_L
J7
H8
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
AA6
TEST9
TEST6
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
@R13
@
R13
2 0_0402_5%
H_PROCHOT# <19>
1
VDDNB_FB_H
VDDNB_FB_L
TEST23
2 R20
THERMDC_CPU
THERMDA_CPU
route as differential
as short as possible
testpoint under package
H10
G9
1K_0402_5% 1
CPU_PROCHOT#
W9
Y9
CPU_TEST18
CPU_TEST19
CPU_SVD
2 300_0402_5%
+1.5V
VDDIO_FB_H
VDDIO_FB_L
AD7
1K_0402_5%
AF6 CPU_THERMTRIP#_R
AC7 CPU_PROCHOT#
AA8
PAD T3
VDD0_FB_H
VDD0_FB_L
CPU_TEST23
2 R19
R11
THERMTRIP_L
PROCHOT_L
MEMHOT_L
W7
W8
DBRDY
TMS
TCK
TRST_L
TDI
CPU_TEST27
CPU_SVC <49>
CPU_SVD <49>
1K_0402_5% 1
< Serial VID Interface clock & data >
THERMDC
THERMDA
VDD1_FB_H
VDD1_FB_L
E9
E8
CPU_SVC
CPU_SVD
CPU_SVC
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
+1.5V
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
PAD
PAD
PAD
PAD
T4
T5
T6
T7
<49>
<49>
R6 1
2 10K_0402_5%
R7 1
2 1K_0402_5%
CPU_THERMTRIP#_R
Q1
1
H_THERMTRIP# <20>
1 510_0402_5% CPU_TEST25H
SIC
SID
ALERT_L
A6
A4
AF4
AF5
AE6
SVC
SVD
M11
W18
R22
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
Y6
AB6
2 R24
0_0402_5%
CLKIN_H
CLKIN_L
G10
AA9
AC9
AD9
AF9
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
+1.5V
A9
A8
VSS
RSVD11
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25H
CPU_TEST25L
VDDA1
VDDA2
B7
A7
F10
C6
PAD
CPU_SIC
CPU_SID
F8
F9
< Filtered PLL Supply Voltage >
MMBT3904_NL_SOT23-3
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
2
R25
1
80.6_0402_1%
H18
H19
AA7
D5
C5
+1.5VS
R17
300_0402_5%
<19>
LDT_RST#
LDT_RST#
< HDT Connector >
C17
@
2
JP2
0.01U_0402_25V7K
+1.5VS
+1.5V
R21
+1.5V
R40
2 300_0402_5%
1
R39
R38
R37
R36
1
1
1
1
2
2
2
2
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
300_0402_5%
<19,49> H_PWRGD
+1.5V
H_PWRGD
< Thermal Sensor >
+3VS
LDT_RST#
U1
C19
@
2
2
4
6
8
10
12
14
16
18
20
22
24
26
SAMTEC_ASP-68200-07
C20
VDD
SCLK
EC_SMB_CK2
THERMDA_CPU
D+
SDATA
EC_SMB_DA2
THERMDC_CPU
2 C21
3300P_0402_50V7-K
D-
ALERT#
THERM#
GND
0.1U_0402_16V7K
0.1U_0402_16V7K
1
@
EC_SMB_CK2 <30,42>
EC_SMB_DA2 <30,42>
+1.5VS
4
ADM1032ARM-1 ZREEL_MSOP8
R18
300_0402_5%
<12,19> LDT_STOP#
LDT_STOP#
Compal Secret Data
C18
2008-09-25
Issued Date
@
0.01U_0402_25V7K
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
JCPUE
+CPU_CORE
VDD decoupling : +CPU_CORE

+CPU_CORE
+CPU_CORE
330U_X_2VM_R6M
C26
+VDDNB
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
+1.5V
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
+CPU_CORE
C35
C34
C28
C29
C36
C37
C38
C25
2
330U_X_2VM_R6M
Near CPU Socket
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
Under CPU Socket
Under CPU Socket
+@
C23
C89
2
Near CPU Socket
1
+ @C24
2
330U_2.5V_M
330U_X_2VM_R6M
+CPU_CORE
330U_2.5V_M
330U_X_2VM_R6M
+CPU_CORE
+CPU_CORE
C30
C31
C32
C33
C39
C40
C41
C90
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
Under CPU Socket
Under CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power

+1.5V
C44
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
C46
0.22U_0603_16V4Z
C47
0.22U_0603_16V4Z
C48
180P_0402_50V8J
C50
180P_0402_50V8J
Under CPU Socket

+1.5V
+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+1.5V
2
C54
0.22U_0603_16V4Z
C51
0.22U_0603_16V4Z
C52
0.22U_0603_16V4Z
C53
JCPUF
0.22U_0603_16V4Z
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
Between CPU Socket and DIMM

+1.5V
C64
0.01U_0402_25V7K
C65
0.01U_0402_25V7K
C56 Co-layout with C75

+1.5V
+1.5V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
C66
C67
1
1
C68
C56
C69
390U_2.5V_M_R10
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
+1.05VS
+1.5V
+
C1124
390U_2.5V_M_R10
1
1
C71
4.7U_0805_10V4Z
C72
4.7U_0805_10V4Z
C73
4.7U_0805_10V4Z
@
+ C75
C74
4.7U_0805_10V4Z
2 330U_D2E_2.5VM_R6M
+1.05VS
VDDR decoupling.
C57
4.7U_0805_10V4Z
C58
4.7U_0805_10V4Z
C59
0.22U_0603_16V4Z
C60
0.22U_0603_16V4Z
C61
1000P_0402_25V8J
C62
1000P_0402_25V8J
C63
180P_0402_50V8J
C70
180P_0402_50V8J
+1.05VS
1
C76
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
C78
0.22U_0603_16V4Z
C79
0.22U_0603_16V4Z
C80
1000P_0402_25V8J
Near CPU Socket Left side
C81
1000P_0402_25V8J
C82
180P_0402_50V8J
C1125
+
2
C83
180P_0402_50V8J
330U_D2E_2.5VM
Near CPU Socket Right side
+1.05VS
2
@
+VDDNB decoupling : Northbridge power

+VDDNB
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
1
C42
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
Compal Secret Data
C49
2008-09-25
Issued Date
22U_0805_6.3V6M
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
+1.5V
+1.5V
JDDRL
C10
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
<6> DDR_A_DQS#1
<6> DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<6> DDR_A_DQS#2
<6> DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
205
G1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#0 <6>
DDR_A_DQS0 <6>
DDR_A_D[0..63]
DDR_A_D6
DDR_A_D7
DDR_A_DM[0..7]
DDR_A_D[0..63]
<6>
DDR_A_DM[0..7]
<6>
1
DDR_A_D12
DDR_A_D13
DDR_A_MA[0..15]
DDR_A_DM1
MEM_MA_RST#
DDR_A_MA[0..15] <6>
MEM_MA_RST# <6>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
+1.5V
+1.5V
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#3 <6>
DDR_A_DQS3 <6>
DDR_A_D30
DDR_A_D31
R310
1K_0402_1%
R48
1K_0402_1%
1
DDR_A_D26
DDR_A_D27
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C85
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1000P_0402_25V8J
C84
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDR_A_D0
DDR_A_D1
+VREF_DQ
+VREF_DQ
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_A_CLK0
<6> DDR_A_CLK#0
<6> DDR_A_BS#0
<6> DDR_A_WE#
<6> DDR_A_CAS#
<6> DDR_CS1_DIMMA#
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
<6> DDR_A_DQS#4
<6> DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6> DDR_A_DQS#6
<6> DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
+3VS
+0.75VS
4
C91
0.1U_0402_16V4Z 2
206
G2
DDR_A_MA15
DDR_A_MA14
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_ODT1
< Close to JDDRH & JDDRL >
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
1
C680
2
C235
2
C351
+1.5V
0.1U_0402_16V4Z
2
C87
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C88
C640
C641
1
0.1U_0402_16V4Z
DDR_A_DQS#5 <6>
DDR_A_DQS5 <6>
0.1U_0402_16V4Z
2
C642
1
0.1U_0402_16V4Z
C643
1
0.1U_0402_16V4Z
2
C644
1
0.1U_0402_16V4Z
C645
1
0.1U_0402_16V4Z
2
C646
C647
1
0.1U_0402_16V4Z
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
+0.75VS
DDR_A_DQS#7 <6>
DDR_A_DQS7 <6>
DDR_A_D62
DDR_A_D63
0.1U_0402_16V4Z
2
C665
C664
1
0.1U_0402_16V4Z
C961
2
4.7U_0603_6.3V6K
SMB_CK_DAT0 <10,20>
SMB_CK_CLK0 <10,20>
Place near DIMM1
+0.75VS
TYCO_2-2013289-1
Compal Secret Data
DIMM_A STD H:5.2 mm
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
<Address: 00>
Date:
R315
1K_0402_1%
R49
1K_0402_1%
DDR_A_MA11
DDR_A_MA7
DDR_A_MA12
DDR_A_MA9
+VREF_CA
DDR_CKE1_DIMMA <6>
DDR_A_BS#2
DDR_CKE1_DIMMA
0.01U_0402_25V7K
<6> DDR_A_BS#2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
4.7U_0805_10V4Z
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1000P_0402_25V8J
DDR_CKE0_DIMMA
<6> DDR_CKE0_DIMMA
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
of
52
+1.5V
+1.5V
JDDRH
C93
DDR_B_DM0
C682
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
<6> DDR_B_DQS#1
<6> DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
<6> DDR_B_DQS#2
<6> DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
<6> DDR_CKE0_DIMMB
2
DDR_B_BS#2
<6> DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
<6> DDR_B_CLK0
<6> DDR_B_CLK#0
DDR_B_MA10
DDR_B_BS#0
<6> DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
<6> DDR_B_WE#
<6> DDR_B_CAS#
DDR_B_MA13
DDR_CS1_DIMMB#
<6> DDR_CS1_DIMMB#
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
<6> DDR_B_DQS#6
<6> DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
+3VS
+0.75VS
4
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
205
G1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#0 <6>
DDR_B_DQS0 <6>
DDR_B_D[0..63]
DDR_B_D6
DDR_B_D7
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DM[0..7]
<6>
<6>
1
DDR_B_D12
DDR_B_D13
DDR_B_MA[0..15]
DDR_B_MA[0..15]
DDR_B_DM1
MEM_MB_RST#
<6>
MEM_MB_RST# <6>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#3 <6>
DDR_B_DQS3 <6>
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_CKE1_DIMMB <6>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_BS#1
DDR_B_RAS#
DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1
DDR_B_ODT1 <6>
+VREF_CA
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
C683
0.1U_0402_16V4Z
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
4.7U_0805_10V4Z
DDR_B_DQS#4
DDR_B_DQS4
<6> DDR_B_DQS#4
<6> DDR_B_DQS4
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_25V8J
DDR_B_D32
DDR_B_D33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C352
C353
3
DDR_B_DQS#5 <6>
DDR_B_DQS5 <6>
DDR_B_D46
DDR_B_D47
+1.5V
DDR_B_D52
DDR_B_D53
0.1U_0402_16V4Z
2
DDR_B_DM6
C666
1
0.1U_0402_16V4Z
DDR_B_D54
DDR_B_D55
0.1U_0402_16V4Z
2
C667
1
C668
1
0.1U_0402_16V4Z
C669
1
0.1U_0402_16V4Z
2
C670
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C671
C672
1
0.1U_0402_16V4Z
2
C673
1
0.1U_0402_16V4Z
C674
C677
1
0.1U_0402_16V4Z
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_DQS#7 <6>
DDR_B_DQS7 <6>
+0.75VS
+1.5V
DDR_B_D62
DDR_B_D63
0.1U_0402_16V4Z
2
C676
SMB_CK_DAT0 <9,20>
SMB_CK_CLK0 <9,20>
1
0.1U_0402_16V4Z
+0.75VS
C675
1
C925
2
4.7U_0603_6.3V6K
+1.5V
1
+ @C86
2
390U_2.5V_M_R10
DDR_B_D0
DDR_B_D1
330U_X_2VM_R6M
C92
1000P_0402_25V8J
0.1U_0402_16V4Z
4.7U_0805_10V4Z
+VREF_DQ
+
C128
2
4
LOTES_AAA-DDR-111-K01
Compal Secret Data
DIMM_B STD H:9.2 mm

<Address: 01>
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
10
of
52
U3B
<34> PCIE_GTX_C_MRX_N[0..15]
<27>
<27>
<25>
<25>
< To WLAN >

< To LAN >
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
< From SB820 : x4 PCIE A-link >
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
880MR1@
U3A
H_CADOP[0..15]
H_CADON[0..15]
H_CADOP[0..15]
<5>
H_CADON[0..15]
<5>
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
< From S1G4 CPU : x16 HT>
<5>
<5>
<5>
<5>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<5>
<5>
<5>
<5>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
301_0402_1%1
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
2 R60
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
C126
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
C129
C130
C131
C132
1
1
1
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
PCIE_CALRP
PCIE_CALRN
PCIE I/F GPP
PCIE I/F SB
R59
R58
1
1
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
M22
M23
R21
R20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
HT_RXCALP
HT_RXCALN
C23
A24
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
HT_TXCALP
HT_TXCALN
RS780M_FCBGA528
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<27>
<27><
<25>
<25><
To WLAN >
To LAN >
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND >

< RX Impedance Calibration. Connect to VDDPCIE >
+1.1VS
H_CADIP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
<5>
H_CADIN[0..15]
<5>
< To S1G4 CPU : x16 HT>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<5>
<5>
<5>
<5>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<5>
<5>
<5>
<5>
R61
2 301_0402_1%
< Transmitter Calibration Resistor to HT_TXCALN >
0718 Place within 1"

layout 1:2
Compal Secret Data

2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Date:
PCIE_MTX_C_GRX_N[0..15] <34>
1.27K_0402_1%
2K_0402_1%
2
2
PCIE_MTX_C_GRX_P[0..15] <34>
PCIE_MTX_C_GRX_N[0..15]
RS780M_FCBGA528
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
880MR1@
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
0718 Place within 1"

layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PART 2 OF 6
PCIE I/F GFX
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N[0..15]
HYPER TRANSPORT CPU I/F
PCIE_GTX_C_MRX_P[0..15]
<34> PCIE_GTX_C_MRX_P[0..15]
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
11
of
52
+AVDDQ
2
2.2U_0603_6.3V4Z
+1.8VS
L4
0_0603_5%
+AVDD2
1
C142
2.2U_0603_6.3V4Z
C145
0.1U_0402_16V7K
+1.8VS
1
L6
2 BLM18PG121SN1D_0603
+AVDDQ
1
C148
R65 1
2.2U_0603_6.3V4Z
+1.1VS
L2
2 BLM18PG121SN1D_0603
+NB_PLLVDD
1
UMA_CRT_HSYNC
UMA_CRT_VSYNC
<15> UMA_CRT_HSYNC
<15> UMA_CRT_VSYNC
2 715_0402_1%
L5
2 BLM18PG121SN1D_0603
1
DAC_RSET(PWM_GPIO1)
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
NB_LDTSTOP#
NB_REFCLK_P
NB_REFCLK_N
R69
R70
2 4.7K_0402_5%
2 4.7K_0402_5%
1
1
T19 PAD
T21 PAD
+VDDA18HTPLL
G14
2 0_0402_5% NB_RESET# D8
NB_PWRGD A10
C10
C12
+1.8VS
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
D7
E7
<19> CLK_SBSRC_BCLK
<19> CLK_SBSRC_BCLK#
A11
B11
F8
E8
+VDDA18PCIEPLL
2.2U_0603_6.3V4Z
L7
2 BLM18PG121SN1D_0603
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
VDDA18HTPLL
<19> NB_REFCLK_P
<19> NB_REFCLK_N
C146
G18
G17
E18
F18
E19
F19
H17
<19> HT_REFCLKP
<19> HT_REFCLKN
+NB_HTPVDD
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
+VDDA18HTPLL
<19> CPU_LDT_REQ#
E17
F17
F15
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
R66 1
C150
T8
2.2U_0603_6.3V4Z
PAD
C25
C24
HT_REFCLKP
HT_REFCLKN
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
T2
T1
GFX_REFCLKP
GFX_REFCLKN
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
Strap pin
<15>
+1.8VS
1
L9
2 BLM18PG121SN1D_0603
C8
AUX_CAL
+VDDA18PCIEPLL
1
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
A22
B22
A21
B21
B20
A20
A19
B19
< LVDS dual channel : channel 1 >
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
< LVDS dual channel : channel 2 >
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
+VDDLTP18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
+VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
PART 3 OF 6
+NB_PLLVDD
+NB_HTPVDD
<15,19,25,27,30,31,34> PLT_RST#
<20> NB_PWRGD
+1.8VS
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
+NB_PLLVDD A12
+NB_HTPVDD D14
B12
C141
2.2U_0603_6.3V4Z
F12
E12
F14
G15
H15
H14
CRT/TVOUT
+AVDD2
C144
PLL PWR
LVTM
+AVDD1
+AVDD1
1
PM
L3
2 BLM18PG121SN1D_0603
U3C
AVDD=100mA
CLOCKs
+3VS
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
E9
F7
G12
TMDS_HPD(NC)
HPD(NC)
D9
D10
SUS_STAT#(PWM_GPIO5)
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
D13
MIS.
+1.8VS
+VDDLTP18
C153
2.2U_0603_6.3V4Z
L8
BLM18PG121SN1D_0603 1
1
+1.8VS
+VDDLT18
C156
C157
0.1U_0402_16V7K 4.7U_0805_10V4Z
2
L10
BLM18PG121SN1D_0603 1
1
PAD T22
SUS_STAT# <15,20>
R84 1
< Strap option pin or gate side-port memory IO >
2 1.8K_0402_5%
AUX_CAL(NC)
880MR1@
RS780M_FCBGA528
C154
< Dedicated power for the DAC which can affect display quality >
2.2U_0603_6.3V4Z
+1.8VS
+1.8VS
R68
R366
2 300_0402_5% NB_PWRGD
2 1K_0402_1% CPU_LDT_REQ#
+1.8VS
R83
2.2K_0402_5%
C149
2
5
U2
Y
NB_LDTSTOP#
NC7SZ08P5X_NL_SC70-5
<7,19> LDT_STOP#
0.1U_0402_16V7K
1
R101
2
0_0402_5%
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet

E
12
of
52
U3D
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
V15
W14
MEM_CKP(NC)
MEM_CKN(NC)
AE12
AD12
SBD_MEM/DVO_I/F
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_COMPP(NC)
MEM_COMPN(NC)
880MR1@
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
+1.8VS
+1.1VS
B
RS780M_FCBGA528
Compal Secret Data
Issued Date
2009-02-12
Deciphered Date
2009-02-12
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet
13
of
52
0.1U_0402_16V7K
C1128
4.7U_0805_10V4Z
C185
0.1U_0402_16V7K
C190
0.1U_0402_16V7K
C186
0.1U_0402_16V7K
C192
0.1U_0402_16V7K
+VDDA18PCIE
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
< 1.8V IO transform power >

F9
G9
AE11
AD11
+1.8VS
1
C197
1U_0402_6.3V4Z
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
880MR1@
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD33_1(NC)
VDD33_2(NC)
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
880MR1@
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
C171
C172
10U_0805_10V4Z
10U_0805_10V4Z
C163
C1126
1
+
C1129
330U_2.5V_M
2
H11
H12
< 3.3V IO power >

+3VS
1
C198
0.1U_0402_16V4Z
C199
0.1U_0402_16V4Z
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
Compal Secret Data

2009-02-12
2009-02-12
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
AE10
AA11
Y11
AD10
AB10
AC10
A
+NB_CORE
1
Issued Date
VDD_CORE:GM=5A/PM=10A
RS780M_FCBGA528
GROUND
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
C162
+NB_CORE
< Core power >
U3F
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
C160
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
C189
4.7U_0805_10V4Z
0.1U_0402_16V7K
< 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
0_0805_5%
C181
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
330U_D2E_2.5VM
0.1U_0402_16V7K
+VDDHTTX
C178
C195
C177
C183
0.1U_0402_16V7K
C176
C196
C175
+1.1VS
10U_0805_10V4Z
0.1U_0402_16V7K
C184
+1.8VS
L15
10U_0805_10V4Z
2A
2
4.7U_0805_10V4Z
0.1U_0402_16V7K
< IO power for HyperTransport transmit interface >
0_0805_5%
C1127
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L14
0.1U_0402_16V7K
0.1U_0402_16V7K
2A
2
+1.1VS
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
C188
10U_0805_10V4Z
H18
G19
F20
E21
D22
B23
A23
C180
+VDDHTRX
C161
2 L44
0.1U_0402_16V7K
C170
0.1U_0402_16V7K
C169
C194
0.1U_0402_16V7K
C164
1U_0402_6.3V4Z
C193
0.1U_0402_16V7K
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805
C174
0.1U_0402_16V7K
+VDDA11PCIE
VDDA_12=2.5A
1U_0402_6.3V4Z
0_0805_5%
C179
< IO power for HyperTransport receive interface >
PART 5/6
C187
0.1U_0402_16V7K
C159
0.1U_0402_16V7K
C168
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
C173
0.1U_0402_16V7K
C167
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
1U_0402_6.3V4Z
L13
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
1U_0402_6.3V4Z
4.7U_0805_10V4Z
C166
J17
K16
L16
M16
P16
R16
T16
C182
2A
C165
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
U3E
+VDDHT
C191
< Digital IO power for HyperTransport interface >
0_0805_5%
0.1U_0402_16V7K
L11
0.1U_0402_16V7K
2A
2
+1.1VS
POWER
Rev
B
401871
Sheet

E
14
of
52
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K >
< VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >

Enables the Test Debug Bus using GPIO.
R92
3K_0402_5%
@ 2
R93
3K_0402_5%
<12> UMA_CRT_VSYNC
+3VS
1 : Disable (RX881, RS880)

0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
< RS880 use register to control PCI-E configure >
These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >
< RS880 SUS_STAT# >
Selects Loading of STRAPS from EPROM

1
<12> AUX_CAL
R85
150_0402_1%
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
<12,20> SUS_STAT#
@ 2
RS880:SUS_STAT#
D1
1 CH751H-40PT_SOD323-2
PLT_RST# <12,19,25,27,30,31,34>
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >
< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
RX881: Enables the Test Debug Bus using PCIE bus

<12> UMA_CRT_HSYNC
R94
3K_0402_5%
+3VS
1 : Disable ( Can still be enabled using nbcfg register access )

0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880)
0 : Enable (RS880)
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
15
of
52
+5VS
+R_CRT_VCC
D7
< CRT CONNECTOR >
+CRT_VCC
F1
2 1A_6VDC_MINISMDC110
2
1
1
@
RB491D_SOT23-3
C237
0.1U_0402_16V4Z
D19
DAN217_SC59 @
D20
DAN217_SC59 @
D21
DAN217_SC59
JCRT
+3VS
RED_L
RED
BLUE
R99
150_0402_1%
R98
150_0402_1%
L22
2 NBQ100505T-800Y-N_2P
RED_L
GREEN
L23
2 NBQ100505T-800Y-N_2P
GREEN_L
BLUE
L24
2 NBQ100505T-800Y-N_2P
BLUE_L
<35>
D_DDCDATA
GREEN_L
RED
R100
150_0402_1%
C239
6P_0402_50V8K
C240
6P_0402_50V8K
HSYNC
BLUE_L
+CRT_VCC
VSYNC
D_DDCCLK
C241
6P_0402_50V8K
C242
6P_0402_50V8K
C243
6P_0402_50V8K
C244
6P_0402_50V8K
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
16
17
GND
GND
2
@ SUYIN_070546FR015S263ZR
GREEN
<35>
<35>
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+CRT_VCC
2
2 0.1U_0402_16V4Z
R817
2 10K_0402_5%
R_HSYNC
<35,42> R_HSYNC
P
OE#
5
1
C245 1
D_HSYNC
L25 1
2 10_0402_5%
HSYNC
L26 1
2 10_0402_5%
VSYNC
U5
SN74AHCT1G125GW_SOT353-5
< SYNC SIGNAL >
+CRT_VCC
R_VSYNC
<35,42> R_VSYNC
P
OE#
5
1
C247
10P_0402_50V8J @
2
Y
C248
10P_0402_50V8J
D_VSYNC
4
U6
+CRT_VCC
+3VS
D_DDCDATA
C255
33P_0402_50V8K
R806
2K_0402_1%
Q32B
3 2N7002KDW_SOT363-6
R805
2K_0402_1%
2
CRT_DATA
1
<35> CRT_DATA
+3VS
R825
4.7K_0402_5%
R824
4.7K_0402_5%
< Display Data Channel >
+3VS
CRT_CLK
CRT_CLK
Q32A
6 2N7002KDW_SOT363-6
1
1
<35>
D_DDCCLK
1
C256
33P_0402_50V8K
C251
470P_0402_50V8J
1
@
C252
470P_0402_50V8J
FOR EMI
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
16
of
52
LCD/PANEL BD. Conn.
R90
100K_0402_5%
2
1
2
R91
2 47K_0402_5%
2N7002KDW_SOT363-6
0.1U_0402_16V7K
3
Q33A
Q4
+LCD_VDD
C260
AO3413_SOT23
0.01U_0402_25V7K
W=60mils
Inrush current = 0A
W=60mils
C259
6 2
150_0603_5%
R807
+3VS
+3VS
+LCD_VDD
C262
Q33B
5
2N7002KDW_SOT363-6
0.1U_0402_16V7K
ENVDD
<35> VGA_ENVDD
R3
10K_0402_5%
< LVDS Connector >
INT_MIC_DATA
<35>
<35>
<35>
<35>
<35>
<35>
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT1LCD_TXOUT2+
LCD_TXOUT2-
<35>
<35>
<35>
<35>
<35>
<35>
LCD_TZOUT0+
LCD_TZOUT0LCD_TZOUT1+
LCD_TZOUT1LCD_TZOUT2+
LCD_TZOUT2-
+LCD_INV
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
GND GMD
JLVDS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
D12
LCD_TXCLK+ <35>
LCD_TXCLK- <35>
LCD_TZCLK+ <35>
LCD_TZCLK- <35>
LCD_EDID_CLK
2.2K_0402_5% 2
1 R117
LCD_EDID_DATA
2.2K_0402_5% 2
1 R118
PACDN042Y3R_SOT23-3
0_0603_5%
W=20mils
R808 1
2
USB20_P9_L
USB20_N9_L
INT_MIC_CLK
2
+3VS_LVDS_CAM
+3VS
+3VS
0.1U_0402_16V4Z
1
2
C265
LCD_EDID_CLK <35>
LCD_EDID_DATA <35>
INT_MIC_CLK <28>
INT_MIC_DATA <28>
+3VS
INVT_PWM
+LCDVDD_R
BKOFF#_R
@ C152
680P_0402_50V7K
B+
+LCD_INV
C264
0.1U_0402_16V4Z
3
Rated Current MAX:3000mA

L45 2
1
FBMA-L11-201209-221LMA30T_0805
ACES_87242-4001-09
@
C268
68P_0402_50V8J
1
C263
0.1U_0402_25V6
C151
680P_0402_50V7K
33_0402_5% 2
R9
BKOFF# <30>
BKOFF#_R
R200
10K_0402_5%
2
1.5A
L20
USB20_P9
+LCDVDD_R
<30> EC_INVT_PWM
<20>
USB20_N9
EC_INVT_PWM
@
1
R96
2
0_0402_5%
1
R97
2
0_0402_5%
USB20_N9_L
USB20_P9_L
<35> VGA_INVT_PWM
INVT_PWM
<20>
R319
10K_0402_5%
+LCD_VDD
1
C266
0.1U_0402_16V7K
C267
4.7U_0805_10V4Z
WCM-2012-900T_0805
L12
1 0_0805_5%
@ C27
4
10P_0402_50V8J
@ R23 1
INT_MIC_CLK
4
10_0402_5%
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
17
of
52
H@
+5VS
H@ D11
F2
1 1.1A_6V_MINISMDC110F-2
1
2
RB161M-20_SOD123-2
+HDMI_5V_OUT
1
C22
H@
HDMI_TX0-
<35> HDMI_TXD0+
<35> HDMI_TXD0-
H@
H@
C272 1
C273 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX0+
HDMI_TX0-
H@
H@
C275 1
C276 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX1+
HDMI_TX1-
HDMI_R_D0-
HDMI_TX1-
L17
<35> HDMI_TXD1+
<35> HDMI_TXD1-
R121
0_0402_5%
HDMI_TX0+
R125
0_0402_5%
HDMI_R_D1-
L19
H@
OCE2012120YZF_0805
R122
0_0402_5%
HDMI_R_D0+
HDMI_TX1+
H@
OCE2012120YZF_0805
R126
0_0402_5%
< HDMI Connector >

JHDMI
HDMI_R_D1+
HDMI_HPD
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
H@
H@
<35> HDMI_TXD2+
<35> HDMI_TXD2-
C277 1
C274 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX2+
HDMI_TX2-
HDMI_TX2-
R123
0_0402_5%
HDMI_R_D2-
HDMI_CLK-
1
H@
H@
C278 1
C279 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
R127
0_0402_5%
HDMI_SDATA
HDMI_SCLK
HDMI_R_CKHDMI_R_CK-
L18
<35> HDMI_CLK0+
<35> HDMI_CLK0-
HDMI_CLK+
HDMI_CLK-
HDMI_TX2+
L16
1
4
H@
OCE2012120YZF_0805
0.1U_0402_16V7K
H@
R124
0_0402_5%
HDMI_R_D2+
HDMI_CLK+
HDMI_R_CK+
HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
OCE2012120YZF_0805
R128
0_0402_5%
HDMI_R_D1+
HDMI_R_D2HDMI_R_CK+
HDMI_R_D2+
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
@ SUYIN_100042MR019S153ZL
< Termination resistor >

2
< Close to Connector >

HDMI_R_CK+
H@
R102 1
2 499_0402_1%
HDMI_R_CK-
H@
R103 1
2 499_0402_1%
HDMI_R_D0-
H@
R104 1
2 499_0402_1%
HDMI_R_D0+
H@
R106 1
2 499_0402_1%
HDMI_R_D1-
H@
R108 1
2 499_0402_1%
HDMI_R_D1+
H@
R109 1
2 499_0402_1%
+3VS
<35> HDMIDAT_VGA
R53
2.2K_0402_5%
H@
H@
Q25
BSH111_SOT23-3
1
+HDMI_5V_OUT
H@
R827
4.7K_0402_5%
H@
R826
4.7K_0402_5%
+3VS
HDMI_SDATA
<35> HDMICLK_VGA
R54
2.2K_0402_5%
H@
2
H@
Q26
BSH111_SOT23-3
HDMI_SCLK
1
D
H@
R114 1
2 499_0402_1%
HDMI_R_D2-
H@
R116 1
2 499_0402_1%
+5VS
HDMI_HPD_R
+5VS
R120 1K_0402_5%
1
2
+3VS
HDMI_HPD
2
< Hot-plug detection & level shift >
Q34A
1
2N7002KDW_SOT363-6
HDMI_R_D2+
R110
H@
C281
H@
100K_0402_5%
0.1U_0402_16V4Z
H@ U7
HPD
R119
100K_0402_5%
<35>
0.1U_0402_16V4Z
P
OE#
5
1
C280
H@
R113
2.2K_0402_5%
H@
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
18
of
52
PLT_RST# <12,15,25,27,30,31,34>
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
AA22
Y21
AA25
AA24
W23
V24
W24
W25
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
1
8.2K_0402_5%
M23
P23
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
NB_REFCLK_P
NB_REFCLK_N
U29
U28
NB_DISP_CLKP
NB_DISP_CLKN
HT_REFCLKP
HT_REFCLKN
T26
T27
NB_HT_CLKP
NB_HT_CLKN
V21
T21
CPU_HT_CLKP
CPU_HT_CLKN
<34> CLK_PCIE_VGA
<34> CLK_PCIE_VGA#
H_PWRGD_L <49>
<25> CLK_PCIE_LAN
<25> CLK_PCIE_LAN#
V23
T23
SLT_GFX_CLKP
SLT_GFX_CLKN
L29
L28
GPP_CLK0P
GPP_CLK0N
<27> CLK_PCIE_MCARD2
<27> CLK_PCIE_MCARD2#
N29
N28
GPP_CLK1P
GPP_CLK1N
M29
M28
GPP_CLK2P
GPP_CLK2N
T25
V25
GPP_CLK3P
GPP_CLK3N
L24
L23
GPP_CLK4P
GPP_CLK4N
P25
M25
GPP_CLK5P
GPP_CLK5N
P29
P28
GPP_CLK6P
GPP_CLK6N
N26
N27
GPP_CLK7P
GPP_CLK7N
T29
T28
GPP_CLK8P
GPP_CLK8N
L25
14M_25M_48M_OSC
25M_CLK_X1
L26
25M_X1
25M_CLK_X2
L27
25M_X2
<12> CLK_SBSRC_BCLK
<12> CLK_SBSRC_BCLK#
<12> NB_REFCLK_P
<12> NB_REFCLK_N
+3VS
<12> HT_REFCLKP
<12> HT_REFCLKN
+1.8VS
1
3
Q21
FDV301N_NL_SOT23-3
level shift to ISL6265

ISL6265 PWROK input, TTL level: 0.8V~2.0V
When this pin is high, the SVI interface is

active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
25M_CLK_X1
2 27P_0402_50V8J
C648 1
<26> CLK_48M_CR
CLK_48M_CR_R
25MHZ_20PF_7A25000012
1
C639
25M_CLK_X2
27P_0402_50V8J
@ R332 20M_0402_5%
@R332
1
2
C582 1
20M_0603_5%
1
2
2
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
BT_PWR#
AJ6
AG6
AG4 BT_RST#
AJ4
BT_PWR# <27>
BT_DET# <27>
BT_RST# <27>
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
CLK_PCI_EC <23,30>
CLK_PCI_SIO <23,31>
NC
G21
H21
K19
G22
J24 R26
OSC
NC
C1
SB_32KHI
32K_X2
C2
SB_32KHO
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
D2
B2
B1
PAD
Close to SB
C94 @
3
T11
+RTCBATT
+RTCVCC
1
C585
2
1
R333
2
120_0402_5%
@
1
R129
2
120_0402_5%
1
R130
2
1K_0402_5%
J1
JUMP_43X39
C583
2008-09-25
2009-09-25
Deciphered Date
for Clear CMOS
Compal Secret Data
Title
Date:
+CHGRTC

SCHEMATIC,MB A6054
B
W=20mils
Issued Date
10P_0402_50V8J
D8
BAS40-04_SOT23-3
18P_0402_50V8J
CPU_LDT_REQ# <12>
H_PROCHOT# <7>
H_PWRGD <7,49>
LDT_STOP# <7,12>
LDT_RST# <7>
2 0_0402_5%
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
1 R42 @
10_0402_5%
SERIRQ <30,31>
C584
OSC
CLK_PCI_SIO
LPC_AD0 <30,31>
LPC_AD1 <30,31>
LPC_AD2 <30,31>
LPC_AD3 <30,31>
LPC_FRAME# <30,31>
32K_X1
Y3
4
<23>
<21,23>
<23>
<23>
<23>
<23>
<23>
SB_32KHI
C586 1
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
SB820M_FCBGA605
2 18P_0402_50V8J
R335
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
R112 0_0402_5%
R370
1M_0402_5%
Y5
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
CLOCK GENERATOR
R329
4.7K_0402_5%
H_PWRGD
<7> CLK_CPU_BCLK
<7> CLK_CPU_BCLK#
PCIE_CALRP
PCIE_CALRN
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
AD29
AD28
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
V2
<23>
<23>
<23>
<23>
0.1U_0402_16V4Z
U21
Y
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
PCIRST#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
1U_0402_6.3V4Z
A_RST#
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
1 590_0402_1%
1 2K_0402_1%
2
2
+3VALW
C581
@
2
R328
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
W2
W1
W3
W4
Y1
R326
R327
+1.1VS_PCIE
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
2
2
2
2
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1
1
1
1
1
1
1
1
Part 1 of 5
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
C579
C573
C574
C575
C576
C580
C577
C578
SB800
PCIE_RST#
A_RST#
PCI INTERFACE
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
P1
L1
RTC
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
U8A
33_0402_5%
1
LPC
R325
2
CPU
2 150P_0402_50V8J
A_RST#
PCI CLKS
C572 1
PCI EXPRESS INTERFACES
Rev
B
401871
Sheet

E
19
of
52
U8D
A13
B13
USB20_P9
USB20_N9
USB_HSD8P
USB_HSD8N
D13
C13
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G12
G14
USB_HSD6P
USB_HSD6N
G16
G18
USB20_P6
USB20_N6
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_HSD2P
USB_HSD2N
J16
J18
USB20_P2
USB20_N2
USB_HSD1P
USB_HSD1N
B17
A17
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
A16
B16
USB20_P0
USB20_N0
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
D25
F23
B26
E26
F25
E22
F22
E21
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
G24
G25
E28
E29
D29
D28
C29
C28
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
10_0402_5%
@C147
@
C147 2
1 10P_0402_50V8J
@C223
@
C223 2
110P_0402_50V8J
USB_OC#0
<29,30> USB_OC#0
AZ_BITCLK_HD
<28> AZ_BITCLK_HD
<31> HDA_BITCLK_MDC
HDA_BITCLK_MDC
<28> AZ_SDOUT_HD
<31> HDA_SDOUT_MDC
<23> HDA_SDOUT
AZ_BITCLK_HD
<28> AZ_SDIN0_HD
<31> HDA_SDIN1
<28> AZ_SYNC_HD
<31> HDA_SYNC_MDC
<31> HDA_RST#_MDC
<28> AZ_RST_HD#
R345
R136
R346
R138
1
1
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
R347
R142
R348
R144
1
1
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
GBE_COL
GBE_CRS
+3VALW
3
GBE_MDIO
1
R352
1
R358
1
R353
1
R354
1
R356
GBE_MDIO
10K_0402_5%
GBE_PHY_INTR
10K_0402_5%
GBE_COL
10K_0402_5%
GBE_CRS
2
10K_0402_5%
GBE_RXERR
2
10K_0402_5%
2
2
GBE_RXERR
+3VALW
GBE_PHY_INTR
CIR_EN#
R95
10K_0402_5%
1
+3VALW
M3
N1
L2
M2
M1
M4
N2
P2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
E23
E24
F21
G29
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
D27
F28
F29
E27
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
CIR_EN#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SMB_CK_CLK1
2
2.2K_0402_5%
SMB_CK_DAT1
2
2.2K_0402_5%
USB-4 Card Reader (3 IN 1)
USB20_P2 <24>
USB20_N2 <24>
USB-2 USB/eSATA
USB20_P1 <29>
USB20_N1 <29>
USB-1 Right side
USB20_P0 <29>
USB20_N0 <29>
USB-0 Right side
EHCI1 / OHCI1
<Wake Up support>
+3VALW
@ R73
10K_0402_5%
GPIO199
GPIO200
<23>
<23>
STRAP PIN
GPIO201
GPIO202
GPIO203
GPIO204
GPIO205
GPIO201
GPIO202
GPIO203
@ R75
@R75
10K_0402_5%
R74
1K_0402_1%
R77
1K_0402_1%
GPIO201
GPIO202
GPIO203
High
High
High
Nile-M
High
High
Low
Nile-S
Low
Low
Low
Danube Marseille
Low
Low
High
Danube Hamburg
GPIO204
GPIO205
Low
Low
Madison LP
Low
High
None
High
Low
Park XT
High
High
M92-XTX
Nile
Danube
R78
10K_0402_5%
@ R79
@R79
10K_0402_5%
R115 CIR@
1K_0402_1%
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
@ R56
10K_0402_5%
MADISON@
R55
1K_0402_1%
MANHA@
R57
1K_0402_1%

SCHEMATIC,MB A6054
Date:
+3VALW
4PCS@
R51
10K_0402_5%
GPIO204
GPIO205
A
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363
USB-6 Bluetooth
USB20_P5 <26>
USB20_N5 <26>
USB20_P6 <27>
USB20_N6 <27>
EHCI2 / OHCI2
SB_SIC
SB_SID
SB820M_FCBGA605
EC_LID_OUT#
USB-8 WLAN
USB-9 Int Camera
USB20_P8 <27>
USB20_N8 <27>
EMBEDDED CTRL
1 10P_0402_50V8J
EMBEDDED CTRL
@ R80
@C143
@
C143 2
HD AUDIO
USB_OC#2
<24,30> USB_OC#2
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
GBE LAN
<30> EC_LID_OUT#
H3
D1
E4
D4
E8
F7
E7
F8
USB OC
EC_LID_OUT#
USB20_P9 <17>
USB20_N9 <17>
R107
10K_0402_5%
USB_HSD9P
USB_HSD9N
HDMI_DET
J12
J14
CLK_REQ4#/SATA_IS0#/GPIO64
SMARTVOLT1/SATA_IS2#/GPIO50
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
<27> CLKREQ_MCARD2#
USB_HSD10P
USB_HSD10N
RSMRST#
EHCI13 / OHCI3
2
R105
10K_0402_5%
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1
E14
E12
<28> PCH_SPKR
<9,10> SMB_CK_CLK0
<9,10> SMB_CK_DAT0
<27> SMB_CK_CLK1
<27> SMB_CK_DAT1
+3VS
USB_HSD11P
USB_HSD11N
<25> CLKREQ_LAN#
F11
E11
SUS_STAT#
G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
USB_HSD12P
USB_HSD12N
2 4.7K_0402_5%
HDMI_DET
B12
A12
R344 1
EC_RSMRST#
<30> EC_RSMRST#
USB_HSD13P
USB_HSD13N
2 2.2K_0402_5% SMB_CK_DAT0
H9
J8
2 2.2K_0402_5% SMB_CK_CLK0
R343 1
USB_FSD0P/GPIO185
USB_FSD0N
OHCI4
R342 1
J10
H11
2
R338
<7> H_THERMTRIP#
<12> NB_PWRGD
+3VS
H@
H_THERMTRIP#
NB_PWRGD
USB_FSD1P/GPIO186
USB_FSD1N
T20
<25> EC_SWI#
USB_RCOMP 1
11.8K_0402_1%
EC_RSMRST#
2
2.2K_0402_5%
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
SB800
PAD
G19
1
R339
<30>
<30>
<30>
<30>
PAD
PAD
PAD
A10
USB_RCOMP
USB 1.1 USB MISC
T14
T12
T13
USBCLK/14M_25M_48M_OSC
USB 2.0
SUS_STAT#
ACPI / WAKE UP EVENTS
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
GPIO
<30>
<30>
<30>
<30>
<12,15>
J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19
Rev
B
401871
Sheet

E
20
of
52
U8B
SATA_STX_DRX_P1
SATA_STX_DRX_N1
<24> SATA_STX_DRX_P1
<24> SATA_STX_DRX_N1
ODD
<24> SATA_RXN1_C
<24> SATA_RXP1_C
SATA_STX_DRX_P3
SATA_STX_DRX_N3
eSATA
<24> SATA_RXN3_C
<24> SATA_RXP3_C
R364 2
R365 2
+1.1VS_SATA
1 1K_0402_1% SATA_CALRP
1 931_0402_1% SATA_CALRN
<32> SATA_LED#
+3VS
R367 1
2 27P_0402_50V8J
SATA_X2
1
2
DO
DI
CLK
CS#
SATA_X2
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
AB14
AA14
SATA_CALRP
SATA_CALRN
AD11
SATA_ACT#/GPIO67
AD16
SATA_X1
AC16
SATA_X2
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
A3
B4
A4
C5
A7
B7
B8
A8
R43
2 150K_0402_5% +3VALW
1 D22
CH751H-40PT_SOD323-2
ACIN
<30,32,43>
MEM_1V5
J5
E2
K4
K9
G2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
NC1
NC2
G27
Y2
SB820M_FCBGA605
+3VALW
U47
20mils
SATA_TX2P
SATA_TX2N
AH28
AG28
AF26
@ R368
10M_0402_5%
27P_0402_50V8J
SATA_RX1N
SATA_RX1P
AG12
AF12
SPI ROM
2
1
@C589
@
C589
AG10
AF10
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
@
Y4
SATA_TX1P
SATA_TX1N
SATA_X1
25MHZ_20PF_7A25000012
1
SATA_RX0N
SATA_RX0P
AH10
AJ10
Part 2 of 5
2 10K_0402_5%
SATA_X1
@C588
@
C588 1
AJ8
AH8
FLASH
<24> SATA_RXN0_C
<24> SATA_RXP0_C
SATA_TX0P
SATA_TX0N
HW MONITOR
HDD
SB800
AH9
AJ9
SERIAL ATA
SATA_STX_DRX_P0
SATA_STX_DRX_N0
VCC
C445
0.1U_0402_16V4Z
HOLD
CS#
CLK
DI
VSS
DO
MX25L1605DM2I-12G_SO8-200mil
2
MEM_1V5 is for gating the

glitch on PCI_AD24
Socket: SP07000F500 & SP07000H900
R86
10_0402_5%
@
+3VS
@ C688
2
1
<19,23> PCI_AD24
1
@R422
@
R422
2
2
0_0402_5%
1 @
R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
@U23
@
U23
Y
C155
10P_0402_50V8J
@
MEM_1V5
0.1U_0402_16V4Z
1
1
@ R424
2
33_0402_5%
VDDR_SW <48>
2
2
0_0402_5%
@ C689
150P_0402_50V8J
4
For VDDR Voltage Switch, AMD suggest

Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet

E
21
of
52
U8E
+1.1VS_VDDC
510mA
1
R369
U8C
71mA
AF22
AE25
AF24
AC22
2
0_0402_5%
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
POWER
43mA
AE28
+VDDPL_3V_PCIE
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
C604
C605
C606
C607
1
1
1
1
2
2
2
2
600mA
+VDDPL_3V_SATA
+1.1VS
1
1
1
1
1
2
2
2
2
2
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AD14
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
C625 2
C626 2
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
200mA
C11
D11
CORE S0
1
2
2
2
2
22U_0805_6.3V6M
M10
C590
1
1
1
1
C596
C594
C597
C598
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V1
L69
2
1
FBMA-L11-201209-221LMA30T_0805
1
R372
1
R373
2
0_0402_5%
2
0_0402_5%
L7
L9
1
R374
2
0_0402_5%
VDDIO_GBE_S_1
VDDIO_GBE_S_2
M6
P8
1
R375
2
0_0402_5%
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
A21
D21
B21
K10
L10
J9
T6
T8
VDDCR_11_S_1
VDDCR_11_S_2
F26
G26
VDDIO_AZ_S
M8
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
A11
B11
VDDPL_33_SYS
M21
VDDPL_11_SYS_S
L22
VDDPL_33_USB_S
F19
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
+1.1VS_CKVDD
400mA
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
CORE S5
2
2
2
2
2
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
PLL
1
1
1
1
1
658mA
USB I/O
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
C617
C618
C619
C620
C621
K28
K29
J28
K26
J21
J20
K21
J22
10U_0805_10V4Z
+1.1VS
2
2
2
2
+1.1VS
C595
External Clock, connect to +1.1VS

directly, no need thick trace
1
1
1
1
C600
C601
C602
C603
check can be removed?
D6
L20
32mA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
1
2
2
C608
C609
+1.1VALW
C615 2
C616 2
113mA
TBD
+VDDIO_AZ
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
47mA
+VDDPL_3V
C623
C624
+VDDPL_11V
17mA
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
2
2
+VDDPL_3V_USB
5mA
197mA
+3V_HWM
+3VALW
+VDDLX_3V
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z
Need to Check
SB820M_FCBGA605
SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
Y4
EFUSE
D8
VSSAN_HWM
M19
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
M20
VSSPL_SYS
+1.1VALW
+VDDCR_USB
197mA
62mA
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
Need to Check
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
+3VALW
check 220ohm bead
+3VALW
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
2
0_0805_5%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
93mA
+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
C610
C611
C612
C613
C614
N13
R15
N17
U13
U17
V12
V18
W12
W18
VDDIO_33_GBE_S
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDRF_GBE_S
3.3V_S5 I/O
1
R371
PCI/GPIO I/O
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLKGEN I/O
2
2
2
GBE LAN
1
1
1
FLASH I/O
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
SERIAL ATA
C591
C592
C593
C599
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
PCI EXPRESS
131mA
+3VS
GROUND
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
Part 5 of 5
SB820M_FCBGA605
+VDDPL_11V
+VDDPL_3V_PCIE
+3VS
+VDDPL_3V
+VDDPL_3V_USB
L76
2
1
FBMA-L11-160808-221LMT 0603
L80
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
0.1U_0402_16V4Z
2
1
FBMA-L11-160808-221LMT 0603
1
C634
2.2U_0603_6.3V4Z
+VDDPL_3V_SATA
+3VS
+3V_HWM
+3VALW
L77
2
1
C628
+3VALW
+3VS
L79
C635
2.2U_0603_6.3V4Z
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
L78
2
1
FBMA-L11-160808-221LMT 0603
1 0_0603_5%
C632
C631
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
C633
2.2U_0603_6.3V4Z
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
C637
2.2U_0603_6.3V4Z
1
R376
1
R52
2
2
0_0402_5% +1.5VS
0_0402_5%
@
C638
2.2U_0603_6.3V4Z
For 3V AZ device
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
22
of
52
REQUIRED STRAPS
AZ_SDOUT
PCI_CLK1
PCI_CLK2
PCI_CLK3
USE
DEBUG
STRAP
PCI_CLK4
Inter CLK
Gen Mode
LPC_CLK0
LCP_CLK1
GPIO200
EC
ENABLE
CLOCKGEN
ENABLE
H,H = Reserved
DEFAULT
H,L = SPI ROM (Default )
CLOCKGEN
DISABLE
L,H = LPC ROM

L,L = FWH ROM
Enable
DEFAULT
+3VS
EC
DISABLE
DEFAULT
+3VS
+3VALW
+3VALW
+3VALW
R393
2.2K_0402_5%
2
1
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
PCI_AD23
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
<19>
<19>
<19>
<19>
<19>
<19,21>
<19>
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
check default
R401
2.2K_0402_5%
2
1
PCI_AD24
R400
2.2K_0402_5%
2
1
PCI_AD25
R399
2.2K_0402_5%
2
1
PCI_AD26
R397
2.2K_0402_5%
2
1
PCI_AD27
+3VS
R396
10K_0402_5%
2
1
R395
10K_0402_5%
2
1
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
R394
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
R386
10K_0402_5%
2
1
+3VS
PULL
HIGH
+3VALW
Disable
<20> HDA_SDOUT
<19>
PCI_CLK1
<19>
PCI_CLK2
<19>
PCI_CLK3
<19>
PCI_CLK4
<19,30> CLK_PCI_EC
<19,31> CLK_PCI_SIO
<20>
GPIO200
<20>
GPIO199
GPIO199
R385
2.2K_0402_5%
2
1
+3VS
Inter CLK
Gen Mode
R384
10K_0402_5%
2
1
+3VS
R380
10K_0402_5%
2
1
DEFAULT
R379
10K_0402_5%
2
1
DEFAULT
R378
10K_0402_5%
2
1
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
IGNORE
DEBUG
STRAP
R383
10K_0402_5%
2
1
DEFAULT
WATCHDOG
TIMER
DISABLE
R382
10K_0402_5%
2
1
FORCE PCIE
GEN1
R381
10K_0402_5%
2
1
Performance
MODE
PULL
LOW
Check Internal PU/PD
LOW POWER ALLOW PCIE WATCHDOG

MODE
GEN2
TIMER
ENABLE
PULL
HIGH
R398
2.2K_0402_5%
2
1
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
23
of
52
< SATA HDD Conn >
+3VS
Place closely JHDD SATA CONN.

1
C201
10U_0805_10V4Z
C202
0.1U_0402_16V7K
JODDB
+3VS rail reserve for SSD

1
C203
0.1U_0402_16V7K
C204
0.1U_0402_16V7K
C205
@
@
10U_0805_10V4Z
C206
C207
@
2
0.1U_0402_16V7K
C208
@
2
0.1U_0402_16V7K
0.1U_0402_16V7K
JHDD
GND
A+
AGND
BB+
GND
24
23
2
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
< SATA ODD Conn >
+5VS
1.2A
SATA_TXP0
SATA_TXN0
C209 1
C210 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
C211 1
C212 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
GND
GND
12
11
10
9
8
7
6
5
4
3
2
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+5VS
C225
1
0.1U_0402_16V7K
SATA_IRX_DTX_P1
SATA_IRX_DTX_N1
C213
C214
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_TXN1
SATA_TXP1
C215
C216
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_RXP1_C <21>
SATA_RXN1_C <21>
SATA_STX_DRX_N1 <21>
SATA_STX_DRX_P1 <21>
ACES_88058-120N
SATA_STX_DRX_P0 <21>
SATA_STX_DRX_N0 <21>
@
SATA_RXN0_C <21>
SATA_RXP0_C <21>
+3VS
+5VS
@ SUYIN_127072FR022G210ZR_RV
eSATA/USB Conn
+USB_VCCB
2A
3
1
2
3
4
+5VALW
<29,30> USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
+USB_VCCB
W=60mils
W=60mils
U11
8
7
6
5
@C373
@
C373 1
2 4.7U_0805_10V4Z
C376
C377
C378
@ D14
2
USB_OC#2 <20,30>
G547E2P11U_SO8
220U_6.3V_M
0.1U_0402_16V7K
1000P_0402_50V7K
3
PJDLC05_SOT23-3
JESATA
1
2
3
4
USB20_N2_R_S
USB20_P2_R_S
Reserve for EMI request

@ R196 1
2 0_0402_5%
WCM-2012-900T_0805
<20> USB20_N2
USB20_N2_R_S
<20> USB20_P2
4
L33
USB20_P2_R_S
C379 1
C380 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_TXP3
SATA_TXN3
<21> SATA_RXN3_C
<21> SATA_RXP3_C
C381 2
C382 2
1 0.01U_0402_25V7K
1 0.01U_0402_25V7K
SATA_RXN3
SATA_RXP3
VBUS
DD+
GND
USB
5
6
7
8
9
10
11
GND
A+
ESATA
AGND
BB+
GND
12
13
14
15
GND
GND
GND
GND
@ TYCO_1759576-1
1
@R198
@
R198
2
0_0402_5%
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet

E
24
of
52
UL1
<11> PCIE_PTX_C_IRX_P3
CL1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P3
22
HSOP
<11> PCIE_PTX_C_IRX_N3
CL2
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N3
23
HSON
17
18
<11> PCIE_ITX_C_PRX_P3
<11> PCIE_ITX_C_PRX_N3
RL19
<20> CLKREQ_LAN#
0_0402_5% 16
31
37
40
LAN_SK_LINK#
LAN_ACTIVITY#
HSIP
HSIN
EECS/SCL
EEDI/SDA
30
32
RL2
RL1
CLKREQB
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
+LAN_REGOUT
1 10K_0402_5%
1 10K_0402_5%
2
2
1
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
2
200mil to LL1
+LAN_REGOUT: Width =60mil
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
DVDD33
DVDD33
27
39
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
33
ENSWREG
EVDD10
21
+LAN_EVDD10
0.1U_0402_16V4Z
34
35
VDDREG
VDDREG
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
0.1U_0402_16V4Z
REGOUT
36
EC_SWI#
+3VS
+3V_LAN
1 RL22
2 1K_0402_5%
ISOLATEB
ENSWREG
+LAN_VDDREG
RL7
15K_0402_5%
1
RL5
2
2.49K_0402_1%
46
RSET
24
49
GND
PGND
+LAN_VDD10
+LAN_VDD10
+3V_LAN
1
LL2
CL18
1U_0402_6.3V4Z
+3V_LAN
+3V_AVDDXTAL
+3V_AVDDXTAL
CL29
0.1U_0402_16V4Z
1
+LAN_VDD10
LAN_ACTIVITY#
RL10 1
150_0402_5%
+3V_LAN
CL15
4.7U_0805_10V4Z
@
CL8
2
1
1U_0402_6.3V4Z
CL26
27P_0402_50V8J
2
CL27
27P_0402_50V8J
1
1
12
Amber LEDAmber LED+
SHLD4
16
PR4-
SHLD3
15
SHLD2
14
SHLD1
13
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
LAN_X2
25MHZ_20PF_7A25000012
1
11
2
1
RL17 150_0402_5%
8
RJ45_MIDI1-
LAN_X1
LAN_ACTIVITY#_R
YL1
2
CL19
2
CL20
2
CL21
2
CL22
JLAN
CL11 close to pin42
+3V_LAN
LAN Conn.
+3V_LAN
WOL_EN#
RL23
0_0402_5%
@
1
1
2
2
RL16
47K_0402_5%
1
AO3413_SOT23
CL14
0.01U_0402_25V7K
CL11
0.1U_0402_16V4Z
2
3
QL1
<30>
ENSWREG
+LAN_VDD10
0.1U_0402_16V4Z
CL19,CL20,CL21,CL22 close to
Pin 3,13,29,45
1
LL3
Reserved For 1.05V Crystal
Vgs=-4.5V,Id=3A,Rds<97mohm
+LAN_VDDREG
2
0_0603_5%
+LAN_REGOUT
RL9
@ 0_0402_5%
RL4
0_0402_5%
CL17
0.1U_0402_16V4Z
1
+3V_LAN
0_0402_5%
+3VALW
0.1U_0402_16V4Z
RL8
+3VALW
Close to Pin 21
CL28
4.7U_0603_6.3V6K
+3V_LAN
+LAN_EVDD10
2
0_0603_5%
RTL8105E-GR QFN _6X6
+3VALW TO +3V_LAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ISOLATEB
PERSTB
2
CL4
2
CL5
2
CL6
2
CL7
0.1U_0402_16V4Z
REFCLK_P
REFCLK_N
<20> EC_SWI#
CL12
0.1U_0402_16V7K
0.1U_0402_16V4Z
CL9
0.1U_0402_16V4Z
19
20
RL25
100K_0402_5%
25
2 EC_SWI#
100K_0402_5%
+3V_LAN
1
2
2.2UH +-5% NLC252018T-2R2K-N
PLT_RST#
+3V_LAN
RL6
1K_0402_1%
CL4,CL5,CL6,CL7 close to
Pin 27,39,47,48
+LAN_VDD10
LL1
<19> CLK_PCIE_LAN
<19> CLK_PCIE_LAN#
<12,15,19,27,30,31,34>
1
RL3
LED3/EEDO
LED1/EESK
LED0
2
LAN_SK_LINK#
2 RL14
1
150_0402_5%
LAN_SK_LINK#_R
2
+3V_LAN
10
Green LED-
Green LED+
LIYO_101005-00803-3
@
RL18 150_0402_5%
RJ45_GND
1
CL36
LANGND
2 1000P_1808_3KV7K
1
CL37
CL38
UL3
LAN_MDI0+
LAN_MDI0-
1
2
3
4
5
6
7
8
LAN_MDI1+
LAN_MDI1-
Place these components

colsed to LAN chip
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0-
CL42 1000P_0402_50V7K
2
1
CL41 1000P_0402_50V7K
2
1
RJ45_MIDI1+
RJ45_MIDI1-
1
RL15
2
75_0402_1%
1
RL13
2
75_0402_1%
4.7U_0603_6.3V6K
RJ45_GND
Compal Secret Data

2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
Date:
CL34
0.1U_0402_25V4K
0.1U_0402_16V4Z
LF-H1201P-2
TD+
TDCT
NC
NC
CT
RD+
RD-
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

1
25
of
52
@ CC1
1
2 100P_0402_50V8J
RC1
6.19K_0402_1%
2
1
UC1
+3VS
1
RC4
<20>
<20>
2
0_0603_5%
USB20_N5
USB20_P5
+VCC_3IN1
4.7U_0805_10V4Z
V1_8
1 CC4
0.1U_0402_16V4Z
1
CC2
1U_0402_6.3V4Z
2
SDWP_MSCLK
2
MSCD#
SD_DATA1
SD_DATA0
MS_DATA3_SD_DATA7
REFE
2
3
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
8
9
10
11
12
SP1
SP2
SP3
SP4
SP5
25
CC3
EPAD
+3VS_CR
USB20_N5
USB20_P5
GPIO0
17
CR_LED#
CLK_IN
24
CLK_48M_CR
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
CR_LED# <32>
CLK_48M_CR <19>
< 48MHz >
MSBS
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
SDCMD
MS_DATA0_SD_DATA5
MS_DATA2_SDCLK
SDCD#
RTS5138-GR_QFN24_4X4
< 3 in 1 Card Reader >

JREAD
22
23
B
SDWP_MSCLK
SD_DATA1
SD_DATA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
GND1 SD-DAT2
GND2
SD-CD
MSBS
MS_DATA2_SDCLK
MS_DATA1_SD_DATA3
MS_DATA0_SD_DATA5
+VCC_3IN1
1
MSCD#
MS_DATA3_SD_DATA7
SDCMD
CC5
0.1U_0402_16V4Z
CC6
1U_0402_6.3V4Z
SD_DATA2_MS_DATA5
SDCD#
B
@TAITW_R009-025-LR_NR
@ CC7
10P_0402_50V8J
@ CC8
10P_0402_50V8J
@ RC21
MS_DATA2_SDCLK
10_0402_5%
@ RC31
SDWP_MSCLK
10_0402_5%
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet

1
26
of
52
< BlueTooth Interface, USB port6 >
< Bluetooth Connector >
+3VS
(MAX=200mA)
+3VS
+BT_VCC
1
2
BT@R201
BT@R201
2 47K_0402_5%
Q27
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
@ ACES_87213-0600G
BT@C386
BT@C386
0.01U_0402_25V7K
BT_PWR#
C487
BT@
@ R50
0_0603_5%
BT@
<19>
BT@C383
BT@C383
0.1U_0402_16V7K
100K_0402_5%
C488
BT@
R199
1
<20>
<20>
USB20_P6
USB20_N6
1 <19>
BT_DET#
AO3413_SOT23
<19>
BT_RST#
BT@
R442 1
2 0_0402_5%
+BT_VCC
C489
Inrush current = 0A
0.1U_0402_16V4Z
1
2
3
4
5
6
USB20_P6
USB20_N6
BT@
1
2
3
4
5 G1
6 G2
JBT
7
8
< PCIe Mini Card for WLAN >

+1.5VS
+3VS
CM1
0.01U_0402_25V7K
CM2
0.1U_0402_16V4Z
CM3
4.7U_0805_10V4Z
CM4
0.01U_0402_25V7K
CM5
0.1U_0402_16V4Z
CM6
4.7U_0805_10V4Z
+1.5VS
+3VS
JWLAN
3
BT_CTRL
BT_CRTL
BT
on module
BT
on module
Enable
Disable
HI
1
BT_PWR#
<20> CLKREQ_MCARD2#
D
<19> CLK_PCIE_MCARD2#
<19> CLK_PCIE_MCARD2
Q8
2
G
2N7002_SOT23-3
<11> PCIE_PTX_C_IRX_N2
<11> PCIE_PTX_C_IRX_P2
<11> PCIE_ITX_C_PRX_N2
<11> PCIE_ITX_C_PRX_P2
LO
+3VS
BT_PWR#
LO
HI
<30>
<30>
E51_TXD
E51_RXD
E51_TXD
E51_RXD
RM1
RM2
2 0_0402_5%
2 0_0402_5%
1
1
E51_TXD_R
E51_RXD_R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
PLT_RST#
WL_OFF# <30>
PLT_RST# <12,15,19,25,30,31,34>
SMB_CK_CLK1
SMB_CK_DAT1
SMB_CK_CLK1 <20>
SMB_CK_DAT1 <20>
USB20_N8
USB20_P8
USB20_N8 <20>
USB20_P8 <20>
FOX_AS0B226-S40N-7F
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
27
of
52
Codec
0.1U_0402_16V4Z
1
1
CA57
+DVDD_IO
2
CA1
CA7
10U_0805_10V4Z
2
2
MIC1_R_R
2
4.7U_0805_10V4Z
CA29
MIC1_L
MIC1_R
16
17
MIC2_L
MIC2_R
25
46
LINE2_L
LINE2_R
PVDD2
39
LINE1_L
LINE1_R
21
22
PVDD1
DVDD
MIC1_R_L
CA23
1
14
15
UA1
40
41
SPK_OUT_R+
SPK_OUT_R-
45
44
HP_OUT_L
HP_OUT_R
32
33
<17> INT_MIC_DATA
1
2
3
RA20 FBMA-L10-160808-301LMT_2P
4
<30> EC_MUTE#
<20> AZ_RST_HD#
MONO_IN
2
100P_0402_50V8J
1
CA12
SENSE_A
PCBEEP
18
1
2
CA15
2.2U_0603_6.3V4Z
+MIC1_VREFO_L
CA47 1
2 0.1U_0603_50V7K
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
2 0.1U_0603_50V7K
1
RA18
Sense Pin
PD#
RESET#
13
CA5
CA6
place close to chip
SPKL+
SPKL-
<29>
<29>
SPKR+
SPKR-
<29>
<29>
RA4
75_0402_1%
RA5
75_0402_1%
HP_L
<29>
HP_R
<29>
CBP
35
CBN
31
MIC1_VREFO_L
6
5
SDATA_IN
EAPD
47
SPDIFO
48
MONO_OUT
20
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
SENSE B
PVSS2
PVSS1
DVSS2
DVSS1
AZ_SYNC_HD
Beep sound
EC Beep
<20>
AZ_BITCLK_HD <20>
<30>
EC_BEEP#
RA7
1
2
47K_0402_5%
AZ_SDOUT_HD <20>
AZ_SDIN0_HD_R
2
RA6
1
33_0402_5%
AZ_SDIN0_HD
PCI Beep
<20>
<20> PCH_SPKR
CA13
1
2
RA8
1
2
47K_0402_5%
MONO_IN
0.1U_0402_16V4Z
1
RA12
10K_0402_5%
+MIC1_VREFO_R CA28 10U_0805_10V4Z
1
2
VREF
27
AC_VREF
JDREF
19
AC_JDREF2 RA9
CPVEE
34
1
CA14
AVSS1
AVSS2
26
37
CA18
0.1U_0402_16V4Z
1 20K_0402_1%
1
2
2.2U_0603_6.3V4Z
CA17
2
2
0.1U_0402_16V4Z
@
CA16
10U_0805_10V4Z
ALC259-GR_QFN48_7X7
DGND
AGND
2
0_0603_5%
Impedance
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
place close to chip

<29> MIC_SENSE
SENSE A
CA4
10
SDATA_OUT
SENSE A
36
43
42
49
7
BCLK
GPIO1/DMIC_CLK
12
CA3
GPIO0/DMIC_DATA
11
0.1U_0402_16V4Z
+5VS
1
1
CA62
@
@
CA58
2
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VS
0_0603_1%
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
SPK_OUT_L+
SPK_OUT_L-
SYNC
<17> INT_MIC_CLK
RA11
2
1
0_0603_1%
@
CA63
2
10U_0805_10V4Z
68 mA
23
24
<29>
@
0.1U_0402_16V4Z
2
+AVDD
4.7U_0805_10V4Z
2
2
10U_0805_10V4Z
place close to chip
<29>
35 mA
2
1
0_0603_1%
place close to chip
+PVDD2
1
CA61
0.1U_0402_16V4Z
CA8
Ext. Mic
2
10U_0805_10V4Z
+3VS_DVDD
DVDD_IO
+3VS
10U_0805_10V4Z
2
2
RA17
+5VS
CA43
CA2
@ RA19
2
1
0_0603_1%
38
+1.5VS
JA1
JUMP_43X39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CA44
CA56
AVDD2
RA1
2
1
0_0603_1%
AVDD1
+3VS
RA2
2
1
0_0603_1%
600 mA
+PVDD1
<29>
5.1K
NBA_PLUG
2
RA10
1
20K_0402_1%
RA21
39.2K_0402_1%
SENSE_A
(PIN 48)
39.2K
SENSE B
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 20)
Compal Secret Data
2009-02-12
Issued Date
Deciphered Date
2009-02-12
Title
Custom
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
1
28
of
52
HeadPhone/LINE Out JACK
Speaker Connector
placement near Audio Codec
<28>
SPKL+
SPKL+
LA2
2 FBMA-L11-160808-800LMT_2P
1
CA22
@ 10U_0805_10V4Z
2
DA9
<28>
SPKL-
<28>
SPKR+
SPKLLA3
SPK_L1
CA24
1U_0402_6.3V4Z
@
1
CA21
@ 10U_0805_10V4Z
2
2
FBMA-L11-160808-800LMT_2P
1
2
PACDN042Y3R_SOT23-3
SPK_R1
SPK_R2
SPK_L1
SPK_L2
SPK_L2
JSPK
1
2
3
4
DA6
SPKR+ LA4
2 FBMA-L11-160808-800LMT_2P
1
CA25
@ 10U_0805_10V4Z
2
<28>
SPKR-
SPKRLA5
<28> MIC1_R_R
USB_EN#
@ C446 1
8
7
6
5
<20>
USB20_N0
MIC1_L
RA25
1
2.2K_0402_5%
+MIC1_VREFO_L
JUSBB
W=80mils
USB_OC#0 <20,30>
L34
+MIC1_VREFO_R
MIC1_R
+USB_VCCA
USB20_N0_R
USB20_P0_R
USB20_P0
RA22
1
2.2K_0402_5%
2 4.7U_0805_10V4Z
G547E2P11U_SO8
<20>
Audio & USB Sub-Board Conn.
W=60mils
2A
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
2
1
1K_0402_5%
RA24
<28> MIC1_R_L
+USB_VCCA
1
2
3
4
RA23
1K_0402_5%
2
1
PACDN042Y3R_SOT23-3
+5VALW
<24,30> USB_EN#
CA27
1U_0402_6.3V4Z
1
@
1
CA26
@ 10U_0805_10V4Z
2
SPK_R2
2
FBMA-L11-160808-800LMT_2P
U25
Ext.MIC/LINE IN JACK
ACES_85204-0400N
@
SPK_R1
1
2
3
4
USB20_P0_R
USB20_N0_R
USB20_N1_R
USB20_P1_R
<28>
<28>
WCM-2012-900T_0805
HP_R
HP_L
<28> NBA_PLUG
<28> MIC_SENSE
HP_R
HP_L
AGND
MIC1_L
MIC1_R
NBA_PLUG
MIC_SENSE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
@ ACES_85201-20051
L35
<20>
USB20_P1
USB20_P1_R
<20>
USB20_N1
USB20_N1_R
WCM-2012-900T_0805
Compal Secret Data
Issued Date
2009-02-12
Deciphered Date
2009-02-12
Title
Size
B
Date:

SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
29
of
52
+3VL
+3VL_EC
L36
1 0_0603_5%
+EC_AVCC
9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC
U14
CLK_PCI_EC
EC_SMB_CK2
R211 1
2 2.2K_0402_5%
<20> EC_SCI#
<32> WL_BT_LED#
0.1U_0402_16V4Z
+3VS
KSI[0..7]
<31,32> KSI[0..7]
R212 1
2 2.2K_0402_5%
EC_SMB_CK1
R213 1
2 2.2K_0402_5%
TP_CLK
R215 1
2 4.7K_0402_5%
TP_DATA
R216 1
2 4.7K_0402_5%
+5VS
<44>
<44>
<7,42>
<7,42>
SYSON
R217 1
2 10K_0402_5%
SUSP#
R218 1
2 10K_0402_5%
LID_SW#_R
R220 2
1 100K_0402_5%
+3VALW
1 100K_0402_5%
+3VL
ON/OFFBTN#
KSO1
KSO2
R221
R222
R223
E51_TXD
R782
2 100K_0402_5%
PLT_RST#
R783
1 100K_0402_5%
CRY1
R227
2 150K_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
1 D15
CH751H-40PT_SOD323-2
OSC
NC
OSC
122
123
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
2 15P_0402_50V8J
EN_DFAN1
IREF
CHGVADJ
ADP_I
<45>
C387
2 0.22U_0603_16V4Z
EN_DFAN1 <5>
IREF
<45>
CHGVADJ <45>
EC_MUTE# <28>
USB_EN# <24,29>
TP_CLK
TP_DATA
TP_CLK <32>
TP_DATA <32>
EC_MUTE#
97
98
R137
99
109 1
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
GPI
R64
4.7K_0402_5%
VGATE <33,49>
WOL_EN# <25>
VLDT_EN <33>
LID_SW#_R <32>
1K_0402_5%
V18R
EC_SI_SPI_SO <31>
EC_SO_SPI_SI <31>
SPI_CLK <31>
SPI_CS# <31>
FSTCHG
BATT_FULL_LED#
FSTCHG <45>
BATT_FULL_LED# <32>
CAPS_LED# <31>
BATT_CHG_LOW_LED# <32>
PWR_ON_LED# <32>
SYSON <33,47>
BATT_LOW_LED#
SYSON
VR_ON
ACIN_D
VR_ON
EC_RSMRST#
<33,49>
R219
1 10K_0402_5%
2
EC_RSMRST# <20>
EC_LID_OUT# <20>
EC_ON <32>
SB_PWRGD
BKOFF#
WL_OFF#
SB_PWRGD <20>
BKOFF# <17>
WL_OFF# <27>
EC_SEL
ENBKL
USB_OC#2
ENBKL <35>
USB_OC#2 <20,24>
SUSP#
PBTN_OUT#
USB_OC#0
124 C391 2
SUSP# <33,45,48,50>
PBTN_OUT# <20>
USB_OC#0 <20,29>
1 4.7U_0805_10V4Z
KB926QFE0_LQFP128_14X14
+3VL
C393
0.1U_0402_16V4Z
0_0603_5% 1
<21,32,43>
R208
2 100K_0402_5%
<45>
1
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
2 0_0603_5%
119
120
126
128
SPI Flash ROM
CRY2
L37
<45>
BATT_TEMPA <44>
ADP_V
SPI Device Interface
XCLK1
XCLK0
R224
20M_0402_5%
+3VL_EC
EC_SEL
EC_VERSION
HIGH
KB926D3
LOW
KB926E0
@ R270
100K_0402_5%
L38
EC_SEL
+3VL_EC
1
C394
R272
100K_0402_5%
1
1
83
84
85
86
87
88
SM Bus
+3VL
ACIN
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
PS2 Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
+EC_AVCC
ACIN_D
68
70
71
72
GPIO
NC
32.768KHZ_12.5PF_Q13MC14610002
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
2 15P_0402_50V8J
77
78
79
80
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_SUSP_LED#
NUM_LED#
Y10
C392
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
FAN_SPEED1
<27> E51_TXD
<27> E51_RXD
<32> ON/OFFBTN#
<32> PWR_SUSP_LED#
<31> NUM_LED#
C390
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
<17> EC_INVT_PWM
<5> FAN_SPEED1
1 47K_0402_5%
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<20> PM_SLP_S3#
<20> PM_SLP_S5#
<20> EC_SMI#
<45> 75W_65W
1 47K_0402_5%
KSO[0..17]
<31,32> KSO[0..17]
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
ACOFF
BATT_TEMPA
C389
2 100P_0402_50V8J ECAGND
100P_0402_50V8J
2
1
C395
0.1U_0402_16V4Z
1
C396
0.1U_0402_16V4Z
C397
1000P_0402_50V7K
1
C398
0.1U_0402_16V4Z
C399
1000P_0402_50V7K
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
+3VL
63
64
65
66
75
76
EC_SMB_DA1
AD
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
EC_BEEP# <28>
ACOFF
PWM Output
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
21
23
26
27
2 2.2K_0402_5%
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
R210 1
12
2 0_0402_5% 13
37
20
38
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
C388
2 47K_0402_5%
CLK_PCI_EC
R8
1
ECRST#
EC_SCI#
WL_BT_LED#
<19,23> CLK_PCI_EC
<12,15,19,25,27,31,34> PLT_RST#
1
2
3
4
5
7
8
10
R209 1
2 0_0402_5%
AGND
+3VL
EC_SMB_DA2
GATEA20
R330 1
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<20> GATEA20
<20> KB_RST#
<19,31> SERIRQ
<19,31> LPC_FRAME#
<19,31> LPC_AD3
<19,31> LPC_AD2
<19,31> LPC_AD1
<19,31> LPC_AD0
69
10_0402_5%
ECAGND
@R44
@
R44 1
GND
GND
GND
GND
GND
10P_0402_50V8J
11
24
35
94
113
@C55
@
C55
1
67
AVCC
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
30
of
52
+3VL
< ROM Part >
< MDC 1.5 Conn >
HOLD#
7
1
@C400
@C400
+3VL
WP#
SCLK
GND
SI
EC_SPICLK
SPI_CLK <30>
2
@
C402
C401
EC_SO_SPI_SI <30>
EC_SPICLK 1
<20> HDA_SDOUT_MDC
<20> HDA_SYNC_MDC
<20> HDA_SDIN1
<20> HDA_RST#_MDC
R231 1
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
+MDC_VCC
MX25L2005CMI-12G_SO8
R230
2 10_0402_5% 1
1
HDA_SDOUT_MDC 3
5
HDA_SYNC_MDC 7
2 33_0402_5%HDA_SDIN1_MDC 9
11
2
4
6
8
10
12
+MDC_VCC
+3VALW
HDA_BITCLK_MDC <20>
1
+3VALW
R81
0_0603_5%
1
2
+1.5VS
@ R82
0_0603_5%
1
2
C403
2 10P_0402_50V8C
@
1
1
C405
1000P_0402_50V7K
R232
1
C406
0.1U_0402_16V4Z
C407
4.7U_0805_10V4Z
@
10_0402_5%
ACES_88018-124G
SO
VCC
GND
GND
GND
GND
GND
GND
<30> EC_SI_SPI_SO
JMDC
CS#
13
14
15
16
17
18
0.1U_0402_16V4Z
SPI_CS#
10P_0402_50V8J
<30>
SPI_CS#
10P_0402_50V8J
U46
Connector for MDC Rev1.5
C404
@
1
10P_0402_50V8J
< LPC Debug Port >

Please place the PAD under DDR DIMM.
H50
6
SERIRQ
PLT_RST#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
10
+3VS
<19,30> SERIRQ
<19,30> LPC_AD3
PLT_RST# <12,15,19,25,27,30,34>
LPC_AD2
<19,30>
LPC_AD0
<19,30>
<19,30> LPC_AD1
LPC_FRAME#
CLK_PCI_SIO <19,23>
2
<19,30> LPC_FRAME#
R234
@
DEBUG_PAD
1
22_0402_5%
2
< KEYBOARD Conn >
KSI[0..7]
KSI[0..7]
KSO[0..17]
<30,32>
C408
22P_0402_50V8J
< For EMI >
KSO[0..17] <30,32>
JKB
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
300_0402_5%
KSO16
2 R235
+3VS
KSO16
KSO17
C438 1
C439 1
2 100P_0402_50V8J
2 100P_0402_50V8J
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
CAPS_LED#
NUM_LED#
C409
C410
C411
C412
C413
C414
C418
C419
C420
C421
C422
C423
C424
C425
C426
C427
C428
C429
C430
C431
C432
C433
C434
C435
C436
C437
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
300_0402_5%
2
CAPS_LED# <30>
1 R252
+3VS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
NUM_LED# <30>
@ ACES_88170-3400
4
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title

SCHEMATIC,MB A6054
Date:
Rev
B
401871
Sheet

E
31
of
52
< Power Button for Debug >
< Power Button Circuit >
< TP on & off BTN on M/B>
ON/OFFBTN#
<30>
KSI6
KSI6
EC_ON
6
5
SMT1-05-A_4P
SW2
<30,31>
KSO0
<30,31>
SMT1-05-A_4P
R786
10K_0402_5%
KSO0
6
5
<43>
51_ON#
Q17B
2N7002KDW_SOT363-6
@ SW1
Sub-B Connector
JLEDB
SW_L
SW_R
<30> WL_BT_LED#
+3VALW
+5VS
+5VALW
<30>
<30>
TP_DATA
TP_CLK
+5VS
ACES_85201-0405N @
@
C221
3
JPOWER
1 1
2 2
3 3
4 4
5 G1
6 G2
D10
1@ C220
SW_L
10P_0402_50V8J
@
C222
C224
8
7
JTPB
1
2
3
4
GND
GND
KSO0
KSI6
1
2
3
4
5
6
@ P-TWO_161011-04021
@C218
C218
1@
10P_0402_50V8J
BATT_CHG_LOW_LED# 2
6
G8
5
G7
4
3
2
1
JTOUCH
0.1U_0402_16V7K
HDD_LED#
<26> CR_LED#
<30> BATT_FULL_LED#
<30> BATT_CHG_LOW_LED#
@ P-TWO_161021-06021
6
5
4
3
2
1
SW_R
SW_L
10P_0402_50V8J
10P_0402_50V8J
<30> PWR_ON_LED#
<30> PWR_SUSP_LED#
1
2
3
4
5
6
7
ON/OFFBTN#
8 <30> ON/OFFBTN#
9
10
11 GND 17
D23
12 GND 18
13
14
15
16
PACDN042Y3R_SOT23-3
@ ACES_85201-1605N
2
ACIN_LED#
<30> LID_SW#_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PACDN042Y3R_SOT23-3
SW_R
ACIN_LED#
1@ C219
10P_0402_50V8J
@C217
C217
1@
10P_0402_50V8J
LED Circuit
DC-IN LED
HDD LED
2
SATA_LED# <21>
<21,30,43>
2
ACIN_LED# 6
2 R779
1
10K_0402_5%
+3VS
1
HDD_LED#
Q17A
2N7002KDW_SOT363-6
ACIN
Q31A
2N7002KDW_SOT363-6
4
Q31B 2N7002KDW_SOT363-6
SCREW
H12
H_3P2
@
FD3
@
FD4
@
2009-09-25
Deciphered Date
Title
H27
H_2P7N
@
H_2P7X3P3N
@
C
H26
H_2P7X3P3N
@
SCHEMATIC,MB A6054
Date:
H25
H_6P8
@
H24
H_3P0
@
H23
H_3P0
@
H22
H_3P0
@
Compal Secret Data

2008-09-25
Issued Date
H21
H_3P0
@
H20
H_3P0
@
H19
H_3P0
@
H18
H_3P0
@
1
FD2
@
H_2P9X3P4
@
H_2P9
@
H_3P3
@
H_3P3
@
H_3P3
@
H_3P3
@
FD1
H17
H_3P0
@
PCB Fedical Mark PAD
H11
H10
H16
H_3P0
@
H37
H14
H_3P0
@
H36
H13
H_4P2X4P7
@
1
H31
H5
H_4P2X4P7
@
H4
H_4P2
@
H3
H_4P7
@
H30
H2
Rev
B
401871
Sheet

E
32
of
52
470_0805_5%
SI4800BDY_SO8
1U_0402_6.3V4Z
4.7U_0805_10V4Z
R305
1.5VS_ENABLE
1
1
R286
2
SUSP
R285
750K_0402_1% +VSB
10M_0402_5%
C466
SUSP
2
1
< +1.1VALW TO +1.1VS >
SUSP
C476
R290
330K_0402_5%
BOOT_ON_1.1V
@R67
@
R67 2
1 0_0402_5%
SUSP
1 0_0402_5% VLDT_EN#
VGATE#
1 0_0402_5%
R300
470_0805_5%
+VSB
Q12B
2N7002KDW_SOT363-6
10M_0402_5%
Q14A
2N7002KDW_SOT363-6
0.01U_0402_25V7K
BOOT_ON_1.1V
2
1
4.7U_0805_10V4Z
2
R291
0.01U_0402_25V7K
4.7U_0805_10V4Z
Q14B
1U_0402_6.3V4Z
C475
C474
@ C158
2
470_0805_5%
+VSB
R63 2
3 1
R287
1 750K_0402_1%
C472
@R62
@
R62 2
BOOT_ON_1.1V
2N7002KDW_SOT363-6
Q12A
2N7002KDW_SOT363-6
RUNON
R251
C471
4.7U_0805_10V4Z
Inrush current = 0A
1
2
3
1U_0402_6.3V4Z
C469
C468
8
7
6
5
SI4800BDY_SO8
BOOT_ON_1.1V
Q6
IRF8113PBF_SO8
Inrush current = 0A
1
2
3
4
S
S
S
G
4.7U_0805_10V4Z
D
D
D
D
390U_2.5V_M_R10
Q3
C470
+1.1VS
+3VS
2N7002KDW_SOT363-6
Q11A
2N7002KDW_SOT363-6
+1.1VALW
8
7
6
5
0.01U_0402_25V7K
< +3VALW TO +3VS >

+3VALW
470_0805_5%
Q11B
2N7002KDW_SOT363-6
Q34B
10U_0805_10V4Z
4.7U_0805_10V4Z
RUNON
C464
C463
2
2
R250
C450
C449
1U_0402_6.3V4Z
C462
4.7U_0805_10V4Z
1
2
3
4
S
S
S
G
D
D
D
D
Inrush current = 0A
Inrush current = 0A
1
2
3
C452
Q5
IRF8113PBF_SO8
8
7
6
5
+5VS
Q2
+1.5VS
+5VS
+5VALW
8
7
6
5
+1.5V
< +1.5V TO +1.5VS >
< +5VALW TO +5VS >
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
< +1.1VALW TO +NB_CORE >

+1.1VALW
+NB_CORE
+5VALW
Inrush current = 0A
+5VALW
R814
R292
330K_0402_5%
SYSON#
R293
C481
Q13B
0.01U_0402_25V7K
BOOT_ON_NB
2N7002KDW_SOT363-6
Q15B
2N7002KDW_SOT363-6
5
<30,47> SYSON
Q15A
2N7002KDW_SOT363-6
2
SUSP#
4
SUSP
Q13A
2N7002KDW_SOT363-6
<48>
VLDT_EN#
<30,45,48,50>
<30>
VLDT_EN
VLDT_EN 2
Q16A
2N7002KDW_SOT363-6
10M_0402_5%
SUSP
470_0805_5%
+VSB
4.7U_0805_10V4Z
R306
R816
100K_0402_5%
100K_0402_5%
C480
100K_0402_5%
3 1
R245
4.7U_0805_10V4Z
1U_0402_6.3V4Z
C478
C479
+5VALW
1
2
3
Q7
IRF8113PBF_SO8
8
7
6
5
< Discharge circuit >
1 0_0402_5%
VGATE#
+5VALW
+5VALW
R802
+0.75VS
+1.5V
+1.8VS
R803
100K_0402_5%
2
100K_0402_5%
@ R47 2
R253
R257
R258
470_0805_5%
470_0805_5%
470_0805_5%
VR_ON#
VR_ON#
<48>
SUSP
Q9
S
2N7002_SOT23-3
D
Q10
2
G
S
SUSP
2N7002_SOT23-3
<30,49>
SYSON#2
G
Q35A
2N7002KDW_SOT363-6
2
VR_ON
Q35B
2N7002KDW_SOT363-6
5
VGATE
Q23
2
G
2N7002_SOT23-3
<30,49>
VGATE#
VLDT_EN#
BOOT_ON_NB
SUSP
1 0_0402_5%
1 0_0402_5%
R46 2
@ R45 2
BOOT_ON_NB
BOOT_ON_NB
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
33
of
52
<11> PCIE_GTX_C_MRX_P[0..15]
<11> PCIE_GTX_C_MRX_N[0..15]
<11> PCIE_MTX_C_GRX_P[0..15]
D
<11> PCIE_MTX_C_GRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
UV1A
Close to UV1
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N15 AA38
PCIE_MTX_C_GRX_P15
Y37
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
Y33
Y32
PCIE_GTX_MRX_N15
PCIE_GTX_MRX_P15
CV1
CV2
1
1
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P15
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N15
Y35
W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P14
CV3
CV4
1
1
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P13
CV5
CV6
1
1
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
V35
U36
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P12
CV7
CV8
1
1
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P11
CV9 1
CV10 1
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
T35
R36
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
T30
T29
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P10
CV11 1
CV12 1
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
P33
P32
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9
CV13 1
CV14 1
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
P35
N36
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
P30
P29
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8
CV15 1
CV16 1
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
N38
M37
PCIE_RX8P
PCIE_RX8N
PCIE_TX8P
PCIE_TX8N
N33
N32
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P7
CV17 1
CV18 1
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
M35
L36
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
N30
N29
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
CV19 1
CV20 1
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
L38
K37
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
L33
L32
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P5
CV21 1
CV22 1
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
K35
J36
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
L30
L29
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P4
CV23 1
CV24 1
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
J38
H37
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
K33
K32
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P3
CV25 1
CV26 1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
H35
G36
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
J33
J32
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P2
CV27 1
CV28 1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
G38
F37
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
K30
K29
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P1
CV29 1
CV30 1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
F35
E37
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
H33
H32
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P0
CV31 1
CV32 1
PCI EXPRESS INTERFACE
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
CLOCK
<19> CLK_PCIE_VGA
<19> CLK_PCIE_VGA#
AB35
AA36
PCIE_REFCLKP
PCIE_REFCLKN
AJ21
AK21
AH16
NC#1
NC#2
NC_PWRGOOD
AA30
PERSTB
CALIBRATION
MANHA@
RV133 1
2 10K_0402_5%
<12,15,19,25,27,30,31>
PLT_RST#
PCIE_CALRP
Y30
RV1
2 1.27K_0402_1%
PCIE_CALRN
Y29
RV2
2 2K_0402_1%
+1.0VS
216-0729002 A12 M96_BGA962
@
A
Compal Secret Data
2008-09-25
Issued Date
Deciphered Date
2009-09-25
Title
Custom
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
1
34
of
52
UV1B
UV1G
MUTI GFX
DPA
+3VS_DELAY
10K_0402_5% 2
1 RV30 @
VGA_PWRSEL0
10K_0402_5% 2
1 RV131 @
VGA_PWRSEL1
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
THERM#_VGA
10K_0402_5% 2
1 RV32
10K_0402_5% 2
1 RV33 M9X@ GPIO23_CLKREQ#
10K_0402_5% 2
1 RV34 @
R_AC_IN
10K_0402_5% 2
1 RV35 @
GENERIC_C
<42>
<42>
<42>
VRAM_ID0
VRAM_ID1
VRAM_ID2
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DPB
DPC
DPD
I2C
LCD
<17> LCD_EDID_CLK
<17> LCD_EDID_DATA
LCD_EDID_CLK
LCD_EDID_DATA
AK26
AJ26
SCL
SDA
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG
AK24
HPD1
GENERAL PURPOSE I/O

C
<42> GPU_GPIO0
<42> GPU_GPIO1
<42> GPU_GPIO2
R_AC_IN
RV17 1
ENBKL
2 10K_0402_5%
<30>
ENBKL
<42> SOUT_GPIO8
<42> SIN_GPIO9
SOUT_GPIO8
SIN_GPIO9
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
<42> GPU_GPIO11
<42> GPU_GPIO12
<42> GPU_GPIO13
T15
VGA_PWRSEL0
<50> VGA_PWRSEL0
PAD
THERM#_VGA
<42> THERM#_VGA
VGA_PWRSEL1
<50> VGA_PWRSEL1
ROMSE_GPIO22
GPIO23_CLKREQ#
<42> ROMSE_GPIO22
T16
T9
T17
T18
T10
PAD
PAD
PAD
PAD
PAD
GENERIC_C
+1.8VS
<18>
RV20
499_0402_1%
HPD
+VGA_VREF
1
+VGA_VREF AH13
RV21
249_0402_1%
XTALOUT
CV49
AU24
AV23
TX0P_DPA2P
TX0M_DPA2N
AT25
AR24
TX1P_DPA1P
TX1M_DPA1N
AU26
AV25
TX2P_DPA0P
TX2M_DPA0N
AT27
AR26
TXCBP_DPB3P
TXCBM_DPB3N
AR30
AT29
HDMI_CLK0+ <18>
HDMI_CLK0- <18>
TX3P_DPB2P
TX3M_DPB2N
AV31
AU30
HDMI_TXD0+ <18>
HDMI_TXD0- <18>
TX4P_DPB1P
TX4M_DPB1N
AR32
AT31
HDMI_TXD1+ <18>
HDMI_TXD1- <18>
TX5P_DPB0P
TX5M_DPB0N
AT33
AU32
HDMI_TXD2+ <18>
HDMI_TXD2- <18>
TXCCP_DPC3P
TXCCM_DPC3N
AU14
AV13
TX0P_DPC2P
TX0M_DPC2N
AT15
AR14
TX1P_DPC1P
TX1M_DPC1N
AU16
AV15
TX2P_DPC0P
TX2M_DPC0N
AT17
AR16
TXCDP_DPD3P
TXCDM_DPD3N
AU20
AT19
TX3P_DPD2P
TX3M_DPD2N
AT21
AR20
TX4P_DPD1P
TX4M_DPD1N
AU22
AV21
TX5P_DPD0P
TX5M_DPD0N
AT23
AR22
R
RB
AD39
AD37
RED
<16>
G
GB
AE36
AD35
GREEN
<16>
LVDS CONTROL
CV324
18P_0402_50V8J
DDC/AUX
150mA
+DPLL_PVDD
CV323
PLL/CLOCK
AM32
AN32
DPLL_PVDD
DPLL_PVSS
AN31
DPLL_VDDC
300mA
+DPLL_VDDC
18P_0402_50V8J
27MCLK
AV33
XTALOUT AU34
BLM18PG121SN1D_0603
+1.8VS
A
<42> GPU_THERMAL_D+
<42> GPU_THERMAL_D-
0.1U_0402_16V4Z +DPLL_PVDD
1
1
1
CV42
CV41
1U_0402_6.3V4Z
CV40
2
2
2
10U_0603_6.3V6M
1
LV3
20mA
+TSVDD
AF29
AG29
AK32
AJ32
AJ33
XTALIN
XTALOUT
DPLUS
DMINUS
THERMAL
TS_FDO
TSVDD
TSVSS
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AK35
AL36
LCD_TZCLK+ <17>
LCD_TZCLK- <17>
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AJ38
AK37
LCD_TZOUT0+ <17>
LCD_TZOUT0- <17>
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AH35
AJ36
LCD_TZOUT1+ <17>
LCD_TZOUT1- <17>
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AG38
AH37
LCD_TZOUT2+ <17>
LCD_TZOUT2- <17>
TXOUT_U3P
TXOUT_U3N
AF35
AG36
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
LCD_TXCLK+ <17>
LCD_TXCLK- <17>
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AW37
AU35
LCD_TXOUT0+ <17>
LCD_TXOUT0- <17>
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AR37
AU39
LCD_TXOUT1+ <17>
LCD_TXOUT1- <17>
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AP35
AR35
LCD_TXOUT2+ <17>
LCD_TXOUT2- <17>
TXOUT_L3P
TXOUT_L3N
AN36
AP37
Near UV1
C
RED
AF37
AE38
BLUE
<16>
AC36
AC38
R_HSYNC
R_VSYNC
<16,42>
<16,42>
RSET
AB34
AVDD
AVSSQ
AD34
AE34
VDD1DI
VSS1DI
AC33
AC34
R2
R2B
AC30
AC31
1
RV11
1
RV12
1
RV13
GREEN
B
BB
BLUE
AD30
AD31
B2
B2B
AF30
AF31
C
Y
COMP
AC32
AD32
AF32
H2SYNC
V2SYNC
AD29
AC29
VDD2DI
VSS2DI
AG31
AG32
2
150_0402_1%
2
150_0402_1%
2
150_0402_1%
CRT
1
2
RV18 499_0402_1%
+AVDD_VGA
CV35
CV34
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
A2VDD
AG33
A2VDDQ
AD33
A2VSSQ
AF33
R2SET
AA29
CV36
1U_0402_6.3V4Z
AM26
AN26
AUX1P
AUX1N
AM27
AL27
DDC2CLK
DDC2DATA
AM19
AL19
AUX2P
AUX2N
AN20
AM20
DDCCLK_AUX3P
DDCDATA_AUX3N
AL30
AM30
DDCCLK_AUX4P
DDCDATA_AUX4N
AL29
AM29
BLM18PG121SN1D_0603
2
1
+1.8VS
LV2
1
CV37
2
2
0.1U_0402_16V4Z
CV38
10U_0603_6.3V6M
<42>
<42>
+VDD1DI
+A2VDD
45mA
+A2VDDQ
10mA
1
LV4
2
0_0603_5%
+3VS_DELAY
+A2VDD
+A2VDDQ
DDC1CLK
DDC1DATA
45mA
+VDD1DI
HSYNC_DAC2
VSYNC_DAC2
BLM18PG121SN1D_0603
2
1
+1.8VS
LV1
70mA
+AVDD_VGA
+VDD1DI
CV33
1U_0402_6.3V4Z
G2
G2B
DDCCLK_AUX5P
DDCDATA_AUX5N
VGA_INVT_PWM <17>
VGA_ENVDD <17>
1
RV22
10U_0603_6.3V6M
2
715_0402_1%
CRT_CLK
CRT_DATA
CRT_CLK <16>
CRT_DATA <16>
HDMICLK_VGA
HDMIDAT_VGA
1
CV46
YV1
27MHZ_16PF_X5H027000FG1H
AK27
AJ27
LVTMDP
RV25
0.1U_0402_16V4Z
VARY_BL
DIGON
216-0729002 A12 M96_BGA962
HSYNC
VSYNC
VREFG
27MCLK
1M_0603_5%
TXCAP_DPA3P
TXCAM_DPA3N
1
CV47
2
2
0.1U_0402_16V4Z
BLM18PG121SN1D_0603
2
1
+1.8VS
LV6
CV48
1U_0402_6.3V4Z
CRT
HDMICLK_VGA <18>
HDMIDAT_VGA <18>
HDMI
AN21
AM21
DDC6CLK
DDC6DATA
AJ30
AJ31
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
AK30
AK29
BLM18PG121SN1D_0603
+1.0VS
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV5
1
1
1
CV43
CV44
2
10U_0603_6.3V6M
216-0729002 A12 M96_BGA962

+DPLL_VDDC
+1.8VS
0.1U_0402_16V4Z
1
1
1
LV7
CV45
2 1U_0402_6.3V4Z
CV51
CV50
2
10U_0603_6.3V6M
+TSVDD
CV52
1U_0402_6.3V4Z
Compal Secret Data
Issued Date
2008-09-25
Deciphered Date
2009-09-25
Title
Size
C
Date:

SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet

1
35
of
52
BLM18PG121SN1D_0603
2
1
MANHA@ LV33
BLM18PG121SN1D_0603
1
2
LV35 MANHA@
MANHA@
CV308
MANHA@
CV310
UV1H
DP C/D POWER
+DPC_VDD18
AP20
AP21
NC_DPC_VDD18#1
NC_DPC_VDD18#2
+DPC_VDD10
AP13
AT13
DP A/B POWER
NC_DPA_VDD18#1
NC_DPA_VDD18#2
AN24
AP24
DPC_VDD10#1
DPC_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
AP31
AP32
AN17
AP16
AP17
AW14
AW16
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AN27
AP27
AP28
AW24
AW26
+DPD_VDD18
AP22
AP23
NC_DPD_VDD18#1
NC_DPD_VDD18#2
NC_DPB_VDD18#1
NC_DPB_VDD18#2
AP25
AP26
+DPD_VDD10
AP14
AP15
DPD_VDD10#1
DPD_VDD10#2
DPB_VDD10#1
DPB_VDD10#2
AN33
AP33
AN19
AP18
AP19
AW20
AW22
DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AN29
AP29
AP30
AW30
AW32
MANHA@
CV316
1U_0402_6.3V4Z
MANHA@
CV309
0.1U_0402_16V4Z
+DPA_VDD18
0.1U_0402_16V4Z
+DPC_VDD18
1U_0402_6.3V4Z
10U_0603_6.3V6M
+1.8VS
MANHA@
CV314
10U_0603_6.3V6M
+1.8VS
MANHA@
CV315
1
D
+DPA_VDD18
200mA
MANHA@
CV311
+1.0VS
MANHA@
CV313
BLM18PG121SN1D_0603
2
1
LV12
2
10U_0603_6.3V6M
CV56
1
LV10
2
0_0603_5%
+DPE_VDD18
2
CV57
2
0_0603_5%
+1.0VS
BLM18PG121SN1D_0603
1
2
LV36
MANHA@
+DPB_VDD18
MANHA@
CV319
MANHA@
CV317
+1.8VS
CV318
MANHA@
+1.8VS
1
LV9
10U_0603_6.3V6M
MANHA@
CV312
+DPA_VDD10
1U_0402_6.3V4Z
+DPD_VDD18
0.1U_0402_16V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
+1.8VS
BLM18PG121SN1D_0603
2
1
MANHA@ LV34
2
0_0603_5%
0.1U_0402_16V4Z
1
LV8
+1.0VS
RV36 150_0402_1%
2
1 AW18
CV58
200mA
1
1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+DPE_VDD18
+DPB_VDD18
+DPB_VDD10
2
CV53
2
CV54
BLM18PG121SN1D_0603
2
1
LV11
+1.0VS
CV55
0.1U_0402_16V4Z
H@
1U_0402_6.3V4Z
H@
DPAB_CALR
AW28
DP PLL POWER
DPA_PVDD
DPA_PVSS
AU28
AV27
+DPA_PVDD
DPCD_CALR
20mA
H@
10U_0603_6.3V6M
1
2
RV37 150_0402_1%
AH34
AJ34
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
AL33
AM33
DPE_VDD10#1
DPE_VDD10#2
DPB_PVDD
DPB_PVSS
AV29
AR28
+DPB_PVDD
AN34
AP39
AR39
AU37
AW35
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPC_PVDD
DPC_PVSS
AU18
AV17
+DPC_PVDD
+DPA_PVDD
20mA
+DPB_PVDD
20mA
1
LV13
2
0_0603_5%
+1.8VS
100mA
+DPE_VDD10
+1.0VS
BLM18PG121SN1D_0603
2
1
LV15
2
10U_0603_6.3V6M
CV60
1
+DPE_VDD10
2
CV64
CV61
1
1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
DPD_PVDD
DPD_PVSS
200mA
+DPF_VDD18
AF34
AG34
+1.8VS
BLM18PG121SN1D_0603
2
1
LV17
2
10U_0603_6.3V6M
CV65
1
+DPF_VDD18
2
CV66
CV67
AK33
AK34
AF39
AH39
AK39
AL34
AM34
1
1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
RV38 150_0402_1%
AM39
2
1
AV19
AR18
2
CV59
+DPD_PVDD
2
CV62
BLM18PG121SN1D_0603
2
1
LV14
+1.8VS
CV63
0.1U_0402_16V4Z
1U_0402_6.3V4Z
DPF_VDD18#1
DPF_VDD18#2
DPE_PVDD
DPE_PVSS
AM37
AN38
NC_DPF_PVDD
NC_DPF_PVSS
AL38
AM35
100mA
+DPF_VDD10
DPF_VDD10#1
DPF_VDD10#2
+DPE_PVDD
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
+DPC_PVDD
20mA
+DPD_PVDD
20mA
+DPE_PVDD
20mA
1
LV16
2
0_0603_5%
+1.8VS
1
LV18
2
0_0603_5%
+1.8VS
DPEF_CALR
216-0729002 A12 M96_BGA962
+1.0VS
BLM18PG121SN1D_0603
2
1
LV19
2
10U_0603_6.3V6M
CV68
1
+DPF_VDD10
2
CV69
CV70
1
1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV71
1
CV72
BLM18PG121SN1D_0603
2
1
LV20
+1.8VS
CV73
10U_0603_6.3V6M
1U_0402_6.3V4Z
Compal Secret Data
2008-09-25
Issued Date
Deciphered Date
2009-09-25
Title
Custom
Date:
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
1
36
of
52
UV1E
+PCIE_VDDR_VGA
MEM I/O
+@
2
CV192
CV78
CV74
CV79
CV83
CV87
CV91
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1
1
1
1
CV75
CV80
CV84
CV88
CV92
CV95
CV98
CV102
CV106
CV109
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1
1
1
1
1
1
1
1
1
CV76
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
CV81
CV85
CV89
CV93
CV96
CV99
CV103
CV107
CV110
1
1
1
BLM18PG121SN1D_0603
CV123
1
2
CV127
CV131
+3VS_DELAY
CV148
+1.8VS
CV152
BLM18PG121SN1D_0603
+VDDR5
0.1U_0402_16V4Z
2
1
LV23
1
1
1
CV156 CV157
CV161
CV158
CV162
10U_0603_6.3V6M
60mA
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1
1
1
AF26
AF27
CV135
AG26
1U_0402_6.3V4Z AG27
170mA
+VDDR5
1U_0402_6.3V4Z
170mA
+VDDR4
+1.8VS
BLM18PG121SN1D_0603
+VDDR4
0.1U_0402_16V4Z
2
1
LV24
1
1
1
CV171 CV172
CV173
10U_0603_6.3V6M
BLM18PG121SN1D_0603
2
1
M9X@ LV25
+1.5VS
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV27
1
1
1
CV186 CV187
CV188
MANHA@
CV303
1U_0402_6.3V4Z
MANHA@
CV304
0.1U_0402_16V4Z
10U_0603_6.3V6M
MPV18
AD12
AF11
AF12
AG11
M20
M21
V12
U12
CORE
VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4
VDDRHA
VSSRHA
VDDRHB
VSSRHB
PLL
+PCIE_PVDD
AB37
MPV18
MPV18
H7
H8
SPV18
AM10
1U_0402_6.3V4Z
MANHA@LV28
MANHA@
LV28
1U_0402_6.3V4Z
2
1
BLM18PG121SN1D_0603
1
1
2
CV189
CV190
CV191
M9X@ LV37
2
1
+VGA_CORE
2
2
1
BLM18PG121SN1D_0603
10U_0603_6.3V6M
0.1U_0402_16V4Z
414mA
+SPV10
PCIE_PVDD
NC_MPV18#1
NC_MPV18#2
NC_SPV18
AN9
SPV10
AN10
SPVSS
AA13
Y13
BBP#1
BBP#2
BACK BIAS
1
+VGA_CORE
MANHA@
CV302
CV195
CV77
CV82
CV86
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
CV196
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74
ISOLATED VDDCI#1
CORE I/O VDDCI#2
VDDCI#3
VDDCI#4
2
1U_0402_6.3V4Z
AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28
M15
N13
R12
T12
MANHA@
CV307
MANHA@
CV305
1U_0402_6.3V4Z
CV94
2A
CV100
CV104
CV108
CV111
CV113
CV115
CV118
CV120
CV124
CV128
CV132
CV136
CV139
CV142
CV145
CV149
CV153
1
1
1
1
1
1
1
1
+1.0VS
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1
1
1
1
1
1
1
1
1
CV105
CV125
CV129
CV133
CV137
CV140
CV143
CV146
CV150
CV154
CV163
CV165
CV167
CV169
CV174
CV176
CV178
CV181
CV183
CV197
CV198
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+
@
CV116
1
1
1
1
1
1
1
1
+
CV326
2
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
CV199
1
LV29
1
+
@
CV114
CV122
CV126
CV130
CV134
CV138
CV141
CV144
CV147
CV151
CV155
CV160
CV164
CV166
CV168
CV170
CV175
CV177
CV179
CV182
CV184
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+VGA_CORE
1
+
CV325
2
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
4A
2
+VGA_CORE
PBY201209T-300Y-N_2P
A
CV200
2
2
1U_0402_6.3V4Z 1U_0402_6.3V4Z
2
10U_0603_6.3V6M
216-0729002 A12 M96_BGA962

1
MANHA@
CV306
Compal Secret Data
2008-09-25
Issued Date
Deciphered Date
2009-09-25
Title

SCHEMATIC,MB A6054
Custom
Date:
2
+1.8VS
BLM18PG121SN1D_0603
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
25A
CV121
+VDDCI
CV97
CV101
CV159
SPV18
0.1U_0402_16V4Z
10U_0603_6.3V6M
AF13
AF15
AG13
AG15
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
1
LV21
CV112
MEM CLK
1
0.1U_0402_16V4Z
BLM18PG121SN1D_0603
2
1
+1.8VS
MANHA@ LV31
AF23
AF24
AG23
AG24
+VDDRHA
68mA
+1.0VS
I/O
+VDDRHB
10U_0603_6.3V6M
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
1U_0402_6.3V4Z
+1.8VS
BLM18PG121SN1D_0603
2
1
+1.8VS
MANHA@ LV30
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
CV90
LEVEL
TRANSLATION
+VDD_CT
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
POWER
CV119
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
136mA
0.1U_0402_16V4Z
1U_0402_6.3V4Z
LV22
1U_0402_6.3V4Z
10U_0603_6.3V6M
+1.8VS
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
390U_2.5V_M_R10
390U_2.5V_M_R10
330U_X_2VM_R6M
D
500mA
PCIE
4A
330U_X_2VM_R6M
+1.5VS
390U_2.5V_M_R10
330U_X_2VM_R6M
Rev
B
401871
Sheet
1
37
of
52
UV1F
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
GND
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#152
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#162
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#176
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AH29
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
216-0729002 A12 M96_BGA962

5
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
GND#100
A39
AW1
AW39
Compal Secret Data
Issued Date
2008-09-25
2009-09-25
Deciphered Date
Title
Date:

SCHEMATIC,MB A6054
Rev
B
401871
Sheet

1
38
of
52
MDB[0..63]
MDA[0..63]
MDB[0..63] <41>
MDA[0..63] <40>
Park uses memory group B only

D
UV1C
UV1D
Close to pin L20
ODTA0
ODTA1
CLKA0
CLKA0B
H27
G27
CLKA0
CLKA0#
CLKA1
CLKA1B
J14
H14
CLKA1
CLKA1#
RASA0B
RASA1B
K23
K19
RASA0#
RASA1#
CASA0B
CASA1B
K20
K17
CASA0#
CASA1#
CSA0B_0
CSA0B_1
K24
K27
CSA0#_0
CSA1B_0
CSA1B_1
M13
K16
CSA1#_0
WEA0B
WEA1B
K26
L15
WEA0#
WEA1#
2 243_0402_1% M12
2 243_0402_1% M27
2 243_0402_1% AH12
MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2
RV45
100_0402_1%
M9X@
+MVREFSA
216-0729002 A12 M96_BGA962
RV47
100_0402_1%
CV204
K21
J20
1 RV51
MANHA@1 RV53
MANHA@1 RV55
RV42
100_0402_1%
M9X@
QSA#[7..0] <40>
RV44
CV203
0.1U_0402_16V4Z
100_0402_1%
<40>
<40>
CLKA0
CLKA0#
<40>
<40>
CLKA1
CLKA1#
<40>
<40>
RASA0#
RASA1#
<40>
<40>
CASA0#
CASA1#
<40>
<40>
CSA0#_0
<40>
Close to pin AA12

+1.5VS
1
ODTA0
ODTA1
MANHA@
RV46
40.2_0402_1%
RV46
100_0402_1%
M9X@
+MVREFSB
CSA1#_0
RV52
<40>
CV205
0.1U_0402_16V4Z
RSVD#1
RSVD#2
RSVD#3
AF28
AG28
AL31
RSVD#5
RSVD#6
H23
J19
MAA13
RSVD#9
RSVD#11
T8
W8
MAB13
CKEA0
CKEA1
<40>
<40>
WEA0#
WEA1#
<40>
<40>
100_0402_1%
+MVREFDB
+MVREFSB
+3VS_DELAY
Y12
AA12
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
QSB_0B/WDQSB_0
QSB_1B/WDQSB_1
QSB_2B/WDQSB_2
QSB_3B/WDQSB_3
QSB_4B/WDQSB_4
QSB_5B/WDQSB_5
QSB_6B/WDQSB_6
QSB_7B/WDQSB_7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
MVREFDB
MVREFSB
TESTEN
@
RV56
10K_0402_5%
M9X@
TESTEN
M9X@
2 RV125
2
RV129
1 4.7K_0402_5%
1
4.7K_0402_5%
TESTA
TESTB
AD28
TESTEN
AK10
AL10
CLKTESTA
CLKTESTB
T7
W7
ODTB0
ODTB1
CLKB0
CLKB0B
L9
L8
CLKB0
CLKB0#
CLKB1
CLKB1B
AD8
AD7
CLKB1
CLKB1#
RASB0B
RASB1B
T10
Y10
RASB0#
RASB1#
CASB0B
CASB1B
W10
AA10
CASB0#
CASB1#
CSB0B_0
CSB0B_1
P10
L10
CSB0#_0
CSB1B_0
CSB1B_1
AD10
AC10
CSB1#_0
CKEB0
CKEB1
U10
AA11
CKEB0
CKEB1
WEB0B
WEB1B
N10
AB11
WEB0#
WEB1#
DRAM_RST
216-0729002 A12 M96_BGA962
B_BA[2..0]
B_BA[2..0] <41>
DQMB#[7..0] <41>
QSB#[7..0] <41>
ODTB0
ODTB1
<41>
<41>
CLKB0
CLKB0#
<41>
<41>
CLKB1
CLKB1#
<41>
<41>
RASB0#
RASB1#
<41>
<41>
CASB0#
CASB1#
<41>
<41>
CSB0#_0
<41>
CSB1#_0
<41>
CKEB0
CKEB1
<41>
<41>
WEB0#
WEB1#
<41>
<41>
AH11
MANHA@
1
2
RV132
1
51_0402_5%
DRAM_RST# <40,41>
MANHA@
RV59
10K_0402_5%
MANHA@
CV206
M9X@
CV206
0.01U_0402_25V7K
Compal Secret Data
Issued Date
0.1U_0402_16V4Z
2008-09-25
2009-09-25
Deciphered Date
Title

SCHEMATIC,MB A6054
Custom
Date:
MAB[13..0] <41>
M9X@ RV54 4.7K_0402_5%

2
1
+1.5VS
RV132
M9X@
0_0402_5%
RV23
10K_0402_5%
MAB[13..0]
QSB[7..0] <41>
ODTB0
ODTB1
68P_0402_50V8J
MANHA@
RV45
40.2_0402_1%
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
CKEA0
CKEA1
NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
MANHA@
RV42
40.2_0402_1%
+MVREFDB
MVREFDA
MVREFSA
2 243_0402_1% L27
2 243_0402_1% N12
2 243_0402_1% AG12
+1.5VS
QSA[7..0] <40>
CKEA0
CKEA1
MANHA@1 RV48
MANHA@1 RV49
MANHA@1 RV50
Close to pin Y12
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MEMORY INTERFACE B
ODTA0
ODTA1
J21
G19
DQMA#[7..0] <40>
A34
E30
E26
C20
C16
C12
J11
F8
+1.5VS
L18
L20
QSA_0B/WDQSA_0
QSA_1B/WDQSA_1
QSA_2B/WDQSA_2
QSA_3B/WDQSA_3
QSA_4B/WDQSA_4
QSA_5B/WDQSA_5
QSA_6B/WDQSA_6
QSA_7B/WDQSA_7
A_BA[2..0] <40>
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
+1.5VS
+MVREFDA
+MVREFSA
C34
D29
D25
E20
E16
E12
J10
D7
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
QSA_0/RDQSA_0
QSA_1/RDQSA_1
QSA_2/RDQSA_2
QSA_3/RDQSA_3
QSA_4/RDQSA_4
QSA_5/RDQSA_5
QSA_6/RDQSA_6
QSA_7/RDQSA_7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
A_BA[2..0]
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MAA[13..0] <40>
CV202
0.1U_0402_16V4Z
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
A32
C32
D23
E22
C14
A14
E10
D9
MAA[13..0]
RV43
100_0402_1%
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
+MVREFDA
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
RV41
100_0402_1%
M9X@
2
MANHA@ RV41
40.2_0402_1%
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
+1.5VS
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
Close to pin L18
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
Rev
B
401871
Sheet
1
39
of
52
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CKEA0
J7
K7
K9
CK
CK
CKE
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSA3
QSA1
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#3
DQMA#1
E7
D3
DML
DMU
QSA#3
QSA#1
G3
B7
DQSL
DQSU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CK
CK
CKE
<39>
<39>
<39>
<39>
<39>
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
QSA2
QSA0
F3
C7
DQSL
DQSU
DQMA#2
DQMA#0
E7
D3
DML
DMU
QSA#2
QSA#0
G3
B7
DQSL
DQSU
T2
RESET
L8
ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
+1.5VS
DRAM_RST# T2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
NC
NC
NC
NC
M7
T7
NC
NC
RV61
243_0402_1%
8PCS@
RESET
ZQ
J1
L1
J9
L9
NC
NC
NC
NC
M7
T7
NC
NC
RV62
243_0402_1%
8PCS@
96-BALL
SDRAM DDR3
K4W2G1646B-HC12_FBGA96~D
+1.5VS
+1.5VS
<39>
<39>
<39>
+1.5VS
<39>
<39>
<39>
<39>
<39>
+1.5VS
F3
C7
DQSL
DQSU
DQMA#4
DQMA#5
E7
D3
DML
DMU
QSA#4
QSA#5
G3
B7
DQSL
DQSU
8PCS@
1
8PCS@
NC
NC
NC
NC
M7
T7
NC
NC
RV69
4.99K_0402_1%
+VREFD_A2
+VREFC_A2
8PCS@
RV68
4.99K_0402_1%
1
CV207
1
CV211
RV78
4.99K_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
8PCS@
8PCS@
M2
N8
M3
BA0
BA1
BA2
CLKA1
CLKA1#
CKEA1
J7
K7
K9
CK
CK
CKE
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSA6
QSA7
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#6
DQMA#7
E7
D3
DML
DMU
QSA#6
QSA#7
G3
B7
DQSL
DQSU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group5
8PCS@
+1.5VS
DRAM_RST# T2
RV64
243_0402_1%
8PCS@
96-BALL
SDRAM DDR3
+1.5VS
MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
8PCS@
Group6
Group7
RESET
L8
ZQ
J1
L1
J9
L9
NC
NC
NC
NC
M7
T7
NC
NC
+1.5VS
96-BALL
SDRAM DDR3
+1.5VS
+1.5VS
8PCS@
RV70
4.99K_0402_1%
8PCS@
+VREFC_A3
RV71
4.99K_0402_1%
+VREFD_A3
1
CV208
RV79
4.99K_0402_1%
8PCS@
8PCS@
8PCS@
RV72
4.99K_0402_1%
+VREFC_A4
1
CV212
RV74
4.99K_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
8PCS@
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VS
8PCS@
RV77
4.99K_0402_1%
1
CV210
CV209
RV76
0.1U_0402_16V4Z 4.99K_0402_1%
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A_BA0
A_BA1
A_BA2
ZQ
+1.5VS
+VREFD_A1
+VREFC_A1
B2
D9
G7
K2
K8
N1
N9
R1
R9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
RESET
J1
L1
J9
L9
RV63
243_0402_1%
+1.5VS
RV66
4.99K_0402_1%
QSA4
QSA5
L8
RV67
4.99K_0402_1%
8PCS@
2
8PCS@
ODT
CS
RAS
CAS
WE
DRAM_RST# T2
1
1
1
RV65
4.99K_0402_1%
RV73
4.99K_0402_1%
K1
L2
J3
K3
L3
8PCS@
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
96-BALL
SDRAM DDR3
CK
CK
CKE
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
+1.5VS
A_BA0
A_BA1
A_BA2
L8
J1
L1
J9
L9
J7
K7
K9
MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47
VREFCA
VREFDQ
+1.5VS
<39,41> DRAM_RST#
CLKA1
CLKA1#
CKEA1
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
BA0
BA1
BA2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+VREFC_A4
+VREFD_A4
J7
K7
K9
M2
N8
M3
Group1
MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33
8PCS@
+VREFD_A4
1
CV213
RV75
4.99K_0402_1%
0.1U_0402_16V4Z
2
8PCS@
8PCS@
CLKA0
CLKA0#
CKEA0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
E3
F7
F2
F8
H3
H8
G2
H7
<39>
<39>
<39>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A_BA[2..0]
A_BA0
A_BA1
A_BA2
VREFCA
VREFDQ
QSA[7..0]
A_BA[2..0]
MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8
+1.5VS
<39>
<39>
<39>
<39> QSA#[7..0]
<39>
D7
C3
C8
C2
A7
A2
B8
A3
UV5
M8
H1
<39>
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+VREFC_A3
+VREFD_A3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A_BA0
A_BA1
A_BA2
<39> DQMA#[7..0]
Group0
MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28
B2
D9
G7
K2
K8
N1
N9
R1
R9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
E3
F7
F2
F8
H3
H8
G2
H7
1
CV214
RV80
4.99K_0402_1%
0.1U_0402_16V4Z
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
BA0
BA1
BA2
MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6
VREFCA
VREFDQ
M2
N8
M3
D7
C3
C8
C2
A7
A2
B8
A3
UV4
M8
H1
MAA[13..0]
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+VREFC_A2
+VREFD_A2
<39>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
MDA23
MDA18
MDA22
MDA19
MDA20
MDA17
MDA21
MDA16
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
E3
F7
F2
F8
H3
H8
G2
H7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MDA[0..63]
MDA[0..63]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<39>
UV3
VREFCA
VREFDQ
0.1U_0402_16V4Z
2
UV2
+VREFC_A1 M8
+VREFD_A1 H1
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
+1.5VS
+1.5VS
+1.5VS
+1.5VS
8PCS@
2 8PCS@
8PCS@
8PCS@
8PCS@
Issued Date
2008-09-25
10U_0603_6.3V
1
CV244
CV245
2
2
2
10U_0603_6.3V
10U_0603_6.3V
8PCS@
8PCS@
8PCS@
2009-09-25
Deciphered Date
Title
Date:
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
8PCS@ 8PCS@1U_0402_6.3V4Z
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
Compal Secret Data
CV230
2
8PCS@
CV243
2
10U_0603_6.3V
CV251
CV242
CV250
CV229
10U_0603_6.3V
1
+1.5VS
1
CV241
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
CV249
2
CV228
2
10U_0603_6.3V
CV240
CV248
CV227
10U_0603_6.3V
1
CV239
CV238
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
CV226
CV225
CV237
CV224
CV223
CV222
2
CV252
0.1U_0402_16V4Z
CV221
CV247
CV220
CV246
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV219
8PCS@
10U_0603_6.3V
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV218
1
2
RV84 56_0402_1%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV217
+1.5VS
8PCS@
CLKA1#
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
8PCS@8PCS@8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
1
2
RV83 56_0402_1%
CV234
0.1U_0402_16V4Z
8PCS@
CLKA1
CV236
CV235
8PCS@
CV233
8PCS@
CV216
1
2
RV82 56_0402_1%
CV232
CLKA0#
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV215
1
2
RV81 56_0402_1%
CV231
CLKA0
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

1
40
of
52
UV6
<39>
MDB[0..63]
M8
H1
VREFCA
VREFDQ
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
M2
N8
M3
BA0
BA1
BA2
<39>
UV7
+VREFC_B1
+VREFD_B1
MDB[0..63]
MAB[13..0]
<39> DQMB#[7..0]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB26
MDB28
MDB27
MDB29
MDB25
MDB30
MDB24
MDB31
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
UV8
+VREFC_B2
+VREFD_B2
M8
H1
VREFCA
VREFDQ
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
CLKB0
CLKB0#
CKEB0
J7
K7
K9
CK
CK
CKE
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSB2
QSB0
F3
C7
DQSL
DQSU
DQMB#2
DQMB#0
E7
D3
DML
DMU
QSB#2
QSB#0
G3
B7
DQSL
DQSU
DRAM_RST#
T2
RESET
L8
ZQ
Group3
Group1
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB23
MDB20
MDB19
MDB18
MDB21
MDB17
MDB22
MDB16
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB2
MDB6
MDB0
MDB5
MDB1
MDB7
MDB3
MDB4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VS
<39>
QSB[7..0]
<39>
<39>
<39>
B_BA0
B_BA1
B_BA2
<39> QSB#[7..0]
<39>
<39>
<39>
CLKB0
CLKB0#
CKEB0
J7
K7
K9
CK
CK
CKE
<39>
<39>
<39>
<39>
<39>
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSB3
QSB1
F3
C7
DQSL
DQSU
DQMB#3
DQMB#1
E7
D3
DML
DMU
QSB#3
QSB#1
G3
B7
DQSL
DQSU
T2
RESET
L8
ZQ
UV9
+VREFC_B3
+VREFD_B3
M8
H1
VREFCA
VREFDQ
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
M2
N8
M3
BA0
BA1
BA2
Group2
Group0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB35
MDB37
MDB32
MDB39
MDB34
MDB38
MDB33
MDB36
+VREFC_B4
+VREFD_B4
M8
H1
VREFCA
VREFDQ
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB45
MDB43
MDB47
MDB41
MDB44
MDB40
MDB46
MDB42
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
CLKB1
CLKB1#
CKEB1
J7
K7
K9
CK
CK
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSB6
QSB7
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMB#6
DQMB#7
E7
D3
DML
DMU
QSB#6
QSB#7
G3
B7
DQSL
DQSU
DRAM_RST#
T2
RESET
L8
ZQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
NC
NC
NC
NC
M7
T7
NC
NC
+1.5VS
+1.5VS
Group5
E3
F7
F2
F8
H3
H8
G2
H7
MDB55
MDB51
MDB54
MDB48
MDB53
MDB49
MDB52
MDB50
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VS
B_BA0
B_BA1
B_BA2
+1.5VS
Group4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<39>
<39>
<39>
CLKB1
CLKB1#
CKEB1
J7
K7
K9
CK
CK
CKE
<39>
<39>
<39>
<39>
<39>
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
ODT
CS
RAS
CAS
WE
QSB4
QSB5
F3
C7
DQSL
DQSU
DQMB#4
DQMB#5
E7
D3
DML
DMU
QSB#4
QSB#5
G3
B7
DQSL
DQSU
DRAM_RST#
T2
RESET
L8
ZQ
Group6
Group7
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
1
2
1
0.1U_0402_16V4Z
2
1
1
4PCS@
4PCS@
4PCS@
CV298
2
10U_0603_6.3V
4PCS@ 2
2
2
2
10U_0603_6.3V
10U_0603_6.3V
4PCS@
4PCS@
4PCS@
Compal Secret Data

2008-09-25
2009-09-25
Deciphered Date
Title
CV292
Date:
CV286
10U_0603_6.3V
1
CV297
CV285
CV296
4PCS@
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
CV295
4PCS@
CV288
10U_0603_6.3V
1
CV284
+1.5VS
CV283
CV290
330U_X_2VM_R6M
@
CV282
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
4PCS@
CV281
CV280
CV279
CV278
4PCS@
CV277
CV294
390U_2.5V_M_R10
CV276
10U_0603_6.3V
1
CV287
2
2
2
2
2
2
2
+1.5VS +1.5VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
4PCS@
4PCS@
4PCS@
4PCS@
1
1
4PCS@
4PCS@
4PCS@
+
+
4PCS@ CV193
2
10U_0603_6.3V
4PCS@
Issued Date
1
CV260
RV104
4.99K_0402_1%
0.1U_0402_16V4Z
2
4PCS@
+1.5VS
CV275
4PCS@
CV274
0.1U_0402_16V4Z
CV273
CV293
CV272
10U_0603_6.3V
1
CV271
CV270
CV269
2
CV299
4PCS@
+VREFD_B4
1
CV259
RV103
4.99K_0402_1%
0.1U_0402_16V4Z
2
4PCS@
+1.5VS
CV268
4PCS@
+VREFC_B4
1
CV258
RV102
4.99K_0402_1%
0.1U_0402_16V4Z
2
4PCS@
4PCS@
CV291
1
2
RV108 56_0402_1%
+VREFD_B3
RV96
4.99K_0402_1%
CV267
CLKB1#
4PCS@
4PCS@
+1.5VS
4PCS@
4PCS@
RV95
4.99K_0402_1%
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
4PCS@ 4PCS@
4PCS@
4PCS@
4PCS@
2
4PCS@
4PCS@
4PCS@
1
2
RV107 56_0402_1%
4PCS@
+VREFC_B3
1
CV257
RV101
4.99K_0402_1%
0.1U_0402_16V4Z
2
4PCS@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV266
4PCS@
RV94
4.99K_0402_1%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV265
CLKB1
+1.5VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV264
0.1U_0402_16V4Z
96-BALL
SDRAM DDR3
+1.5VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CV263
4PCS@
4PCS@
CV262
1
2
RV106 56_0402_1%
1
CV289
4PCS@
+VREFD_B2
1
CV256
+1.5VS
CV261
CLKB0#
0.1U_0402_16V4Z
2
4PCS@ @
RV93
4.99K_0402_1%
4PCS@
4PCS@
RV100
4.99K_0402_1%
0.1U_0402_16V4Z
2
2
4PCS@
+VREFC_B2
1
CV255
RV99
4.99K_0402_1%
4PCS@
1
2
1
CV254
RV98
4.99K_0402_1%
0.1U_0402_16V4Z
2
4PCS@
+VREFD_B1
+VREFC_B1
1
CV253
4PCS@
1
2
RV105 56_0402_1%
+1.5VS
1
2
4PCS@
+1.5VS
CLKB0
96-BALL
SDRAM DDR3
+1.5VS
RV92
4.99K_0402_1%
RV91
4.99K_0402_1%
4PCS@
RV88
243_0402_1%
Default
RV90
4.99K_0402_1%
4PCS@
NC
NC
RV89
4.99K_0402_1%
RV97
4.99K_0402_1%
M7
T7
96-BALL
SDRAM DDR3
@
B
NC
NC
NC
NC
NC
NC
4PCS@
M7
T7
RV87
243_0402_1%
96-BALL
SDRAM DDR3
+1.5VS
+1.5VS
NC
NC
NC
NC
NC
NC
4PCS@
J1
L1
J9
L9
M7
T7
RV86
243_0402_1%
J1
L1
J9
L9
NC
NC
NC
NC
4PCS@
J1
L1
J9
L9
RV85
243_0402_1%
<39,40> DRAM_RST#
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

1
41
of
52
CONFIGURATION STRAPS
STRAPS
+3VS_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
GPU by the system BIOS
GPU by VBIOS
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1)
GPIO[13:11]
MEMORY SIZE
0 0 0
0 0 1
0 1 0
128MB
GPIO[13:11]
1 0 0
(M25P05A)
256MB
64MB
<35> GPU_GPIO0
<35> GPU_GPIO1
<35> GPU_GPIO2
<35> SOUT_GPIO8
<35> SIN_GPIO9
<35> ROMSE_GPIO22
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
SOUT_GPIO8
SIN_GPIO9
@ RV109
@RV109
@RV110
@
RV110
@RV111
@
RV111
@RV112
@
RV112
@RV113
@
RV113
@RV114
@
RV114
<35> GPU_GPIO11
<35> GPU_GPIO12
<35> GPU_GPIO13
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
RV115
@RV116
@
RV116
@RV117
@
RV117
H@ RV118
H@ RV119
@RV120
@
RV120
@RV121
@
RV121
<16,35> R_VSYNC
<16,35> R_HSYNC
<35> HSYNC_DAC2
<35> VSYNC_DAC2
2
2
2
2
2
2
1
1
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
DESCRIPTION OF DEFAULT SETTINGS
RECOMMENDED SETTINGS
TX_PWRS_ENB
GPIO0
PIN
PCIE FULL TX OUTPUT SWING
2
2
2
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
TX_DEEMPH_EN
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED
BIF_GEN2_EN_A
GPIO2
PCIE GNE2 ENABLED
2
2
2
2
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
BIF_CLK_PM_EN
GPIO8
BIF_CLK_PM_EN
BIF_VGA DIS
GPIO9
VGA Controller ENABLED
0 (Enable)
BIOS_ROM_EN
GPIO_22_ROMCSB
Enable Extermal BIOS device
GPIO[13:11]
ROM Configurations
0 0 1
VSYNC_DAC2
IGNORE VIP DEVICE STRAPS
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
11
STRAPS
GPIO5_AC_BATT TEST
ROMIDCFG(2:0)
+3VS
+3VS
VIP_DEVICE_STRAP_ENA
M9X@ CV345
AUD[1]
HSYNC
AUD[0]
VSYNC
2
S
M9X@
1
M9X@ RV135
100K_0402_5%
MANHA@
0_0603_5%
RV3
QV1
AO3413_SOT23
M9X@
1
1
2
G
3
2
0_0402_5%
1
M9X@ RV60
PCIE_OK
<48>
47K_0402_5%
M9X@ QV2
M9X@
SSM3K7002FU_SC70-3
RV134
1
D
0.1U_0402_16V4Z
2
M9X@ RV136
100K_0402_5%
CV322
RSVD
HSYNC_DAC2
RSVD
GENERICC
0
C
100mA
AMD RESERVED CONFIGURATION STRAPS
0.01U_0402_25V7K
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3VS_DELAY
HSYNC_DAC2
GENERICC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
+1.8VS
RV124
10K_0402_5%
@
STRAPS
PIN
GPU
VRAM_ID0 <35>
VRAM_ID1 <35>
VRAM_ID2 <35>
1
VRAM size
Compal Part Number#
Vendor Part Number#
VRAM_ID 2,1,0
RV123
10K_0402_5%
@
2
RV122
10K_0402_5%
@
Park M2
RV128
10K_0402_5%
@
512M 64Mx16 (x4)
HYN
H5TQ1G63BFR-12C
SA000032400
000
512M 64Mx16 (x4)
SAM
K4W1G1646E-HC12
SA000035700
001
1G 128Mx16
(x4)
HYN
1G 128Mx16
(x4)
SAM
K4W2G1646B-HC12
SA00003MQ00
0 1 1 (Reserve)
1G 64Mx16
(x8)
HYN
H5TQ1G63BFR-12C
SA000032400
100
1G 64Mx16
(x8)
SAM
K4W1G1646E-HC12
SA000035700
101
2G 128Mx16
(x8)
HYN
2G 128Mx16
(x8)
SAM
K4W2G1646B-HC12
SA00003MQ00
RV127
10K_0402_5%
@
2
RV126
10K_0402_5%
@
2
GPIO21_BB_EN
GPIO_28_TDO
VRAM_ID[2:0]
DVPDATA
(2,1,0)
Madison M2
0 1 0 (Reserve)
1 1 0 (Reserve)
1 1 1 (Reserve)
External VGA Thermal Sensor

+3VS
1
RV130
A
0.1U_0402_16V4Z
CV301
1
2
2200P_0402_50V7K
<35> GPU_THERMAL_D-
UV1
UV1
M92 XTX
M92@
Madison
MADISON@
Park
PARK@
CV300
<35> GPU_THERMAL_D+
UV1
2
0_0402_5%
1
UV11
1
VDD
SCLK
EC_SMB_CK2 <7,30>
D+
SDATA
EC_SMB_DA2 <7,30>
D-
ALERT#
THERM#_VGA <35>
THERM#
GND
Compal Secret Data
2008-09-25
Issued Date
2009-09-25
Deciphered Date
Title
SCHEMATIC,MB A6054
ADM1032ARMZ-2REEL_MSOP8
Date:
Rev
B
401871
Sheet

1
42
of
52
VS
VIN
PR2
5.6K_0402_5%
2
PC6
.1U_0402_16V7K
ACIN
<21,30,32>
PACIN
PACIN
<45>
LM393DG_SO8
PD1
GLZ4.3B_LL34-2
PR7
10K_0402_1%
1
PR8
10K_0402_1%
+CHGRTC
Vin Detector
3.3V
VIN
PC5
0.068U_0402_10V6K
PR6
20K_0402_1%
2
1
@ SINGA_2DW-0005-B03
PR4
10K_0402_1%
1
2
PU1A
PR5
22K_0402_1%
1
2
PC4
100P_0402_50V8J
PC3
1000P_0402_50V7K
PC2
100P_0402_50V8J
N1
PR3
84.5K_0402_1%
PC1
1000P_0402_50V7K
+
1
SMB3025500YA_2P
DC_IN_S2
10A_125V_451010MRL
PJP1
DC_IN_S1
PF1
DC30100A700
PR1
1M_0402_1%
1
2
VIN
PL1
High 18.384 17.901 17.430

Low 17.728 17.257 16.976
PD3
CHGRTCP
PR11
200_0603_5%
1
2
N1
200_0603_5%
PC10
PR12
100K_0402_1%
1U_0805_25V4Z
VS
51_ON#
PC7
0.22U_0603_25V7K
PC8
0.1U_0603_25V7K
PR13 1K_1206_5%
1
2
PD4
PR15
22K_0402_1%
1
2
ACON
PU1B
7
LM393DG_SO8
+
1
PC13
1000P_0402_50V7K
@ PR25
66.5K_0402_1%
1
2
1000P_0402_50V7K
PC12
SP093MX0000
PR23
10K_0402_1%
+3VALW
+1.1VALWP
@ JUMP_43X118
OCP(min) = 7.7A
+1.1VALW
+3VLP
+3VL
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)
(12A,480mils, Via NO.= 24)

1
PJ18
OCP(min) = 18.7A
+5VALW
+1.0VSP
@ JUMP_43X118
PJ7
(5A,200mils, Via NO.= 10)
+1.5VP
+VSB
@ JUMP_43X39
PJ9
+2.5VSP
+2.5VS
+VGA_COREP
@ JUMP_43X79
2
1
(1A,40mils ,Via NO.= 2)
(11A,440mils ,Via NO.= 22)
+1.8VSP
+VDDNBP
+1.8VS
@ JUMP_43X79
(2.5A,100mils, Via NO.= 5)
PQ3
DTC115EUA_SC70-3
+VGA_CORE
@ JUMP_43X118
PJ10
+0.75VS
+5VALWP
+1.0VS
@ JUMP_43X118
PJ21
2 2
1 1
PJ12
1
PACIN
PJ20
1
OCP(min) = 19.16A
PJ11
+0.75VSP
@ JUMP_43X39
@ JUMP_43X118
(120mA,40mils, Via NO.= 1)
(2.5A,100mils, Via NO.= 5)
+1.5V
@ JUMP_43X118
PJ19
2 2
1 1
PJ8
2
@ JUMP_43X79
OCP(min) = 7.9A
+VSBP
PR27
47K_0402_1%
2
2
1
G
PQ2
SSM3K7002FU_SC70-3
D
1
@ JUMP_43X118
PJ5
2
@ JUMP_43X118
PJ4
2 2
1 1
+5VALWP
PJ3
PJ2
1
PC11
1000P_0402_50V7K
PR24
499K_0402_1%
PR26
191K_0402_1%
PJ1
+3VALWP
+CHGRTC
<45>
PD5
RB715F_SOT323-3
2
1
3
EN0
<46>
+RTCBATT
@ MAXEL_ML1220T10
PR17
499K_0402_1%
PR22
560_0603_5%
1
2 +RTCBATT
PR21
560_0603_5%
1
2
PR20
2.2M_0402_5%
2
1
+
1
PR19
100K_0402_1%
1
2
VL
B+
PR16 1K_1206_5%
1
2
PR14 1K_1206_5%
1
2
N3
RLS4148_LL34-2
RTC Battery
PBJ1
VIN
<32>
GND
PC9
10U_0805_10V4Z
PR18
N2
IN
1
2
G920AT24U_SOT89-3
OUT
+CHGRTC
PU2
3.3V
2
PR10
68_1206_5%
2
PR9
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3
RLS4148_LL34-2
BATT+
PD2
RLS4148_LL34-2
Precharge detector
15.97V/14.84V FOR
ADAPTOR
(20A,800mils ,Via NO.= 40)

1
+VDDNB
OCP(min) = 20.14A
@ JUMP_43X79
(4A,160mils ,Via NO.= 8)
PJ13
+1.05VSP
+1.05VS
@ JUMP_43X79
(1.5A,60mils, Via NO.= 3)
Issued Date
Compal Secret Data
2008/9/25
Deciphered Date
2009/9/25
Title
Size
Date:
SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
D
43
of
52
PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 56 degree C
VMB
PF2
15A_65V_451015MRL
1
2
1
2
PR29
47K_0402_1%
+3VLP
PC14
1000P_0402_50V7K
Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K

Rset = 3 * 7.87K = 23.61K ==> 23.7K
Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
PC15
0.01U_0402_25V7K
1
PR32
1K_0402_1%
@PD6
@
PD6
VL
PC16
0.1U_0603_25V7K
PR30
23.7K_0402_1%
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
PR39
100_0402_1%
<46>
PR33
11.3K_0402_1%
2
PR40
1K_0402_1%
PR34
11.3K_0402_1%
1
G718TM1U_SOT23-8
VS_ON
PU3
+3VLP
PR38
100_0402_1%
PR37
6.49K_0402_1%
2
1
PJSOT24C_SOT23-3
PR31
23.7K_0402_1%
PD8
2
@
2
PJSOT24C_SOT23-3
SUYIN_200045MR009G171ZR
@
BATT+
2
PR28
1K_0402_1%
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
PL2
SMB3025500YA_2P
1
2
GND
GND
GND
GND
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
10
11
12
13
1
2
3
4
5
6
7
8
9
BATT_S1
1
2
3
4
5
6
7
8
9
PJP2
PH1
BATT_TEMPA <30>
2
100K_0402_1%_NCP15WF104F03RC
PH2
EC_SMB_DA1 <30>
100K_0402_1%_NCP15WF104F03RC
2
EC_SMB_CK1 <30>
PQ6
TP0610K-T1-E3_SOT23-3
1
2
1
@ PC19
@PC19
0.22U_0603_25V7K
PH2 near main Battery CONN :

BAT. thermal protection at 90 degree C
Recovery at 56 degree C
PR45
22K_0402_1%
1
2
VL
2
1
PR43
100K_0402_1%
+VSBP
1
@ PC20
0.1U_0603_25V7K
B+
PR48
0_0402_5%
2
POK
PQ7
SSM3K7002FU_SC70-3
2
G
<46,47>
@ PC22
.1U_0402_16V7K
PR47
100K_0402_1%
Issued Date
Compal Secret Data
2008/9/25
Deciphered Date
2009/9/25
Title
Size
Date:
SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
D
44
of
52
PC163
10U_1206_25V6M
1
2
B+
PR49
0.015_2512_1%
1
4
1
2
3
PC162
10U_1206_25V6M
1
2
CHG_B+
4
PJ22
2
@ JUMP_43X79 CSIN
CSIP
ICM
PHASE
18
VREF
UGATE
17
CHLIM
BOOT
16
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
GND
PGND
13
PL4
10U_LF919AS-100M-P3_4.5A_20% PR67
0.02_1206_1%
1
2CHG 1
4
PR75
20K_0402_1%
DL_CHG
26251VDD
1 2
PQ21
AO4466_SO8
@PC41
@
PC41
680P_0603_50V7K
PD14
RB751V-40TE17_SOD323-2
6251VDDP
@PR69
@
PR69
4.7_1206_5%
PC38
0.1U_0603_25V7K
BST_CHGA 2
1
3
2
1
DH_CHG
PR70
2.2_0603_5%
BST_CHG 1
2
BATT+
PR74
4.7_0603_5%
PC43
4.7U_0805_6.3V6K
VIN
VADJ
PR79
10K_0402_1%
1
2
PR80
47K_0402_1%
1
@ PD15
GLZ4.3B_LL34-2
2
Iin = 2.512 ADP_I
ADP_V <30>
PR78
309K_0402_1%
CP mode
Vaclim=2.39*(Rb//152K/(Rt//152K+Rb//152K))
(75W)
2
1
PR65
2.2_0603_5%
LX_CHG
ISL6251AHAZ-T_QSOP24
PR77
31.6K_0402_1%
Iinput=(1/PR49)((0.05*Vaclm)/2.39+0.05)
where Vaclm=0.6221V, Iinput=3.15A
Vaclm=1.09986V, Iinput=3.65A
PC167
10U_1206_25V6M
2
1
19
2 PACIN
G
PQ18
SSM3K7002FU_SC70-3
PC166
10U_1206_25V6M
2
1
CSIP
VCOMP
20
PC40
10U_1206_25V6M
2
1
CSIN
PQ19
AO4466_SO8
PC39
10U_1206_25V6M
2
1
ICOMP
D
PC32
0.1U_0603_25V7K
CSOP
21
CSOP
CELLS
5
6
7
8
CSON
PC30
0.047U_0603_16V7K
1
2
PR62
20_0603_5%
2
1
PR63
20_0603_5%
PC34
0.1U_0603_25V7K
1
2
3
2
1
22
CSON
PD13
2
1SS355_SOD323-2
EN
PR58
200K_0402_1%
1
2 VIN
PQ16
DTC115EUA_SC70-3
PR61
20_0603_5%
1
2
ACOFF
3
3
<30> CHGVADJ
PR76
15.4K_0402_1%
1
2
PD11
1
1SS355_SOD323-2
2
G
<30> 75W_65W
23
12
PQ5
SSM3K7002FU_SC70-3
1
PR35
5.49K_0402_1%
6251aclim
1 2
PR72
53.6K_0402_1%
6251VREF 1
2
ACSET ACPRN
PC29
0.1U_0603_25V7K
2
1
6251VREF
ADP_I
PR73
120K_0402_1%
<30>
1
PC42
0.01U_0402_25V7K
2
1
ACOFF
IREF
ACOFF
<30>
PR71
154K_0402_1%
2
1
DCIN
5
6
7
8
2
PC36
@ 100P_0402_50V8J
1
2
24
PR66
47K_0402_1%
1
2
PC37 .1U_0402_16V7K
PQ22
DTC115EUA_SC70-3
<30>
0.01U_0402_25V7K
DCIN
6.81K_0402_1%
2
PR68
22K_0402_5%
PACIN 1
2
ACON
6800P_0402_25V7K
2
PR64
PR56
10K_0402_1%
SUSP# <30,33,48,50>
PC44
.1U_0402_16V7K
2
G
PC35
1
2
VDD
PQ20
SSM3K7002FU_SC70-3
6251_EN
PU4
1
PC33
1
PACIN
VIN
PC28
.1U_0402_16V7K
PR59
150K_0402_1%
1
RB715F_SOT323-3
PC27
2.2U_0603_6.3V6K
2
1
PR57
10K_0402_1%
2
1
<30> FSTCHG
6251VDD
PR60
100K_0402_1%
PQ15
DTC115EUA_SC70-3
PQ17
SSM3K7002FU_SC70-3
<43>
PQ11
AO4407A_SO8
8
7
6
5
PR54
47K_0402_1%
1
2
2 FSTCHG
PR55
100K_0402_1%
2
1
2
1
PD12
1SS355_SOD323-2
1
2
2
G
3
PR53
100K_0402_1%
DCIN
PQ14
DTC115EUA_SC70-3
4407A*1
4407A*2
PD10
<43>
PR51
10_0603_5%
1
2
1
2
P3
PR52
47K_0402_1%
PC25
5600P_0402_25V7K
PC26
0.1U_0603_25V7K
PQ12 TP0610K-T1-E3_SOT23-3
PR50
200K_0402_1%
PQ13
DTA144EUA_SC70-3
1
2
3
90W
120W
P3
PC164
10U_1206_25V6M
2
1
PC24
10U_1206_25V6M
2
1
PQ10
AO4407A_SO8
8
7
6
5
1
2
3
VIN
1
2
3
PC23
10U_1206_25V6M
2
1
P2
PQ9
AO4407A_SO8
8
7
6
5
PQ8
AO4407A_SO8
8
7
6
5
(120W) Iin = 3.35 ADP_I

Vin = 7.57 ADP_V
CC=0.25A~3.6A
CHGVADJ=(Vcell-4)*9.445
IREF=0.9133*Icharge
Vcell
IREF=0.228V~3.29V
4V
VCHLIM need over 95mV
4.2V
1.898V
4.35V
3.315V
CELLS
CELL number
CHGVADJ
0V
Iada=0~3.421A(65W)
CP=3.15A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=high
Iada=0~3.947A(75W)
CP=3.63A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=low
Iada=0~4.737A(90W)
CP=4.36A
PR49=0.015, PR72=53.6k, PR75=20k, PR35=unpop, PQ5=unpop
Iada=0~6.316A(120W)
CP=5.81A
PR49=0.015, PR72=8.25k, PR75=26.7k, PR35=unpop, PQ5=unpop
CP= 92%*Iada
VDD
GND
Float
Issued Date
Compal Secret Data
2008/9/25
Deciphered Date
2009/9/25
Title
Date:
SCHEMATIC,MB A6054
Rev
B
401871

D
Sheet
45
of
52
AO4712 Rds(on) = 15/18
Ipeak = 5A
Imax = 3.5A
F = 245K
PR81
13K_0402_1%
1
2
PR82
30K_0402_1%
1
2
PR83
20K_0402_1%
1
2
B++
Ipeak = 5A
Imax = 3.5A
F = 305K
PC45
1U_0603_10V6K
2VREF_51125
PR84
19.1K_0402_1%
1
2
B++
PC48
4.7U_0805_25V6-K
2
1
1
2
5
6
7
8
POK
<44,47>
10
UGATE2
UGATE1
21
LX_3V
11
PHASE2
PHASE1
20
LX_5V
LG_3V
12
LGATE2
LGATE1
19
LG_5V
2VREF_51125
VL
PC56
220U_6.3VM_R15
1 2
2
3
2
1
NC
VIN
PQ28
SSM3K7002FU_SC70-3
RT8205EGQW_WQFN24_4X4
@ PC58
680P_0603_50V7K
PC60
4.7U_0805_10V6K
2
G
2
1
PC61
0.1U_0603_25V7K
1
2
G
VL
B++
PQ27
SSM3K7002FU_SC70-3
+5VALWP
@ PR90
4.7_1206_5%
PQ26
AO4712_SO8
4
18
17
16
2
PR93
@ 0_0402_5%
ENTRIP2
14
EN
ENTRIP1
EN0
PL7
4.7UH_SIL104R-4R7PF_5.7A_30%
1
2
UG_3V
PC54
PR88
.1U_0402_16V7K
BST_5V 1
2
1
2
0_0603_5%
UG_5V
VREG5
22
PC59
1U_0402_6.3V6K
2
1
Total capacitor 220uF

ESR = 15mohm
23
BOOT1
PR91
499K_0402_1%
1
2
B+
PGOOD
BOOT2
13
<43>
PR92
100K_0402_1%
@ PC57
680P_0603_50V7K
VREG3
1
2
3
24
GND
@ PR89
4.7_1206_5%
VO1
BST_3V
15
PQ25
AO4712_SO8
1 2
PC55
220U_6.3VM_R15
8
7
6
5
PC53
.1U_0402_16V7K
PR87
1
2
1
2
0_0603_5%
VO2
SKIPSEL
PL6
4.7UH_SIL104R-4R7PF_5.7A_30%
1
2
+3VALWP
5
6
7
8
1
2
3
3
2
1
FB1
REF
PQ23
AO4466_SO8
ENTRIP1
P PAD
TONSEL
25
FB2
PU5
PC47
4.7U_0805_25V6-K
2
1
PR86
150K_0402_1%
2
PC46
2200P_0402_50V7K
ENTRIP1
1
2
8
7
6
5
PC51
4.7U_0805_25V6-K
2
1
PC50
4.7U_0805_25V6-K
2
1
PQ24
AO4466_SO8
PR85
150K_0402_1%
1
2
ENTRIP2
@ JUMP_43X118
PC52
4.7U_0805_10V6K
+3VLP
1
PC49
2200P_0402_50V7K
2
1
PC168
10U_1206_25V6M
2
1
B+
ENTRIP2
PJ24

ESR = 15mohm
PR94
100K_0402_1%
<44>
VS_ON
PQ29
PR95
100K_0402_1%
DTC115EUA_SC70-3
A
PR96
42.2K_0402_1%
VS
Compal Secret Data
2008/9/25
Issued Date
Deciphered Date
2009/9/25
Title
SCHEMATIC,MB A6054
Custom
Date:
Rev
B
401871
Sheet
1
46
of
52
PJ25
1
2
2
PC63
4.7U_0805_25V6-K
PC62
4.7U_0805_25V6-K
1.1V_B+
B+
@ JUMP_43X118
Ipeak = 12A
Imax = 8.4A
F = 315K
11
10
2
PR102
6.19K_0402_1%
PQ31
DL_1.1V
4
1
LGATE
+5VALW
RT8209BGQW_WQFN14_3P5X3P5
PC69
4.7U_0805_10V6K
(+1.1VALW, +1.1VS, NB_CORE)
+
2
TPCA8028-H_SOP-ADVANCE8-5
PR103
4.75K_0402_1%
1
2
+1.1VALWP
PC66
390U_2.5V_M
CS
VDDP
NC
PGND
GND
PGOOD
@ PC70
47P_0402_50V8J
1
2
PC67
4.7U_0603_6.3V6K
3
2
1
LX_1.1V
15
14
12
@ PR100
4.7_1206_5%
FB
PHASE
0.1U_0603_25V7K
VDD
DH_1.1V
13
VOUT
UGATE
@ PC68
680P_0603_50V7K
PL9
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2
PC65
BST_1.1V
TON
PQ30
TPCA8030-H_SOP-ADV8-5
3
2
1
PR99
0_0603_5%
1
2
PR101
100_0603_1%
1
2
+5VALW
PU6
EN/DEM
@ PC64
.1U_0402_16V7K

ESR = 6.3mohm
BOOT
PR98
0_0402_5%
1
2
POK
<44,46>
PR97
255K_0402_1%
1
2
PR104
10K_0402_1%
PJ26
11
VDDP
10
9
2
PR110
6.19K_0402_1%
+5VALW
1
2
@ PR108
4.7_1206_5%
PQ33
DL_1.5V
4
1
PGND
LGATE
0.1U_0603_25V7K
RT8209BGQW_WQFN14_3P5X3P5
PC75
220U_6.3VM_R15
CS

ESR = 2.73mohm
B
+1.5VP
PC78
4.7U_0805_10V6K
1
+
2
PR111
10K_0402_1%
1
2
PU8
APL5508-25DC-TRL_SOT89-3
PJ14
+3VS
@ JUMP_43X39
OUT
+2.5VSP
GND
1
PR112
10K_0402_1%
IN
1
2
PC80
1U_0603_10V6K
PGOOD
GND
6
@ PC79
47P_0402_50V8J
1
2
PC76
4.7U_0603_6.3V6K
B+
15
14
LX_1.5V
FB
DH_1.5V
12
13
PHASE
VDD
UGATE
@ PC77
680P_0603_50V7K
Ipeak = 11A
Imax = 7.7A
F = 315K
PL11
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2
VOUT
3
2
1
TON
BOOT
PQ32
PC74
BST_1.5V
PR109
100_0603_1%
1
2
PU7
+5VALW
@ PC73
.1U_0402_16V7K
NC
EN/DEM
0_0402_5%
3
2
1
2
1
SYSON
@ JUMP_43X118
4
PR107
0_0603_5%
1
2
PR106
<30,33>
2
PC72
4.7U_0805_25V6-K
1
2
5
PR105
255K_0402_1%
1
2
PC71
4.7U_0805_25V6-K
1.5V_B+
PC81
4.7U_0805_6.3V6K
Compal Secret Data
2008/9/25
Issued Date
2009/9/25
Deciphered Date
Title
Size
Date:

SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
1
47
of
52
GND
@ JUMP_43X79
1
2
RT9173DPSP_SO8
+1.05VSP
1
1
2
+5VALW
GND
SW
IN
BS
GND
SW
IN
POK
PL18
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2
+1.8VSP
2
PR166
0_0402_5%
TP
11
MP2121DQ-LF-Z_QFN10_3X3
PR165
4.7_1206_5%
PC91
680P_0603_50V7K
NC
PC83
0.22U_0402_10V4Z
10
VOUT
EN/SYNC
PD16
PC85
.1U_0402_16V7K
1
PJ16
FB
PU10
1
NC
PC129
10U_0805_10V4Z
NC
REFEN
PC128
10U_0805_10V4Z
1
2
GND
PC127
0.1U_0402_25V6
2
1
+5VALW
PC82
1U_0603_6.3V6M
S PQ4
SSM3K7002FU_SC70-3
PR117
10.5K_0402_1%
2
G
VCNTL
PC87
10U_0805_6.3V6M
@ PC90
.1U_0402_16V7K
VR_ON#
PR115
0_0402_5%
1
2
1
<33>
PR113
6.98K_0402_1%
PR195
10K_0402_1%
PQ48
PC86
.1U_0402_16V7K
2
G
VDDR_SW
1
<21>
VIN
2
D
@ PR194
10K_0402_1%
PR118
402K_0402_1%
2
1
PU9
1
SUSP# <30,33,45,50>
PR193
12.4K_0402_1%
SSM3K7002FU_SC70-3
316K_0402_1%
PR116
0.9V
2
1
+5VALW
PC84
4.7U_0805_6.3V6K
PC89
22U_0805_6.3V6M
LOW
PR114
200K_0402_1%
1
2
1.05V
PC88
22U_0805_6.3V6M
HIGH
VDDR
1 2
VDDR_SW
PJ15
@ JUMP_43X79
B340A_SMA2
+1.5V
+1.5V
NC
REFEN
NC
VOUT
NC
GND
+3VALW
1
VCNTL
GND
VIN
PC93
1U_0603_6.3V6M
+0.75VSP
S PQ34
SSM3K7002FU_SC70-3
PR120
1K_0402_1%
1
D
2
G
RT9173DPSP_SO8
PC95
10U_0805_6.3V6M
@ PC96
.1U_0402_16V7K
PR121
0_0402_5%
1
2
SUSP
<33>
PC94
.1U_0402_16V7K
1
PC135
22U_0805_6.3V6M
PR170
7.32K_0402_1%
FB
@ PC136
.1U_0402_16V7K
PR119
1K_0402_1%
+1.0VSP
PR168
1.82K_0402_1%
<30,33,45,50> SUSP#
EN
POK
GND
PR169
0_0402_5%
1
2
PCIE_OK
2
3
4
VOUT
VOUT
PC134
0.01U_0402_25V7K
VCNTL
VIN
VIN
8
7
PJ17
@ JUMP_43X79
PU11
PC92
4.7U_0805_6.3V6K
<42>
PU14
APL5930KAI-TRG_SO8
PR196
PC133
100K_0402_1% 4.7U_0805_6.3V6K
6
5
9
PC132
1U_0603_6.3V6M
@ PJ23
JUMP_43X79
+3VS
+5VALW
+1.5V
Madison / Park
PCIE : 1.0V
M96 / M92
PCIE : 1.1V
PR170 = 7.32K
PR170 = 4.75K
Compal Secret Data
2008/9/25
Issued Date
2009/9/25
Deciphered Date
Title
Size
Date:

SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet

1
48
of
52
CPU_B+
PC125
2
1
1 2
2
26
UGATE1
BOOT1
25
BOOT1
3
2
1
5
TP
49
24
ISN1
ISP1
23
ISP1
VW1
22
21
FB1
20
19
18
RTN0
RTN1
17
PQ40
UGATE1
3
2
1
PR149
0_0603_5%
BOOT1 1
2 1
COMP1
@PR161
@
PR161
2
1
1 2
PC118
2
1
0.1U_0603_16V7K
2
PR154
4.02K_0402_1%
@ PC124
1000P_0402_50V7K
4
@PR162
@
PR162
6.81K_0402_1%
2
1
@ PC126
2
1
54.9K_0402_1% 1200P_0402_50V7K
PR163
@ 36.5K_0402_1%
PR164
@ 36.5K_0402_1%
2008/9/25
2009/9/25
Deciphered Date
Title
Compal Secret Data
Issued Date
Date:
+CPU_CORE
PR152
16.5K_0402_1%
@ PC117
680P_0603_50V7K
LGATE1
@ PC123
180P_0402_50V8J
1
1 2
@ PR151
4.7_1206_5%
PQ42
@ TPCA8028-H_SOP-ADVANCE8-5
VW1
3
2
1
PR153
0_0402_5%
1 VSEN1
PQ41
5
4
@ PR160
1K_0402_5%
2
1
PL15
0.36UH_PCMC104T-R36MN1R17_30A_20%
PC116
0.22U_0603_10V7K
PC121
1000P_0402_50V7K
PHASE1
@ PR156 @
@PR156
@PC122
PC122
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
54.9K_0402_1% 1200P_0402_50V7K
PR145
4.02K_0402_1%
CPU_B+
PR148 0_0402_5%
PC112
2
1
0.1U_0603_16V7K
LGATE0
1RTN1
+1.5V
@ PC111
680P_0603_50V7K
ISN0
UGATE1
VW0
PR141
16.5K_0402_1%
ISP0
COMP0
12
+CPU_CORE
11
3
2
1
PHASE1
ISN1
27
COMP1
PHASE1
VDIFF1
FB0
VSEN1
10
PC113
1U_0603_10V6K
LGATE1
@ PR139
4.7_1206_5%
28
LGATE0
@ PQ39
29
PGND1
30
PC115
10U_1206_25V6M
2
1
LGATE1
VDIFF0
31
PVCC
OCSET
LGATE0
3
2
1
ISL6265AHRTZ-T_TQFN48_6X6
PC114
10U_1206_25V6M
2
1
RBIAS
+5VS
PQ38
ENABLE
PC109
10U_1206_25V6M
2
1
32
PR159
6.81K_0402_1%
2
1
@ PC161
68U_25V_M_R0.36
3
2
1
5
6
7
8
37
UGATE_NB
39
PGND0
ISN1
38
SVC
ISP1
COMP0
PHASE_NB
40
PGND_NB
LGATE_NB
DIFF_1
PC120
180P_0402_50V8J
42
PHASE0
VW0
PR158
41
UGATE0
33
10_0402_1%
RTN_NB
34
PHASE0
PR157
1K_0402_5%
2
1
OCSET_NB
UGATE0
SVD
@ PR191
@PR191
10_0402_1%
2
1
2
+CPU_CORE
44
PWROK
PR192
43
PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
PC110
0.22U_0603_10V7K
3
2
1
PQ37
PR137
0_0603_5%
BOOT0 1
2 1
PR150
1K_0402_1%
1
2
VSEN_NB
BOOT0
PR146
0_0402_5%
2
1 VSEN0
0_0402_5%
2 PR147 1 RTN0
PR190
10_0402_1%
2
1
DIFF_0
45
35
ISP0
ISN0
10_0402_1%
PR155
PC119
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
FSET_NB
36
BOOT0
14
46
BOOT_NB
PGOOD
13
FB_NB
OFS/VFIXEN
PR189
+CPU_CORE
COMP_NB
VCC
VSEN0
PR142
0_0402_5%
PR144
95.3K_0402_1%
2
1
47
48
VIN
<7>
PHASE0
BOOT_NB
ISP0
<30,33> VR_ON
PR143
21.5K_0402_1%
2
1
1
PR140
0_0402_5%2
@ PC106
680P_0603_50V7K
CPU_B+
CPU_VDDNB_RUN_FB_L
1
2
Ipeak = 36A
Imax = 25.2A
F = 300K
PC105
220U_D2_4VM

ESR = 2.22mohm
UGATE0
ISL6265_PWROK
CPU_SVD
CPU_SVC
PQ36
AO4712_SO8
PC108
10U_1206_25V6M
2
1
1
2
2
PR138 0_0402_5%
PR188
10_0402_1%
1
2
UGATE_NB
16
<7>
<7>
2
@PR136
@
PR136 0_0402_5%
+VDDNBP
PHASE_NB
1
PR133
0_0402_5%
15
<19> H_PWRGD_L
+
2
LGATE_NB
ISN0
<7,19> H_PWRGD
@ PR125
4.7_1206_5%
<7>
PR135
@ 105K_0402_1% PU12
VGATE
+
2
B+
PL13
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
PC104
0.22U_0603_10V7K
4
CPU_VDDNB_RUN_FB_H
@PR131
@
PR131
105K_0402_1%
@ PR134
10K_0402_1%
LGATE_NB
PHASE_NB
<30,33>
PR130
0_0402_5%
1
2
2
2
PR187
10_0402_1%
1
2
+VDDNB
PR129
11K_0402_1%
2
1
PC107
0.1U_0603_25V7K
1
PR132
105K_0402_1%
PR124
2.2_0603_1%
BOOT_NB 1
2 1
PR128
0_0402_5%
2
1
PR127
2_0603_5%
+3VS
+5VS
+
2
3
2
1
PHASE_NB
PR126
22K_0402_1%
2
1
PC103
0.1U_0603_16V7K
CPU_B+
PQ35
AO4466_SO8
+
2
PC102
1000P_0402_50V7K
2
1
1
+5VS
UGATE_NB
@ PC160
68U_25V_M_R0.36
PR123
2_0603_5%
1
2
PC100
1000P_0402_50V7K
PC99
68U_25V_M_R0.36
PC98
68U_25V_M_R0.36
PR122
44.2K_0402_1%
PL12
HCB4532KF-800T90_1812
1
2
PC101
10U_1206_25V6M
2
1
5
6
7
8
PC97
33P_0402_50V8J
2
1
SCHEMATIC,MB A6054
Rev
B
401871
Sheet

E
49
of
52
2 B+_core
4.7U_0805_25V6-K
PC139
2
1
DH_VCORE
1
BST_VCORE
PR171
0_0603_5%
PC143
0.1U_0603_25V7K
Ipeak =20A
Imax = 14A
F = 231K
+5VALW
15
PR173
4.7_0603_5%
UG
BOOT
16
PQ43
27138_VCC
PVCC
2 PC146
14
3
2
1
680P_0603_50V7K
1
2
PC150
10U_1206_25VAK
PC153
+
@
PC148
390U_2.5V_M
1
2
@ PC149
10U_1206_25VAK
VO
PR176
5.36K_0402_1%
3
2
1
5
ISEN_VCORE 1
11
1 2
ISEN
@ PR174
4.7_1206_5%
12
+VGA_COREP
0.56UH_ETQP4LR56WFC_21A_20%
1
2
PQ45
PGND
DL_VCORE
13
10
FB
NC
FSET
EN
PC152
.1U_0402_16V7K
LG
APW7138NITRL_SSOP16
0_0402_5%
VCC
PQ44
2
1
<30,33,45,48> SUSP#
PL17
7138_VCC
PC147
2.2U_0603_6.3V6K
2
1
2.2U_0603_6.3V6K
PR175

ESR = 3.33mohm
3
2
1
VIN
PHASE
PGOOD
GND
PU15
PR172
0_0603_5%
0_0402_5%
10U_1206_25VAK
PC138
2
1
LX_VCORE
10U_1206_25VAK
PC137
2
1
PL16
HCB4532KF-800T90_1812
PR177
B+
1.0
0.95
0.95
0.9
0.9
2
2
PR186
10K_0402_1%
2
VGA_PWRSEL0 <35>
1
PC158
.1U_0402_16V7K
2
G
3
1
1
VGA_PWRSEL1 <35>
1.12
1.2
2
G
SSM3K7002FU_SC70-3
PQ47
PR184
4.22K_0402_1%
1000P_0402_50V7K
PR183
28K_0402_1%
PR185
10K_0402_1%
1
2
SSM3K7002FU_SC70-3
PQ46
1.2
PR182
5.9K_0402_1%
@ PC165
1000P_0402_50V7K
@ PC155
0.01U_0402_25V7K
PR181
4.22K_0402_1%
1
2
M96/M92
voltage
+VGA_CORE
@PC157
@
PC157
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)
10_0402_1%
@ PC156
2200P_0402_25V7K
2
B
Madison/Park
SEL1 SEL0 voltage
57.6K_0402_1%
PR180
2
1
1
2
1
2
@ PC154
22P_0402_50V8J
@ PR179
49.9K_0402_1%
PR178
PC159
.1U_0402_16V7K
FSW=1/(75E-12*57.6K)=231.48KHz
Madison
Park
M96
M92
PR183 = 28K
PR183 = 12K
Compal Secret Data
Issued Date
2008/10/23
Deciphered Date
2009/10/23
Title
Custom
Date:
5
SCHEMATIC,MB A6054
Rev
B
401871
Sheet
1
50
of
52
PIR (Product Improve Record)

NALAE LA-6054P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
NO
DATE
PAGE
MODIFICATION LIST
---------------------------------------------------------------------------------------------------------------------------1
2009/12/14
33
Change JLEDB pin define as customer request
2009/12/14
25,28,30
Delete JODDB, JBT and JUSBB support pin
2009/12/14
33
Change JPOWER Pin2 from GND to NC
2009/12/15
28
Add R95 at JWLAN Pin5 for BT/WLAN combo Mini Card
2009/12/15
25,30
Change U11, U25 P/N from SA00002XX00 to SA000033H00
2009/12/15
28
Reverse JBT pin definition
2009/12/16
27
Change CC2 from 0.1u to 100P (SE071101J80), and add BOM structure @
2009/12/17
33
Cgange JPOWER footprint to ACES_87151-1207_12P (ZIF_)
2009/12/17
33
Cgange JTPB footprint to P-TWO_161011-04021_4P-T (NO ZIF), and reverse pin definition
10
2009/12/17
33
Cgange JLEDB footprint to ACES_85201-1205N_12P (ZIF_)
11
2009/12/17
25
Cgange JUSBB footprint to ACES_85201-20051_20P (ZIF_)
12
2009/12/17
33
Change H36, H37 footprint from H_3P3 to H_3P8
Compal Secret Data
2007/5/18
Issued Date
Deciphered Date
2008/5/18
Title
Size
Date:
SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
1
51
of
52
Version Change List ( P. I. R. List ) for Power Circuit

Page#
Item Title
Solution Description
DVT : modification from EVT
P47
change voltage divider to less than 10K
change PR104, PR111, PR112 to 10K; PR103 to 4.75K
P47
change 1.1V, 1.5V OCP value
change PR102, PR110 to 6.19K
P48
enlarge output cap
change PC88, PC89 to 22uF(SE000000I10)
P49
don't use NIPPON cap
change PC98, PC99 to SF000000S80
P49
pull high RTN1 1.5V
change PR150 to mount
P50
APW7138 pin6 is NC
change PR179, PC154, PC156 to unmount
P46
choke need to meet thermal module height
change PL6, PL7 to SH000006380
P45
change system power from 90W to 120W
P49
production line request
change PC98, PC99 to 68uF; add PC160, PC161 68uF
P45
EMI request for ISN issue
add PC162, PC163, PC164 10uF 1206
P48
mount snubber circuit
mount PR165, PC91
P44
OTP setting common
change PR30 and PR31 to 19.6K; PR34 to 7.87K; PR33 to 8.66K
P48
change IC to low cost
change PU9 and PU11 to RT9173
P48
change VDDR(1.05V) circuit to switchable
add PR193, PR194, PR195 & PQ48
change PR72 to 8.25K, PR75 to 26.7K; PQ11 to mount
PVT : modification from DVT
P49
cost down
change PC98, PC99, PC160, PC161 to SF000000W00
P46
common circuit
change PC45 to 1uF
P46
common circuit
mount PC59
P46
change PQ29 solution
change PQ29 to DTC115EUA
P45
add 65W/75W selection circuit
Add PR35 and PQ5, unmount
P47
prevent OVP for HW's cost down
change PC66 to 390uF
P48
PCIE_OK pull high +3VS
add PR196=100K
P50
For 7138 output sensing stability
add PC165=1000p unmount
P45
Add PC166, PC167, 10uF 1206
P46
Add PC168, 10uF 1206
PreMP : modification from PVT

P44
Thermal request change OTP
change PR30, PR31 to 23.7K; PR33, PR34 to 11.3K
P45
modify 65W/75W resistor
change PR72 to 53.6K; PR75 to 20K; mount PR35 and PQ5
P48
modify 1.05V voltage setting
change PR113 to 6.98K
P50
modify VGA_CORE Choke
change PL17 to SH12056BM00
P43
modify RTC circuit
Compal Secret Data
2007/5/18
Issued Date
Deciphered Date
2008/5/18
Title
Size
Date:
SCHEMATIC,MB A6054
Document Number
Rev
B
401871
Sheet
1
52
of
52

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NALAE LA-6054P Schematics Document

2009-02-04 Rev. 0.2

Compal Secret Data

Compal Electronics, Inc.

Wednesday, May 19, 2010

Model Name : NALAE

AMD S1G4 CPU

1.5V DDRIII 1066/1333MHZ

File Name : LA-6054P

Hyper Transport Link 2.6GHz

PCIeMini Card WLAN

Madison & Park

RTL 8105E 10/100

Power On/Off CKT.

Audio & USB/B

MDC 1.5 Conn

Power Circuit DC/DC

Compal Secret Data

Compal Electronics, Inc.

Wednesday, May 19, 2010

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A

Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.9A

NALAE Hamburg AMD DIS

DESIGN CURRENT 180mA

DESIGN CURRENT 300mA

Ipeak = 12A, Imax = 8.4A, Iocp_min = 18.7A

DESIGN CURRENT 12A

DESIGN CURRENT 3.5A

Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A

Ipeak = 11A, Imax = 7.7A, Iocp_min = 19.16A

DESIGN CURRENT 11A

DESIGN CURRENT 1.5A

DESIGN CURRENT 2.5A

DESIGN CURRENT 20A

Ipeak = 20A, Imax = 14A, Iocp_min = 20.14A

Compal Electronics, Inc.

Wednesday, May 19, 2010

SB820M Madison@ or PARK@

@ : just reserve , no build

S5 S4/ Battery only

S5 S4/AC & Battery

SMBUS Control Table

I2C / SMBUS ADDRESSING

CLOCK GENERATOR (EXT.)

ADI1032-1 CPU 98H

ADI1032-2 VGA 9AH

Compal Secret Data

Compal Electronics, Inc.

Wednesday, May 19, 2010

Near CPU Socket

< From NB >

< VLDT_A & VLDT_B : HyperTransport I/O ring power >

< FAN Control Circuit : Vout = 1.6 x Vset >

Compal Secret Data

Compal Electronics, Inc.

Wednesday, May 19, 2010

< DDR2 VREF is 0.5 ratio >

< Processor DDR3 Memory Interface >

< From/To SO_DIMMB >

Place them close to CPU within 1"