Clock Jitter

Clock jitter is a characteristic of the clock source and the clock

signal environment.
It can be defined as deviation of a clock edge from its ideal
location.
Clock jitter is typically caused by clock generator circuitry,
noise, power supply variations, interference from nearby
circuitry etc. Jitter is a contributing factor to the design margin
specified for timing closure.

Clock Jitter

Clock Jitter
Based on how it is measured in a system, jitter is of following types

Period jitter
Period jitter is the deviation in cycle time of a clock signal with
respect to the ideal period over a number of randomly selected
cycles. It can be specified an average value of clock period deviation
over the selected cycles.
Cycle to cycle jitter
C2C is the deviation in cycle of two adjacent clock cycles over a
random number of clock cycles. This is used to determine the high
frequency jitter.
Phase jitter
It is the frequency domain representation of rapid, short-term,
random fluctuations in the phase of a waveform. This can be
translated to jitter values for use in digital design.

Clock Jitter
Effects
Since the jitter affects the clock delay of the circuit and the
time the clock is available at sync points, setup and hold of
the path elements are affected by it.

Depending on whether the jitter causes to clock to be slower

or faster, there can be setup hold or setup violations. This will
in turn lead to performance or functional issues for the chip.

Bus Arbiter
It is desired that more than one independent processor in
system requires access to same set of system resources for
example memory size is 64 KB and require a single RD/WR
signal.
Design a system that accept data from each independent
processor and arbitrate (mediate) which one is granted access
to memory at any one time.
Each independent processor will initiate a memory-required
signal when it wants access to memory and will deactivate the
same when the job is over. If more than one processor
request for the bus at the same time, access should be
granted on round robin basis.

Bus Arbiter
This is in order to ensure that no one independent processor
is locked out while another has continuous access.
Continuous access is to be granted to any one processor for a
period of time. This time period should be separately
programmable from the data bus of one the period is not
explicitly set, a 128 clock cycle delays should default.

Bus Arbiter