UNIVERSITATEA DUNREA DE JOS DIN GALAI

FACULTATEA AUTOMATICA, CALCULATOARE, INGINERIE

ELECTRICA SI ELECTRONICA
SPECIALIZAREA INGINERIA SISTEMELOR

PROIECT ASDN

Student : Sum Ting Wong

ndrumtor : CRISTINEL CRACIUN
Grupa: 2222a

Cerine
S se minimizeze funcia :
f=
i s se implementeze cu pori logice de tip I, SAU, NU, I-NU,
SAU-NU, utiliznd un numar minim de pori i circuite integrate.

Aspecte teoretice
Algebra boolean opereaz pe o mulime B = { x/ x: { 0, 1}}.
n aceast mulime binar se definesc trei legi de compoziie: complementarea
(negare, ,,NU, NOT, inversare logic), disjuncia ( sum logic, +, SAU,
OR, U ) i conjuncia ( produs logic, *, I, AND, ).
Toate relaiile definite pe B au un caracter dual, adic relaiile rmn valabile
dac se fac schimbrile: + cu * i respectiv 0 cu 1 ( teorema dualitii ).
n mulimea B se poate alege o structura de ase axiome duale pe baza crora
se definesc teoremele i proprietile care stau la baza algebrei boolene.
Acestea sunt prezentate in continuare:

Proprieti :
1. Mulimea B este o mulime nchis:

X,Y B X + Y B ; X,Y B X*Y B;

2. Asociativitatea:

X +(Y + Z) = (X + Y) + Z ; X * (Y * Z)= (X * Y) * Z;
3. Comutativitatea:

X + Y = Y +X ; X * Y = Y * X ;
4. Distributivitatea:

X + (Y * Z) = (X + Y)*(X + Z) ; X * (Y + Z) = X * Y + X * Z;
5. Element neutru:


X+0=0+X=X; X*1=1*X=X;
6. Complementul(operaii cu negatul):

X + X = 1 ; X * X = 0;

Relaii :
1. Idempotena:

X + X +.......+X = X; X * X*.*X = X;
2. Operaii cu 1 i 0:

X + 1 = 1; X * 1 = X;

X + 0 = X; X * 0 = 0;

0 =1
1 = 0;
3. Involuia:

X = X;
4. Absorbia:

X + XY = X; X(X + Y) = X;
5. Relaiile lui De Morgan:

X Y = XY , XY = X + Y ;
6. Legile de idempoten:

X * X = X; X + X = X;

Tabel de adevar
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Diagrama Veitch-Karnaugh

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

AND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

OR
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Rezolvare
Tabel de adevr :

f = BC+D(

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

BC
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0

Diagrama Veitch- Karnaugh :

D(
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0

1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0

0
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0

Funcia minimizata cu diagrama Veitch- Karnaugh este:

f=
Se aplica legea lui DeMorgan pentru a gasi f si pentru a folosi doar porti
SI si porti SI-NU si se obtine:
f=
S1
S4

S5
S2
S3

Simulare folosind Veriwell :

S6

module project(inA,inB,inC,inD,outF);
input inA,inB,inC,inD;
output outF;
wire outF,S1,S2,S3,S4,S5,S6
not p1(S1,inA);
not p2(S2,inC);
not p3(S3,inD);
nand p4(S4,S1,inC,inD);
nand p5(S5,inB,inC,S2);
nand p6(S6,S3,inD);
endmodule

BIBLIOGRAFIE
1. Rustem POPA Curs de ASDN
2. http://ro.wikipedia.org/wiki
3. http://www.scribd.com/

ANEXE

module project_test;
reg A,B,C,D;
wire F;
initial
begin
$vw_dumpvars;
$monitor($time, "A=%b B=%b C=%b D=
%b F=%b",A,B,C,D,F);
#10 A=0; B=0; C=0; D=0;
#10 D=1;
#10 C=1; D=0;
#10 D=1;
#10 C=0; D=0; B=1;
#10 D=1;
#10 D=0; C=1;
#10 D=1;
#10 D=0; C=0; B=0; A=1;
#10 D=1;
#10 C=1; D=0;
#10 D=1;
#10 C=0; D=0; B=1;
#10 D=1;
#10 D=0; C=1;
#10 D=1;
#10 $finish;
end
project test(A,B,C,D,F);
endmodule