DIGITAL ELECTRONICS (331102)

PRACTICAL: 07

TO STUDY PARALLEL ADDER AND PARALLEL

SUBTRACTOR
1.0 AIM :

 To study parallel adder and parallel substractor.

2.0 PRIOR CONCEPTS :

 Knowledge of working of AND, OR, NOT gate.

 Knowledge of working of NAND and Ex - OR gates.

 Working of Half and full adder.

 Working of Half and Full Substractor.

3.0 INTRODUCTION :

 Number of full adder circuits depends on no. of bits in inputs. i.e. for two-bit
numbers, two full adders are needed, for 3-bit numbers three adders are needed
and so on.

 The carry output of previous adder circuit is connected to the carry input of the
next adder circuit.

 Either a half adder can be used for least significant position or full adder is used
with carry input tied to zero as there is no carry into the least significant bit
position.

28 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
 DIGITAL ELECTRONICS (331102)

4.0 EXERCISE :

4.1 Design a 2-bit parallel adder and fill the truth table as shown below

29 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
 DIGITAL ELECTRONICS (331102)

5.0 ASSIGNMENT :

5.1 Draw the 4-bit parallel adder circuit and state its truth table.
5.2 Design the single digit BCD adder using 4-bit adders.
5.3 Draw 8-bit adder as a cascade of two 4-bit adders.
5.4 From above figures of parallel adder, design a 4 - bit parallel substractor.

Grades for Exercise: .................................................

Grades for Assignment: .................................................

Signature of Lab Co-ordinators: .................................................

30 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))