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PRACTICAL: 10
3.0 INTRODUCTION
The most common error detection code used is the parity bit.
A parity bit is an extra bit included with a binary message to make the total
number of 1's either odd or even.
In case of even parity, the parity bit is chosen so that the total number of 1's in
the coded message is even.
Alternatively, odd parity can be used in which the total number of 1's in the
coded message is made odd.
At the receiving-end a parity checker is used to detect single bit error in the
transmitted data word by regenerate the parity bit in the same fashion as the
generator and then compare with the parity bit transmitted.
39 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
An even-parity bit checker will produce an error (“1”) if the number of bits in the
entire group of digits – including the parity bit – is not an even number.
Example: For the following group of digits – 10111 – the error output would be a
“0”; for 10101, the error output would be a “1”.
5.0 EXERCISE :
40 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
5.2 Fill up the following truth table for an even parity generator.
41 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
5.3 Fill up the following truth table for an even parity checker.
5.4 Can we design the whole circuit using NAND gates? Why or Why not?
42 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
6.0 ASSIGNMENTS :
6.1 With reference to the figures of even parity checker and generator draw
the figures of odd parity generator and checker.
6.2 Can the even – parity checker detect the following error in transmission?
Why or why not?
Transmitted data : 0101 0011
Received date : 0100 0010
6.3 Design the parity generator circuit using NAND gate.
6.4 Design the parity checker circuit using NOR gate.
43 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))