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VLSI Testing
Testing
Introduction
Introduction
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org
Reading
Reading Material
Material
Text Book:
M.L. Bushnell and V.D. Agrawal, Essentials of
1.
2.
3.
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Acknowledgement
Acknowledgement
Prof. Hideo Fujiwara, NAIST, Japan
Prof. Kewal K. Saluja, Univ. of Wisconsin, USA
Prof. Michiko Inoue, NAIST, Japan
Prof. Vishwani D. Agrawal, Auburn Univ., USA
Prof. Samiha Mourad, Santa Clara Univ., USA
Prof. Erik Larsson, Linkoping Univ., Sweden
Dr. Rubin Parekhji, TI, Bangalore
Dr. Subir Roy, TI, Bangalore
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VLSI
VLSI Realization
Realization Process
Process
Customers need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer
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Definitions
Definitions
Design synthesis: Given an I/O function, develop a
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Verification
Verification vs.
vs. Test
Test
Verification
Verifies correctness of
design.
Performed by simulation,
hardware emulation, or
formal methods.
Test
Verifies correctness of
manufactured hardware.
Two-part process:
1. Test generation: software
process executed once
during design
2. Test application: electrical
tests applied to hardware
Test application performed on
every manufactured device.
Responsible for quality of
devices.
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Problems
Problems of
of Ideal
Ideal Tests
Tests
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Real
Real Tests
Tests
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Testing
Testing as
as Filter
Filter Process
Process
Good chips
Prob(good) = y
Fabricated
chips
Pr
s
s
pa
(
ob
=
)
st
te
te
st
)
w
lo
=l
ow
Defective chips
Prob(bad) = 1- y
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Mostly
good
chips
Tested
chips
Mostly
bad
chips
Roles
Roles of
of Testing
Testing
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Costs
Costs of
of Testing
Testing
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Design
Design for
for Testability
Testability (DFT)
(DFT)
DFT refers to hardware design styles or added hardware
that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Primary
Primary
bus
Logic
Logic
outputs
inputs
block A
block B
(PO)
(PI)
Test
input
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Test
output
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Testing
Testing Principle
Principle
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ADVANTEST
ADVANTEST Model
Model
T6682
T6682 ATE
ATE
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Cost
Cost of
of Manufacturing
Manufacturing
Testing
Testing
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40,000
100
al
t
To st
co
Fixed cost
25,000
20,000
50
Va
l
b
ria
Average cost
t
s
co
50k
100k
150k
Cost
Cost Analysis
Analysis Graph
Graph
0
200k
Miles Driven
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A
A Modern
Modern VLSI
VLSI Device
Device
System-on-a-chip
System-on-a-chip (SOC)
(SOC)
Data
terminal
DSP
core
RAM
ROM
Interface
logic
Mixedsignal
Codec
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Transmission
medium
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