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PR #2 Sistem Digital

1.

2.

3. Consider figure below. This cell blocks implements the function


Derive the CMOS complex gate that implements this cell.

4. Using NOR plane such as in Figure 3.66 Fundamental of Digital Logic with VHDL Design.

Draw a picture of PLA programmed to implement


The PLA should have the inputs x1, x2, x3. The Product terms P1, P2, P3, P4. The output f1 and f2

5. Fungsi :
i.

ii.

)
)

a. Implementasi fungsi diatas menggunakan AND-OR PAL dengan 4 masukan (a,b,c,d), 4


product term (P1, P2, P3, P4) dan 2 output (f1, f2)
b. Implementasi f1 menggunakan 2 input LUT

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