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BTSE

Link
Interface

SN

Link
Interface

TRAU
SGSN

BSC

PCU

BSC
Control

BTSE
OMC

LMT

Fig. 1 BSC architecture (MN1780EU09MN_0001 BSC Architecture, 4)

Abis

Asub

via PCMB

BSC
BTSE
PCM30/24

Link
Interface
.
.
.

Link
Interface

via PCMS

SN-1
SN-0

Link
Interface
.
.
.

Link
Interface

TRAU
PCM30/24
SGSN

BTSE

Gb
via PCMG
Fig. 2 Asub, Abis and Gb interfaces (MN1780EU09MN_0001 BSC Architecture, 5)

4x16 kbit/s
Traffic Channels

4x16 kbit/s
Traffic Channels
3 2 1 0

3 2 1 0

BSC
Link
Interface
Abis

SN-1
SN-0

.
.
.

Link
Interface
.
.
.

Link
Interface

Link
Interface

Asub

TRAU

Gb
SGSN

Packet
Control Unit
3 2 1 0

4x16 kbit/s
Packet Data
Channels

Permanent Virtual
Connection PVC
in Frame Relay
(64 kbit/s
channelized)
Fig. 3 BSC traffic channel switching (MN1780EU09MN_0001 BSC Architecture, 6)

CCSS 7
64 kbit/s

CCSS 7
64 kbit/s

4x16 kbit/s TCH

1x16 kbit/s TCH

BSC

TRAU

MSC

PCU
BTSE

LAPD

Abis

LAPD

Asub

A
BSS GPRS Protocol
(over Frame Relay)

Gb

SGSN

Fig. 4 SBS external and internal signaling (MN1780EU09MN_0001 BSC Architecture, 7)

LPDLM&LPDLR

Um

BTSE

LPDLS

TRAU

BSC
PCMB
Abis

PCU

CCSS7

PCMS
Asub

MSC
PCMA
A

BSSGP
SGSN
PCMG
Gb

Fig. 5 Interfaces and signaling (MN1780EU09MN_0001 BSC Architecture, 8)

CCSS 7
64 kbit/s

CCSS 7
64 kbit/s

4x16 kbit/s TCH

1x16 kbit/s TCH

BSC

BTSE

LAPD

Abis

TRAU

MSC

LAPD

Asub

Fig. 6 CCSS#7signaling (MN1780EU09MN_0001 BSC Architecture, 9)

CCSS 7
64 kbit/s

BTSE

BSC

CCSS 7
64 kbit/s

TRAU

MSC

LAPD
LAPD

Abis

Asub

Not used

Fig. 7 CCSS7 and LAPD signaling (MN1780EU09MN_0001 BSC Architecture, 10)

Line Termination
QTLP

Clock

Line Termination

PLLH

QTLP

Line Termination

Line Termination
QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processors
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 8 BSC internal architecture (MN1780EU09MN_0001 BSC Architecture, 13)

QTLP

LPDLM/R

BTSE

LPDLS

Line
Termination

Line
Termination

TRAU

CCS7

BTSE

Line
Termination

Line
Termination

P
C
U

BSC

B
S
S
G
P

B
S
S
G
P

Switching
Network
Peripheral Processors

L
A
P
D

C
C
S
7

SGSN

BSSGP

Telephony
Processor
Fig. 9 Switching network (MN1780EU09MN_0001 BSC Architecture, 15)

Line Termination

Clock

Line Termination

QTLP

PLLH

QTLP

Line Termination

Line Termination
QTLP

QTLP

Line Termination
Switching
Network

QTLP

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
P
S
P
S
X
G
X
PO

L
A
P
D

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 10 Peripheral processor for CCSS7 (MN1780EU09MN_0001 BSC Architecture, 17)

Line Termination

Line Termination

Clock

Line Termination

QTLP

PLLH

QTLP

Line Termination

Line Termination

QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 11 Peripheral processor for LAPD (MN1780EU09MN_0001 BSC Architecture, 18)

QTLP

Clock

Line Termination

QTLP

PLLH

QTLP

Line Termination

Line Termination

QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Periphal
Processors

Fig. 12 Telephony processor (TDPC, MEMT) (MN1780EU09MN_0001 BSC Architecture, 19)

Line Termination

Line Termination

Clock

QTLP

PLLH

Line Termination
QTLP

Line Termination

Line Termination

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 13 Administrative processor (MPCC, UBEX) (MN1780EU09MN_0001 BSC Architecture, 21)

QTLP

Line Termination

Clock

Line Termination

QTLP

PLLH

QTLP

Line Termination

Line Termination

QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 14 Line termination QTLP (MN1780EU09MN_0001 BSC Architecture, 22)

QTLP

Port 0

TRAU 1
BTSE 1

Port 1

TRAU 2
BTSE 2

B
A

Port 2

TRAU 3
BTSE 3

Port 3

BTSE 4

QTLP
Fig. 15 Mixed configuration of QTLP (ports 0 ... 2: transparent mode, port 3: selection mode) (MN1780EU09MN_0001 BSC Architecture, 23)

Line Termination

Clock

QTLP

PLLH

Line Termination
QTLP

Line Termination

Line Termination
QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

QTLP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

C
C
S
7

Telephony Processors
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC

TDPC

DK 40
DK 40

UBEX
to OMC

Hard Disk
Disk
Hard

P
P
X
X

Peripheral
Processors

Fig. 16 Hard Disk (MN1780EU09MN_0001 BSC Architecture, 24)

SNAP

...

...

And more . . .

LOG

BSC Event Log Files

MEASURE_DIR

Perform. Measurem. (active)

READY_CTR

CTR Measurements (for upload)

READY_MEAS

Perform. Measurem. (for upload)


Remote Inventory Files

REMINV

SWH_DIR/RSUSWLH/0

BSC software

SWH_DIR/RSUSWLH/1

BTSM software

SWH_DIR/RSUSWLH/2

TRAU software

SWH_DIR/RSUDB/0

BSC database

TRACE_IMSI

IMSI Traces

TRACE_CTR

Cell Traffic Records

Fig. 17 System directories on Hard Disk (MN1780EU09MN_0001 BSC Architecture, 25)

Line Termination
QTLP

Clock

Line Termination

PLLH

QTLP

Line Termination

Line Termination

QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processor
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 18 O&M interface on IXLT (MN1780EU09MN_0001 BSC Architecture, 26)

QTLP

BSC
TRAU
BTSE

MSC

IXLT

SBS
X.21/V.11

LMT
Fig. 19 Connection BSC - LMT (MN1780EU09MN_0001 BSC Architecture, 27)

No transcoding

SBS
64 kbit/s

64 kbit/s

nailed-up
connection

BSC
BTSE

TRAU

IXLT

X.25 Line

S IE M E N S
N IX D O R F

S IE M E N S
N IX D O R F

MSC

PSDN

S IE M E N S
N IX D O R F

64 kbit/s

OMC-B
Fig. 20 Connection BSC - OMC (MN1780EU09MN_0001 BSC Architecture, 28)

Line Termination
QTLP

Clock

Line Termination

PLLH

QTLP

Line Termination

Line Termination
QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

QTLP

B
S
S
G
P

P
P
L
D

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processors
MEMT

to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

TDPC

C
C
S
7

P
P
X
X

Peripheral
Processors

Fig. 21 Clock PLLH (MN1780EU09MN_0001 BSC Architecture, 29)

SNAP

Gb:
standard interface

BSC

i/f

i/f

SGSN

PCU
BTSE

Abis:
proprietary

PCU tasks
Management of GPRS radio resources
Protocol conversion (packet data interworking)
Tasks comparable to classical BSC
Remote (until now BTS tasks): PC, TA,...

Fig. 22 PCU functions (MN1780EU09MN_0001 BSC Architecture, 30)

BSC

max. 2 PCUs

PCU
PPCU
Peripheral Packet
Control Unit

Providing
Service

cell 1

PPCU

PCU
PPCU

PPCU

Cold
Standby

Providing
Service

Cold
Standby

cell 3

cell n+1

cell 2

cell n+1

cell n

cell n+x

cell n+2

Fig. 23 PCU implementation with PPCU (MN1780EU09MN_0001 BSC Architecture, 31)

Cell E

Cell C

Cell A
Cell B

PPXU-0

Cell F

Cell D

PPXU-1

PPXU-2

To SGSN
GPRS traffic is automatically distributed among (working) PPXU
well balanced
in case of failure, packet traffic is automatically redistributed
among the remaining PPXU (load sharing)
Fig. 24 Load sharing between PPXU (MN1780EU09MN_0001 BSC Architecture, 31)

Clock

Line Termination

Line Termination

PLLH

QTLP

QTLP

Line Termination

Line Termination

QTLP

QTLP

Line Termination

Line Termination
Switching
Network

QTLP

SNAP

B
S
S
G
P

P
P
X
X

B
S
S
G
P

P
P
X
X

...

B
S
S
G
P

Administrative
Extended Bus
L
A
P
D

P
P
X
X

P
P
X
X

Telephony Processors

Administrative
Extended Bus

MEMT

C
C
S
7

P
P
X
X

Telephony
System Bus

TDPC

Administrative
System Bus
to LMT

O&M
Interface

Administrative
Processor

IXLT

MPCC
UBEX

to OMC

Fig. 25 Bus systems (MN1780EU09MN_0001 BSC Architecture, 32)

QTLP

Q
T
L
P
8

Q
T
L
P
7

Q
T
L
P
6

Q
T
L
P
5

Q
T
L
P
4

Q
T
L
P
3

P P P P P
P P P P P
L L L L L
D D D D D
14 13 12 11 10

P
P
L
D
9

P
P
L
D
8

P
P
L
D
3

Expansion
P
W
R
S
0

Q
T
L
P
2

Q
T
L
P
S
1

P
P
L
D
7

P
P
L
D
6

P
P
L
D
5

P
P
L
D
4

P
W
R
S
1

Fuse and Alarm


Panel

P
W
R
S
0

P
L
L
H
0

Q
T
L
P
1

Q
T
L
P
0

T
D
P
C
0

M
E
M
T
0

Base
D I U S
K X B N
40 L E 1
0 T X 6
0 0 0

Q
T
L
P
S
0

P
P
C
C
1

P
P
C
C
0

MM
P P
C C
C C
0 1

P
P
L
D
2

P
P
L
D
1

P
P
L
D
0

M
E
M
T
1

T
D
P
C
1

P
L
L
H
1

S
N
1
6
1

U
B
E
X
1

P
W
R
S
1

I D
X K
L 40
T 1
1

Fig. 26 BSC rack (BSC "classic", without PCU) (MN1780EU09MN_0001 BSC Architecture, 35)

Lamp Panel

Q
T
L
P
8

Q
T
L
P
7

Q
T
L
P
6

Q
T
L
P
5

Q
T
L
P
4

Q
T
L
P
3

P
P
C
U
0

P
P
C
U
1

P
P
C
U
3

Expansion
P
W
R
S
0

Q
T
L
P
2

Q
T
L
P
S
1

P
P
C
U
2

P
P
L
D
6

P
P
L
D
5

P
P
L
D
4

P
P
L
D
3

P
W
R
S
1

Fuse and Alarm


Panel

P
W
R
S
0

P
L
L
H
0

Q
T
L
P
1

Q
T
L
P
0

T
D
P
C
0

M
E
M
T
0

Base
D I U S
K X B N
40 L E 1
0 T X 6
0 0 0

Q
T
L
P
S
0

P
P
C
C
1

P
P
C
C
0

MM
P P
C C
C C
0 1

P
P
L
D
2

P
P
L
D
1

P
P
L
D
0

M
E
M
T
1

T
D
P
C
1

P
L
L
H
1

S
N
1
6
1

U
B
E
X
1

P
W
R
S
1

I D
X K
L 40
T 1
1

Fig. 27 BSC rack (BSC "classic", fully equipped with PPCU) (MN1780EU09MN_0001 BSC Architecture, 36)

Lamp Panel

Lamp Panel
Q
T
L
P
7

Q
T
L
P
6

Q
T
L
P
5

Q
T
L
P
4

Q
T
L
P
3

P
P
X
X
7

P
P
X
X
6

P
P
X
X
5

Expansion
E
P
W
R
0

Q
T
L
P
2

Q
T
L
P
S
1

P
P
X
X
4

P
P
X
X
3

P
P
X
X
2

E
P
W
R
1

Fuse and Alarm


Panel

P
W
R
S
0

P
L
L
H
0

Q
T
L
P
1

Q
T
L
P
0

T
D
P
C
0

M
E
M
T
0

Base
D I U S
K X B N
40 L E A
0 T X P
0 0 0

Q
T
L
P
S
0

P
P
X
X
1

P
P
X
X
0

MM
P P
C C
C C
0 1

M
E
M
T
1

P
L
L
H
1

T
D
P
C
1

S
N
A
P
1

U
B
E
X
1

P
W
R
S
1

I
X
L
T
1

Fig. 28 BSC rack (BSC High Capacity 1st Step) (MN1780EU09MN_0001 BSC Architecture, 37)

Q
T
L
P
8

P
W
R
S

P
L
L
H

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
C
C

P
P
C
C

P
P
L
D

P
P
L
D

P
P
L
D

P
L
L
H

P
W
R
S

D
K
4
0

I
X
L
T

U
B
E
X

S
N
1
6

T
D
P
C

M
E
M
T

M
P
C
C

M
P
C
C

M
E
M
T

T
D
P
C

S
N
1
6

U
B
E
X

I
X
L
T

D
K
4
0

Fig. 29 DC power distribution in the base subrack (MN1780EU09MN_0001 BSC Architecture, 40)

P
W
R
S

P
L
L
H

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
X
X

P
P
X
X

P
L
L
H

P
W
R
S

D
K
4
0

I
X
L
T

U
B
E
X

S
N
A
P

T
D
P
C

M
E
M
T

M
P
C
C

M
P
C
C

M
E
M
T

T
D
P
C

S
N
A
P

U
B
E
X

I
X
L
T

Fig. 30 DC power distribution in the base subrack (BSC High-Capacity 1st Step) (MN1780EU09MN_0001 BSC Architecture, 41)

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

14

13

12

11

10

E
P
W
R

Q
T
L
P

Q
T
L
P

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

E
P
W
R

Fig. 31 DC power distribution in the expansion subrack (no PCU, BSC "classic") (MN1780EU09MN_0001 BSC Architecture, 42)

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
C
U

15

14

E
P
W
R

Q
T
L
P

Q
T
L
P

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
C
U

P
P
C
U
13

P
P
C
U

12

11

10

P
P
L
D

P
P
L
D

P
P
L
D

P
P
L
D

E
P
W
R

Fig. 32 DC power distribution in the expansion subrack (2 PCU, BSC "classic") (MN1780EU09MN_0001 BSC Architecture, 43)

Q
T
L
P

Q
T
L
P

Q
T
L
P

E
P
W
R

Q
T
L
P

Q
T
L
P

Q
T
L
P

P
P
X
X
15

14

Q
T
L
P

Q
T
L
P

P
P
X
X

13

P
P
X
X
12

11

P
P
X
X
7

P
P
X
X
10

P
P
X
X
5

E
P
W
R
3

Fig. 33 DC power distribution in the expansion subrack (fully equipped with PCU, BSC HC 1st Step) (MN1780EU09MN_0001 BSC Architecture, 43)