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Lesson 1
8051/8031Architecture
overview
2011
2011
2011
CPU Registers
8- bit A (Accumulator) Register
8-bit B Register
8- bit PSW (Processor Status
Word)
8-bit Stack Pointer SP
2011
A as Accumulator in instructions
B for MUL and DIV
PSW for Processor Status Word
for flag bits and register-bank
selection bits
SP for stack at internal memory
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2011
Execution Unit
IR
ID
Control
and
Sequencer
Circuits
SP
A
B
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Temp 1
Temp 2
ALU
+, ,
or
Rotate
DAA
OR,
AND,
XOR
PSW
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10
PSW
PSW.0
PSW.1
PSW.2
PSW.3
PSW.4
PSW.5
PSW.6
PSW.7
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P
F1
OV
RS0
Zero flag
User Flag1
Default value
= All 0s
Overflow flag
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PC
Default value
= 0000H
2011
Not an
SFR
Increases by
01H for next
instruction
fetch
12
Internal bus
Fetch
Decode
Execution
IR
ID
Control
and
Sequencer
Circuits
13
Instruction Execution
Instruction
STAGE 1
Fetch
STAGE 2
Instruction
Decode
STAGE 3 to n
Instruction
Execute
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clock
cycle (s)
Time
14
2011
15
16
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17
SFRs
Internal RAM
Program
memory
AD0 AD7
A8-A15
Buses
Ports P0
Interface and P2
option Unit
ALE
PSEN
Internal Bus 16-bit
RD
Internal Bus
Address
WR
8-bit
Microcontrollers-...
2nd
Ed.
Raj
Kamal
2011
Pearson Education
Bus 16-bit
PC
program
memory
or data
memory
18
Internal Devices
19
Internal Devices
Serial Interface SI-option UART full
duplex or half duplex serial
synchronous bits with separate clock
bits
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P0
T0
SI
T1
IR
ID
Reset
Osc
Interrupt
Control
Execution
unit
Condition test
branch logic
Internal
ROM
A8-A15
P2
WDT
IO and internal
devices SFRs
Port P3
Port P1
AD0-AD8
A, B,PSW, SP
DPTR
Register Banks of 8
registers and
internal RAM
PC
22
2011
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Bit- Addresses
PSW.7
D7H
PSW.6
D6H
D5H
D4H
D3H
PSW.5
PSW.4
D2H
PSW.2
D1H
D9H
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PSW
Default value
= All 0s
PSW.7
Byte
Address
= D0H
PSW.3
PSW.1
PSW.0
PSW.7PSW.0
PSW.0
Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education
24
Accumulator
A and B
A
Default
value
= 00H
SFR
Address
E0H
Bit-Addresses
E0-E7H
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For
MUL
and DIV
SFR
Address
F0H
Default
value
= 00H
Bit-Addresses
F0-F7H
25
SP
Default value
= 07H
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SFR
Address
81H
Increases by
01H before
push,
decreases
after pop by
01H
26
Lower byte
Default
value
= 0000H
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DPTR
Higher byte
DPL
DPH
SFR
Address
82H
SFR
Address
83H
27
8051
Internal ROM
External ROM
Internal ROM Addresses
Used when EA = 1
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constants
and
stored
tables
Memory
28
Bank-registers and
Internal RAM
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8051
special
feature
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Internal RAM
including 4
Registers Banks
External RAM
A,B, PSW
8 registers
each
bank
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8051 Pins
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RST
P3.7 to P3.0
XTAL2
XTAL1
VSS
VDD
P0.0 to P0.7
EA
ALE
8051 PSEN
P2.7 to P2.0
AD0 AD7
options
P1.0 to P1.7
A8-A15
P3 options
WR, RD, T1, T0, INT1/GT1, INT0/GT0,
TxD/CLK, RxD/Data
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Oscillator Circuit
XTAL
XTAL1
C-Osc
8051
XTAL2
C-Osc
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Supply circuit
< 1cm
VSS
8051
VDD
Cd
decoupling
capacitor
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Reset circuit
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Internal Resistance
VDD
< 1cm
RST
8051
VSS
Cd
decoupling
capacitor
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VDD
8051
< 1cm
Push
button
for
manual
reset
RST
VSS
Cd
decoupling
capacitor
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Summary
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We learnt
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We learnt
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We learnt
Internal Devices
T0 and T1
SI
WDT
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We learnt
Pins
Port P0 with option of AD0-AD7
Port P1
Port P2 with option of AD8-AD15,
Port P3 with options WR, RD, T1, T0,
INT1/GT1, INT0/GT0, TxD/CLK,
RxD/Data
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We learnt
Pins
VDD and VSS
XTAL1and XTAL2
EA, ALE, PSEN, RST
2011
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