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  • Design and Simulation of Moore Logic Circuit Based SAR Analog To Digital Converter

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    AI Coordinator - CSC Journals
    57 vizualizări13 pagini
    In this work the circuit of 4 bit successive approximation Register Analog to digital converter is designed and simulated by using Multisim 11 program. Here the proposed circuit is designed with the sequential synchronous logic circuit idea by using Moore theory for the first time, so the state diagram is built and then implemented by using J-k flip flop, the proposed circuit is tested by DC and AC input voltages, so that the maximum voltage is 5 v and minimum voltage is 0 v, and so the step voltage will be 0.3125 v. SAR ADC needs Digital to Analog circuit, Latch circuit, and comparator which compare between the input voltage and the voltage results from the DAC, and all these circuits were built in this work with all they needs.

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    Design and Simulation of Moore Logic Circuit based SAR Analog to Digital Converter

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    In this work the circuit of 4 bit successive approximation Register Analog to digital converter is designed and simulated by using Multisim 11 program. Here the proposed circuit is designed with the sequential synchronous logic circuit idea by using Moore theory for the first time, so the state diagram is built and then implemented by using J-k flip flop, the proposed circuit is tested by DC and AC input voltages, so that the maximum voltage is 5 v and minimum voltage is 0 v, and so the step voltage will be 0.3125 v. SAR ADC needs Digital to Analog circuit, Latch circuit, and comparator which compare between the input voltage and the voltage results from the DAC, and all these circuits were built in this work with all they needs.

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    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    57 vizualizări13 pagini

    Design and Simulation of Moore Logic Circuit Based SAR Analog To Digital Converter

    Încărcat de

    AI Coordinator - CSC Journals
    In this work the circuit of 4 bit successive approximation Register Analog to digital converter is designed and simulated by using Multisim 11 program. Here the proposed circuit is designed with the sequential synchronous logic circuit idea by using Moore theory for the first time, so the state diagram is built and then implemented by using J-k flip flop, the proposed circuit is tested by DC and AC input voltages, so that the maximum voltage is 5 v and minimum voltage is 0 v, and so the step voltage will be 0.3125 v. SAR ADC needs Digital to Analog circuit, Latch circuit, and comparator which compare between the input voltage and the voltage results from the DAC, and all these circuits were built in this work with all they needs.

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    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
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    din 13

    Design and Simulation of Moore Logic Circuit based

    SAR Analog to Digital Converter


    Osama Q.J Al-Thahab
    Engineering Faculity/Electgrical Department
    University of Babylon
    Babylon, Iraq

    oalthahab@yahoo.com

    Hanaa mohsin ali


    Engineering Faculity/Electgrical Department
    University of Babylon
    Babylon, Iraq

    ahanaamohsin@yahoo.com

    Abstract

    Keywords:

    1. Introduction

    2. Types of ADC
    2.1 Flash ADC

    Logic Encoder

    2.2 Digital ramp ADC

    FIGURE1:

    FIGURE2:

    2.3 Tracking ADC

    FIGURE

    2.4 Successive Approximation ADC

    FIGURE4

    3. proposed Moore SAR Logic circuit

    FIGURE 5:

    0000

    1
    1000
    0

    0100
    0

    0
    0001

    1100
    1

    0010

    0110

    0011

    1010
    1

    0101

    0
    0111

    1001

    1
    1110

    1011

    1101

    1111

    FIGURE 6:

    previous State
    y4 y3 y2 y1

    Next State
    X= 0
    X= 1

    TABLE 1:

    J4K4

    Input (X= 0)
    J3K3
    J2K2

    TABLE 2:

    J1K1

    J4K4

    Input (X= 1)
    J3K3
    J2K2

    J1K1

    000

    001

    011

    010

    110

    111

    101

    100

    00
    01
    11
    10

    TABLE 3:

    X
    CLK

    y1

    X
    y4

    y3

    y2

    y2

    y1

    y3
    y4
    SET
    J

    CLK

    5V

    ~Q
    RESET

    SET
    J

    CLK
    K

    ~Q
    RESET

    SET
    J

    CLK
    K

    ~Q
    RESET

    X
    CLK
    SET
    J

    CLK
    K

    4. Digital To Analog Circuit

    y1

    y1 y2
    y2 y3
    y3 y4
    y4

    ~Q
    RESET

    FIGURE 8:

    X
    CLK

    jksarblock

    LSB
    Do

    MSB
    D1

    2R

    2R

    D2
    2R

    D3
    2R

    2R

    y1
    y2
    y3
    y4

    Ref

    y1
    y2
    y3
    y4

    DAC
    (b)

    FIGURE 9:

    5. Comparator

    6. Clock

    VCC
    GND

    Clouck

    FIGURE 10:

    7. JK-Counter

    CLK

    8. Latch

    y1

    y3 y2 y1
    SET
    J

    VCC
    5V

    y2
    Q

    y3

    CLK
    K

    ~Q
    RESET

    CLK

    SET
    J

    CLK
    K

    ~Q
    RESET

    SET
    J

    CLK
    K

    CLK

    y1

    CLK

    y1 y2
    y2 y3
    y3

    ~Q
    RESET

    JK-counter

    y1

    Q1

    y2

    Q2

    SET

    y3

    y4

    CLK

    Q3

    ~Q

    Q4

    RESET

    CLK

    SET
    D

    CLK

    ~Q

    RESET

    SET
    D

    CLK

    ~Q

    RESET

    SET
    D

    CLK

    ~Q

    RESET

    FIGURE 11:

    y1
    y2
    y3
    y4
    CLK

    y1
    y2
    y3
    y4
    CLK

    Q1
    Q2
    Q3
    Q4

    DLatch1

    Q1
    Q2
    Q3
    Q4

    9. Proposed Moore SAR ADC

    10. Results and Discussion

    COMPARATOR_VIRTUAL

    G
    T
    A

    Vref
    X
    CLK

    y1

    X
    CLK

    y1
    y2
    y3
    y4

    y1 y2
    y2 y3
    y3 y4
    y4

    y1
    y2
    y3
    y4

    jksarblock

    DCD_HEX_DIG_RED

    DAC
    y1
    y2
    y3
    y4
    CLK

    Q1

    y1
    y2
    y3
    y4
    CLK

    Q1 Q2
    Q2 Q3
    Q3 Q4
    Q4

    DLatch1

    5V

    VCC
    GND

    CLK

    CLK

    Clouck

    y1

    CLK

    y1 y2
    y2 y3
    y3

    JK-counter

    FIGURE 12:

    COMPARATOR_VIRTUAL

    G
    T
    A

    Vref
    X
    CLK

    X
    CLK

    y1

    y1 y2
    y2 y3
    y3 y4
    y4

    y1
    y2
    y3
    y4

    y1
    y2
    y3
    y4

    jksarblock

    DAC
    y1
    y2
    y3
    y4
    CLK

    y1
    y2
    y3
    y4
    CLK

    Clouck

    CLK

    CLK

    CLK

    JK-counter

    FIGURE 13

    y1

    y1 y2
    y2 y3
    y3

    Q1

    Q1 Q2
    Q2 Q3
    Q3 Q4
    Q4

    DLatch1

    5V

    VCC
    GND

    3 V

    DCD_HEX_DIG_RED

    FIGURE 14:

    COMPARATOR_VIRTUAL

    G
    T
    A

    Vref
    y1
    y2
    y3
    y4

    y1
    y2
    y3
    y4

    1.5 V

    DAC
    y1
    y2
    y3
    y4
    CLK

    y1
    y2
    y3
    y4
    CLK

    DLatch1

    FIGURE 15:

    Q1

    Q1 Q2
    Q2 Q3
    Q3 Q4
    Q4

    DCD_HEX_DIG_RED

    COMPARATOR_VIRTUAL

    G
    T
    A

    Vref
    y1
    y2
    y3
    y4

    y1
    y2
    y3
    y4

    DCD_HEX_DIG_RED

    5 V

    DAC
    y1
    y2
    y3
    y4
    CLK

    Q1

    y1
    y2
    y3
    y4
    CLK

    Q1 Q2
    Q2 Q3
    Q3 Q4
    Q4

    DLatch1

    FIGURE 16:

    COMPARATOR_VIRTUAL

    G
    T
    A

    Vref
    y1
    y2
    y3
    y4

    y1
    y2
    y3
    y4

    5 Vpk
    10 Hz
    0

    DAC
    y1
    y2
    y3
    y4
    CLK

    y1
    y2
    y3
    y4
    CLK

    DLatch1

    FIGURE 17:

    Q1

    Q1 Q2
    Q2 Q3
    Q3 Q4
    Q4

    DCD_HEX_DIG_RED

    11. Conclusion

    12. Future work

    13. REFERENCES

    Engineering.

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