Final Project Report

CMOS Amplifier Configurations

Yuan Tian & Kevin Bradshaw
ECEN 325-503
Instructor: Sebastian Hoyos
November 30, 2015
Items
1
2
3
4
5
6
7

Pre-lab
Title Page
Intro /Theory / Procedure
Summary
Experimental Results /
Analysis / Discussion
Problems Encountered
Conclusion
Questions
Total

Grade Assigned
20%
5%
10%
40%
5%
5%
15%
100%

Student's Grade

Objective:
The purpose of this lab was to explore the properties of MOSFET amplifier circuits, and to use
all the knowledge we learned from previous labs to design a CMOS amplifier that meets certain
specifications.
The requirements for this project are listed below:
1. Voltage Gain ( A v 50 .
2. Input Impedance ( R 200k.
3. 3 dB Bandwidth > 200kHz.
4. Harmonic distortion below -30dB with Vimax = 5mVpk (10mVpp) measured at 10kHz
input sinusoidal signal.
5. Vcc = no minimum required, but absolute max=5V.
6. Rload = 8.
7. Use a minimum of 3 MOSFETs in design.
Introduction/Theory:
For this design, three common-source CMOS configuration circuits were set up in series. Every
common-source CMOS stage provides a particular voltage gain depending on different designs.
The desired final voltage gain can be obtained by coupling these stages together. A commondrain CMOS configuration circuit, which can serve as a buffer, is coupled in series with the
output of the third common-source CMOS stage. An ideal common-drain CMOS circuit has
unity voltage gain and can transfer the voltage from the common sources having a high output
impedance to a low impedance level on the output.

Figure 1: Common-Source
Configuration

Figure 2: Common-Drain
Configuration

When designing the components of circuit configurations shown above, some important
relationships and equations are used to determine components values. The equations and
relationships used are listed below:

R2
)
R1 + R2

1.

V G=V DD (

2.

1
I D = (V GS V TH )2
2

3.

A V =RD g m

4.

V GS=V G V S

5.

gm=

6.

V s=I D R S

7.

V GS = gm =>

8.

R D =>

2 ID
= 2 I D= (V GS V TH )
( V GSV TH )

AV

I D =>

gm =>

AV

= 1 or

AV =

R D R L
RS

depending on the

stage being looked at.

Both the parameters in the above relationship (8) for the voltage gain equation are related to
each other, meaning that the output cant be simply predicted by varying just one parameter.
In the early design stage, drain current is kept constant to obtain drain resistance value
provided with a constant power supply. A resistance value that is approximately close to the
required load resistance is used at the source resistor. With this in mind, gate resistances that
set the gate source voltage should make a ratio that bias it directly in the middle range of the
power supply to guarantee maximum swing. Large capacitors are required to couple between
stages without changing the bias points between stages.
After applying all the design principles mentioned, a Pspice simulation was obtained, and is
shown in Figure 3 below. The following figures show the simulations for the required results:
1. The voltage input, output, and swing of the circuit is shown in Figure 4.
2. The total harmonic distortion measurements is shown in Figure 5.
3. The bode plot of the frequency response is shown in Figure 6.
4. Total power dissipation measurements is shown in Figure 7.
Figure 3: Pspice Simulation
Design

Figure 4: Voltage Gain, Input and

Output

Figure 5: Total Harmonic Distortion

Measurement

Figure 6: Bandwidth Measurement

Figure 7: Total Power Dissipation

Procedure:
The first step of our design was to set up a common source amplifier configuration to achieve a
gain again with a high input impedance. The first amplifier was tested by itself to get a proper
gain and bias points. The values for the common source can be found in Table 1. Following this,
another common source was constructed with the same values, tested, and coupled to the original
amplifier to achieve an even higher gain. A third common source was added to achieve a gain
that met the specification of above fifty. All three amplifiers were coupled together with large
capacitors. Lastly, in order to bring the output impedance from the amplifier down to the small 8
load, a BJT darlington pair configuration was used. This was so that the right amount of high
current could be used on the small load. The following is how each different configuration was
calculated:
1. First, the power supply chosen was 4 Volts so that we can optimize a high gain of
approximately 4 with each stage and obtain a gain of above (and near to in order
to account for distortion) 50 V/V. If a gain of 4 was achieved for each common

source, the gain would be approximately 64, the nearest approximation of 3

MOSFETS coupled together.
2. Basic Common Source Calculation
a. We chose a source resistance and drain resistance so that there's a drop of
about VDD/2. RS chosen as 100 and RD chosen as 50k.
b. To bias the circuit using the gate resistors, a large 1M potentiometer was
placed in between the gate pin. The gate resistance was then varied to find
the best option for the gate source voltage. All values listed in the Table 1
are tweaked so that the best gain and voltage swing could be accounted
for.
3. Basic Common Drain Calculation
a. The parameter for the design was to drive an 8 load. This was used in
our buffer stage with a source resistance that was only slightly larger than
the load. Again a large potentiometer was placed in between the gate pin.
The gate resistance was then varied again to find the best option for the
gate source voltage.
b. We noticed there was a substantial amount of current flowing through the
one BJT so we decided to use a darlington pair in order to distribute the
current and also to drive the small load. One darlington pair wasn't enough
to distribute the current so two in parallel with each other were added in
the common drain buffer.
The following images are each stage of the amplifier design biased and tested separately with the
point set in the middle of each voltage swing. Each test was first examined with a larger input
signal in order to detect a clearer image. In order for each stage to stay in its biased region, the
stages are then coupled together using fairly large capacitances.
Figure 8: First Common Source Amplifier
Stage

Figure 9: Second Common Source Amplifier

Stage

Figure 10: Third Common Source Amplifier

Stage

Figure 11: Common Drain (Source Follower Buffer) Amplifier Stage

Figure 12: Common Source Amplifier Stages Combined

Figure 13: All Stages Combined

Gain achieved reached was about 38.5 after all three common sources and the common drain.
There was a fairly large amount of distortion at the end of the buffer. This is because of the large
current being supplied to the signal in the darlington pair because when the signal was tested
through only the common sources, there was almost no distortion.

Data Tables/Experimental Results:

Table 1: Common-Source Pspice
Simulation Components and
Measurements

R1

Parameter

Value
500 K

R2

400 K

RD

45 K

Rs

100

VG

Capacitors

100 uF
1.778 V

ID

42.72 uA
Transistors

CD4007

Table 2: Actual Common-Source

Components and Measurements

R1

Parameter

Value
500 K

R2

400 K

First Stage R D

14.68 K

First Stage R s

100

Second Stage R D

10 K

Second Stage R S

100

Third Stage R D

22 K

Third Stage R S

100

Capacitors
Transistors

10 uF
CD4007
42.72 uA

Gain

Table 3: Common-Drain Pspice

Simulation Components and
Measurements

Table 4: Actual Common-Drain

ParameterComponents and Measurements

R1

Value
200 K

R2

600 K

Rs

10
Capacitors
Transistors

10 uF
Q2N2222

Parameter
R1

Value
60 K

R2

600 K

Rs

10
Capacitors
Transistors

100 uF
Q2N2222

Problems Encountered:
The one major problem that we encountered was setting the operating point of the amplifiers.
When we would set up the circuits, we would use the values provided to us or solved for in the
pre-lab. However, these values needed to be adjusted in order to achieve the operating point and
the correct characteristics. Any trouble that we had when our amplifiers werent working

properly was because the operating point was not set correctly. Other than that, we experienced
problems using the equipment in the lab from just about any station that we worked on. It was
very difficult to get a 5 mVpk on the function generators and when achieved, the oscilloscopes
hard trouble reading the signal. This caused a lot of unnecessary time waste.
Conclusion:
This lab helped us to understand the characteristics of the MOS transistor configurations. We
learned how important biasing the correct operating point is in determining the output behavior.
We also learned a lot about the engineering design process from the beginning until the end. The
beginning being brainstorming the types of configurations we could add together to achieve
some of the parameters. The middle being testing and refining the design so that it could properly
meet all requirements. The end being summarizing all our efforts on the design so that we can
expand on our knowledge of transistor technologies. Amplifier designs are a very important
aspect in signal processing in electrical engineering and this project has been a great introduction
to becoming design engineers capable of learning how to follow guidelines while optimizing the
product.