module fsm(stage,out,inp,clk,rst);

parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
input inp,clk,rst;
output out;
output [1:0]stage;
reg out;
reg [1:0]stage;
reg [1:0]nextstage;
always@(inp or stage)
begin
case(stage)
s0:if(inp)nextstage=s1;
else nextstage=s0;
s1:if(inp)nextstage=s0;
else nextstage=s2;
s2:if(inp)nextstage=s3;
else nextstage=s0;
s3:nextstage=s0;
endcase
end
always@(posedge clk)
begin
if(rst)
begin
stage=s0;
out=0;
end
else
begin
stage=nextstage;
case(stage)
s0:out=0;
s1:out=0;
s2:out=0;
s3:out=1;
endcase
end
end
endmodule
module fsm_tb();
reg inp1,clk1,rst1;
wire out1;
wire [1:0]stage1;
fsm D1(.stage(stage1),.out(out1),.inp(inp1),.clk(clk1),
.rst(rst1));
initial $monitor("stage=%d out=%b inp=%b clk=%b rst=%b",
stage1,out1,inp1,clk1,rst1);
initial begin
#3 clk1=0;rst1=1;inp1=0;
#3 clk1=1;rst1=1;inp1=0;
#3 clk1=0;rst1=0;inp1=1;
#3 clk1=1;rst1=0;inp1=1;
#3 clk1=0;rst1=0;inp1=0;
#3 clk1=1;rst1=0;inp1=0;
#3 clk1=0;rst1=0;inp1=1;
#3 clk1=1;rst1=0;inp1=1;

#3 clk1=0;rst1=0;inp1=1;
#3 clk1=1;rst1=0;inp1=0;
#3 clk1=0;rst1=0;inp1=1;
#3 clk1=1;rst1=0;inp1=1;
#3 clk1=0;rst1=0;inp1=0;
#3 clk1=1;rst1=0;inp1=0;
#3 clk1=0;rst1=0;inp1=0;
#3 clk1=1;rst1=0;inp1=0;
end
endmodule