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always @(clk)
begin
a = 0;
a < = 1;
$display(a);
end
Answer
Verilog used four-level deep queue for the current simulation time:
1. Active events (blocking statements).
2. Inactive events (#0 delays, etc).
3. Non-blocking assign updates (non-blocking statements).
4. Monitor Events ($display, $monitor).
So $display(a); displays 0.
2. What is the difference between a = #10 b; and #10 a = b; ?
Answer
In a = #10 b; current value of "b" will be assigned to "a" after 10 units of time (like transport delay). In #10 a
= b; the simulator will execute a = b; after 10 units of time (like inertial delay).
3. Let "a" be a 3 bit reg value.
initial
begin
a < = 3'b101;
a = #5 3'b000;
a < = #10 3'b111;
a < = #30 3'b011;
a = #20 3'b010;
a < = #5 3'b110;
end
What will be the value of "a" at time 0,5,10,... units till 40 units of time?
Answer
0 - 101
5 - 000
10 - 000
15 - 111
20 - 111
25 - 010
30 - 110
35 - 011
40 - 011
(This helps in understanding the concepts of blocking and non-blocking statements).
4. Write a verilog code to swap contents of two registers with and without using a temporary register.
Answer
The easiest and efficient way to generate sine wave is using CORDICalgorithm.