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MAP notes

Chapter 2: 16 Bit Microprocessor: 8086 Part 1

Q1. List the features of 8086 microprocessor.
It requires +5V power supply
It is a 40 pin IC
Available in three clock rates: 5,8 and 10 MHz
It is a 16 bit microprocessor
Size of data bus is 16 bits
Size of address bus is 20 bits
Direct memory access upto 1Mb = 2

Note: Size of the memory always depends on the number of address lines.
Two separate units: Bus Interface Unit and Execution Unit
External Co processor (8087) supported
6 byte instruction queue present to help speed up instruction execution
Has multiplexed address and data bus
It consist two memory banks viz. odd memory bank and even memory bank

Q2. Draw the internal architecture of 8086.

Q3. Explain the register organization of 8086

General purpose registers:
There are in all 4 general purpose registers viz. AX, BX, CX, DX each of 16 bits i.e. 2 bytes
i.e. 1 word. These 4 registers are actually are pairs of 8 registers viz. AH, AL, BH, BL, CH,
CL, DH, DL each of 8 bits i.e. 1 byte. The letter X specify complete 16 bit register. The
letters L and H specify lower and higher bytes of a register.

Segment registers:
There are 4 segment registers in the Bus interface unit, size of each segment register is 16

Code Segment Register (CS register)

Data Segment Register (DS register)

Extra Segment Register (ES register)

Stack Segment Register (SS register)

Segment registers give the base address (segment address) to select any memory segment.
Operand register or Temporary register:
It is a 16 bit register which can store 16 bit data. This register cannot be used by the
programmer/user. It is used by the p to store intermediate data or results therefore it is
called as temporary register.
Pointers and Index Registers:
The 16 bit register from where the p will take 16 bit effective address is called memory

There are three pointer registers as follows:

- Instruction pointer (IP)

- Stack Pointer (SP)

- Base Pointer (BP)

Also there are 2 index registers which have multiple purposes such as:

- Can be used for pointer addressing of data

- Used as source in some string processing instructions

- Used to store Offset address

Note: The index registers are also a type of memory pointers but having multiple purpose
There are two index registers as follows:

- Source Index register (SI)

- Destination Index Register (DI)

Q4. Explain the special uses of general purpose registers.

1. AL/AX (Accumulator): It is intermediate register between the ALU and the

memory. Mostly, but not always the results of arithmetic and logical operations are
stored in the accumulator and then from there it is transferred to wherever required.

It is the most important general purpose register of the p.

Eg: When the instruction DIV BL is executed what the p does is that it divide
content of AX register with the content of BL register by default and after dividing the

quotient is by default stored in the AL register and remainder is stored in the AH


2. BX (Base Register): To select any memory location particularly in the data

segment we require two addresses : base address (stored in the segment register) and
offset address which can be stored in the base register in certain addressing modes.

3. CL/CX (Counter Register): It is used as a default counter register during loop,

shift, rotate, repeat instructions. It can be used as 8 bit counter as well as 16 bit

4. DX (Data register): During multiplication and division operations when the result
goes beyond 16 bits i.e. 32bits, then the upper 16 bits are stored in the DX register.

Q5. Draw the flag register of 8086. Explain the status flags.

Carry Flag:
During an addition operation if a carry is generated from the MSB or during a subtraction
operation a borrow is generated carry flag sets indicating a carry or borrow respectively.
Therefore when
CF = 1; carry is generated
CF = 0; carry not generated
Auxiliary carry flag:
During an addition operation if a carry is generated from the lower nibble to the higher nibble,
then AC flag sets.

Parity flag:

When an addition, subtraction, multiplication, division or any logical operation takes place
then depending on the result the parity flag gets affected.

p checks the 8 LSBs of the result:

If the number of ones in the 8 LSBs are 0/2/4/6/8 then the parity flag sets i.e. PF = 1
indicating even parity

If the number of ones in the 8 LSBs are 1/3/5/7 then the parity flag resets i.e. PF = 0
indicating odd parity

Zero flag:

Whenever any arithmetic or logical operation takes place and the result is 0 then zero flag sets
to indicate that the result is 0 i.e. ZF = 1.

Eg: Let A = 80H

B = 80H

SUB B instruction is executed. The result obtained is 00H in A register. When p checks this
it has to reflect it somewhere that the result is zero, so it reflects in bit 7 which is reserved for
zero flag by setting its value to 1 i.e. ZF = 1

Sign flag:

Whenever the result of any arithmetic operation is negative the sign flag sets i.e. SF = 1 else
remain in the reset state i.e. SF = 0.

Overflow flag (Bit 12):

Q6. Draw the flag register of 8086 and explain the control flags.

Interrupt flag (Bit 10):

Interrupt flag is used to control the maskable interrupts of the p 8086 which arrive at the
INTR pin. Lets see how it controls the interrupts.

Shown above is the internal circuitry to control the maskable interrupts. When Bit 10 of Flag
register is 0 i.e.

IF = 0, input to the AND gate is 0 therefore o/p of AND gate goes low. Therefore any input to
the AND gate wont be recognized hence any interrupt occurring on the INTR pin wont be
acknowledged as it is not recognized.
When IF = 1 and interrupt on the INTR pin occurs it is recognized and given to the internal
INTR circuitry through AND gate and then acknowledged.
Trap Flag (Bit 9):
This flag is used to detect any error in the program (debugging) by executing the program in
single stepping mode.
- If logic 0 is stored in TF, then the p will execute all the instructions of a program in one
operation (free run operation)
Eg: When we execute the program and press key F9, the entire program gets executed in one
stroke. The imp. Point to understand is that when we press the key F9, value 0 gets placed bit
9 of the flag register therefore Trap flag resets i.e. TF = 0.
- If logic 1 is stored in TF, then the p will execute one instruction of the program at a time,
after executing each instruction p will execute INT1 (software interrupt), so p will branch
from main program to subroutine.
The subroutine has a program which displays the result in different registers of p on the
screen, so after each instruction the programmer can verify the result.
Eg: We use F8 function key to execute the program in single stepping mode. When we press
key F8 value 1 gets placed into bit 9 of flag register, hence trap flag sets i.e. TF = 1.

Direction Flag (Bit 11):

In the above example we see two memory blocks. The offset address of first memory block is
placed in the SI register and offset address of the second memory block is placed in the DI
Now we need to manually increment SI and DI after each byte transfer from data segment to
extra segment.
To avoid all this what we do is after moving one byte from Data segment to extra segment
we clear the direction flag (CLD instruction is used to clear the direction flag) which puts SI
and DI in auto increment mode.
In other words whenever DF = 0, SI and DI increment automatically.

If we are copying the data from the last location we set the direction flag (STD instruction is
used to set the direction flag) which puts the SI and DI in auto decrement mode.
In other words whenever DF = 1, SI and DI decrement automatically.

Q7. Explain how queuing speeds up the processing of 8086 operations.

This queue is based on FIFO (first in first out) basis which means that the byte which
comes first also goes out first from this register.

p 8086 has created 2 logical units within its architecture one is the bus interface unit (BIU)
and the other is the execution unit (EU).
While the EU is decoding an instruction or executing an instruction which does not require
the use of buses, the BIU fetches upto six bytes from the memory.
The BIU stores these prefetch bytes in FIFO register called as queue register.
When the EU is ready for the next instruction it simply takes (fetches) the next byte from the
instruction queue in the BIU.
This is much faster than sending out address to the system memory and waiting for memory
to send back the next instruction bytes.
This is a simple example of a car manufacturer which defines a person to make a car. Now
that person starts making the engine, then on its completion, he starts preparing the outer
body and continues.
We need to understand is that the person is completing one task and then starting another,
hence to manufacture one car will take a lot of time.
The manufacturer came up with an idea, that why not increase my staff. Instead of one staff
Ill make it 5.
First : Engine manufacture
Second : Body manufacture
Third : Seat manufacture

Fourth : Painting
Fifth : Tyre manufacture
Now what happens that the work got divided and each person is busy. After completion of
first module it goes to second and so on till the fifth.
So every module is continuously busy, and the work got divided.

1 person can do the work in 1 sec, now the work got divided, but first time all the modules
are in wait state and waiting for the previous one to complete i.e. M2 is waiting for M1 to
complete. So time taken is same i.e. 1s. But after the entire cycle is complete once, now the
time taken is only 0.2 sec.

Q8. List the steps in physical address generation in 8086 microprocessor. Calculate the
physical address for the given CS = 2340H, IP = 76A9H.
Since address bus is of 20 bits = Physical address is of 20 bits
The calculation is as follows:
Physical address (PA) = BA + EA
But addition is a little different, lets understand with an example:

Let BA = 1000H = 0001 0000 0000 0000 = 16 bit

EA = 3467H = 0011 0100 0110 0111 = 16 bit

Now base address is always appended with 0H i.e. 0000B at the end internally by the

Therefore BA now becomes = 0001 0000 0000 0000 0000 = 10000H


PA = 0001 0000 0000 0000 0000


= 10000H

0011 0100 0110 0111 =


0001 0011 0100 0110 0111 =



CS = BA = 2340H
IP = EA = 76A9H
PA = BA + EA
= 23400H = 0010 0011 0100 0000 0000

76A9H =

0111 0110 1010 1001

2AAA9H = 0010 1010 1010 1010 1001

Q9. State the function of following assembly language programming tools. a. Editor b.
Assembler c. Linker d. Debugger

It is used to type the assembly language statements for the program and save in a file.

The file containing the text of assembly language statements is called as source file
and has the extension .asm


Assembler is a software which reads the text from the source file, translates into
respective binary codes and saves into two files, one with the extension .obj called as
object file and one with the extension .lst called as list file.

The object file contains binary codes and addresses of the instructions.

The list file contains assembly language statements, binary codes, and offset address
for each instruction.

Assembler indicates syntax errors if any in the source file.


Large assembly language programs are usually divided into many small modules.

The code for each module are separately developed, tested and finally linked into a
single large executable program.

The linker is used to join many object files into a single large object file.

Usually linker produces files with the extension .exe which can be directly loaded in
the memory and executed.


It enables the program to be loaded into the system memory, execute it and then
debug it. It also enables to insert breakpoints at any desired locations, change the
content of register, memory location and rerun the program.

Q10. Explain memory segmentation.

The p 8086 has 20 address lines therefore the number of memory locations it can
access is 2
= 1048576 = 1 Mb.
Address varies from

0000 0000 0000 0000 0000

1111 1111 1111 1111 1111

Hence our main aim is to access a memory location and from there access data.

The main point to understand is that the size of the registers is 16 bit and address is of
20 bits.

Therefore 8086 uses the memory segmentation scheme to access 1 Mb of memory or

1M locations.

The memory is divided into segments or blocks. The length of the segment is 64 Kb.
Two registers are used, one to access a segment and one to move within the segment
(select any location within the segment).

Consider the memory given on next slide:

Two steps to access any location within a memory:

Select the segment with the help of base address or segment address (starting
address (indicating start of any segment). It means that the segment register contains
the base address with the help of which we are able to select any segment.

Now to move within the segment or in other words to select any location within the
segment we use offset address or effective address which we get from any pointer or
index register or any general purpose register.

Now these segments are logical segments, it means that there is no physical division within
the memory.
The segments can either be Code Segment, Data Segment, Extra Segment, Stack segment.
Code segment : when a segment is assigned as code segment, it is used to store the codes or
Data Segment : when a segment is assigned as data segment, it is used to store data used in
the programs
Extra Segment : it is also another segment used to store data
Stack Segment : it is used to store stack of data and address of main program during
subroutine call

Q11. Explain the concept of pipelining in 8086

When one instruction is getting decoded and executed and simultaneously next
instruction is being fetched from the memory is called as pipelining process.

In 8086 with the help of queue register 6 instruction bytes are prefetched in the queue
register, whenever the EU requires bytes for decoding and execution purpose it just
has to fetch from the queue register instead of going to the main memory and waist its

By the time it is decoding and executing the byte fetched from the queue, p does not
allow the buses to remain idle, the external bus goes to the memory and fetches the
next bytes and places in the queue.

This is actually parallel processing and similar to a water pipe where the water
continues to remain in motion. Similar way the instruction bytes are in continuous
motion i.e. from the memory to the BIU then into the queue then to the execution unit
for execution.

In other words the motion of bytes does not stop anywhere ideally unless and until a
branch instruction arises in the queue.

Note: The p does not perform the next fetch operation till at least two bytes of the
instruction queue are emptied.

This is a simple example of a car manufacturer which defines a person to make a car. Now
that person starts making the engine, then on its completion, he starts preparing the outer
body and continues.
We need to understand is that the person is completing one task and then starting another,
hence to manufacture one car will take a lot of time.

1 person can do the work in 1 sec, now the work got divided, but first time all the modules
are in wait state and waiting for the previous one to complete i.e. M2 is waiting for M1 to
complete. So time taken is same i.e. 1s. But after the entire cycle is complete once, now the
time taken is only 0.2 sec.

Q12. Draw the pin diagram of 8086.

Q13. State the functions for the following pins of 8086

AD 0 AD 15 - (Pin 16 - 2) - Multiplexed Address Data Bus
From pin number 16 2 are used by the multiplexed address data bus.
Multiplexing address and data lines means that the same lines are used for address and data.
Therefore the same lines are used to carry address information as well as data.
During T1 state of every machine cycle ALE signal goes high and enables the latches, during
this T1 state address which is generated by the p is available on this multiplexed bus.
After T1 state gets over ALE signal goes low which disables the latches and DEN signal also
goes low which enables the Transrecievers. Now data is available on the multiplexed bus.
A 16 /S 3 -

A 19 /S 6 (Pin 38 35) Multiplexed address status bus

These lines work as Address Bus (A16 A19) during T1 state of every machine cycle i.e.
when ALE signal goes high.
T2 onwards these work as status signals S3 to S6
S3 and S4 gives the status of the memory segment currently accessed.
S5 gives the status of Interrupt Flag.
S6 remains low in general.

INTR (Pin 18):

This is input pin to the microprocessor.

It is an interrupt pin and the input is level triggered, which means that when logic high arrives
on this pin it gets activated.
An interrupting device such as keyboard, printer etc. is not directly connected to this pin but
through a PIC (IC 8259).
Interrupts arriving on this pin can be masked with the help of IF flag.
When the instruction CLI is executed, IF flag gets cleared and interrupts arriving on this pin
are masked (they dont get any response).
NMI (Pin 17):
This is an input pin to the p .
It is a positive edge triggered input.
It is a non maskable interrupt.
For any interrupt to be recognized the i/p at this pin should be high for at least 2 clock cycles
Whenever there is a power failure this pin comes into use.
INTA (Pin 24):
This is an acknowledge signal going out from the p to the PIC (IC 8259).
Whenever the p is interrupted on the INTR pin with a high signal, if the p accepts the
interrupt which means that the IF is set, it sends an acknowledgement signal to the PIC from
where the interrupt came, indicating that it has accepted the interrupt.
RD (Pin 32) Read:
This is an active low pin
It is an output pin. Whenever the p performs memory read or i/o read operation, this pin
goes low to indicate read operation. This pin is always used along with M/IO to indicate
memory read or I/O read.

READY (Pin 22):

This is an input acknowledgement signal from the slow peripheral devices to the
microprocessor to indicate that data transfer is complete.
Eg. Printer connected to microprocessor.
The main use of this pin is to insert wait states into the timing of the microprocessor.
If the READY pin is at logic 0 level, the p enters wait states into its timing cycle and
remains idle.
The need for this is because the speed of the p is very fast, it operates in MHz and speed of
peripheral device like printer is slow as compared to that of the p. Hence p sends data at a
faster rate continuously to the peripheral, which may cause loss of data, hence the peripheral
sends a low signal on the READY input to send the data at a slower rate by adding wait states
to its timing cycle.
Once one slot of data is received by the peripheral then it sends an acknowledgement high
signal on its input to indicate that data transfer is complete and send the next slot of data.

CLK (Pin 19) Clock:

Clock pin provides the basic timing signal to the microprocessor.

Vcc (Pin 40) ; GND (Pin 1 and 20):

Vcc i.e. +5V is applied at pin 40 and is used as power supply
There are two layers of 8086, hence two separate GND pins for two layers of 8086 chip are
used. This helps in improve noise rejection.

RESET (Pin 21):

It causes the processor to immediately terminate its present activity .
The 8284 clock generator provides this signal
This signal must be active high for at least 4 clock cycles
It clears all the flag register, the instruction queue, DS,SS, ES and IP register and sets the bits
of the CS register
Hence whenever the processor boots the reset vector address of 8086 is FFFF0H (as CS =
FFFFH and IP = 0000H)
Note: The reset vector is the default location a central processing unit will go to find the first
instruction it will execute after a reset. That is to say, the reset vector is a pointer or address
where the CPU should always begin as soon as it is able to execute instructions.

ALE (Pin 25):

ALE stands for Address Latch Enable.
As we studied in the previous slides about latch. Latch has an input pin STB which is
connected to the o/p pin of the p i.e. ALE
As the name suggests, it is used to enable the latch by generating a high signal during T1 state
of every machine cycle.
As soon as ALE pin goes high, latches gets enabled, address which is available on the address
bus goes to the input of the latches where it is latched (it holds the address at its o/p).
Now ALE goes low after T1 state gets over, hence disabling the latches (as STB also goes
Now data is available on the multiplexed A/D bus.
Since latches are disabled hence data which arrives at latches get no response.

TEST (Pin 23):

It is an active low input line dedicated for 8087 math co processor(numeric processor).
When this pin is high in the maximum mode, it indicates to the microprocessor that it is busy.

Whenever those instructions arrive in the program which are dedicated to the co processor
then they are sent to the co processor for execution.
While the co processor is busy executing those instructions it sends a high signal on the
TEST pin of the p indicating that it is busy executing those instructions, till then the p
remains in idle state.

MN/MX (Pin 33):

This is an input pin to the p which will indicate the processor will work in which mode.
If input to this pin is high i.e. if the pin is connected to Vcc (+5V) then p will enter in
minimum mode
If input to this pin is low i.e. if the pin is connected to GND (0V) then p will enter in
maximum mode

BHE/ S 7 (Pin 34):

S 7 is used for future development.
BHE is active low o/p signal and stands for Bus High Enable.
This o/p pin is used to activate the odd memory bank, when the o/p of this pin is low it
activates the odd memory bank and data is available on the higher order data bus (D8 D15)
If this pin goes high then odd memory bank gets disabled and any type of data transfer from
the higher order data bus is disabled.

WR Write (Pin 29):

This is an o/p pin is used in minimum mode, i.e. MN/MX = 1

It is connected to the memory or I/O device. When this pin goes low it indicates write

It is used along with M/IO pin to indicate whether memory write or io write operation.
M/IO (Pin 28):
This is an o/p pin used in minimum mode, to distinguish between a memory operation and io
When this pin is low it indicates io operation and is used with RD and WR.
For Eg. M/IO is high, and RD is also low whereas WR is high, then memory read operation
takes place.
For Eg. M/IO is high, and WR is also low whereas RD is high, then memory write operation
takes place.
In similar manner IO read and IO write operation takes place, only M/IO is low.

HOLD (Pin 31):

It is input pin used in the minimum mode. The i/p comes from the DMA controller which is
acting another bus master (as it also has data and address lines) requesting the p to release
the system bus.
In response 8086 completes the current machine cycle and releases the system bus.
In other words it tristates its external system bus.

HLDA (Pin 30):

It is acknowledge signal generated by the p to the DMA controller after releasing the system
bus, indicating that it has released the system bus.
After which DMA operation takes place.

DEN (Pin 26) Data Enable:

This pin is used to activate the octal bus Transreciever IC 8286 . It is connected to the OE pin
of the Transreciever which consist of 8 bidirectional buffers. Actually when DEN goes low
OE goes low and all the internal buffers get activated.

DT/R (Pin 27) Data transmit/ Receive:

This pin is used to decide the direction of data flow i.e. either data will flow from the p to
memory or io device or data will flow from the memory or io device to the p.
When this pin goes high i.e. when DT/R = 1, which indicates data transmit from p to
memory or io device
In other words whenever write operation takes place, DT/R goes high, hence flow of data is
from the p.
When this pin goes low i.e. when DT/R = 0, which indicates receive i.e. p receives data
from memory or io device.
In other words whenever read operation takes place, DT/R goes low, hence flow of data is
towards the p.

S 2 , S1 , S 0 (Pin 28 26) Status lines:

These are the active low status lines used in maximum mode which reflect the type of
operation being carried out by the processor. It indicates which machine cycle is currently in
Refer table below:

LOCK (Pin 29):

This pin is used in the maximum mode.
When a programmer is executing some important instructions during which no interrupt can
be tolerated (such as when we restart our computer and there are some updates which the
windows is taking at that time if any other command is given to the PC it will not react to it)
at that time what the programmer does it writes a LOCK prefix alongside the instruction, due
to which this pin goes low indicating to the external bus masters such as DMA that it cannot
take control over the system bus.
When the next instruction arrives without the LOCK prefix then this pin goes high and allows
other bus masters to access gain over the system bus.

QS 1 ,QS 0 (Pin 24 25):

QS stands for queue status. It means that outside the chip we come to know what is the status
of the queue register inside the microprocessor.
Lets understand from the table below:

RQ0 / 0 , RQ 1 / 1 :
This signal works in the maximum mode when more than one processor is connected in the
RQ stands for bus request. GT stands for bus grant.
0 has the higher priority than 1. It means that when two processors simultaneously asks the
8086 to release the system bus, the processor which is connected at pin 31 will get bus grant
first then the one which is connected at pin 30.
The external processor will send a low signal as a request to the p to release the system bus,
the p will complete its current machine cycle and release the bus i.e. it will grant the bus to
the bus master by sending a low signal.
After using the system bus again the external bus master will send a low signal thereby
releasing back the system bus to the p.

Q14. Draw the physical address calculation unit to generate 20 bit physical address.