Power Electronics Converters, Applications, and Design

Chapter 1 Power Electronic Systems
Copyright © 2003 Chapter 1 Introduction 1-1

by John Wiley & Sons, Inc.
Power Electronic Systems
• Block diagram
• Role of Power Electronics
• Reasons for growth

Linear Power Supply
• Series transistor as an adjustable resistor

• Low Efficiency
• Heavy and bulky
Switch-Mode Power Supply
• Transistor as a switch
• High Efficiency
• High-Frequency Transformer

Basic Principle of Switch-Mode Synthesis
• Constant switching frequency

• pulse width controls the average
• L-C filters the ripple

Application in Adjustable Speed Drives
• Conventional drive wastes energy across the throttling

valve to adjust flow rate
• Using power electronics, motor-pump speed is adjusted
efficiently to deliver the required flow rate

Scope and Applications

Power Processor as a Combination of
Converters
• Most practical topologies require an energy

storage element, which also decouples the input
and the output side converters
Power Flow through Converters
• Converter is a general term

• An ac/dc converter is shown here
• Rectifier Mode of operation when power from ac to dc
• Inverter Mode of operation when power from ac to dc

AC Motor Drive
• Converter 1 rectifies line-frequency ac into dc

• Capacitor acts as a filter; stores energy; decouples
• Converter 2 synthesizes low-frequency ac to motor
• Polarity of dc-bus voltage remains unchanged
– ideally suited for transistors of converter 2
Matrix Converter
• Very general structure

• Would benefit from bi-directional and bi-polarity switches
• Being considered for use in specific applications
Interdisciplinary Nature of Power Electronics

Chapter 2 Overview of Power
Semiconductor Devices
Copyright © 2003 Chapter 2 Power Semiconductor 2-1

by John Wiley & Sons, Inc. Switches: An Overview
Diodes
• On and off states controlled by the power circuit

Diode Turn-Off
• Fast-recovery diodes have a small reverse-recovery time

Thyristors
• Semi-controlled device
• Latches ON by a gate-current pulse if forward biased
• Turns-off if current tries to reverse
Thyristor in a Simple Circuit
• For successful turn-off, reverse voltage required

for an interval greater than the turn-off interval
Generic Switch Symbol
• Idealized switch symbol

• When on, current can flow only in the direction of the arrow
• Instantaneous switching from one state to the other
• Zero voltage drop in on-state
• Infinite voltage and current handling capabilities

Switching Characteristics (linearized)
Switching Power Loss is

proportional to:
• switching frequency
• turn-on and turn-off times

Bipolar Junction Transistors (BJT)
• Used commonly in the past

• Now used in specific applications
• Replaced by MOSFETs and IGBTs

Various Configurations of BJTs

MOSFETs
• Easy to control by the gate

• Optimal for low-voltage operation at high switching frequencies
• On-state resistance a concern at higher voltage ratings

Gate-Turn-Off Thyristors (GTO)
• Slow switching speeds

• Used at very high power levels
• Require elaborate gate control circuitry

GTO Turn-Off
• Need a turn-off snubber

IGBT

MCT

Comparison of Controllable Switches

Summary of Device Capabilities

Chapter 3
Review of Basic Electrical and
Magnetic Circuit Concepts
Copyright © 2003 Chapter 3 Basic Electrical and 3-1

by John Wiley & Sons, Inc. Magnetic Circuit Concepts
Symbols and Conventions
• Symbols
• Polarity of Voltages; Direction of Currents
• MKS SI units

Sinusoidal Steady State

Three-Phase Circuit

Steady State in Power Electronics

Fourier Analysis

Distortion in the Input Current
• Voltage is assumed to be sinusoidal

• Subscript “1” refers to the fundamental
• The angle is between the voltage and the current fundamental

Phasor Representation

Response of L and C

Inductor Voltage and Current in
Steady State
• Volt-seconds over T equal zero.

Capacitor Voltage and Current
in Steady State
• Amp-seconds
over T equal zero.

Ampere’s Law
• Direction of magnetic field due to currents

• Ampere’s Law: Magnetic field along a path

Direction of Magnetic Field

B-H Relationship; Saturation
• Definition of permeability

Continuity of Flux Lines
φ1 + φ2 + φ3 = 0
Concept of Magnetic
Reluctance
• Flux is related to ampere-turns by reluctance

Analogy between Electrical and
Magnetic Variables

Analogy between Equations in
Electrical and Magnetic Circuits

Magnetic Circuit and its
Electrical Analog

Faraday’s Law and Lenz’s Law

Inductance L
• Inductance relates flux-linkage to current

Analysis of a Transformer

Transformer Equivalent Circuit

Including the Core Losses

Transformer Core
Characteristic

Chapter 4
Computer Simulation
Copyright © 2003 Chapter 4 Computer Simulation of Power 4-1

by John Wiley & Sons, Inc. Electronic Converters & Systems
System to be Simulated
• Challenges in modeling power electronic systems

Large-Signal System Simulation
• Simplest component models

Small-Signal Linearized Model for
Controller Design
• System linearized around the steady-state point

Closed-Loop Operation: Large Disturbances
• Simplest component models

• Nonlinearities, Limits, etc. are included

Modeling of Switching Operation
• Detailed device models

• Just a few switching cycles are studied

Modeling of a Simple Converter
• Input voltage takes on two discrete values

Trapezoidal Method of Integration
• The area shown above represents the integral

A Simple Example
• The input voltage takes on two discrete values

Modeling using PSpice
• Schematic approach
is far superior

PSpice-based Simulation
• Simulation results

Simulation using MATLAB

MATLAB-based Simulation
• Simulation results

Chapter 5
Diode Rectifiers
Copyright © 2003 Chapter 5 Line-Frequency Diode 5-1

by John Wiley & Sons, Inc. Rectifiers
Diode Rectifier Block Diagram
• Uncontrolled utility interface (ac to dc)

A Simple Circuit
• Resistive load

A Simple Circuit (R-L Load)
• Current continues to flows for a while even after the input

voltage has gone negative
A Simple Circuit (Load has a dc back-emf)
• Current begins to flow when the input voltage exceeds the dc back-emf
• Current continues to flows for a while even after the input voltage has
gone below the dc back-emf
Single-Phase Diode Rectifier Bridge
• Large capacitor at the dc output for filtering and energy

storage
Diode-Rectifier Bridge Analysis
• Two simple (idealized) cases to begin with

Redrawing Diode-Rectifier Bridge
• Two groups, each with two diodes

Waveforms with a
purely resistive load
and a purely dc current
at the output
• In both cases, the dc-side

voltage waveform is the same

Diode-Rectifier Bridge Input Current
• Idealized case with a purely dc output current

Diode-Rectifier Bridge Analysis with AC-
Side Inductance
• Output current is assumed to be purely dc

Understanding Current Commutation
• Assuming inductance in this circuit to be zero

Understanding Current Commutation (cont.)
• Inductance in this circuit is included

Current Commutation Waveforms
• Shows the volt-seconds needed to commutate current

Current Commutation in Full-Bridge Rectifier
• Shows the necessary volt-seconds

Understanding Current Commutation
• Note the current loops for analysis

Rectifier with a dc-
side voltage

DC-Side Voltage and Current Relationship
• Zero current corresponds to dc voltage equal to the peak of

the input ac voltage
Effect of DC-Side Current on
THD, PF and DPF
• Very high THD at low current values

Crest Factor versus the Current Loading
• The Crest Factor is very high at low values of current

Diode-Rectifier with a Capacitor Filter
• Power electronics load is represented by an equivalent load

resistance
Diode Rectifier Bridge
• Equivalent circuit for analysis on one-half cycle basis

Diode-Bridge Rectifier: Waveforms
• Analysis using MATLAB

Diode-Bridge Rectifier: Waveforms
• Analysis using PSpice

Input Line-Current Distortion
• Analysis using PSpice

Line-Voltage Distortion
• PCC is the point of common coupling

Line-Voltage Distortion
• Distortion in voltage supplied to other loads

Voltage Doubler Rectifier
• In 115-V position, one capacitor at-a-time is charged from the

input.
A Three-Phase, Four-Wire System
• A common neutral wire is assumed

Current in A Three-Phase, Four-Wire
System
• The current in the neutral wire can be very high

Three-Phase, Full-Bridge Rectifier
• Commonly used

Three-Phase, Full-Bridge Rectifier: Redrawn
• Two groups with three diodes each

Three-Phase, Full-Bridge Rectifier Waveforms
• Output current is
assumed to be dc

Three-Phase, Full-Bridge Rectifier: Input
Line-Current
• Assuming output current to be purely dc and zero ac-side

inductance
• Including the ac-side inductance

3-Phase Rectifier: Current Commutation
• output
current is
assumed to be
purely dc

Rectifier with a Large Filter Capacitor
• Output voltage is assumed to be purely dc

• THD, PF and DPF as functions of load current

Crest Factor versus the Current Loading
• The Crest Factor is very high at low values of current

Three-Phase Rectifier Waveforms
• PSpice-based analysis

Chapter 6
Thyristor Converters
• Controlled conversion of ac into dc
Copyright © 2003 Chapter 6 Thyristor Converters 6-1

Thyristor Converters
• Two-quadrant conversion

Primitive circuits
with thyristors

Thyristor Triggering
• ICs available

Full-Bridge Thyristor Converters
• Single-phase and three-phase

Single-Phase Thyristor Converters
• Two groups with two thyristor each

1-Phase Thyristor Converter Waveforms
• Assuming zero ac-side inductance

Average DC Output Voltage
• Assuming zero ac-side inductance

Input Line-Current Waveforms
• Harmonics, power and reactive power

1-Phase Thyristor Converter
• Finite ac-side inductance; constant dc output

current
Thyristor Converter Waveforms
• Finite ac-side inductance

Thyristor Converter: Discontinuous Mode
• This mode can occur in a dc-drive at light loads

• PSpice-based simulation

Thyristor Converter Waveforms:
Discontinuous Conduction Mode
• PSpice-based simulation

DC Voltage versus Load Current
• Various values of delay angle

Thyristor Converters: Inverter Mode
• Assuming the ac-side inductance to be zero

• Family of curves at various values of delay angle

• Importance of extinction angle in inverter mode

• Waveforms at start-up

3-Phase Thyristor Converters
• Two groups of three thyristors each

3-Phase Thyristor Converter Waveforms
• Zero ac-side inductance; purely dc current

DC-side voltage
waveforms
assuming zero ac-
side inductance

Input Line-Current Waveform
• Zero ac-side inductance

Input line-current
waveforms
assuming zero ac-
side inductance

Three-Phase Thyristor Converter
• AC-side inductance is included

Current Commutation Waveforms
• Constant dc-side current

Input Line-Current Waveform

Input Line-Current Harmonics

Input Line-Current Harmonics
• Typical and idealized

Three-Phase Thyristor Converter
• Realistic load
• Realistic load; continuous-conduction mode

• Realistic load; discontinuous-conduction mode

Thyristor Inverter
• Constant dc current

Thyristor Inverter Waveforms

Thyristor Inverter
• Family of curves at various values of delay angle

Thyristor Inverter Operation
• Importance of extinction angle

Thyristor Converters: Voltage Notching
• Importance of external ac-side inductance

Limits on Notching and Distortion
• Guidelines

Thyristor Converter Representation
• Functional block diagram

Chapter 7
DC-DC Switch-Mode Converters
• dc-dc converters for switch-mode dc power

supplies and dc-motor drives
Copyright © 2003 Chapter 7 DC-DC Switch-Mode 7-1
by John Wiley & Sons, Inc. Converters
Block Diagram of DC-DC Converters
• Functional block diagram

Stepping Down a DC Voltage
• A simple approach that shows the evolution

Pulse-Width Modulation in
DC-DC Converters
• Role of PWM
Step-Down DC-DC Converter
• Pulsating input to
the low-pass filter

Step-Down DC-DC Converter: Waveforms
• Steady state; inductor current flows continuously

Step-Down DC-DC Converter: Waveforms at
the boundary of Cont./Discont. Conduction
• Critical current below which inductor current

becomes discontinuous
Step-Down DC-DC Converter:
• Steady state; inductor current discontinuous

Step-Down DC-DC Converter: Limits of
Cont./Discont. Conduction
• The duty-ratio of 0.5 has the highest value of the

critical current
Step-Down DC-DC Converter: Limits of
• Output voltage is kept constant

Step-Down Conv.: Output Voltage Ripple
• ESR is assumed to be zero

Step-Up DC-DC Converter
• Output voltage must be greater than the input

Step-Up DC-DC Converter Waveforms
• Continuous current conduction mode

Step-Up DC-DC Converter: Limits of
• The output voltage is held constant

Step-Up DC-DC Converter: Discont.
Conduction
• Occurs at light loads


Step-Up DC-DC Converter: Effect of
Parasitics
• The duty-ratio is generally limited before the

parasitic effects become significant
Step-Up DC-DC Converter Output Ripple

Step-Down/Up DC-DC Converter
• The output voltage can be higher or lower than

the input voltage

Step-Up DC-DC Converter: Waveforms
• Continuation conduction mode


Step-Up DC-DC Converter:
• This occurs at light loads


Step-Up DC-DC Converter: Effect of
Parasitics
• The duty-ratio is limited to avoid these parasitic

effects from becoming significant
Step-Up DC-DC Converter:
Output Voltage Ripple

Cuk DC-DC Converter
• The output voltage can be higher or lower than

the input voltage

Cuk DC-DC Converter: Waveforms
• The capacitor
voltage is assumed
constant

Converter for DC-Motor Drives
• Four quadrant operation is possible

Converter Waveforms
• Bi-polar voltage switching

Converter Waveforms
• Uni-polar voltage switching

Output Ripple in Converters for DC-Motor
Drives
• bi-polar and uni-polar voltage switching

Switch Utilization in DC-DC Converters
• It varies significantly in various converters

Equivalent Circuits in DC-DC Converters
• replacing inductors and capacitors by current

and voltage sources, respectively
Reversing the Power Flow in DC-DC Conv.
• For power flow from right to left, the input

current direction should also reverse

Chapter 8
Switch-Mode DC-AC Inverters
• converters for ac motor drives and

uninterruptible power supplies
Copyright © 2003 Chapter 8 Switch-Mode DC- 8-1
by John Wiley & Sons, Inc. Sinusoidal AC Inverters
Switch-Mode DC-AC Inverter
• Block diagram of a motor drive where the power

flow is unidirectional
• Block diagram of a motor drive where the power

flow can be bi-directional
• Four quadrants of operation

One Leg of a Switch-Mode DC-AC Inverter
• The mid-point shown is fictitious

Synthesis of a Sinusoidal Output by PWM

Details of a Switching Time Period
• Control voltage can be assumed constant during

a switching time-period
Harmonics in the DC-AC Inverter Output
Voltage
• Harmonics appear around the carrier frequency

and its multiples
Harmonics due to Over-modulation
• These are harmonics of the fundamental

frequency

Output voltage Fundamental as a Function
of the Modulation Index
• Shows the linear and the over-modulation

regions; square-wave operation in the limit
Square-Wave Mode of Operation
• Harmonics are of the fundamental frequency

Half-Bridge Inverter
• Capacitors provide the mid-point

Single-Phase Full-Bridge DC-AC Inverter
• Consists of two inverter legs

PWM to Synthesize Sinusoidal Output
• The dotted curve is the desired output; also the

fundamental frequency
Analysis assuming Fictitious Filters
• Small fictitious filters eliminate the switching-

frequency related ripple

DC-Side Current
• Bi-Polar Voltage switching

Output Waveforms:
Uni-polar Voltage
Switching
• Harmonic
components around
the switching
frequency are absent

DC-Side Current in a Single-Phase Inverter
• Uni-polar voltage switching

Sinusoidal Synthesis by Voltage Shift
• Phase shift allows voltage cancellation to

synthesize a 1-Phase sinusoidal output
Single-Phase Inverter
• Analysis at the fundamental frequency

Square-Wave and PWM Operation
• PWM results in much smaller ripple current

Push-Pull Inverter
• Low Voltage to higher output using square-wave

operation
Three-Phase Inverter
• Three inverter legs; capacitor mid-point is

fictitious
Three-
Phase
PWM
Waveforms

Three-Phase Inverter Harmonics

Three-Phase Inverter Output
• Linear and over-modulation ranges

Three-Phase Inverter: Square-Wave Mode
• Harmonics are of the fundamental frequency

Three-Phase Inverter: Fundamental
Frequency
• Analysis at the fundamental frequency can be

done using phasors
Square-Wave and PWM Operation
• PWM results in much smaller ripple current

DC-Side Current in a Three-Phase Inverter
• The current consists of a dc component and the

switching-frequency related harmonics
Square-Wave Operation
• devices conducting are indicated

PWM Operation
• devices conducting are indicated

Short-Circuit States in PWM Operation
• top group or the bottom group results in short

circuiting three terminals
Effect of Blanking
Time
• Results in
nonlinearity

Effect of Blanking Time
• Voltage jump when the current reverses direction

• Effect on the output voltage

Programmed Harmonic Elimination
• Angles based on the desired output

Tolerance-Band Current Control
• Results in a variable frequency operation

Fixed-Frequency Operation
• Better control is possible using dq analysis

Transition from Inverter to Rectifier Mode
• Can analyze based on the fundamental-

frequency components
Summary of DC-AC Inverters
• Functional representation in a block-diagram form

Chapter 9
Zero-Voltage or Zero-Current Switchings
• converters for soft switching
Copyright © 2003 Chapter 9 Resonant Converters 9-1

One Inverter Leg
• The output current can be positive or negative

Hard Switching Waveforms
• The output current can be positive or negative

Turn-on and Turn-off Snubbers
• Turn-off snubbers are used

Switching Trajectories
• Comparison of Hard versus soft switching

Undamped Series-Resonant Circuit
• The waveforms shown include initial conditions

Series-Resonant Circuit with
Capacitor-Parallel Load
• The waveforms shown include initial conditions

Impedance of a Series-Resonant Circuit
• The impedance is capacitive below the

resonance frequency
Undamped Parallel-Resonant Circuit
• Excited by a current source

Impedance of a Parallel-Resonant Circuit
• The impedance is inductive at below the

resonant frequency
Series Load Resonant (SLR) Converter
• The transformer is ignored in this equivalent

circuit
SLR Converter Waveforms
• The operating frequency is below one-half the

resonance frequency
• The operating frequency is in between one-half the

resonance frequency and the resonance frequency
• The operating frequency is above the resonance

frequency
Lossless Snubbers in SLR Converters

frequency
SLR Converter Characteristics
• Output Current as a function of operating

frequency for various values of the output voltage
SLR Converter Control
• The operating frequency is varied to regulate

the output voltage

Parallel Load Resonant (PLR) Converter
• The transformer is ignored in this equivalent

circuit
PLR Converter Waveforms
• The current is in a discontinuous conduction

mode
• The operating frequency is below the resonance

frequency

frequency
PLR Converter Characteristics
• Output voltage as a function of operating

frequency for various values of the output current
Hybrid-Resonant DC-DC Converter
• Combination of series and parallel resonance

Parallel-Resonant Current-Source Converter
• Basic circuit to illustrate the operating principle

at the fundamental frequency

Parallel-Resonant Current-Source Converter
• Using thyristors; for induction heating

Class-E Converters
Optimum mode

Class-E Converters
Non-Optimum
mode

Resonant Switch Converters
Classifications

ZCS Resonant-Switch Converter
• One possible implementation

• Waveforms; voltage is regulated by varying the

switching frequency

• A practical circuit

ZVS Resonant-Switch Converter
• Serious limitations

ZVS Resonant-Switch Converter
• Waveforms

MOSFET Internal Capacitances
• These capacitances affect the MOSFET switching

ZVS-CV DC-DC Converter
• The inductor current must reverse direction

during each switching cycle
ZVS-CV DC-DC Converter
• One transition is shown

ZVS-CV Principle Applied to DC-AC Inverters
• Very large ripple in the output current

Three-Phase ZVS-CV DC-AC Inverter
• Very large ripple in the output current

Output Regulation by Voltage Control
• Each pole operates at nearly 50% duty-ratio

ZVS-CV with Voltage Cancellation
• Commonly used

Resonant DC-Link Inverter
• The dc-link voltage

is made to oscillate

Three-Phase Resonant DC-Link Inverter
• Modifications have been proposed

High-Frequency-Link Inverter
• Basic principle for selecting integral half-cycles of the

high-frequency ac input
• Low-frequency ac output is synthesized by selecting

integral half-cycles of the high-frequency ac input
• Shows how to implement such an inverter

Chapter 10
Switching DC Power Supplies
• One of the most important applications of power

electronics
Copyright © 2003 Chapter 10 Switching 10-1
by John Wiley & Sons, Inc. DC Power Supplies
Linear Power Supplies
• Very poor efficiency and large weight and size

Switching DC Power Supply: Block Diagram
• High efficiency and small weight and size

Switching DC Power Supply: Multiple
Outputs
• In most applications, several dc voltages are

required, possibly electrically isolated from each other
Transformer Analysis
• Needed to discuss high-frequency isolated supplies

PWM to Regulate Output
• Basic principle is the same as discussed in Chapter 8

Flyback Converter
• Derived from buck-boost; very power at small power

(> 50 W ) power levels

Flyback Converter
• Switch on and off states (assuming incomplete core

demagnetization)
Flyback Converter
• Switching waveforms (assuming incomplete core

demagnetization)
Other Flyback Converter Topologies
• Not commonly used

Forward Converter
• Derived from Buck; idealized to assume that the

transformer is ideal (not possible in practice)
Forward Converter:
in Practice
• Switching waveforms (assuming

incomplete core demagnetization)

Forward Converter: Other Possible Topologies
• Two-switch Forward converter is very commonly used

Push-Pull Inverter
• Leakage inductances become a problem

Half-Bridge Converter
• Derived from Buck

Full-Bridge Converter
• Used at higher power levels (> 0.5 kW )

Current-Source Converter
• More rugged (no shoot-through) but both switches

must not be open simultaneously
Ferrite Core Material
• Several materials to choose from based on applications

Core Utilization in Various Converter
Topologies
• At high switching frequencies, core losses limit

excursion of flux density
Control to Regulate Voltage Output
• Linearized representation of the feedback control

system
Forward Converter: An Example
• The switch and the diode are assumed to be ideal

Forward Converter:Transfer Function Plots
• Example
considered earlier

Flyback Converter:Transfer Function Plots
• An example

Linearizing the PWM Block
• The transfer function is essentially a constant with

zero phase shift
Gain of the PWM IC
• It is slope of the characteristic

Typical Gain and Phase Plots of the Open-
Loop Transfer Function
• Definitions of the crossover frequency, phase and

gain margins
A General Amplifier for Error Compensation
• Can be implemented using a single op-amp

Type-2 Error Amplifier
• Shows phase boost at the crossover frequency

Voltage Feed-Forward
• Makes converter immune from input voltage

variations
Voltage versus Current Mode Control
• Regulating the output voltage is the objective in both

modes of control
Various Types of Current Mode Control
• Constant frequency, peak-

current mode control is used
most frequently

Peak Current Mode Control
• Slope compensation is needed

A Typical PWM Control IC
• Many safety control

functions are built in

Current Limiting
• Two options are shown

Implementing
Electrical
Isolation in the
Feedback Loop
• Two ways are shown

Implementing Electrical Isolation in the
Feedback Loop
• A dedicated IC for this application is available

Input Filter
• Needed to comply with the EMI and harmonic limits

ESR of the Output Capacitor
• ESR often dictates the peak-peak voltage ripple

Chapter 11
Power Conditioners and Uninterruptible
Power Supplies
• Becoming more of a concern as utility de-regulation

proceeds
Copyright © 2003 Chapter 11 Power Conditioners 11-1
by John Wiley & Sons, Inc. and UPS
Distortion in the Input Voltage
• The voltage supplied by the utility may not be

sinusoidal

Typical Voltage Tolerance Envelope for
Computer Systems
• This has been superceded by a more recent

standard
Typical Range of Input Power Quality

Electronic Tap Changers
• Controls voltage magnitude by connecting the

output to the appropriate transformer tap

Uninterruptible Power Supplies (UPS)
• Block diagram; energy storage is shown to be in

batteries but other means are being investigated

UPS: Possible Rectifier Arrangements
• The input normally supplies power to the load as

well as charges the battery bank

UPS: Another Possible Rectifier
Arrangement
• Consists of a high-frequency isolation transformer

UPS: Another Possible Input Arrangement
• A separate small battery charger circuit

Battery Charging Waveforms as Function of
Time
• Initially, a discharged battery is charged with a

constant current

UPS: Various Inverter Arrangements
• Depends on applications, power ratings

UPS: Control
• Typically the load is highly nonlinear and the voltage

output of the UPS must be as close to the desired
sinusoidal reference as possible
UPS Supplying Several Loads
• With higher power UPS supplying several loads,

malfunction within one load should not disturb the
other loads

Another Possible UPS Arrangement
• Functions of battery charging and the inverter are

combined

UPS: Using the Line Voltage as Backup
• Needs static transfer switches

Chapter 12
Introduction to Motor Drives
• Motor drives are one of the most important

applications of power electronics
Copyright © 2003 Chapter 12 Introduction to 12-1

by John Wiley & Sons, Inc. Motor Drives
Control Structure of Drives
• Very general description

Servo Drives
• The basic structure is the same regardless of the

drive that is selected

An Example of Adjustable Speed Drives
• The speed of the drive response is not important

here

A Representation of the Load on a Drive
• This cycle may repeat continuously

Two Coupling Mechanisms
• Commonly used

Instantaneous Waveforms of Torque and
Current
• Their RMS values may determine the limit

Simplified Circuit of a Drive
• Allows discussion of various parameters and

operating conditions on losses and ratings

Control of Servo Drives
• The structure is application dependent

Limiters in the Control Structure
• By providing ramp limiters, for example, drive can

be prevented from “triping” under sudden changes

Chapter 13
DC-Motor Drives
•These drives continue to be used
Copyright © 2003 Chapter 13 DC Motor Drives 13-1

DC-Motor Structure
• With permanent magnets or a wound field

DC-Motor Equivalent Circuit
• The mechanical system can also be represented as

an electrical circuit
Four-Quadrant Operation of DC-Motor
Drives
• High performance drives may operate in all four

quadrants
DC-Motor Drive Torque-Speed
Characteristics and Capabilities
• With permanent magnets

DC-Motor Drive Capabilities
• Separately-Excited field
Controlling Torque, Speed and Position
• Cascaded control is commonly used

Small-Signal Representation of DC
Machines
• Around a steady state operating point

Electrical Time-Constant of the DC Machine
• The speed is assumed constant

Mechanical Time-Constant of the DC
Machine
• The load-torque is assumed constant

DC-Motor Drive: Four-Quadrant Capability
• If a diode-rectifier is used, the energy recovered

during regenerative braking is dissipated in a resistor
Ripple in the Armature Current
• Bi-polar and uni-polar voltage switchings

Control of Servo Drives
• A concise coverage is presented in “Electric Drives: An

Integrative Approach” by N. Mohan (www.MNPERE.com)
• Non-linearity is introduced
Converters for Limited Operational
Capabilities
• Two switches for 2-quadrant operation and only one

switch for 1-quadrant operation
Line-Controlled Converters for DC Drives
• Large low-frequency ripple in the dc output of

converters
Four Quadrant Operation using Line
Converters
• Two options to achieve 4-quadrant operation

Effect of Discontinuous Current Conduction
• Speed goes up unless it is controlled

Open-Loop Speed Control
• Adequate for general-purpose applications

DC Drive Characteristics and Capabilities
• Line current in switch-mode

and line-converter drives

Chapter 14
Induction Motor Drives
• Extremely large potential as adjustable speed drives
Copyright © 2003 Chapter 14 Induction 14-1

Pump Application: Adjustable Flow rate
• Fixed versus adjustable speed drive

Per-Phase Representation
• Assuming sinusoidal steady state

Important Relationships in an Induction
Machine
• Not necessary for our purposes to know the

exact expressions for constants used here
Torque-Speed Characteristics
• The linear part of the characteristic is utilized in

adjustable speed drives
Plot of Normalized Rotor Current
• It increases with slip and slip frequency

Acceleration Torque at Startup
• Intersection represents the equilibrium point

Torque Speed Characteristics at various
Frequencies of Applied Voltage
• The air gap flux is kept constant

Adjusting Speed of a Centrifugal Load
• The load torque is proportional to speed squared

Frequency at Startup
• The torque is limited to limit current draw

Increasing Speed at Startup
• The ramp rate of frequency depends on load inertia

Phasor Diagram at Small Value of Slip
Frequency
• The rotor branch is assumed to be purely

resistive

Voltage Boost to Keep Air Gap Flux at its
Rated Value
• Depends on the torque loading of the machine

Induction Motor Drive Capability Curves
• Mainly two regions

Generator Mode of Operation
• Rotor speeds exceed the synchronous speed

Regenerative Braking Mode to Slow Down
• Machine is made to go into the generator mode

Per-Phase Equivalent Circuit at Harmonic
Frequencies
• The magnetizing branch is ignored

Torque Pulsations due to Harmonics
• Rotations of fields due to the fifth and the

seventh harmonics are in opposite directions
Classification of Converter Systems
• PWM-VSI is now most commonly use

PWM-VSI System
• Diode rectifier for unidirectional power flow

PWM-VSI System
• Options for recovered energy during

regenerative braking
General-Purpose Speed Controller
• High dynamic performance is not the objective

here
Change in Switching Frequency based on the
required Fundamental Frequency
• Can be significant in large power ratings

Field-Oriented Control
• A concise coverage is presented in “Advanced Electric

Drives: Analysis, Control and Modeling using Simulink” by
N. Mohan (www.MNPERE.com)
Square-Wave VSI Waveforms
• Large peak-peak ripple in currents

CSI Drives
• Mostly PWM-VSI drives are used

Comparison of Three Types of Inverter
Systems
• PWM-VSI is by far the most commonly selected

system now
Speed Control by Adjusting the Stator Voltage
• Highly inefficient in
most cases

Controlling the Stator Voltage Magnitude
• Results in distorted current and torque pulsations

Torque-Speed Curves for Wound-Rotor
Machines
• Highly energy-inefficient unless using energy

recovery schemes
Static Slip Recovery
• Applications in very large power ratings where the

speed is to be adjusted over a very limited range
Chapter 15
Synchronous Motor Drives
• A large variety of applications – higher efficiency
Copyright © 2003 Chapter 15 Synchronous 15-1

Rotor Structure
• Permanent-magnet or wound with a field

winding

Per-Phase Representation
• In sinusoidal steady state

Phasor Diagram
• Optimum operation

Rotor Position
• Needs closed-loop operation knowing the rotor

position
Synchronous Motor Drive
• Controller based on steady state operation

Trapezoidal Waveform Synchronous Motor
• used in applications where speed of response not critical

Load-Commutated Inverter (LCI) Drive
• Used in very large power ratings

LCI Drive Controller
• Line converter controls the dc-link current

Three-Phase Cycloconverter
• Low-frequency ac output is
synthesized

Chapter 16
Residential and Industrial Applications
• Significant in energy conservation; productivity
Copyright © 2003 Chapter 16 Residential and 16-1

by John Wiley & Sons, Inc. Industrial Applications
Improving Energy Efficiency of Heat Pumps
• Used in one out of three new homes in the U.S.

Loss Associated with ON/OFF Cycling
• The system efficiency is improved by ~30

percent

Inductive Ballast of Fluorescent Lamps
• Inductor is needed to limit current

Rapid-Start Fluorescent Lamps
• Starting capacitor is needed

Electronic Ballast for Fluorescent Lamps
• Lamps operated at ~40 kHz

Induction Cooking
• Pan is heated directly by circulating currents –

increases efficiency

Industrial Induction Heating
• Needs sinusoidal current at the desired

frequency: two options
Welding Application
• Three options

Switch-Mode Welders
• Can be made much lighter weight

Integral Half-Cycle Controllers
• Used for heating

Chapter 17
Electric Utility Applications
• These applications are growing rapidly
Copyright © 2003 Chapter 17 Electric 17-1

by John Wiley & Sons, Inc. Utility Applications
HVDC Transmission
• There are many such systems all over the world

HVDC Poles
• Each pole consists of 12-pulse converters

HVDC Transmission: 12-Pulse Waveforms
• Idealized waveforms
HVDC Transmission: Converters
• Inverter mode of operation

Control of HVDC Transmission System
• Inverter is operated at the minimum extinction

angle and the rectifier in the current-control mode

HVDC Transmission: DC-Side Filters
Tuned for the lowest (12th

harmonic) frequency

HVDC Transmission: AC-Side Filters
Tuned for the lowest (11th

and the 13th harmonic)
frequencies

Effect of Reactive Power on Voltage
Magnitude
• Illustration of the basic principle

Thyristor-Controlled Inductor (TCI)
• Increasing the delay angle reduces the reactive

power drawn by the TCI
Thyristor-Switched Capacitors (TSCs)
• Transient current at switching must be minimized

Instantaneous VAR Controller (SATCOM)
• Can be considered as a reactive current source

Characteristics of Solar Cells
• The maximum power point is at the knee of the

characteristics
Photovoltaic Interface
• This scheme uses a thyristor inverter

Harnessing of Wing Energy
• A switch-mode inverter may be needed on the

wind generator side also

Interface with 3-Phase Utility Grid
• Uses a thyristor inverter

Interface of SMES
• Can be used for utility load leveling

Active Filters for Harmonic Elimination
• Active filters inject a nullifying current so that the

current drawn from the utility is nearly sinusoidal
Chapter 18
Utility Interface
• Power quality has become an important issue
Copyright © 2003 Chapter 18 Utility Interface 18-1

Various Loads Supplied by the Utility Source
• PCC is the point of common coupling

Diode-Rectifier Bridge
• Bock diagram

Typical Harmonics in the Input Current
• Single-phase diode-rectifier bridge

Harmonic Guidelines: IEEE 519
• commonly used for specifying limits on the input

current distortion

Harmonic Guidelines: IEEE 519
• Limits on distortion in the input voltage supplied

by the utility
Reducing the Input Current Distortion
• use of passive filters

Power-Factor-Correction (PFC) Circuit
• For meeting the harmonic guidelines

Control
• generating the switch on/off signals

• Operation during each half-cycle

Thyristor Converters for 4-Quadrant
Operation
• Two back-to-back connected 2-quadrant converters

Switch-Mode Converter Interface
• Bi-directional power flow; unity PF is possible

• Rectifier and Inverter modes based on the

direction of power flow
Switch-Mode Converter Control
• DC bus voltage is maintained at the reference

value

• Waveforms in the rectifier mode

3-Phase Switch-Mode Converter Interface
• Rectifier and Inverter modes based on the

direction of power flow
EMI: Conducted Interefence
• Common and differential modes

Switching Waveforms
• Typical rise and fall times

Conducted EMI
• Various Standards

Conducted EMI
• Filter arrangement

Review of Basic Semiconductor Physics
Copyright © by John Wiley & Sons 2003 Semiconductor Physics - 1

Current Flow and Conductivity
Area = A
• Charge in volume Adx = dQ dx = v dt
= q n A d x = q n A vdt
• Current density J = (dQ/dt)A-1 Electrons moving
Current with velocity v
=qnv Density
= J
• Metals - gold, platinum, silver, copper, etc.

• n = 1023 cm-3 ; s = 107 mhos-cm
• Insulators - silicon dioxide, silicon nitride, aluminum oxide

• n < 103 cm-3 ; s < 10-10 mhos-cm
• Semiconductors - silicon, gallium arsenide, diamond, etc.

• 108 < n <1019 cm-3 ; 10-10 < s < 104 mhos-cm

Thermal Ionization
broken bond
-
• Si atoms have
thermal vibrations ionized
about equilibrium silicon
atom
+
point.
• Small percentage of
Si atoms have large +
enough vibrational
energy to break -
covalent bond and free
electron
liberate an electron.
covalent bond
neutral silicon atom

Electrons and Holes
• T3 > T2 > T1 -
A
t = T1
• Density of free electrons
= n : Density of free
holes = p
• p = n = ni(T) = intrinsic generation of B
B
carrier density.
- +
• ni2(T) = C exp(-qEg/(kT )) A
= 1020 cm-6 at 300 °K t = T
2
• T = temp in °K
• k = 1.4x10-23 joules/ °K recombination of B apparent
movement
• Eg = energy gap = 1.1 eV
-
of "Hole"
in silicon
A
•q= 1.6x10-19 coulombs t = T
3

Doped Semiconductors
• Extrinsic (doped) semiconductors:p = po ≠ n = no ≠ ni

• Carrier density estimates:
• Law of mass action nopo = ni2(T)
• Charge neutrality Na + no = Nd + po
• P-type silicon with Na >> ni: • N-type silicon with Nd >> ni:
po ≈ Na , no ≈ ni2/ Na no ≈ Nd , po ≈ ni2/ Nd
extra valance
empty
- electron
-
bond
A D

Nonequilibrium and Recombination
• Thermal Equilibrium - Carrier generation = Carrier recombination
• n = no and p = po
• Nonequilibrium - n > no and p > po

• n = no + dn and p = no + dn ; dn = excess carrier density
• Excess holes and excess electrons created in equal numbers by breaking of covalent
bonds
• Generation mechanisms -light (photoelectric effect), injection, impact ionization
• Recombination - removal of excess holes and electrons

• Mechanisms - free electron captured by empty covalent bond (hole) or trapped by
impurity or crystal imperfection
• Rate equation: d(dn)/dt = - dn/t
• Solution dn = dn (0) e -t/t
Carrier Lifetimes
• t = excess carrier lifetime

• Usually assumed to be constant. Changes in two important situations.
• t increases with temperature T
• t decreases at large excess carrier densities ; t = to/[1 + (dn/nb)2 ]
• Control of carrier lifetime values.

• Switching time-on state loss tradeoff mandates good lifetime control.
• Control via use of impurities such as gold - lifetime killers.
• Control via electron irradiation - more uniform and better control.

Current Flow
Drift Diffusion
dn dp
+ +
-
-
e
J
+ p
- Jn
+
-
- +
x x
+ V -
• Jdiff = Jn + Jp = q Dndn/dx - q Dp dp/dx
• Jdrift = q µn n E + q p µp E
• Dn/mn = Dp/mp = kT/q ; Einstein relation
• µn = 1500 cm2/V-sec
for silicon at
room temp. and Nd < 1015 cm-3 • D = diffusion constant, m = carrier mobility
• µp = 500 cm2/V-sec for silicon at
room temp. and Na < 1015 cm-3 • Total current density J = Jdrift + Jdiff

PN Junction
metallurgical junction
P N
N N ND
ND A
A
N N
A A
x x
- N
D - N
D
Step (abrupt) junction Linearly graded junction

Formation of Space Charge Layer
metallurgical
junction x
• Diffusing electrons and holes ionized ionized
leave the region near acceptors donors
metallurgical junction depleted
of free carriers (depletion P + N
region). + +
Electric
field
- opposing
• Exposed ionized impurities - + diffusion
Diffusing
form space charge layer.
electrons + +
Diffusing
holes
+
-
• Electric field due to space + +
charge opposes diffusion.
space charge
layer width = W

Quantitative Description of Space Charge Region
r
• Assume step junction.
qN
d
d 2F r x
= - e -x p xn
dx 2
r = - qNa ; x < 0 -qN a
w
r = qNd ; x > 0
E
dF
= - E(x ) x
dx
qNa(x +x p )
E(x ) = e ; - xp <x <0
qNd (x - x n) E max
E(x ) = e ; 0< x < x n
xn
F
Fc = - ÛE(x )dx
ı
x
- xp
Fc
qNax p 2!+!qNd x n2
Fc = - depletion layer
2e

Contact (Built-in, Junction) Potential
dF dn
• In thermal equilibrium Jn = q µn n dx + q Dn dx = 0
n(xn)
F(xn)
Dn Ûdn
• Separate variables and integrate ; Û
ıdF = - Ù
µn ı n
F(xp) n(xp)
kT ÈNaNd˘
• F(xn) - F(xp) = Fc = q lnÍ 2 ˙ ; Fc = contact potential
Î ni ˚
• Example
• Room temperature kT/q = 0.025 eV

• Na = Nd = 1016 cm-3 ; ni2 = 1020 cm-6
• Fc = 0.72 eV

Reverse-Biased Step Junction
• Starting equations
• W(V) = x n(V) + x p(V) V +

+
qNax p2!+!qNdx n2 P
+
N
• V + Fc = -
2e
+ +
+
• Charge neutrality qNax p = qNdx n Wo
W(V)
F
• Solve equations simultaneously
• W(V) = Wo 1+V/Fc x
F
c
2eFc(Na+Nd) Fc + V
• Wo =
qNaNd
x (V)
n
2Fc
- x p(V)
• Emax = 1!+!V/Fc
Wo

Forward-Biased PN Junction
++ N • Forward bias favors

P
+ diffusion over drift.
p-side drift n-side drift
region
W(V) region
Wo
ni 2 qV • Excess minority
ni 2 qV
p n(0) =
Nd
exp(
kT
)
carrier injection into
exp( ) = np (0)
Na kT
both p and n drift
x p n(x) = pn (0) exp(
x
)
regions.
np (x) = np (0) exp(- ) Lp
Ln
np o
p • Minority carrier
no
x diffusion lengths.
!!∞ È ni 2 ˘˙
• Ln = [Dntn]0.5
!-!∞ È
Í ni 2 ˘
˙ Í
Qn = Ú!np (x)dx = q Í np (0)!-! !˙ Qp = !pn(x)dx = q Í p n(0)!-!
Ú !
ÈÎ Na ˚ Î Nd ˙ ˚ • Lp = [Dptp]0.5
0
È 0

Ideal PN Junction I-V Characteristics
• Excess carriers in drift regions recombined and thus more must be constantly injected if
the distributions np(x) and pn(x) are to be maintained.
• Constant injection of electrons and holes results in a current density J given by
Qn Qp È Ln Lp ˘ È qV ˘
2
J = t + t = q ni Í + Í ˙
n p N t N t
˙ Í exp( kT )!-!1˙
Î an d p˚ Î ˚
È qV ˘ È Ln Lp ˘
J = Js Í ˙ 2
Í exp( kT )!-!1˙ ; Js = q ni Í + ˙
Î ˚ ÎNatn Ndtp˚
J i
J
v
- Js
v
reverse combined
forward bias bias characteristic v

Reverse Saturation Current
• Carrier density gradient

V + immediately adjacent to
+ depletion region causes
+ reverse saturation current to
P N
+ + flow via diffusion.
Wo • Js independent of reverse
W(V) voltage V because carrier
density gradient unaffected by
applied voltage.
np o
p
no
+ • Js extremely temperature
n p (x) p (x) sensitivity because of
n
dependence on ni2(T.)
x
Electric field, J
s
Impact Ionization
-
• E ≥ EBD ; free electron can
acquire sufficient from the field Si
between lattice collisions (tc ≈ - -
10-12 sec) to break covalent bond.
- Si
• Energy = 0.5mv2 = q Eg ; v = q EBDtc
-
-
• Solving for EBD gives Si
2! Eg! m
EBD = Electric field E -
q! tc2
• Numerical evaluation
• m = 10-27 grams, Eg = 1.1 eV, tc = 10-12 sec.
(2)! (1.1)! (1027)

• EBD = = 3x105 V/cm
-19
(1.6x10 )! (10 ) -24
• Experimental estimates are 2-3.5x105 V/cm

Lecture Notes
Diodes for Power Electronic Applications
OUTLINE
• PN junction power diode construction

• Breakdown voltage considerations
• On-state losses
• Switching characteristics
• Schottky diodes
• Modeling diode behavior with PSPICE
Copyright © by John Wiley & Sons 2003 Diodes - 1

Basic Structure of Power Semiconductor Diodes
Anode
i
10
P+ 19 -3 microns
N = 10 cm
A
breakdown
v 14 -3 voltage
N- epi N = 10 cm
D dependent
19 -3
N+ substrate N = 10 cm 250
D
microns
Cathode
anode i
1
i
R on
B VBD
v v
ª 1 V v
cathode

Breakdown Voltage Estimate - Step Junction
F
• Non- punch- thr ough di ode. Dr i ft
W(V)
r egi on l ength Wd > W(BV BD) =
l ength of space char ge r egi on at
br eak down. x
Fc
• W(V) = Wo 1+V/Fc
Fc + V
2eFc(Na+Nd )
• Wo =
qNaNd 4!Fc
• (Emax )2 = (EBD)2 = BV BD
Wo 2
2Fc
• Emax = 1!+!V/Fc
Wo
• Sol ve for W(BV BD) and BV BD
• Power di ode at r ev er se br eak down:
Na >> Nd ; E = EBD ; V = BV BD >> Fc to obtai n (put i n Si val ues)
e!EBD2 1.3x 1017
Wo 2!BV BD 2eFc
BV BD = = ; [V]
• W2(BV BD) = ; Wo
2= 2!q!Nd Nd
Fc q!Nd
2!BV BD
W(BV BD) = = 10- 5 BV BD ; [µ m]
EBD
• Concl usi ons
1. Lar ge BV BD (103 V) r equi r es Nd < 1015 cm - 3
2. Lar ge BV BD (103 V) r equi r es N- dr i ft r egi on > 100 µ m

Breakdown Voltage - Punch-Through Step Junction
• Punch-through step junction - W(BVBD) > Wd
• At breakdown:
- V + • V1 + V2 = BVBD
P+ N- N
+ • E1 + E2 = EBD
W qNdWd2
d
Electric
• BVBD = EBD Wd -
2e
E1 + E 2 field
V
1 e(EBD)2
E2 • If Nd << (required
V2 2q(BVBD)
x value of Nd for non-punch-thru
diode), then
qNdWd qNdWd2
• E1 = ; V1 = • BVBD ≈ EBD Wd and
e 2e
• Wd(Punch-thru)
• V2 = E2 Wd ≈ 0.5 Wd(non-punch-thru)

Effect of Space Charge Layer Curvature
diffusing incident acceptor impurities
acceptor
impurities S i O2
• If radius of curvature is comparable
to depletion layer thickness, electric
field becomes spatially nonuniform.
+
P
R
depletion • Spatially nonuniform electric field
layer N- reduces breakdown voltage.
+
N
• R > 6 W(BVBD) in order to limit
breakdown voltage reduction to 10%
• Impurities diffuse as fast laterally as vertically or less.
• Not feasible to keep R large if

• Curvature develops in junction boundary and in BVBD is to be large ( > 1000 V).
depletion layer.

Control of Space Charge Layer Boundary Contour
field plates
• Electrically isolated conductors
(field plates) act as equipotential
P+ surfaces.
depletion layer • Correct placement can force

boundary depletion layer boundary to have
N- larger radius of curvature and t;hus
minimize field crowding.
SiO2 • Electrically isolated p-regions

(guard rings)has depletion regions
P P
P+ which interact with depletion region
guard ring of main pn junction.
depletion
layer
- • Correct placement of guard rings
boundary N
can result in composite depletion
N+
region boundary having large radius
aluminum of curvature and thus minimize field
contact crowding.
Surface Contouring to Minimize Field Crowding
depletion layer
boundary
N+ N+
SiO
2
N-
N-
P+ P+
bonding pad bonding pad
high field
region
• Large area diodes have depletion • Proper contouring of surface can

layers that contact Si surface. mimimize depletion layer curvature and
• Difference in dielectric constant of Si thus field crowding.
and air causes field crowding at surface. • Use of a passivation layer like SiO2 can
• Electric fields fringing out into air also help minimize field crowding and
attract impurities to surface that can also contain fringing fields and thus
lower breakdown voltage. prevent attraction of impurities to
surface.
Conductivity Modulation of Drift Region
• Forward bias injects holes into drift
region from P+ layer. Electrons
x attracted into drift region from N+
+ + -
layer. So-called double injection.
P N - N+
W • If Wd ≤ high level diffusion length La ,

d
carrier distributions quite flat with p(x)
p(x) = n(x) log scale ≈ n(x) ≈ na.
16
= n a = 10
• For na >> drift region doping Nd, the
p (x) resistance of the drift region will be
n p (x) 14 n
n no = 10 quite small. So-called conductivity
p modulation.
no
n p =10 6
po
no
x
• On-state losses greatly reduced below
those estimated on basis of drift region
low-level (Nd) ohmic conductivity.
Drift Region On-State Voltage Estimate
QF q!A!Wd!na
• IF = = ; Current needed
t t
to maintain stored charge QF.
W
d
q![µn!+!µp]!na!A!Vd x
• IF = ;
Wd
Ohm’s Law (J = sE)
+ + -
P N - N+
IF
Wd2
• Vd = ; Equate above + V - + V -
![µn!+!µp]!t j d
Cross-sectional
two equations and solve for Vd
area = A
• Conclusion: long lifetime t minimizes Vd.

Diode On-State Voltage at Large Forward Currents
µo
• µn + µp = ; nb ≈ 1017 cm-3 . i
na
1!+!
nb
• Mobility reduction due to increased 1
carrier-carrier scattering at large na. R on
v
q!na!A!Vd µo ª 1 V
• IF = ; Ohms Law
Wd na
1!+! If!Wd
nb
• Vd =
with density-dependent mobility. q!µo!nb!A
• Vd = IF Ron
• Invert Ohm’s Law equation to find Vd as
function IF assuming na >> nb.
• V = Vj + Vd
Diode Switching Waveforms in Power Circuits
Q rr = I t /2
rr rr
di /d t d i /d t
F I F R 0. 25 I rr
I
rr
t t t
3 4 5 diF diR
• dt and dt determined
V on t
V
FP
rr by external circuit.
t • Inductances or power
t V
V
R semiconductor devices.
2 rr
t
t 5
1 S =
t
4

Diode Internal Behavior During Turn-on
t interval
1
- +
- + di F
P + - + N- N+
Csc(V) =
e!A
V FP ≈ IF R d + L
i (t) - + !W(V) dt
F
Wd
Rd = L = stray or
q!m n!Nd !A wiring inductance
Cs c Rd L
t interval
2
- +
P+ - + N- N+
i (t) - +
F
Vj ≈ 1.0 V
time
• Injection of excess
time carriers into drift
time
region greatly
reduces Rd.
x

Diode Internal Behavior During Turn-off
t - t interval
3 4
i (t)
- + N+
R
P+ - N-
- +
+
Vj ≈ 1.0 V • R d i ncr eases as ex cess
Rd
car r i er s ar e r emoved vi a
C sc L r ecombi nati on and car r i er
sweep- out (negati ve cur r ent).
time
time time di R
• Vr = I r r R d + L
dt
t s i nt e r v a l
• I nsuffi ci ent ex cess car r i er s r emai n to suppor t I r r , so
P +N- j uncti on becomes r ev er se- bi ased and cur r ent

decr eases to zer o.
• Vol tage dr ops fr om V r r to V R as cur r ent decr eases

to zer o. Negati v e cur r ent i ntegr ated ov er i ts ti me
dur ati on r emov es a total char ge Qr r .

Factors Effecting Reverse Recovery Time
diR diR trr • If stored charge removed mostly

• Irr = t = ; Defined on by sweep-out Qrr ≈ QF ≈ IF t
dt 4 dt (S!+!1)
switching waveform diagram
• Using this in eqs. for Irr and trr

and assuming S + 1 ≈ 1 gives
Irr!trr diR trr2
• Qrr = = ; Defined
2 dt 2(S!+!1)
2"IF"t
on waveform diagram trr = and
diR
dt
• Inverting Qrr equation to solve for trr yields
diR diR
2Qrr(S+1) 2Qrr Irr = 2"IF"t"
dt dt
trr = and Irr =
diR (S!+!1)
dt

Carrier Lifetime-Breakdown Voltage Tradeoffs
• Low on-state losses require Conclusions

kT
L= D!t = !t 1. Higher breakdown voltages
q![µn!+!µp]
require larger lifetimes if low
L = Wd ≥ W(V) = 10-5BVBD on-state losses are to be
maintained.
• Solving for the lifetime yields 2. High breakdown voltage

Wd2 devices slower than low
t= = 4x10-12 (BVBD)2 breakdown voltage
(kT/q)![µn+µp]
devices.
3. Turn-off times shortened

• Substituting for t in Irr and trr equations gives
diR
IF by large but Irr is
dt
• trr = 2.8x10-6 BVBD
(diR/dt) increased.
diR
• Irr = 2.8x10-6 BVBD IF!
dt

Schottky Diodes
anode
aluminum
SiO2 contact -
Characteristics rectifying
• V(on) = 0.3 - 0.5 volts.

P P
• Breakdown voltages guard

≤ 100-200 volts. ring
depletion layer depletion layer
boundary with N boundary
• Majority carrier device - no guard rings without guard
stored charge. rings
• Fast switching because of lack

of stored charge. N+
aluminum
cathode
contact -
ohmic
Physics of Schottky Diode Operation
• Electrons diffuse from Si to Al

because electrons have larger + V -
i(t)
average energy in silicon
Aluminum n-type Si
compared to aluminum.
Electron Energy
• Depletion layer and thus potential
barrier set up. Gives rise to
E
rectifying contact. Si
E
Al
• No hole injection into silicon. No
source of holes in aluminum. Thus
- +
diode is a majority carrier device. Al - + N-Si
+
• Reverse saturation current much Depletion layer
Diffusing
larger than in pn junction diode.
electrons
This leads to smaller V(on) (0.3 -
0.5 volts)

Schottky Diode Breakdown Voltage
• Breakdown voltage limited to

100-200 volts. anode
• Narrow depletion region

widths because of heavier
drift region doping needed for
P P
low on-state losses.
• Small radius of curvature of

depletion region where
metallization ends on surface 16
N ≈ 10
of silicon. Guard rings help to
mitigate this problem. +
N
• Depletion layer forms right at

silicon surface where cathode
maximum field needed for
breakdown is less because of
imperfections, contaminants.

Schottky Diode Switching Waveforms
• Schottky diodes switch much
faster than pn junction diodes. No Current
minority carrier storage.
I
F
• Foreward voltage overshoot VFP
much smaller in Schottky diodes. t
Drift region ohmic resistance RW. V
FP
• Reverse recovery time trr much

V(on)
smaller in Schottky diodes. No
minority carrier storage. t
voltage
• Reverse recovery current Irr
comparable to pn junction diodes. C(Schottky) ≈ 5 C(PN)
space charge capacitance in
Schottky diode larger than in pn
R (Sch.) << RW (pn)
junction diode becasue of W
narrower depletion layer widths
resulting from heavier dopings.

Ohmic Contacts
• Electrons diffuse from Al into p-

type Si becasue electrons in Al
have higher average energy.
• Electrons in p-type Si form an Electron Energy

accumulation layer of greatly
E
enhanced conductivity. Al
E
• Contact potential and rectifying Si
junction completely masked by Accumulation layer
i(t)
enhanced conductivity. So-called P-Si or
-
Al
ohmic contact. - N+-Si
• In N+ Si depletion layer is very Diffusing

narrow and electric fields approach electrons
impact ionization values. Small
voltages move electrons across
barrier easily becasue quantum
mechanical tunneling occurs.

PN Vs Schottkys at Large BVBD
• Minority carrier drift region • Desired breakdown voltage
relationships 1.3x1017
q"[µn"+"µp]"na"A"Vd requires Nd = and
• IF ≈ BVBD
Wd
Wd ≥ 10-5 BVBD
• Maximum practical value of na =1017

• Large BVBD (1000 V) requires Nd
cm-3 and corresponding to
µn + µp = 900 cm2/(V-sec)
= 1014 cm-3 where µn + µp =
1500 cm2/(V-sec)
• Desired breakdown voltage requires
Wd ≥ 10-5 BVBD IF Vd
• ≈ 3.1x106
IF Vd A [BVBD]2
= 1.4x106
A BVBD
• Conclusion: Minority carrier
• Majority carrier drift region devices have lower on-state
relationships
losses at large BVBD.
q"[µn"+"µp]"Nd"A"Vd
• IF ≈
Wd

PSPICE Built-in Diode Model
• Circuit diagram • Components
• Cj - nonlinear space-charge capacitance
+ i
diode
• Cd - diffusion capacitance. Caused by excess
+
carriers. Based on quasi-static description of
v i (v ) stored charge in drift region of diode.
Cj j C
v d dc j
diode -
• Current source idc(vj) models the exponential
Rs I-V characteristic.
-
• Rs accounts for parasitic ohmic losses at high
v = vj + R i
diode s diode currents.

Stored Charge in Diode Drift Region - Actual
Versus Quasi-static Approximation
x
+ -
• One dimensional diagram of a
P N N+
power diode.
n(x,t) n(x,t)
time
• Quasistatic view of decay of
time
excess carrier distribution
time
during diode turn-off.
n(x,t) = n(x=0,t) f(x)
x
0 Wd • Redistribution of excess
carriers via diffusion ignored.
time Equ;ivalent to carriers moving
with inifinte velocity.
time time
• Actual behavior of stored

charge distribution during
x turn-off.

Example of Faulty Simulation Using Built-in Pspice Diode Model
L
stray
50 nH
I o
+
D
f • Test circuit example - step-down converter.
V 50 A
d
100 V - • PSPICE diode model parameters - (TT=100ns

Sw
Cjo=100pF Rs=.004 Is=20fA)
Diode
Voltage
0V
-100V
-200V
-300V • Diode voltage transient

-400V
-500V
0s 100ns 200ns 300ns 400ns 500ns
time
Diode
Current
100A
50A
0A
-50A
-100A
• Diode current transient.
0s 100ns 200ns 300ns 400ns 500ns
time

Improved (lumped-charge) Diode Model
N - region
• More accurately model distributed nature p(x) = n(x)
of excess carrier distribution by dividing
it into several regions, each described by + N+
P Q3 Q
a quasi-static function. Termed the Q1 Q 4 region
region 2
lumped-charge approach.
x
d d
1
i
diode • Circuit diagram of improved diode model. Circuit written in
+
D
terms of physical equations of the lumped-charge model.
v Gd
CJ j
- Vsense1
5 6 7 8
+ -
2
Rs + + +
Ee Re Em Rm Edm Cdm
3 - - - Rdm
+
Emo
- 0
4
+
Vsense2 - • Detailed equations of model given in subcircuit listing.
9
• Many other even better (but more complicated models available in
technical literature..
Details of Lumped-Charge Model
Subcircuit Listing
.Subckt DMODIFY 1 9 Params: Is1=1e-6, Ise=1e-40, Tau=100ns, • Symbolize subcircuit listing into
+Tm=100ns,Rmo=Rs=.001, Vta=.0259, CAP=100p, Gde=.5,
+ Fbcoeff=.5, Phi=1, Irbk=1e20,Vrbk=1e20
SCHEMATICS using SYMBOL
*Node 1= anodeand Node 9 = cathode WIZARD
Dcj 1 2 Dcap ; Included for space charge capacitance and reverse
*breakdown. • Pass numerical values of
.model Dcap D (Is=1e-25 Rs=0 TT=0 Cjo={CAP} M={Gde} parameters Tau, Tm, Rmo,Rs, etc.
+FC={Fbcoeff} Vj={Phi} +IBV={Irbk} BV=Vrbk}) by entering values in PART
Gd 1 2 Value={(v(5)-v(6))/Tm +Ise*(exp(v(1,2)/Vta)-1)}
*Following components model forward and reverse recovery. ATTRIBUTE window (called up
Ee 5 0 VALUE = {Is1*Tau*(exp(V(1,2)/(2*Vta))-1)}; Ee=Qe within SCHEMATICS).
Re 5 0 1e6
Em 6 0 VALUE = {(V(5)/Tm-i(Vsense1))*Tm*Tau/(Tm+Tau)} • See reference shown below for
*Em=Qm more details and parameter
Rm 6 0 1e6
extraction procedures.
Edm 7 0 VALUE = {v(6)};Edm=Qm
Vsense1 7 8 dc 0 ; i(vsense1)=dQm/dt • Peter O. Lauritzen and Cliff L. Ma,
Cdm 8 0 1
Rdm 8 0 1e9 "A Simple Diode Model with
Rs 2 3 4e-3 Forward and Reverse Recovery",
Emo 3 4 VALUE={2*Vta*Rmo*Tm*i(Vsense2) IEEE Trans. on Power Electronics,
+/(v(6)*Rmo+Vta*Tm)}; Vm
Vsense2 4 9 dc 0
Vol. 8, No. 4, pp. 342-346, (Oct.,
.ends 1993)
Simulation Results Using Lumped-Charge Diode Model
Diode voltage and current waveforms Simulation Circuit

L
Diode
10V stray
Voltage
50 nH
0V 0V
.
Io
D
+ V f
-10V d 50 A
410ns 415ns 420ns
-100V
- 100 V
Sw
-200V
0s 100ns 200ns 300ns 400ns 500ns

time
Diode
Current
• Note soft reverse
50A
recovery and forward
voltage overshoot.
Qualitatively matches
0A
experimental
measurements.
-50A
0s 100ns 200ns 300ns 400ns 500ns
time

Lecture Notes
Bipolar Junction Transistors (BJTs)
Outline
• BJT structure and I-V characteristics
• Physical operation of power BJTs
• Breakdown voltage
• Second breakdown
• On-state voltage
• Safe operating areas
Copyright © by John Wiley & Sons 2003 BJTs - 1

Basic Geometry of Power BJTs
emitter
base
opening metallization
emitter
metallization
S i O2
N+ N+ N+ N+
P
-
N
N+
collector
Features to Note
• Multiple narrow emitters - minimize emitter current crowding.
• Multiple parallel base conductors - minimize parasitic resistance in series with the base.

BJT Construction Parameters
base emitter collector
+ 19 -3
10 m N 10 cm base NPN
BJT
16 -3 emitter
5 -20 P 10 cm
m
50-200 m
N
- 10
14
cm
-3 collector
(collector drift
region)
19 PNP
N+
-3 base
250 m 10 cm BJT
collector emitter
Features to Note
• Wide base width - low (<10) beta.
• Lightly doped collector drift region - large breakdown voltage.
Darlington-connected BJTs
C B E
i E,D
I
C
N+ N+
i
B,D i
I B, M
P
B
B D
N- S i O2
M
D1
I + i i
C N
b = = b Db M+ b D+ b M C,D C, M
IB
• Composite device has respectable beta.

Power BJT I-V Characteristic
quasi-saturation
hard
saturation -1 / R
d second breakdown
Features to Note
I B5 > I etc
i B4
C
I
B5 • 2nd breakdown - must be
avoided.
I
B4
active region primary

• Quasi-saturation - unique to
I B3 breakdown power BJTs
I
B2
• BVCBO > BVCEO - extended
blocking voltage range.
I
B1
I < 0
B
I = 0
B
BV
CEO v
BV BV
CEO(sus)
CBO
BJT Internal Current Components
E-B depletion
B C-B depletion
layer
I layer
B • Ine and Ipe flow via diffusion. Inc
and Ipc flow via drift.
I pE + I + I
I pC C C
E N-
E
N+ P
• Ine >> Ipe because of heavy emitter
- I - I nC
nE doping.
W • Ine ≈ Inc because Lnb = {Dnb tnb}1/2

base
<< Wbase and collector area much
p,n p,n larger than emitter area.
Carrier distributions in
normal active region electrons
p • Ipc << other current components
no
holes because very few holes in b-c space
charge region.
npo
p holes
no

Power BJT Current Gain b
• IC ≈ Inc since Ipc very small : IB = - IC - IB = - Inc+ Ine + Ipe
• IB/ IC = 1/b = (Ine - Inc)/Inc + Ipe/Inc
• (Ine - Inc)/Inc represents fraction of electrons injected into base that

recombine in the base. Minimize by having large values of tnb (for long
diffusion lengths) and short base widths Wbase
• Ipe proportional to pno = (ni)2/Nde ; Minimize via large Nde
• Short base width conflicts with need for larger base width needed in HV
BJTs to accomodate CB depletion region.
• Long base lifetime conflicts with need for short lifetime for faster
switching speeds
• Trade-offs (compromises) in these factors limit betas in power BJTs to

range of 5 to 20

Beta versus Collect Current
log ( h )
FE
b
max
-1
Proportional to I
C
log ( I )
C
I I
C,max C,max
10
• Beta decrease at large collector current due to high level injection effects
(conductivity modulation where dn = dp) in base.
• When dn = dp, base current must increase faster than collector current to provide
extra holes. This constitutes a reduction in beta.
• High level injection conditions aided by emitter current crowding.

Emitter Current Crowding
lateral
voltage drop
B B
E
+
N
current crowding
current crowding
C
• IB proportional to exp{qVBE/(kT)}
• Later voltage drops make VBE larger at edge of emitters.
• Base/emitter current and thus carrier densities larger at edge of emitters. So-called emitter
current crowding.
• This emitter current crowding leads to high level injection at relatively modest values of
current.
• Reduce effect of current crowding by breaking emitters into many narrow regions connected
electrically in parallel.

Quasi-saturation in Power BJTs
B
E
Power BJT N+ P N - N+
+ V
BC -
Active region stored charge
VBC < 0
Quasi-saturation stored charge
VBC > 0 but drift region not

completely filled with excess
virtual base
carriers.
Q
2
Q1
Hard saturation
VBC > 0 and drift region
filled with excess carriers.
virtual base
• Beta decreases in quasi-saturation because effective base width (virtual base) width has increased.

Generic BJT Application - Clamped Inductive Load
Vdc
D Model of an
F I o inductively-loaded
switching circuit
R
B
+ Q
v
i
-
• Current source Io models an inductive load with an L/R time constant >> than switching period.
• Positive base current turns BJT on (hard saturation). So-called forward bias operation.
• Negative base current/base-emitter voltage turns BJT off. So-called reverse bais operation.
• Free wheeling diode DF prevents large inductive overvoltage from developing across BJT
collector-emitter terminals.

Power BJT Turn-on Waveforms
I
B,on
i (t) t
B
t d,on
V
BE,on
v (t) t
BE
V
BE,off
t ri
Io
i (t)
C
t fv1
t
fv2
V V
dc CE,sat
v (t)
CE

Excess Carrier Growth During BJT Turn-on
carrier
density time
versus
position
time
x
+
N P N- N+
emitter base collector collector
drift region contact
• Growth of excess carrier distributions begins after td(on) when B-E junction becomes forward biased.
• Entrance into quasi-saturation discernable from voltage or current waveform at start of time tvf2.
• Collector current “tailing” due to reduced beta in quasi-saturation as BJT turns off.
• Hard saturation entered as excess carrier distribution has swept across dirft region.

Turn-off Waveforms with Controlled Base Current
I B,off
I B,on diB /dt
i (t)
B t
V
BE,on
V
BE,off
ts
tfi
I
o
i (t)
C
trv
1
V
CE,sat
V
dc
v (t)
CE tr v
2
• Base current must make a controlled transition (controlled value of -diB/dt) from
positive to negative values in order to minimize turn-off times and switching losses.

Controlled Turn-off Excess Carrier Removal
Q2
time
Q1 Q3
time
+ +
N P N- N
• ts = storage time = time required to remove excess charge Q3.

• trv1 = time to remove charge Q2 holding transistor in quasi-saturation.
• trv2 = time required for VCE to complete its growth to Vdc with BJT in active region.
• tfi = time required to remove remaining stored charge Q1 in base and each edge of cut-off.

Turn-off Waveforms with Uncontrolled Base Current
I B,on I B,off
i (t) t
B
VBE,on
t s
v (t)
BE VBE,off
t collector current
fi1 "tailing"
t fi2
Io
i (t)
C
t rv1
VCE,sat
V
dc
v (t)
CE
t
rv2
• Excessive switching losses with collector current tailing.

Uncontrolled Turn-off Excess Carrier Removal
time
carrier time
density
versus
position
time
time
x
+
N P N- N+
• Uncontrolled base current removes stored charge in base faster than in collector drift region.
• Base-emitter junction reverse biased before collector-base junction.
• Stored charge remaining in drift region now can be only removed by the negative base current
rather than the much larger collector current which was flowing before the B-E junction was
reverse biased.
• Takes longer time to finish removal of drift region stored charge thus leading to collector current
“tailing” and excessive switching losses.

Darlington Switching Behavior
V
dc
D
F
R
B
+ Q
D
v
i Q
- M
D
1
• Turn-on waveforms for Darlington very similar to single BJT circuit.

• Turn-on times somewhat shorter in Darlington circuit because of large base drive for main BJT.
• Turn-off waveforms significantly different for Darlington.
• Diode D1 essential for fast turn-off of Darlington. With it, QM would be isolated without any
negative base current once QD was off.
• Open base turn-off of a BJT relies on internal recombination to remove excess carriers and takes
much longe than if carriers are removed by carrier sweepout via a large collector current.

Darlington Turn-off Waveforms
I I B,off
B,on di B /dt
i (t)
B t
i (t)
B,D
t
be
i B , M (t)
I B,off
i (t) t
C,D
I o
i C , M (t) t
V
BE,on
vB E (t) t
V BE,off
Q & Q on Q off
D M D
V
CE,sat
Vd c
v (t) t
CE

Power BJT Breakdown Voltage
• Blocking voltage capability of BJT limited by breakdown of CB junction.

• BVCBO = CB junction breakdown with emitter open.
• BVCEO = CB junction breakdown with base open.
• BVCEO = BVCBO/(b)1/n ; n = 4 for npn BJTs and n = 6 for PNP BJTs
• BE junction forward biased even when base current = 0 by reverse current from CB junction.
• Excess carriers injected into base from emitter and increase saturation current of CB junction.
• Extra carriers at CB junction increase likelyhood of impact ionization at lower voltages , thus
decreasing breakdown voltage.
• Wide base width to lower beta and increase BVCEO .
• Typical base widths in high voltage (1000V) BJTs = 5 to 10 and BVCEO = 0.5 BVCBO .

Avoidance of Reach-thru
B - V CB +
+ + C
+ -
E N+ P N N+
+ +
+
Reach-thru of CB depletion across base to emitter
• Large electric field of depletion region will accelerate electrons from emitter across base and
into collector. Resulting large current flow will create excessive power dissipation.
• Avoidance of reach-thru
• Wide base width so depletion layer width less than base width at CB junction breakdown.
• Heavier doping in base than in collector so that most of CB depletion layer is in drift region
and not in the base.

Second Breakdown
• Precipitious drop in C-E voltage and perhaps

rise in collector current.
• Simultaneous rise in highly localized regions of

power dissipation and increases in temperature
of same regions.
1. Direct observations via infrared cameras.
2. Evidence of crystalline cracking and even
localized melting.
• 2nd breakdown during BJT turn-off in • Permanent damage to BJT or even device
step-down converter circuit. failure if 2nd breakdown not terminated within
a few µsec.

2nd Breakdown and Current Density Nonuniformities
• Minority carrier devices prone to thermal runaway.
• Minority carrier density proportional to ni(T) which increases exponentially with temperature.
• If constant voltage maintained across a minority carrier device, power dissipation causes
increases in temp. which in turn increases current because of carrier increases and thus better
conduction characteristic.
• Increase in current at constant voltage increases power dissipation which further increases
temperature.
• Positive feedback situation and potentially unstable. If temp. continues to increase, situation
termed thermal runaway.
• Current densities nonuniformities in devices an accenuate

I problems.
• Assume JA > JB and TA > TB
+ J
A J
V B • As time proceeds, differences in J and T between regions A
- and B become greater.
• If temp. on region A gets large enough so that ni > majority
J > J carrier doping density, thermal runaway will occur and
A B
device will be in 2nd breakdown.
Current Crowding Enhancement of 2nd Breakdown Susceptibility
B lateral voltage
drop E
+
N
P
• Emitter current crowding
during either turn-on or turn-off
accenuates propensity of BJTs
N
to 2nd breakdown.
current crowding current crowding
C
lateral voltage drop

• Minimize by dividing emitter
B into many narrow areas
E
connected electrically in
+ parallel.
N
current
C crowding

Velocity Saturation and Second Breakdown
Electron drift velocity
B
6
8x10
cm/sec E + N- +
C
N P Jc N
Electric field
E sat = 15 kV/cm
E
E max
B
E + N- +
C
N P Jc N x
• Large current density in drift region - BJT active.
E • Jc > qµnNd Esat . Extra electrons needed to carry

1
extra current.
x
• Negative space density gives rise to nonuniform
electric field.
• Moderate current in drift region -
BJT active • Emax may exceed impact ionization threshold
while total voltage < BVCEO.
• Electric field E1 = Jc/(qµnNd) < Esat

Contributions to BJT On-State Losses
E
+
N R
c
- V
BE,sat - V BC,sat
V
BE,sat
P
+ +
I - - V BC,sat
C V
d
N
- + I
C
N+
Re
• VBE,sat - VBC,sat typically 0.1-0.2 V at

C moderate values of collector current.
• Pon = IC VCE,sat
• Rise in VBE,sat - VBC,sat at larger currents
due to emitter current crowding and
• VCE,sat = VBE,sat - VBC,sat + Vd + IC(Rc + Re)
conductivity modulation in base.

BJT Safe Operating Areas
Forward bias safe operating area Reverse bias safe operating area
log( i C ) switching trajectory of diode-

clamped inductive load circuit
I
CM i
C
I
-5 CM
10 sec
RBSOA
T j,max
-4
10 sec
V
BE,off < 0
2nd -3 V =0
2nd 10 sec BE,off
breakdown
breakdown
dc BV v
BV CBO CE
BV log ( v )
CEO CE
Lecture Notes
Power MOSFETs
Outline
• Construction of power MOSFETs
• Physical operations of MOSFETs
• Power MOSFET switching Characteristics
• Factors limiting operating specfications of MOSFETs
• COOLMOS
• PSPICE and other simulation models for MOSFETs
Copyright © by John Wiley & Sons 2003

MOSFETs - 1
Multi-cell Vertical Diffused Power MOSFET (VDMOS)
contact to source
source
diffusion
conductor
field
oxide
gate
oxide
gate
width
N+ N+ N+ N+
P P
N-
gate N+
conductor

MOSFETs - 2
Important Structural Features of VDMOS
source gate conductor

body-source
field oxide
short
gate oxide
N+ N+ N+ N+
P (body) P (body)
N- parasitic i channel
(drift region) BJT
D length
integral
N+ diode
drain
1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation
layer functions.
4. Division of source into many small areas connected electrically in parallel.
Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.

MOSFETs - 3
Alternative Power MOSFET Geometries
Source
boddy-source short
Oxide
N+ N+
Gate
P Channel
P conductor
length • Trench-gate MOSFET
Parasitic BJT Integral
N- ID
ID diode • Newest geometry. Lowest
N+ on-state resistance.
Drain
gate oxide
gate source
N+ N+ P
• V-groove MOSFET.
P
• First practical power
N MOSFET.
i
N+
D • Higher on-state
resistance.
drain

MOSFETs - 4
MOSFET I-V Characteristics and Circuit Symbols
i
D [v - V = v ]
GS GS(th) DS
ohmic
i
VGS5 D
active
VG S 4 actual
VG S 3
linearized
V
GS2
VG S 1
v
V GS
v
V
GS
<V
GS(th) BV
DS GS(th)
DSS
D D
G
G
N-channel P-channel
MOSFET MOSFET
S S

MOSFETs - 5
The Field Effect - Basis of MOSFET Operation
VGG3
V
GG1 +
+ SiO
SiO 2
2 + + + + + + + + + + +
+ + + + + + + + + + +
+ +
N N
ionized P
depletion layer
acceptors
P boundary inversion layer
ionized with free electrons
N acceptors
VG G 2 N depletion layer boundary

+
SiO
2
+ + + + + + + + + + + • Val ue deter mi ned by sever al factor s
1. Type of mater i al used for gate conductor
+ 2. Dopi ng densi ty of body r egi on di r ectl y
N
beneath gate
ionized depletion layer 3. I mpur i ti es/bound char ges i n ox i de
P acceptors boundary eox
free electrons
4. Ox i de capaci tance per uni t ar ea Cox =
N t ox
t ox = ox i de thi ck ness
Thr eshol d Vol tage V GS(th)

• Adjust thr eshol d vol tage dur i ng devi ce
• V GS wher e str ong i nv er si on l ayer has for med. fabr i cati on vi a an i on i mpl antati on of
i mpur i ti es i nto body r egi on just beneath
Typi cal v al ues 2- 5 v ol ts i n power MOSFETs
gate ox i de.

MOSFETs - 6
Drift Velocity Saturation
electron
drift velocity
• Mobility also decreases because large
8 x 1 06
values of VGS increase free electron
cm/sec density.
• At larger carrier densities, free carriers

collide with each other (carrier-carrier
4 electric
1.5x10 V/cm field scattering) more often than with lattice and
mobility decreases as a result.
• In MOSFET channel, J = q µn n E
• Mobilty decreases, especially via carrier-
= q n v n ; velocity v n = µn E
carrier scattering leead to linear transfer
curve in power devices instead of square
• Velocity saturation means that the law transfer curve of logic level MOSFETs.
mobility µn inversely proportional to
electric field E.
MOSFETs - 7
Channel-to-Source Voltage Drop
• VGS = VGG = Vox + VCS(x) ;

V + VCS(x) = ID1RCS(x)
GG V
+ DD1 I
D1
Vo x(x) • Larger x value corresponds be being

closer to the drain and to a smaller
V (x) inversion
+ Vox .
N CS
x depletion
P
• Smaller Vox corresponds to a smaller
N channel thickness. Hence reduction in
N+ channel thickness as drain is
approached from the source.

MOSFETs - 8
Channel Pinch-off at Large Drain Current
• Appar ent di l emma of
channel di sappear i ng at
+
V D D 2+ I
D2 dr ai n end for l ar ge I D
avoi ded.
V Vo x(x)
GG
1. Lar ge el ectr i c fi el d at dr ai n
V (x) inversion
+ end or i ented par al l el to
N CS
depletion dr ai n cur r ent fl ow. Ar i ses
x
velocity fr om l ar ge cur r ent fl ow i n
saturation channel constr i cti on at
P region dr ai n.
N
N+ 2. Thi s el ectr i c fi el d tak es
over mai ntenance of
mi ni mum i nver si on l ayer
thi ck ness at dr ai n end.
• I D2 > I D1 so V CS2(x ) > V CS1(x ) and thus channel
nar r ower at an gi ven poi nt. • Lar ger gate- sour ce bi as
V GG postpones fl atteni ng
• Total channel r esi stance fr om dr ai n to sour ce of I D vs V DS unti l l ar ger
i ncr easi ng and cur ve of I D vs V DS for a fi x ed V GS
val ues of dr ai n cur r ent ar e
fl attens out. r eached.
MOSFETs - 9
MOSFET Switching Models for Buck Converter
V
d D
Io
r
D DS(on)
F
R
G
Cgd
+ G
V
GG
C
gs
S
• Buck converter using power MOSFET.
D
• MOSFET equivalent circuit valid for
on-state (triode) region operation.
C
gd
G I = f(V )
D GS
C
gs
• MOSFET equivalent circuit valid for off-
S state (cutoff) and active region operation.
MOSFETs - 10
MOSFET Capacitances Determining Switching Speed
gate
source
C gs C
gd
C
N+ gd2
N+ P idealization
C
P gd
Cd s
N actual
C gd1
drain-body
N+ depletion layer
v
v = v 200 V DS
GS DS
drain
• Gate-source capacitance Cgs approximately

constant and independent of applied voltages.
• Gate-drain capacitance Cgd varies with applied

voltage. Variation due to growth of depletion layer
thickness until inversion layer is formed.
MOSFETs - 11
Internal Capacitances Vs Spec Sheet Capacitances
MOSFET internal capacitances Reverse transfer or feedback capacitance
C gd C
bridge
G D
+V -
C gs Cd s b
S C gd
Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Input capacitance
G D Output capacitance
G D
C iss
S
C oss
S
C iss = C gs + C gd
C oss = C gd + C d s
MOSFETs - 12
Turn-on Equivalent Circuits for MOSFET Buck Converter
Vi n Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
dur i ng td(on). dur ing tr i .
D I o
F D I o
F
C
DC C
R C gd1 DC
G R C gd1
G
+
V i
G +
GG C V
gs i
GG G C
gs
Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
V
dur i ng tfv1. in
dur ing tfv2.
I o I o r
DS(on)
R
G
R Cg d 1
G +
V i C
G gs
+ GG C gd2
V i
GG G

MOSFETs - 13
MOSFET-based Buck Converter Turn-on Waveforms
V
GG+
t = R (C + C )
G gd1 gs
v (t)
GS
V
G S , Io
t = R (C + C )
G gd2 gs
V
GS(th)
i (t)
G
t
Charge on C
Charge on C + Cg d gd
gs
V in
t
fv2
• Free-wheeling diode
assumed to be ideal.
v (t)
DS
i (t)
(no reverse recovery
D
current).
Io
t
t ri V t
d(on) t fv1 DS(on)

MOSFETs - 14
Turn-on Gate Charge Characteristic
V
Vgs V V d
d1 d2
Vgs,on
I
I V D1
d3 Cgd
V + D1
t g
mo + +
Specified I Vgs C C V
D1 gs ds ds
- -
Q gate g (V - V )
Q Q m gs t
on p
Vgs V + I /gm
Q t D1
(Vt+ID1/gm) T1
V
Qon = ı![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
Û t
t
Vgs,off Vgs,off V
gs,on
Vds,on I
d
Û ! I
Qp = ı!Cgd(Vds)!Vds dVds D1
t
Vd
V
Vgs,on ds
QT = Qon + Qp + ı![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
Û V
V ds,on
(Vt+ID1/gm) d
t
MOSFETs - 15
Turn-on Waveforms with Non-ideal Free-wheeling Diode
Vi n
Io i D (t)
F
Io + I rr
I rr t
C gd1
I rr R
G
i (t)
D +
t rr V i
Io
GG G Cgs
t t
ri
V • Equivalent circuit for

GS,I
V o
GS(th) estimating effect of free-
t wheeling diode reverse
recovery.
Vin
v (t)
DS
t
MOSFETs - 16
MOSFET-based Buck Converter Turn-off Waveforms
t 2= R (C
G gd2
+ C )
gs
v (t)
GS t1= R (C + C )
G gd1 gs • Assume ideal fr ee-
V
GG V V
GS(th)
w heeling diode.
G S , Io
• Essentially the
t inver se of the tur n- on
i (t)
G
pr ocess.
t
d(off)
v (t)
DS • Model quanitatively
i (t)
D using the same
I o
V
in equivalent cir cuits as
for tur n- on. Simply
use cor r ect dr iving
t voltages and initial
t
rv2
t rv1 t fi conditions

MOSFETs - 17
dV/dt Limits to Prevent Parasitic BJT Turn-on
gate D
source
Cg d
+ N+ G
N parasitic
BJT
P P
Cg d
N
+
N S
dVDS
drain
• Large positive Cgd
dt
could turn on parasitic BJT.
D
L+
• Turn-on of T+ and reverse recovery of Df- will
D
F+ dv DS
produce large positive Cgd in bridge circuit.
T+ I o dt
D
L- • Parasitic BJT in T- likely to have been in reverse
active mode when Df- was carrying current. Thus
DF - stored charge already in base which will increase
T-
dv DS
likeyhood of BJT turn-on when positive Cgd is
dt
generated.
MOSFETs - 18
Maximum Gate-Source Voltage
• V GS(max) = maxi mum per mi ssi bl e gate-
sour ce vol tage.
• I f V GS >V GS(max) r uptur e of gate oxi de by

l ar ge el ectr i c fi el ds possi bl e.
• EBD(oxi de) ≈ 5- 10 mi l l i on V/cm

• Gate oxi de ty pi cal l y 1000 anstr oms thi ck
• V GS(max) < [5x106] [10- 5] = 50 V
• Ty pi cal V GS(max) 20 - 30 V
• Stati c char ge on gate conductor can r uptur e

gate oxi de
• Handl e MOSFETs w i th car e (gr ound
y our sel f befor e handl i ng devi ce)
• Pl ace anti - par al l el connected Zener di odes
betw een gate and sour ce as a pr otecti ve
measur e

MOSFETs - 19
MOSFET Breakdown Voltage
depletion layer boundary depletion layer boundary
without field plate with field plate action
action of gate electrode of gate electrode
+ +
N N N
P P
+
N
• BVDSS = drain-source breakdown

2. Appropriate length of drain drift region
voltage with VGS = 0
• Caused by avalanche breakdown of

3. Field plate action of gate conductor
drain-body junction overlap of drain region
• Achieve large values by 4. Prevent turn-on of parasitic BJT with

body-source short (otherwise BVDSS
1. Avoidance of drain-source reach-
through by heavy doping of body = BVCEO instead of BVCBO)
and light doping of drain drift region

MOSFETs - 20
MOSFET On-state Losses
gate
source
accumulation
channel layer
resistance resistance
+
N N+
P
P
I drift region
source region D resistance
N
resistance
drain region
resistance
+
N
drain
• On-state power dissipation Pon = • rDS(on) dominated by drain drift resistance

for BVDSS > few 100 V
Io2 rDS(on)
Vd BVDSS2
• rDS(on) = ≈ 3x10-7
!ID A
• Large VGS minimizes accumulation
• rDS(on) increases as temperature increases.
layer resistance and channel
Due to decrease in carrier mobility with
resistance increasing temperature.

MOSFETs - 21
Paralleling of MOSFETs
Rd
• MOSFETs can be easily
paralleled because of Q
1
positive temperature G
coefficient of rDS(on).
• Positive temperature coefficient leads to thermal

stabilization effect.
• If rDS(on)1 > rDS(on)2 then more current and thus

higher power dissipation in Q2.
• Temperature of Q2 thus increases more than

temperature of Q1 and rDS(on) values become
equalized.
MOSFETs - 22
MOSFET Safe Operating Area (SOA)
log ( i )
D
I
DM • No distinction betw een
-5
FBSOA and RBSOA. SOA
10 sec
is squar e.
10 - 4 sec
Tj , m a x • FB = for w ar d bias.
10
-3
sec
V GS ≥ 0.
• RB = r ever se bias.
DC
V GS ≤ 0.
BV
DSS
• No second br eakdow n.
log ( v )
DS

MOSFETs - 23
Structural Comparison: VDMOS Versus COOLMOS™
source
gate
cond
uctor
N+ N+ N+ N+
+ +
P P
• Conventional
vertically oriented
N-
power MOSFET
N+
drain
source
gate
cond
uctor
• COOLMOS™ structure
N+ N+ N+ N+
P P (composite buffer structure,
b b
W super-junction MOSFET,
P N P super multi-resurf
MOSFET)
b b b
• Vertical P and N regions of
width b doped at same
N+ density (Na = Nd)
drain
MOSFETs - 24
COOLMOS™ Operation in Blocking State
source
gate
cond • COOLMOS™ structure partially
uctor
depleted.
N+ N+ N+ N+
P P
b b • Arrows indicate direction of
depletion layer growth as device
N -
P
turns off.
V1
P
+ • Note n-type drift region and
N+
adjacent p-type stripes deplete
drain uniformly along entire vertical
length.
source
gate
cond
• COOLMOS™ structure at edge
uctor of full depletion with applied
N+ N+ N+ N+ voltage Vc. Depletion layer
P P
b b
N reaches to middle of vertical P
and N regions at b/2.
Ec Ec -
P P
Vc • Using step junction formalism,
+ Vc = (q b2 Nd)/(4 e) = b Ec,max/2
N+
• Keep Ec,max ≤ EBD/2. Thus
drain Nd ≤ ( e EBD)/(q b)

MOSFETs - 25
COOLMOS™ Operation in Blocking State (cont.)
source
gate
cond
uctor
N+ N+ N+ N+
P P P
b N b
Ev Ev
Ev
P -
P
V
Ec Ec
+
N+
drain
V > Vc
• For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
• Ev spatially uniform since space charge compensated for by Ec. Ev ≈ V/W for V >> Vc.
• Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.
• At breakdown Ev = EBD ≈ 300 kV/cm ; V = BVBD = EBDW

MOSFETs - 26
COOLMOS™ Operation in ON-State
source
gate
cond
uctor
• On-state specific resistance ARon [Ω-cm2]
N+ N+ Ro n N+ N+
P P much less than comparable VDMOS
b b because of higher drift region doping.
P P -
V1 • COOLMOS™ conduction losses much
N
less than comparable VDMOS.
+
N+
drain
ID R
L
• Ron A = W/(q µnNd) ; Recall that Nd = (e EBD)/(q b)
• Breakdown voltage requirements set W = BVBD/ EBD.
• Substituting for W and Nd yields Ron A = (b BVBD)/(e µn EBD2)

MOSFETs - 27
Ron A Comparison: VDMOS versus COOLMOS™
• COOLMOS at BVBD = 1000 V. Assume b ≈ 10 µm. Use EBD = 300 kV/cm.

• Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 Ω-cm . Corresponds to Nd = 4x1015 cm-3
• Typical VDMOS, Ron A = 3x10-7 (BVBD)2

• Ron A = 3x10-7 (1000)2 = 0.3 Ω-cm ; Corresponding Nd= 1014 cm3
• Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40

• At BVBD = 600 V, ratio = 1/26.
• Experimentally at BVBD = 600 V, ratio is 1/5.
• For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, “Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model”, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)

MOSFETs - 28
COOLMOS™ Switching Behavior
• Larger blocking voltages Vds > depletion
• MOSFET witching waveforms for clamped inductive load. voltage Vc, COOLMOS has smaller Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.
• Small blocking voltages Vds < depletion

v (t)
voltage Vc, COOLMOS has larger Cgs, Cgd,
GS V GS,Io
and Cds than comparable (same Ron and
V BVDSS) VDMOS.
GS(th)
t
• Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V • Turn-on delay time - shorter
DS(on)
d
• Current rise time - shorter
• Voltage fall time1 - shorter
t
td ( o n ) t r i t fv1 t t rv1 tfi • Voltage fall time2 - longer
fv2 t d(off)
• Turn-off delay time - longer
i (t) t rv2 • Voltage rise time1 - longer
D Io
• Voltage rise time2 - shorter
t • Current fall time - shorter
MOSFETs - 29
PSPICE Built-in MOSFET Model
Circuit components
Drain
RD • RG, RDS, RS, RB, and RD = parasitic

Cgb
ohmic resistances
Cbd
• Cgs Cgd, and Cgb = constant voltage-

Cgd independent capacitors
RG RB
RDS Idrain • Cbs and Cbd = nonlinear voltage-
Gate Bulk dependent capacitors (depletion layer
capacitances)
Cgs Cbs
• Idrain = f(Vgs, Vds) accounts for dc

RS characteristics of MOSFET
Source
• Model developed for lateral (signal level)

MOSFETs
MOSFETs - 30
Lateral (Signal level) MOSFET
Body-source short Cgs G Cgd

• Body-source short keeps Cbs constant.
S D
N+ N+
C bg
• Body-source short puts Cbd between drain and
source.
P
C bs C bd
• Variations in drain-source voltage relatively
Drain-body small, so changes in Cbd also relatively small.
Source-body B
depletion layer
depletion layer
• Capacitances relatively independent of terminal

• Cgs, Cbg, Cgd due to electrostatic
voltages
capacitance of gate oxide. Independent
of applied voltage
• Consequently PSPICE MOSFET model has
voltage-independent capacitances.
• Cbs and Cbd due to depletion layers.
Capacitance varies with junction voltage.
MOSFETs - 31
Vertical Power MOSFET
Body-
source source gate
short
Cg s
Cbg
N+
Cg d N+
Cbs P
P
Cb d N
N+
drain
drain-body depletion layer
• Drain-drift region and large drain-source
voltage variations cause large variations in • MOSFET circuit simulation
drain-body depletion layer thickness models must take this variation
into account.
• Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.
• Moderate changes in Cgb and Cbs.

MOSFETs - 32
Inadequacies of PSPICE MOSFET Model
4
MTP3055E
C gd V = 0
GS • Cgs and Cgd in PSPICE model are
[nF] constant independent of terminal voltages
2 SPICE model
• In vertical power MOSFETs, Cgd varies

Motorola subcircuit model substantially with terminal voltages.
0
0V
10V V 20V 30V
DS
60V
MTP3055E V
DS
• Comparison of transient response of drain-
40V
source voltage using PSPICE model and
Motorola an improved subcircuit model. Both
SPICE
20V subcircuit model models used in same step-down converter
model circuit.
0V
0s 100ns 200ns 300ns
Time

MOSFETs - 33
Example of an Improved MOSFET Model
• Developed by Motorola for their TMOS line of
power MOSFETs
Drain • M1 uses built-in PSPICE models to describe

dc MOSFET characteristics. Space charge
LDRAIN capacitances of intrinsic model set to zero.
DGD
CGDMAX
• Space charge capacitance of DGD models
RDRAIN1 voltage-dependent gate-drain capacitance.
RGDMAX • CGDMAX insures that gate-drain capacitance
RDRAIN2
does not get unrealistically large at very low
LGATE RGATE DBODY
drain voltages.
M1 • DBODY models built-in anti-parallel diode
Gate CGS inherent in the MOSFET structure.
RDBODY
RSOURCE • CGS models gate-source capacitance of
MOSFET. Voltage dependence of this
LSOURCE capacitance ignored in this model.
• Resistances and inductances model parasitic
Source components due to packaging.
• Many other models described in literature. Too
numerous to list here.
MOSFETs - 34
Another Improved MOSFET Simulation Model
Drain
• M2 and M3 are SPICE level 2
L
D
MOSFETs used along with Voffset to
model voltage dependent behavior of
R Cgd.
d
M2 M3
• JFET Q1 and Rd account for voltage drop
Dsub
V offset Q
1
in N- drain drift region
+
-
Gate M1
• Dsub is built-in SPICE diode model used
LG R
G to account for parasitic anti-parallel diode
in MOSFET structure.
RS
LS
• Reference - "An Accurate Model for
Power DMOSFETs Including Inter-
Source electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
• LG, RG, LS RS, LD, RD - parasitic Johnson, IEEE Trans. on Power
inductances and resistances Electronics, Vol. 6, No. 2, pp. 192-198,
(April, 1991)
• M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.
MOSFETs - 35
Lecture Notes
Thyristors (SCRs)
OUTLINE
• SCR construction and I-V characteristics.

• Physical operation of SCRs.
• Switching behavior of SCRs
• dv/dt and di/dt limitations and methods of
improving them.
• SCR drive circuit considerations.
Copyright © by John Wiley & Sons 2002 SCRs -1

Thyristor (SCR) Geometry
Gate Cathode
19
N+ -3 19
N+
-3 1 0m • Cross-sectional
10 cm 10 cm
J3 view showing
17
P 10 cm- 3 30-
100 m vertical
J 2
orientation of
13 14 50-
N 10 - 5x10 cm- 3 1000 SCR.
m
J1
17 • SCRs with
P 10 cm- 3 30-
50 µ kiloamp ratings
+ 19 -3
P 10 cm
have diameters
Anode of 10 cm or
greater.
Gate and cathode metallization for
slow (phase control) thyristor. Gate and cathode metallization
for fast (inverter grade) SCR
cathode gate wafer
distributed
gate
cathode area
(metallization
wafer
not shown)

Thyristor I-V Characteristics
i • SCR triggerable from forward blocking

A
state to on-state by a gate current pulse.
forward
on-state • Thyristor latches on and gate cannot turn it
i > 0 off. External circuit must force SCR off.
I G
H i = 0
G • Current to several kiloamps for V(on) of 2-
I
-V BO 4 volts.
RW
M
V
VH B O vAK • Blocking voltages to 5-8 kilovolts.
forward blocking
state • VBO = breakover voltage ; I BO =
breakover current
Thyristor circuit symbol.
+ VA - • VH = holding voltage I H = holding current
i K
A cathode
anode • Maximum junction temperature = 125 °C -

iG limited by temperature dependence of
VBO.
gate

SCR Model and Equivalent Circuit
One dimensional SCR model.
A
P1 • BJTs in equivalent circuit in active region.
J
(N - ) 1
• Use Ebers-Moll equations for BJTs
N1
J
P 2
2 • IC1 = -a1IE1 + ICO1 ; IC2 = -a2IE2 + ICO
G J
3
(N + )
N2 • IA = IE1 ; I K = -IE2 = IA + IG
K
• IC1 + IB1 + IE1 = 0
Two transistor equivalent circuit
A a IG!+!ICO1!+!ICO2
• IA =
J
1 1!-!!a1!-!a2
Q
1
J
2
• Blocking state a1 + a2 << 1
Q
2
J G
3
• At breakover a1 + a2 ≈ 1
K

Thyristor Turn-on Process
A
• In forward blocking state, both BJTs active.
• If a1 + a2 < 1, connection is stable. Q1
Q2
• If VAK = VBO or if positive gate current pulse is applied
G
a1 + a2 becomes equal to unity and circuit connection becomes
K
unstable and SCR switches on.
Holes attracted
by negative
charge of injected
• Negative charge of electrons swept into n1
p electrons layer partially compensate positive charge
1 +
J1
n1 J 2 depletion of ionized donors exposed by growth of
+ + - width - no gate depletion of junction J2.
+ - + + current
J
2 - - -
- - J 2 depletion • Growth of depletion reduces width of
+ p - bases of Qnpn and Qpnp and thus
2 width - with
J3 gate current
- increases a1 and a2.
n2 Electrons
injected in
response to • Holes attracted by first wave of injected
gate current elctrons attract additional electrons and so
flow on - regenerative action.

Thyristor On-state Latchup
• Negative gate current causes lateral voltage
drops as indicated which lead to current
SCR with negative gate current crowding in center of cathode.
K
Negative gate • Conventional SCRs (phase control) have large
current G area cathodes - negative gate current cannot
remove stored charge from center of large
+
N N+ cathode area.
P
+ - - +
• SCR stays latched on in spite of negative gate
N- current.
P
A
• External circuit must force anode current to
negative values in order that enough stored
charge be removed from SCR so that it can
turn off.

Thyristor On-state Operation
G
A
N2 P N P
K 2 1 1
x
total
carrier
N NA
density D
2 1
1
NA
N
2 D1
x
• On-state: all three junctions forward biased and BJTs

in equivalent circuit saturated.
• On-state stable because saturated BJTs have

a 1 + a 2 << 1.
• On-state voltage V AK(on) = Vj1 - Vj2 + Vj3 + Vn

Thyristor Turn-on Behavior
i (t)
G
T
A t
v d iF
A
TB dt Io
i (t)
vB A
T t t
C d(on)
v tr
C
Io tp s
control v (t)
AK
t
v vB v • td(on) = turn-on delay time; time required for charge

A C
injection by gate current to make a1 + a 2 = 1.
t
• tr = time required for anode current to reach on-state
value. Anode current rate-of-rise di F/dt limited by
external inductance.
• Time intervals that T can be on
A
• tps = time required for plasma to spread over whole
i cathode area from cathode periphery near gate.
G
t
Delay or trigger angle • VAK does not attain on-state value until complete area
of cathode is conducting.
Thyristor Turn-off Behavior
diR
t
dt 3
t2
iA (t)
I I t
R R
t1
4 Turn-off waveforms
dv
F
dt
v (t) V t
AK REV
recovery time t q> t

3
• SCR turn-off quite similar to power diode turn-off.
• Anode current rate-of-fall controlled by external inductance.
• Reverse voltage overshoot caused by external inductance.

• Junction J1 is blocking junction in reverse bias. J3 has low
breakdown voltage (20-40 volts) because of the heavy doping on
both sides of the junction.
Thyristor di/dt Limit at Turn-on
i G
G K
N2 P2 N2
i (t)
G
N
1
P1
t
i
A A
• SCR first turns on at cathode periphery nearest gate. • Use shaped gate current pulse for
rapid turn-on.
• Current constricted to small areas during initial phases of turn-
on, td(on) and tr.
• If anode current rate-of-rise, diF/dt, not kept less than some

specified maximum, current density in constricted area will be
too large.
• Localized power dissipation too high and thermal runaway

likely.

Thyristor Re-applied dv/dt Limits
d vF
dt VF
• Removal of all stored charge in SCR requires a
v (t)
minimum time tq.
AK
t • Application of positive dVF/dt larger than a specified
value before tq results in a pulse of positive anode
V REV current which may produce unintentioned turn-on of
forward the SCR.
recover
y • Avoidance of unintentioned turn-on requires
current dVF/dt < dVF,max/dt and remaining in reverse bias
iA (t) for a minimum time tq.
t
A
dv I
F < BO
dt C j2
max Rate effect
C j2 dv
100 V/ms < F < 2000 V/ms
G dt
max
K
Methods of Improving Thyristor di/dt Rating
distributed
gate
• Interdigitated gate-cathode structure used to greatly
wafer
increase gate-cathode periphery.
• Distance from periphery to center of any cathode region

significantly shortened.
• Ability of negative gate current to break latching

condition in on-state increased.
cathode area • Combination of pilot thyristor, diode, and iterdigitated

(metallization
not shown) gate-cathode geometry tgermed a gate-assisted turn-off
thyristor or GATT
A
• Use of pilot thyristor to increase turn-on gate
current to main thyristor.
pilot
main thyristor • Larger gate current increases amount of initial
thyristor conducting area of cathode and thus improves
G diF/dt capabiities.
• Diode allowes negative gate current to flow from

K main SCR.

Improvement in dv/dt Rating Via Cathode Shorts
dv
C j2 AK
A • Current thru Cj2 indistinguishable from positive gate current with
dt
respect to turn-on of SCR.
• If current thru Cj2 bypasses junction J3, then SCR will not be
turned on by the large displacement currents.
G
C j2 • Cathode shorts provide this desirable bypass. Most effective with
J
3 interdigitaated gate-cathode geometry.
K dVFÔÔ
Cathode • dt ÔÔÔ significantly increased.
shorting max
structure cathode
short K G
N
+
N+ N+ N
+
N-
P+
A
Thyristor Gate Trigger Requirements
V
G trigger maximum gate
K circuit load power
line dissipation Equivalent circuit of
minimum
V
G temperature
G SCR drive circuit
RG
maximum
V +
temperature G
G
I
I I V G
minimum G G G
trigger 1 2 R
GG
current
i (t)
G
Gate current must be on for a specified

minimum time interval (few tens of
microseconds) to guarantee SCR turn-on

Lecture Notes
Gate Turn-off Thyristors (GTOS)
OUTLINE
• GTO construction and I-V characteristics.

• Physical operation of GTOs.
• Switching behavior of GTOS
Copyright © by John Wiley & Sons 2003 GTOs - 1

GTO (Gate Turn-off Thyristor) Construction
gate
metallization cathode
• Unique features of the GTO. metallization
copper cathode
• Highly interdigitated gate- contact plate
cathode structure (faster
switching)
• Etched cathode islands

(simplify electrical contacts)
• Anode shorts (speed up

turn-off) N+ N+
P
• GTO has no reverse blocking
N-
capability because of anode
shorts P+ N+ P+ N+ P+
• Otherwise i-v characteristic the anode

anode J3 J1 J2
same as for standard SCR shorts
anode
GTO circuit symbol

gate
cathode

GTO Turn-off Gain
I
A • Large turn-off gain requires a2 ≈ 1, a1 << 1
Q
1 • Make a1 small by
I'
Q G 1. Wide n1 region (base of Q1) - also needed
2
for large blocking voltage
2. Short lifetime in n1 region to remove excess
carriers rapidly so Q1 can turn off
• Turn off GTO by pulling one or both of the BJTs out • Short lifetime causes higher on-state losses
of saturation and into active region.
• Anode shorts helps resolve lifetime delimma
• Force Q2 active by using negative base current IG ’ to 1. Reduce lifetime only moderately to keep
IC2 on-state losses reasonable
make IB2 <
b2 2. N+ anode regions provide a sink for
excess holes - reduces turn-off time
• IB2 = a1 IA - I'G ; IC2 = (1 - a1 ) IA
• Make a2 ≈ unity by making p2 layer
(1!-!a1)!IA ! (1!-!a1)!(1!-!a2)!IA ! relatively thin and doping in n2 region
• a1 IA - I'G < = heavily (same basic steps used in making
b2 a2
beta large in BJTs).
IA ! a2
• I'G < ; boff = = turn-off gain • Use highly interdigitated gate-cathode
boff (1!-!a1!-!a2)
geometry to minimize cathode current
crowding and di/dt limitations.
Maximum Controllable Anode Current
K
G N+ G
• Large negative gate current creates

shrinking lateral voltage drops which must be
plasma kept smaller than breakdown voltage
of J3.
P
• If J3 breaks down, it will happen at
N
gate-cathode periphery and all gate
current will flow there and not sweep
G K out any excess carriers as required to
turn-off GTO.
N+
• Thus keep gate current less than
IG,max and so anode current restricted
IG,max
P
by IA <
boff

GTO Step-down Converter
• GTO used in medium-to-high power applications I

where electrical stresses are large and where other D o
solid state devices used with GTOs are slow e.g. free- f
wheeling diode D F.
+
• GTO almost always used with turn-on and turn-off

snubbers. V
d R
s
1. Turn-on snubber to limit overcurrent from D F
reverse recovery.
D
L s
2. Turn-off snubber to limit rate-of-rise of voltage - s
to avoid retriggering the GTO into the on-state.
C
s
• Hence should describe transient behavior of GTO in
circuit with snubbers.

GTO Turn-on Waveforms
IG • GTO turn on essentially the same as for a

iG standard thyristor
M t
I "backporch" • Large I GM and large rate-of-rise insure all
t GT
d current cathode islands turn on together and have
good current sharing.
i
A
tw • Backporch current I GT needed to insure all
1 t cathode islands stay in conduction during

entire on-time interval.
v • Anode current overshoot caused by free-

A wheeling diode reverse recovery current.
K t
• Anode-cathode voltage drops precipitiously
v
GK because of turn-on snubber
t

GTO Turn-off Waveforms
iG
• ts interval
t Time required to remove sufficient stored charge to
IG approximate
bring BJTs into active region and break latch condition
T waveform
for analysis
• tfi interval
purposes 1. Anode current falls rapidly as load current
ttail commutates to turn-off snubber capacitor
Io 2. Rapid rise in anode-cathode voltage due to stray
i
inductance in turn-off snubber circuit
A t
• tw2 interval
t
fi 1. Junction J3 goes into avalanche breakdown because
ts V
dv dv d of inductance in trigger circuit. Permits negative gate
<
dt dt current to continuing flowing and sweeping out
tg max
charge from p2 layer.
q
2. Reduction in gate current with time means rate of
v anode current commutation to snubber capacitor
A t
K slows. Start of anode current tail.
approximate waveform
for analysis purposes
• ttail interval
v
G 1. Junction J3 blocking, so anode current = negative
V t
K tw GG gate current. Long tailing time required to remove
2 - remaining stored charge.
2. Anode-cathode voltage growth governed by turn-off
snubber.
3. Most power dissipation occurs during tailing time.
Lecture Notes
Insulated Gate Bipolar Transistors (IGBTs)
Outline
• Construction and I-V characteristics
• Physical operation
• Limitations and safe operating area
• PSPICE simulation models
Copyright © by John Wiley & Sons 2003 IGBTs - 1

Multi-cell Structure of IGBT
• IGBT = insulated gate bipolar transistor.

contact to source
emitter
diffusion
conductor
field
oxide
gate
oxide
gate
width
N+ N+ N+ N+
P
N-
P
buffer layer
N+ (not essential)
P+ collector
metallization
gate
conductor

Cross-section of IGBT Cell
gate
emitter
SiO
2 + +
J N N
3 P
Ls
J
2
N-
+
N
P+
J - Unique feature of IGBT collector

1 Buffer layer
Parasitic thyristor (not essential)
• Cell structure similar to power MOSFET (VDMOS) cell.

• P-region at collector end unique feature of IGBT compared to MOSFET.
• Punch-through (PT) IGBT - N+ buffer layer present.
• Non-punch-through (NPT) IGBT - N+ buffer layer absent.

Cross-section of Trench-Gate IGBT Unit Cell
Emitter
boddy-source short
Oxide
N+ N+
Gate
Channel
• Non-punch-thru IGBT
P conductor P
length
Parasitic
ID N- ID
SCR
P+
Collector
Emitter
boddy-source short
Oxide
N+ N+
Gate
Channel
P conductor P
length • Punch-thru IGBT
Parasitic
I N- ID
SCR D
N+
P+
Collector

IGBT I-V Characteristics and Circuit Symbols
increasing V
i GE
C i
v C
GE4
• No Buffer Layer
v GE3
VRM ≈ BV
CES
v
• With Buffer Layer
v V GE
GE2 GE(th)
V ≈0 v GE1
RM • Transfer curve
v
CE
V BV
RM • Output characteristics CES
drain collector
gate
gate
• N-channel IGBT circuit symbols
source
emitter

Blocking (Off) State Operation of IGBT
gate
emitter
SiO
2 + +
J N N
3 P
Ls
J
2
N-
+
N
P+
J - Unique feature of IGBT collector Buffer layer

1 (not essential)
Parasitic thyristor
• Blocking state operation - VGE < VGE(th) • With N+ buffer layer, junction J1 has
• Junction J2 is blocking junction - n+ drift small breakdownvoltage and thus IGBT
region holds depletion layer of blocking has little reverse blocking capability -
junction. anti-symmetric IGBT
• Without N+ buffer layer, IGBT has large

• Buffer layer speeds up device turn-off
reverse blocking capability - so-called
symmetric IGBT

IGBT On-state Operation
gate
emitter
+ +
N N
P • MOSFET section designed

lateral (spreading)
N-
to carry most of the IGBT
resistance
+
collector current
N
+ + + + P+ + + + +
collector • On-state VCE(on) =

VJ1 + Vdrift + ICRchannel
gate
emitter
+ +
N N
P • Hole injection into drift

N-
region from J1 minimizes
N
+
Vdrift.
+
P
collector

Approximate Equivalent Circuits for IGBTs
Conduction path resulting collector

drift region
resistance in thyristor turn-on (IGBT
V latchup) if current in this
V J1
drift path is too large
gate
I R gate
C channel
Principal
(desired) Body region
path of spreading
resistance
• Approximate equivalent circuit for collector
IGBT valid for normal operating current emitter
conditions.
• IGBT equivalent circuit showing
• VCE(on) = VJ1 + Vdrift + IC Rchannel transistors comprising the parasitic
thyristor.
Static Latchup of IGBTs
lateral (spreading)
resistance gate
J emitter
3
+ +
N N
J2 N-
+
N
J1
+ + + P+ + + + +
collector
Conduction paths causing lateral voltage drops and turn-on
of parasitic thyristor if current in this path is too large
• Lateral voltage drops, if too large, will forward bias junction J3.
• Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor.
• Large power dissipation in latchup will destroy IGBT unless terminated quickly.
External circuit must terminate latchup - no gate control in latchup.

Dynamic Latchup Mechanism in IGBTs
J emitter gate
3
+ +
N N
J2 P
lateral
(spreading) expansion of
resistance N- depletion region
+
N
J1
+
P
collector
• MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into
N- layer, the base region of the pnp BJT.
• Expansion of depletion layer reduces base width of pnp BJT and its a increases.
• More injected holes survive traversal of drift region and become “collected” at junction J2.
• Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and
latchup soon occurs.
• Manufacturers usually specify maximum allowable drain current on basis of dynamic
latchup.

Internal Capacitances Vs Spec Sheet Capacitances
C gc C
bridge
G C
+V -
C ge C ce b
E C gc
Bridge balanced (Vb=0) Cbridge = C gc = C res
G C
G C
C ies
E
C oes
C ies = C g e + C gc E
C oes = C gc + C ce

IGBT Turn-on Waveforms
v (t) V
GE GG+
• Turn-on waveforms for
IGBT embedded in a t
stepdown converter.
• Very similar to turn-on t

waveforms of MOSFETs. d(on)
Io
• Contributions to tvf2. i (t)
C
t
• Increase in Cge of t
ri
MOSFET section at low
collector-emitter
V
voltages. V C E(on)
DD
• Slower turn-on of pnp v (t)
CE
BJT section. t fv1 t
t fv2

IGBT Turn-off Waveforms
• Turn-off waveforms for IGBT
V embedded in a stepdown
GE(th V
GG- converter.
v (t) )
GE
t • Current “tailing” (tfi2) due to
stored charge trapped in drift
region (base of pnp BJT) by rapid
turn-off of MOSFET section.
t
fi2 MOSFET
current • Shorten tailing interval by either
t d(off)
reducing carrier lifetime or by
BJT
i (t)
t current putting N+ buffer layer adjacent to
C rv t
t injecting P+ layer at drain.
fi1
• Buffer layer acts as a sink for

excess holes otherwise trapped
V
DD in drift region becasue lifetime in
t buffer layer can be made small
v (t) without effecting on-state losses -
CE
buffer layer thin compared to drift
region.
IGBT Safe Operating Area
• Maximum collector-emitter
i voltages set by breakdown
C
voltage of pnp transistor -
2500 v devices available.
-5
10 sec
-4
10 sec • Maximum collector current set
FBSOA
by latchup considerations - 100
DC A devices can conduct 1000 A
v for 10 µsec and still turn-off
CE
dv via gate control.
i re-applied CE
C
dt
1000 V/ ms
• Maximum junction temp. = 150 C.
2000 V/ ms
RBSOA • Manufacturer specifies a

3000 V/ m s
maximum rate of increase of
v re-applied collector-emitter
CE
voltage in order to avoid latchup.

Development of PSpice IGBT Model
Cm
gate
source Coxs
Coxd
+ +
N N
Cgdj
P
Ccer Cdsj
Drain-body or N-
+ Rb
base-collector N
Cebj + Cebd
depletion layer
P+
drain
• Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer. • Reference - "An
Experimentally Verified
• Nonlinear capacitor Cebj + Cebd due to P+N+ junction IGBT Model
Implemented in the
• MOSFET and PNP BJT are intrinsic (no parasitics) devices SABER Circuit
Simulator", Allen R.
• Nonlinear resistor Rb due to conductivity modulation of N- drain drift region of Hefner, Jr. and Daniel
MOSFET portion. M. Diebolt, IEEE Trans.
on Power Electronics,
• Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N-P junction). Vol. 9, No. 5, pp. 532-
542, (Sept., 1994)
• Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.

Parameter Estimation for PSpice IGBT Model
• Built-in IGBT model requires nine parameter values.
• Parameters described in Help files of Parts utility program.
• Parts utility program guides users through parameter estimation process.

• IGBT specification sheets provided by manufacturer provide sufficient
informaiton for general purpose simulations.
• Detailed accurate simulations, for example device dissipation studies, may
require the user to carefully characterize the selected IGBTs.
Drain
Cebj +
Cgdj Cebd • Built-in model does not model
Ccer ultrafast IGBTs with buffer
Coxd Rb
layers (punch-through IGBTs) or
Gate Cdsj reverse free-wheeling diodes
Cm +
Coxs
Source
PSpice IGBT - Simulation Vs Experiment
0V 5V 10 V 15 V 20 V 25 V
1
nF
Data from IXGH40N60 spec sheet
Simulated C versus V CE
GC
0.75
nF for IXGH40N60
V =0V
GE
0.5
nF
0.25
nF
0
100 V 200 V 300 V 400 V 500 V
Collector - emitter Voltage

Lecture Notes
Emerging Devices
Outline
• Power JFET Devices

• Field-Controlled Thyristor
• MOS-Controlled Thyristor
• High Voltage Integrated Circuits/ Discrete Modules
• New Semiconductor Materials
Copyright © by John Wiley & Sons 2003 Emerging Devices - 1

Power JFET Geometry
N-channel JFET
gate
source
D
+ + +
N N N
lgs
+ + G
P P lc
Recessed gate
JFET - w channel
cross-section. N
l gd S
+
N
P-channel JFET
drain
• Gate-source geometry highly interdigitated as in MOSFETs.
• Width w = µms to a few tens of µms ; lc < w ; lgs minimized. G
• lgd set by blocking voltage considerations.

S

Power JFET I-V Characteristics
Output characteristics
VGS Transfer curve.
iD
VGS1 VGS2 VGS3 VGS4 v
D
S
blocking
gain µ
vD VGS
S
• Power JFET is a normally-on device. Substantial current flows when gate-

source voltage is equal to zero.
• Opposite to BJTs, MOSFETs, and IGBTs which are normally-off devices.

Controlling Potential Barrier in JFETs
electron • |VGS| > |Vp| (pinchoff voltage)

V =0
potential DS potential barrier to electron flow
-V (x)
CS x from source to drain created. No
drain current can flow.
increasing V
DS • Suppress potential barrier by
increasing VDS at fixed VGS.
When VDS > µ |VGS| substantial
- + drain currents flow.
V
DD
+
• Blocking capability limited by
P magnitude of electric field in drift
E
GS region. Longer drift regions have
larger blocking voltage capability.
V (x) N D
S CS
E • Normally-off JFET created by
+ DS
V
GG
having narrow enough channel
-
N P+ width so that the channel is pinched
off at zero gate-source voltage.
G

JFET On and Off States
JFET in on-state
JFET in blocking state
D D
depletion depletion region
region
+ +
VD D
VD D -
P+
N P+ P+
- P+
G G
S + -
S VGG
• Channel open between drain and source. • Channel pinched-off (closed) between
drain and source.

Bipolar Static Induction Transistor (BSIT)
BSIT in blocking state JFET in on-state
D
D
depletion region
depletion
region
+
V +
DD
-
P+ P+ VD D
N
- P+ P+
G
S
- G
S +
V
GG
• Channel width and channel doping chosen
so that at zero gate-source voltage, • Forward bias gate-channel junction to
depletion layers of gate-channel junction reduce depletion region width and open up
pinch-off the channel. channel.
• Narrower channel than normally-on JFET. • Substantial current flow into gate.

JFET Switching Characteristics
• Equivalent circuits of JFETS nearly identical to those of MOSFETs
• Switching waveforms nearly identical to those of MOSFETs including values of

various switching time intervals
• JFET VGS starts at negative values and steps to zero at turn-on while MOSFET VGS starts
at zero and steps to positive value at turn-on
• FET on-state losses somewhat higher than for MOSFET - technology related not fundamental
• Normally-off JFET (Bipolar static induction transistor or BSIT) switching characteristics

more similar to those of BJT
• Differences between BSIT and BJT observable mainly at turn-off
1. BSIT has no quasi-saturation region and thus only one current fall time (no current tailing) at
turn-off.
2. Overall turn-off times of BSIT shorter than for BJT
3. Differences due to fact that BSIT has no in-line pn junction that can block sweep-out of
excess carriers as does BJT

Field-Controlled Thyristor (FCT)
Vertical Cross-section Circuit symbol
cathode anode
gate
+ +
+ N + N
P P
gate
N-
cathode
+
P
Injecting contact - anode

unique feature of FCT
• Sometimes termed a bipolar static induction thyristor (BSIThy).

FCT I-V Characteristics
iA
V
GK
• FCT has a normally-on
V V V characteristic.
GK1 GK2 GK3
• Can be made to have a
FCT output characteristics
normally-off
characteristic.
1. Reduce channel
width so that zero-bias
-V
RM
depletion layer width
V
AK of gate-channel
junction pinches off
V
AK
channel
2. Then termed a
blocking gain m Transfer curve bipolar static induction
thyristor (BSIThy).
V
GK

Physical Operation of FCT
• FCT essentially a power JFET with an injecting contact at • Cascode switching
the drain circuit.
• Implement a normally-
off composite switch.
• Injecting contact causes conductivity modulation of drain
drift region and results in much lower on-state losses • R1 and R2 insure that
voltage across
MOSFET not overly
• At turn-off, gate draws large negative current similar to a large. Permits use of
GTO because of stored charge in drift region low voltage-high
current device.
HV
• FCT not a latching switch as is a GTO. FCT has no
regenerative action.
R1
• FCT can be made a normally-off device by using narrow

channel widths so that zero-bias width gate depletion layer
pinchs off channel. R2
Vcontrol
R1 >> R2 ≈ 1-10 Meg

FCT Switching Characteristics
• FCT switching waveforms qualitatively similar to thyristor or GTO
including large negative gate current at turn-off.
• FCT has gate-controlled turn-on and turn-off capabilities similar to GTO.
• FCT switching times somewhat shorter than GTO.
• Gate drive must be continuously applied to FCT because FCT has no

latching characteristic.
• FCT has much larger re-applied dv/dt rating than GTO because of lack of
latching action.
• FCT hasdi/dt limits because of localized turn-on and then expansion of

turned-on region across entire device cross-section.
JFET-Based Devices Vs Other Power Devices
• Blocking voltage capability of JFETs comparable to BJTs and MOSFETs.
• JFET on-state losses higher than MOSFETs - technology limitation.
• Switching speeds of normally-on JFET somewhat slower than those of MOSFET - technology
limitation.
• BSIT switching times comparable to BJTs - in principle should be faster because of lack of in-
line pn junction trapping stored charge at turn-off.
• No second breakdown in normally-on JFETs, similar to MOSFETs.
• BSITs and BSIThy have and possibly limitations.
• JFET-based power devices much less widely used because of normally-on characteristic. This
has also slowed research and development efforts in these devices compared to other devices.
P-MCT (P-type MOS-controlled Thyristor
Unit cell vertical cross-section
SiO 2
A conductor
• Complete MCT composed of
tens of thousands of identical
cells connected in parallel.
G G
+ +
N N
P+ • P-designation refers to doping
P P of the lightly-doped P- layer
ON-FET which contains the depletion
ON-FET channel layer of the blocking junction.
channel N
OFF-FET
channels
P-
• Note that ON and OFF FETs
are positioned at the anode end
+
N of the device.

P-MCT Equivalent Circuit & Circuit Symbol
P-MCT equivalent circuit P-MCT circuit symbol
anode
anode
i
A
+
gate
v
gate AK
OFF-FET ON-FET
-
cathode
cathode
• P-MCT used with anode grounded.
• Gate-anode voltage is input drive voltage.
• Use P-MCT in circuits with negative voltages.

N-MCT (N-type MOS-controlled Thyristor
Vertical cross-section of N-MCT unit cell

• N-MCT composed of
SiO 2 thousands of cells
K conductor
connected electrically in
parallel.
• N-designation refers to the

G G N- layer which contains the
+ +
P P depletion layer of the
blocking junction.
+
N-
-
N N
ON-FET
ON-FET channel
channel P
OFF-FET
channels • Note that the ON and OFF
FETs are positioned at
N- the cathode end of the
P+ device.

N-MCT Equivalent Circuit & Circuit Symbol
N-MCT equivalent circuit N-MCT circuit symbol
anode
anode
ON-FET
OFF-FET gate
gate
cathode
cathode
• N-MCT used with cathode grounded.
• Gate-cathode voltage is input drive voltage.
• Use N-MCT in circuits with positive voltages.

Gate-controlled Turn-on of MCTs
• Turn on MCT by turning on the ON-FET

• Positive gate-cathode voltage for N-MCT
• Negative gate-anode voltage for P-MCT
• These polarities of gate voltage automatically keep the OFF-FET in cutoff.
• ON-FET delivers base current to the low-gain BJT in the thyristor equivalent circuit
and activates that BJT.
• PNP transistor in the N-MCT
• NPN transistor in the P-MCT
• Low-gain transistor activates the higher gain transistor and thyristor latches on.
• Once higher gain transistor, which is in parallel with ON-FET is activated, current
is shunted from ON-FET to the BJT and the ON-FET carries very little current in
the MCT on-state.
• Only 5-10% of the cells have an ON-FET.
• Cells are close-packed. Within one excess carreier diffusion length of each other.
• Adjacent cells without an ON-FET turned on via diffusion of excess carriers from
turned-on cell.
Gate-controlled Turn-off of MCTs
• Turn MCT off by turning on the OFF-FET
• Negative gate-cathode for the N-MCT
• Positive gate-anode voltage for the P-MCT
• These gate voltage polarities automatically keep the ON-FET in cut-off.
• OFF-FET shunts base current away from the higher gain BJT in the thyristor
equivalent circuit and forces it to cut-off.
• NPN transistor in the N-MCT.
• PNP transistor in the P-MCT.
• Cut-off of higher gain BJT then forces low-gain BJT into cut-off.
• Every MCT cell has an OFF-FET.
• OFF-FET kept activated during entire MCT off-state to insure no inadvertent

activation of the thyristor.
Maximum Controllable Anode Current
• If drain-source voltage of OFF-FET reaches approximately 0.7 V during turn-off,

then MCT may remain latched in on-state.
• Higher-gain BJT remains on if OFF-FET voltage drop, which is the base-emitter

voltage of the BJT reaches 0.7 volts.
• Thus maximum on-state current that can be turned off by means of gate control.
• P-MCT have approximately three times larger gate-controlled anode current

rating than a similar (same size and voltage rating) N-MCT.
• OFF-FET of the P-MCT is an n-channel MOSFET which has three times larger
channel mobility than the p-channel OFF-FET of the N-MCT.

Rationale of OFF-FET Placement
• Turning off the BJT with the larger P-MCT cross-section showing
value of a most effective way to rationale for OFF-FET placement
break the latching condition
a1 + a2 = 1 A
G
• BJT with the smaller base width has
the larger value of a.
N+ N+
• P-MCT ; PNP BJT has smaller base
P+
width P P
• N-MCT ; NPN BJT has smaller OFF-FET OFF-FET
base width
N
• OFF-FET put in parallel with base-
emitter of larger gain BJT so that P- Wider of two base regions
OFF-FET shorts out base-emitter
N+
when the FET is activated.
K

MCT Switching Waveforms
Gate-cathode
voltage N-MCT Step-down Converter
V
Tn
+ I
o
V
Tp t
V
d
t
t
fv1 d,off N-MCT
Anode-cathode
voltage t
fv2
t
rv1 -
V
d
P-MCT Step-down Converter
t
rv2
t - Io
Anode
current
I
o V
d
P-MCT
+
t ri2 t
fi1 t
t
d,on
t ri1
Copyright © by John Wiley & Sons 2003 t
fi2
Emerging Devices - 21
MCT Turn-on Process
• Turn-on delay time td,on - time required for gate voltage to reach ON-FET threshold
starting from reverse-bias value of VGG,off
• Current rise time tri1 and tri2

• tri1 ; ON-FET turns on accepting all the current the gate drive voltage will permit.
ON-FET in its active region.
• tri2 ; NPN and PNP BJTs turn on and current shunted away from ON-FET. BJTs
and ON-FET in their active regions.
• Voltage fall time tfv1 and tfv2

• tfv1 ; BJTs in their active regions so voltage fall initially fast.
• tfv2 ; BJTs in quasi-saturation, so their gain is reduced and rate of voltage fall
decreases.
• At end of voltage fall time interval, BJTs enter hard saturation and MCT is in
the on-state.
• Gate-cathode voltage should reach final on-state value in times no longer than a
specified maximum value (typically 200 nsec). Insure that all paralleled cells turn on
at the same time to minimize current crowding problems.
• Keep gate-cathode at on-state value for the duration of the on-state to minimize
likelyhood of inadvertant turn-off of some cells if current is substantially reduced
during on-state.

MCT Turn-off Process
• Turn-off delay time td,off - time required to turn-off the ON-FET, activate the OFF-
FET, and break the latching condition by pulling the BJTs out of hard saturation
and into quasi-saturation.
• Requires removal of substantial amount of stored charge, especially in the base
regions of the two BJTs (n1 and p2 thyristor layers).
• Voltage rise times trv1 and trv2

• trv1 ; time required to remove sufficient stored charge so that BJTs leave quasi-
saturation and enter active region and blocking junction (J2) becomes reverse-
biased.
• trv2 ; BJTs in active region and their larger gain causes anode voltage to rapidly
complete growth to power supply voltage Vd
• Current fall time tfi1 and tfi2

• tfi1 ; Initial rapid fall in current until high gain BJT (NPN BJT in the P-MCT
equivalent circuit) goes into cutoff.
• tfi2 ; stored charge still remaining in base (drift region of thyristor) of the
low-gain BJT removed in this interval. The open-base nature of the turn-off
casuses longer time interval giving a "tail" to the anode current decay.
• Gate-cathode voltage kept at off-state value during entire off-state interval to

prevent accidental turn-on.

MCT Operating Limitations
• Imax set by maximum controllable anode current. • MCT safe operating area. Very
Presently available devices have 50-100 A ratings. conservatively estimated.
• Vmax set by either breakover voltage of thyristor

section or breakdown rating of the OFF-FET. Anode
Presently available devices rated at 600 V. 1000-2000 current
v devices prototyped. I
max
dvDS
• dt limited by mechanisms identical to those in
thyristors. Presently available devices rated at 500-
1000 V/sec.
diD
• dt limited by potential current crowding problems.
Anode-cathode voltage V
Presently available devices rated at 500 A/sec. BO

High Voltage (Power) Integrated Circuits
• Three classes of power ICs
1. Smart power or smart/intelligent switches

• Vertical power devices with on-chip sense and protective features and
possibly drive and control circuits
2. High voltage integrated circuits (HVICs)

• Conventional ICs using low voltage devices for control and drive
circuits and lateral high voltage power devices
3. Discrete modules
• Multiple chips mounted on a common substrate. Separate chips for
drive, control, and power switch and possibly other functions.
• PIC rationale
• Lower costs
• Increased functionality
• Higher reliability
• Less circuit/system complexity

Issues Facing PIC Commercialization
• Technical issues
• Electrical isolation of high voltage devices from low voltage components
• Thermal management - power devices generally operate at higher

temperatures than low power devices/circuits.
• On-chip interconnections with HV conductor runs over low voltage

devices/regions.
• Fabrication process should provide full range of devices and components

- BJTs, MOSFETs, diodes, resistors, capacitors, etc.
• Economic issues
• High up-front development costs
• Relative cost of the three classes of PICs
• Need for high volume applications to cover development

expenses.

Dielectric Isolation
Si0 2 S G D E B
+
N N+ N
+
P
• Dielectrically isolated tubs -
P SiO2 isolation and silicon
N -
thin film overgrowth.
N+
Si wafer Si wafer
SiO
2
Si wafer with SiO 2
Si wafer with SiO 2
Wafers bonded together
A metallurgically C
• Wafer bonding and
subsequent wafer
Top Si wafer thinned
Si wafer thinning.
for circuit fabrication
Si wafer with SiO 2

Si wafer with SiO 2
Bottom wafer
Clean, flat surfaces
dielectrically isolated
contacted at elevated
from top thin Si film
temperatures under
pressure B D

Self-Isolation and Junction Isolation
Lateral Logic
Lateral HV MOSFET Level MOSFET
D G S D G S
+
• Self-isolation - only feasible
N N- N
+
N
+
N
+
P P with MOSFET devices.
P - substrate
isolated regions
+ -
N + +
P N P N
• Junction isolation.
parasitic
P diode

High-Voltage Low-Voltage Cross-overs
Electric field lines
Metal at +V
SiO 2
+
N
N -
N-
P+ • Field-crowding and
premature breakdown.
depletion
layer
P- @ -V
Poly-silicon
field shield Metal at +V
SiO 2
+
N
N -
N - P
+ • Use of field shields to
minimize field crowding
depletion problems at HV/LV
layer
cross-overs.
P - @ -V

Smart or Intelligent Switch Using MOSFETs
Lateral Logic
Vertical Power MOSFET Level MOSFET
G S Diode
S G S D
• Cross-sectional
diagram of switch.
+ + + + + +
N N N N N N
P P P P
-
N
+
N
D
• Add additional components on vertical
• Circuit diagram MOSFET wafer as long as no major
process changes required.
Diode
• PN junction formed from N- drift region
and P-body region always reverse-biased
if drain of power MOSFET positive
respect to source. Provides electrical
Power Lateral Logic
MOSFET Level MOSFET
isolation of the two MOSFETs.

Smart Power Switch Using BJTs
Vertical Power Lateral Logic Lateral Logic
NPN BJT Level NPN BJT Level PNP BJT
E B E E B C E C B
+ + + + P P +
N N N N N
P + P +
P - P - Cross-sectional view
- N epi N epi
N epi
+ +
N N
+
N P-epi
+
N
C • Three electrically isolated BJTs diagramed

• PN junction isolation via P-epi and top-side P+ diffusion
• Double epitaxial process squence

• P-epi grown on N+ substrate
• N+ buried layer diffused in next
• N-epi for drift region grown over P-epi
• P+ isolation diffusions to P-epi
• Diffusion for base and emitters of BJTs

High Voltage Integrated Circuits (HVICs)
Lateral HV Lateral Logic Lateral Logic

DMOSFET Level NPN BJT Level PNP BJT
D G S E B C E C B
N+ N+ N+ P P N+ HVIC using
P+ P P+ P N
+
P
+
N - epi -
N epi N - epi junction isolation
N+ N+
P-substrate
Lateral HV Lateral Logic Lateral Logic

N-channel Level N-MOSFET Level P-MOSFET
DMOSFET
S G D S G D
D G S
N+ N - P N
+ N+ N+ P
+
P
+
P+ P
N HVIC using self-
isolation
P- substrate

Discrete Module Example - IXYS I3M IGBT Module
• Intelligent isolated half-bridge
• 200 A - 1080 V
• Built-in protection and sensing of
overcurrents, overvoltages,
overtemperatures, short circuits.
• Modules with only IGBTs and anti-
parallel diodes available with
ratings of 3300V - 1200A

IGCT - Integrated Gate Commutated Thyristor
Turn-on
Q1
C1 Cn
Qn
10V - 5A
GCT Gate
Control
Q1 Qn
20V - 6 A
C1 C2 Cn
• Specially designed GTO with low 50,000 µF

inductance gate drive circuit GCT Cathode
Turn-off
• Ratings
• Blocking voltage - 4500V • Approximate gate drive circuit
• Controllable on-state current - 4000A • Ion ≈ 500 A 10µsec
• Average fwd current - 1200A
• Ioff - full forward current 10 usec
• Switching times - 10µsec
• Very low series inductance - 3 nH
Emitter Turn-off Thyristor
Q1
C1 Cn
Qn
10V - 5A
GTO or GCT
Control
Qn
Qn
Q1
Q1
• Performance similar to IGCTs

• Advantages over IGCTs
• Simpler drive circuit
• Easier to parallel - MOSFETs in series with GTO
have positive temperature coefficient
• Series MOSFETs can be used for overcurrent sensing

Economic Considerations in PIC Availability
• PIC development costs (exclusive of production costs)
• Discrete modules have lower development costs
• Larger development costs for smart switches and HVICs
• Production costs (exclusive of development costs) of smart switches and

HVICs lower than for discrete modules.
• Reliability of smart switches and HVICs better than discrete modules.

• Greater flexibility/functionality in discrete modules
• Wider range of components - magnetics, optocouplers
• PICs will be developed for high volume applications

• Automotive electronics
• Telecommunications
• Power supplies
• Office automation equipment
• Motor drives
• Flourescent lighting ballasts

Summary of Silicon Power Device Capabilities
Vo f f
Thyristors
5 kV
4 kV GTOs, IGCTs, ETOs
3 kV
MCT
s Io
IGBT
2 kV n
s
BJTs
1 kHz
1 kV 10 kHz
MOSFET
100 kHz
s
1 MHz
500 A 1000 A 1500 A 2000 A 3000 A
Frequency

New Semiconductor Materials for Power Devices
• Silicon not optimum material for power devices
• Gallium arsenide promising material

• Higher electron mobilities (factor of about 5-6) - faster switching speeds
and lower on-state losses
• Larger band-gap Eg - higher operating temperatures
• Silicon carbide another promising materials

• Larger bandgap than silicon or GaAs
• Mobilities comparable to Si
• Significantly larger breakdown field strength
• Larger thermal conductivity than Si or GaAs
• Diamond potentially the best materials for power devices
• Largest bandgap
• Largest breakdown field strength
• Largest thermal conductivity
• Larger mobilities than silicon but less than GaAs
Properties of Important Semiconductor Materials
Property Si GaAs 3C-SiC 6H-SiC Diamond
Bandgap @ 300 °K [ev ] 1.12 1.43 2.2 2.9 5.5
Relative dielectric 11.8 12.8 9.7 10 5.5

constant
Saturated drift 1x107 2x107 2.5x107 2.5x107 2.7x107

velocity [cm/sec]
Thermal conductivity 1.5 0.5 5.0 5.0 20

[Watts/cm-°C]
Maximum operating 300 460 873 1240 1100

temperature [°K]
Intrinsic carrier 1010 107 - - -

density [cm-3] @ 25 °C
Melting temperature [°C] 1415 1238 Sublime Sublime Phase

>1800 >1800 change
Electron mobility 1400 8500 1000 600 2200

@ 300 °K [cm2/V-sec]
Breakdown electric 2-3x105 4x105 2x106 2x106 1x107

field [V/cm]

On-State Resistance Comparison with Different Materials
• Specific drift region resistance of majority carrier device
4"q"(BVBD)2
• Ron•A ≈
e"mn"(EBD)3
• Normalize to silicon - assume identical areas and breakdown

voltages
Ron(x)"A eSi"mSi ÈE ˘3
Í BD,Si˙
Ron(Si)"A = resistance ratio = ex"mx ÍE ˙
Î BD,x ˚
• Numerical comparison
Material Resistance Ratio
Si 1
GaAs 6.4x10-2
SiC 9.6x10-3
Diamond 3.7x10-5

Material Comparison: PN Junction Diode Parameters
• Approximate design formulas for doping density and drift region length of HV pn
junctions
• Based on step junction P+N-N+ structure
e"[EBD]2
• Nd = drift region doping level ≈ 2"q"BV
BD
2"BVBD
• Wd = drift region length ≈ E
BD
• Numerical comparison - 1000 V breakdown rating
Material Nd Wd
Si 1.3x1014 cm-3 67 µm
GaAs 5.7x1014 50
SiC 1.1x1016 10
Diamond 1.5x1017 2

Material Comparison: Carrier Lifetime Requirements
• Drift region carrier lifetime required for 1000 V pn junction diode
• Approximate design formula based on step junction
q"Wd2 4"q"[BVBD]2
t ≈ k"T"m =
n k"T"mn"[EBD]2
• Numerical comparison
Material Lifetime
Si 1.2 µsec
GaAs 0.11 µsec
SiC 40 nsec
Diamond 7 nsec
• Shorter carrier lifetimes mean faster switching minority carrier

devices such as BJTs, pn junction diodes, IGBTs, etc.

Recent Advances/Benchmarks
• Gallium arsenide
• 600V GaAs Schottky diodes announced by Motorola. 250V available from IXYS
• 3” GaAs wafers available
• Silicon carbide
• 3” wafers available from Cree Research - expensive
• 600V -6A Schottky diodes available commercially - Infineon Technologies AG (Siemens spinoff)
• Controlled switches also demonstrated
• 1800V - 3A BJT with beta of 20
• 3100V - 12A GTO
• Diamond
• Polycrystalline diamond films of several micron thickness grown over large (square
centimeters) areas
• Simple device structures demonstrated in diamond films.
• PN junctions
• Schottky diodes

Projections
• GaAs
• Devices such as Schottky diodes which are preesently at or near
commercial introduction will become available and used.
• GaAs devices offer only incremental improvements in performance over
Si devices compared to SiC or diamond.
• Broad introduction of several types of GaAs-based power devices
unlikely.
• SiC
• Rapid advances in SiC device technology
• Spurred by the great potential improvement in SiC devices compared to
Si devices.
• Commercially available SiC power devices within 5-10 years.
• Diamond
• Research concentrated in improving materials technology.
• Growth of single crystal material
• Ancilliary materials issues - ohmic contacts, dopants, etc.
• No commercially available diamond-based power devices in the
forseeable future (next 10-20 years).

Lecture Notes
Snubber Circuits
Outline
A. Overview of Snubber Circuits
B. Diode Snubbers
C. Turn-off Snubbers
D. Overvoltage Snubbers
E. Turn-on Snubbers
F. Thyristor Snubbers
Copyright © by John Wiley & Sons 2003 Snubbers - 1

Overview of Snubber Circuits for Hard-Switched Converters
Function: Protect semiconductor devices by: Types of Snubber Circuits
• Limiting device voltages during turn-off transients

1. Unpolarized series R-C snubbers
• Used to protect diodes and thyristors
• Limiting device currents during turn-on transients
2. Polarized R-C snubbers

• Limiting the rate-of-rise (di/dt) of currents through
• Used as turn-off snubbers to shape the turn-on
the semiconductor device at device turn-on
switching trajectory of controlled switches.
• Used as overvoltage snubbers to clamp voltages
applied to controlled switches to safe values.
• Limiting the rate-of-rise (dv/dt) of voltages across
• Limit dv/dt during device turn-off
the semiconductor device at device turn-off
3. Polarized L-R snubbers

• Shaping the switching trajectory of the device as it
• Used as turn-on snubbers to shape the turn-off
turns on/off
switching trajectory of controlled switches.
• Limit di/dt during device turn-on

Need for Diode Snubber Circuit
di V
Df d
=
d t Ls
+ Ls Io
Rs
Io i Df (t) t
V Df Cs I rr
d
- Sw
v (t) t
Df Vd
• Ls = stray inductance
• S w closes at t = 0 • Diode voltage

di Ls
without snubber Ls
• Rs - Cs = snubber circuit d t
diLs
• Diode breakdown if Vd + Ls > BVBD
dt

Equivalent Circuits for Diode Snubber
Ls
• Simplified snubber -
the capacitive snubber
+ Rs
Ls
Vd Diode cathode
snap-off anode
- + +
Vd v Cs
Cs
-
i Df -
t
• Rs = 0
• Worst case assumption-
diode snaps off instantaneously •v = -v
Cs Df
at end of diode recovery
d2vCs vCs Vd
• Governing equation - + =
dt2 LsCs !LsCs
• Boundary conditions - vCs(0+) = 0 and iLs(0+) = Irr

Performance of Capacitive Snubber
Cbase
• vCs(t) = Vd - Vd cos(wot) + Vd sin(wot)
Cs
È I ˘2
1 Í rr ˙
• wo = ; Cbase = Ls Í ˙
LsCs ÎV d˚
Ï Cbase ¸
• Vcs,max =
Ì
Vd 1!+! 1!+! !
˝
Ó Cs ˛
V 3
Cs,max
Vd
2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
C base
Cs

Effect of Adding Snubber Resistance
Snubber Equivalent Circuit
Ls i(t)
d2i di i
+ - • Governing equation Ls + Rs + =0
Rs dt2 dt C s
V v (t)
d Df • Boundary conditions
Cs di(0+) Vd!-!IrrRs
- + i(0+) = Irr and =
dt Ls
Diode voltage as a function of time
Vdf e-at
Vd (t) = - 1 - h!cos(f)
sin(wat - f + z) ; Rs ≤ 2 Rb
Rs È ˘
1 Í (2-x) h ˙
wa = wo 1-!(a/!wo)2 ; a = 2!L ; wo = -1
; f = tan Í ˙
s LsCs Î 4!-!hx2˚
Cs Rs Vd Ls![Irr]2
h = C ; x = R ; Rb = I ; Cb = 2 ; z = tan-1(a/wa)
b b rr Vd

Performance of R-C Snubber
3
• At t = tm vDf(t) = Vmax
R s,opt
C s = Cbase = 1.3
tan-1(wa/a)
R
f!-!x base
• tm = wa + w ≥0
a 2
Vmax V max
• =1+ 1!+!h-1!-!x exp(-atm)
Vd V
d
Cs Rs 1
• h = and x=
Cbase Rbase
R sI rr
Ls!Irr2 Vd V
d
• Cbase = and Rbase =
0
Vd2 Irr
0 1 Rs 2
R base

Diode Snubber Design Nomogram
Wtot
2
3 L s I r r /2
WR
2
L s I r r /2
2
0
0 V max
for R = R
0 Vd s s,opt
0
00
0 0
0 0
0 0 00
0 00 0 0 0 0 00
1 R s,op
R base
0
0 1 2 3
C s / Cbase

Need for Snubbers with Controlled Switches
Step-down converter Switch current and voltage waveforms
L s di
L1 dt
L2 I rr
Io i
sw
V
d
i L s di V Io
sw + I dt
o d
Sw
vsw
L3
- vsw
to t t t t t6
3 4 5
1
• L1 , L 2 , L 3 = stray inductances
Switching trajectory of switch

• L s = L1 + L 2 + L 3 idealized
i sw switching
t6 t 5 loci
to turn-off
• Overvoltage at turn-off
t1 due to stray inductance
turn-on
• Overcurrent at turn-on due to
diode reverse recovery
t
4 t3 vsw
Vd

Turn-off Snubber for Controlled Switches
Turn-off
D Io snubber
+ i f
DF
V
d Ds Step-down converter with turn-off snubber
S Rs
- w i
Cs Cs
Equivalent circuit during switch turn-off.

Io
Df
• Simplifying assumptions
V 1. No stray inductance.
d
Io - i
sw
i sw 2. isw(t) = Io(1 - t/tfi)
Cs
3. isw(t) uneffected by snubber circuit.

Turn-off Snubber Operation
2
I ot I ot
• Capacitor voltage and current for 0 < t < tfi iCs(t) = and v (t) =
tfi Cs 2C t
s fi
Iotfi
• For Cs = Cs1, vCs = Vd at t = tfi yielding Cs1 =
2Vd
Circuit waveforms for varying values of Cs
i i i
sw sw sw
Io
i i i
Df Df Df
tf i tf i t
fi
i
Cs
V
d
v
Cs
Cs < Cs 1 Cs = Cs 1 Cs > C
s
1

Benefits of Snubber Resistance at Switch Turn-on
vs w
t rr
D Io Io
f
• Ds shorts out Rs
Rs i I rr
during Sw turn-off. D
f
V
d
• During Sw turn-on, Vd
Sw Ds Io
Ds reverse-biased and i sw Rs
Cs Cs discharges thru Rs.
I rr
discharge
• Turn-on with Rs > 0
t rr
of C s
• Energy stored on Cs dissipated
• Turn-on with Rs = 0
in Rs rather than in Sw.
vs w
• Energy stored on Cs dissipated
Io
• Voltage fall time kept quite
V in Sw.
d short.
i sw t ri • Extra energy dissipation in Sw

t
2 because of lengthened voltage
0 t ri + t rr fall time.

Effect of Turn-off Snubber Capacitance
1 Energy dissipation
total Wbase
W /
W
0.8 WR = dissipation in
resistor
0.6
W / Wbase WT = dissipation in
R
0.4
WT / W base
switch Sw
W
0.2
Iotfi
Cs1 =
0 2Vd
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Cs / Cs1
Wtotal = WR + WT
i
sw
Io
Wbase = 0.5 VdIotfi
Cs < Cs1 RBSOA
Cs = Cs1 Switching trajectory

Cs > Cs1
V vs w
d

Turn-off Snubber Design Procedure
Selection of Cs
• Minimize energy dissipation (WT) in BJT at turn-on
• Minimize WR + WT
• Keep switching locus within RBSOA

Snubber recovery time (BJT in on-state)
• Reasonable value is Cs = Cs1
• Capacitor voltage = Vd exp(-t/RsCs)
• Time for vCs to drop to 0.1Vd is 2.3 RsCs
• BJT must remain on for a time of 2.3 RsCs

Selection of Rs
Vd
• Limit icap(0+) = R < Irr
s
Vd
• Usually designer specifies Irr < 0.2 Io so Rs = 0.2 Io

Overvoltage Snubber
Ls
kV
+ d
D R i
f Io ov s
w
Vd
Io V
d
Sw Dov
- C ov v
s
w
o t
fi
• Step-down converter with
overvoltage snubber comprised
of Dov, Cov, and Rov. • Switch Sw waveforms without overvoltage snubber
• tfi = switch current fall time ; kVd = overvoltage on Sw

• Overvoltage snubber limits
overvoltage (due to stray I diLs Io
nductance) across Sw as it • kVd = Ls = Ls
dt tfi
turns off.
kVdtfi
• Ls =
Io
Operation of Overvoltage Snubber
i π LsCov
Ls
• Dov on for 0 < t <
L 2
s
+
Dov R π LsCov
ov
• tfi <<
V 2
d
+ i
Ls • Equivalent circuit while
C v
- ov Cov inductor current decays to zero
- +
L
s + v Cov (0+) = Vd i Ls(0+) = I o
Vd v
C Cov
ov t
• Dov,Cov provide alternate path - - i (t) = Io cos[ ]
for inductor current as Sw turns Ls ! Ls!Cov
off.
• Switch current can fall to zero

Discharge of C ov thru R ov
much faster than Ls current. Charge-up of C ov from L s
with time constant R ov C
ov
• Df forced to be on DV sw,max
(approximating a short ckt) by Io i
Ls
after Swis off.
• Equivalent circuit after turn-off I V • Energy transfer from L s to Cov

o d
of Sw.
Cov !(DV sw,max )2 Ls!(I o)2
v
s =
2 2
w p! Ls!Cov
0
Copyright © by John Wiley & Sons 2003 4
Snubbers - 16
Overvoltage Snubber Design
Ls!Io2
• Cov =
(Dvsw,max)2
• Limit Dvsw,max to 0.1Vd
kVd!tfi
• Using Ls = in equation for Cov yields
!!Io
kVdtfiIo2 100k!tfi!Io
• Cov = =
!Io(0.1Vd)2 !!Vd
tfiIo
• Cov = 200 k Cs1 where Cs1 = which is used
!2Vd
in turn-off snubber
• Recovery time of Cov (2.3RovCov) must be less

than off-time duration, toff, of the switch Sw.
toff
• Rov ≈
2.3!Cov

Turn-on Snubber
Step-down converter
+ + with turn-on snubber
D I D
f o f
R
Ls Ls
Io
Snubber • Snubber reduces Vsw at switch
D turn-on due drop across
circuit Ls
R V inductor Ls.
V Ls Ls d
d D
D f • Will limit rate-of-rise of switch
Ls
current if Ls is sufficiently
Sw large.
- Sw -
i sw
Io
With Without
snubber snubber
Switching trajectory with and without turn-on snubber.

di sw
Ls
dt
v
sw
V
d
Turn-on Snubber Operating Waveforms
v I rr
Small values of snubber inductance (Ls < Ls1) s
w
disw
• controlled by switch S w
dt V
and drive circuit. d Io
LsIo
• Dvsw =
tri i
s
t ri t rr
w
v I rr
Large values of snubber inductance (Ls > Ls1) s
disw Vd Io
reduced
w
• limited by circuit to <
dt Ls tri
V
d
Vdtri Io
• Ls1 =
Io
i
s
disw w
• Irr reduced when Ls > Ls1 because Irr proportional to Ls Io
dt t ≈ >
ri t rr+ t
on
V
d
Turn-on Snubber Recovery at Switch Turn-off
+
D Io R
f Io I o R Lsexp(-R Lst/L s ) Ls
is
w V
Io d
R
V Ls Ls
d
vs
D t rv
Ls
w
- Sw
• Switch waveforms at turn-off with turn-on snubber in circuit.
• Assume switch current fall time • Overvoltage smaller if tfi smaller.

tri = 0.
• Time of 2.3 Ls/RLs required for inductor current to decay to 0.1 Io
• Inductor current must discharge
thru DLs- RLs series segment. • Off-time of switch must be > 2.3 Ls/RLs

Turn-on Snubber Design Trade-offs
Selection of inductor
• Larger Ls decreases energy dissipation in switch at turn-on
• Wsw = WB (1 + Irr/Io)2 [1 - Ls/Ls1]
• WB = VdIotfi/2 and Ls1 = Vdtfi/Io
• Ls > Ls1 Wsw = 0
• Larger Ls increases energy dissipation in RLs

• WR = WB Ls / Ls1
• Ls > Ls1 reduces magnitude of reverse recovery current Irr
• Inductor must carry current Io when switch is on - makes

inductor expensive and hence turn-on snubber seldom used
Selection of resistor RLs
• Smaller values of RLs reduce switch overvoltage Io RLs at turn-off
• Limiting overvoltage to 0.1Vd yields RLs = 0.1 Vd/Io
• Larger values of RLs shortens minimum switch off-time of 2.3 Ls/RLs

Thyristor Snubber Circuit
P
1 3 5
- va n + Ls
3-phase thyristor circuit with snubbers A

- vbn + Ls
B i
d
• van(t) = Vssin(wt), vbn(t) = Vssin(wt - 120°), - v cn + Ls
vcn(t) = Vssin(wt - 240°) C
Cs
4 6 2
Rs
Phase-to-neutral waveforms a v
v bn
an
• vLL(t) = 3 Vssin(wt - 60°)
3
• Maximum rms line-to-line voltage VLL = V
2 s
v LL = v v v w t
bn an= ba 1

Equivalent Circuit for SCR Snubber Calculations
Assumptions
• Trigger angle a = 90° so that vLL(t) = maximum = 2 VLL
Equivalent circuit after T1 reverse recovery

• Reverse recovery time trr << period of ac waveform so that
vLL(t) equals a constant value of vba(wt1) = 2 VLL i

Ls
2 Ls P
• Worst case stray inductance Ls gives rise to reactance equal
+ T1 after Cs
to or less than 5% of line impedance. recovery
V (w t1)
Vs 2VLL VLL ba i
• Line impedance = = = T 3 (on) T1 Rs
2Ia1 6Ia1 3Ia1
-
A
where Ia1 = rms value of fundamental component of the
line current.
VLL
• wLs = 0.05
3Ia1

Component Values for Thyristor Snubber
• Use same design as for diode snubber but adapt the formulas to the
thyristor circuit notation
È ˘2
Í Irr ˙
• Snubber capacitor Cs = Cbase = Ls Í ˙
ÎVd ˚
diLs
• From snubber equivalent circuit 2 Ls = 2 V LL
dt
diLs 2VLL 2VLL

• Irr = trr = t rr = trr = 25 wIa1 trr
dt 2Ls 0.05!VLL
2!
3!Ia1 w
• Vd = 2 VLL
0.05!VLL È25!wI ˘ 2
Í a1trr˙ 8.7!wIa1 trr
• Cs = C base = Í ˙ =
3!Ia1w Î ! 2VLL ˚ VLL
Vd
• Snubber resistance Rs = 1.3 Rbase = 1.3
Irr
2V LL 0.07!VLL
• Rs = 1.3 =
25wIa1 trr !wIa1 trr
• Energy dissipated per cycle in snubber resistance = W R
LsIrr 2 CsV d2
• WR = + = 18 w I a1 V LL(trr )2
2 2

Drive Circuits
Outline
• Drive circuit design considerations
• DC-coupled drive circuits
• Isolated drive circuits
• Protection measures in drive circuits
• Component/circuit layout considerations
Copyright © by John Wiley & Sons 2003 Drive Ckts - 1

Functionality of Gate/Base Drive Circuits
• Turn power switch from off-state to on-state
• Minimize turn-on time through active region where power dissipation is large
• Provide adequate drive power to keep power switch in on-state
• Turn power switch from on-state to off-state
• Minimize turn-off time through active region wherepower dissipation is large
• Provide bias to insure that power switch remains off
• Control power switch to protect it when overvoltages or overcurrents are sensed
• Signal processing circuits which generate the logic control signals not considered part of the drive circuit
• Drive circuit amplifies control signals to levels required to drive power switch
• Drive circuit has significant power capabilities compared to logic level signal processing circuits
• Provide electrical isolation when needed between power switch and logic level signal processing/control circuits

Drive Circuit Design Considerations
• Drive circuit topologies
• Output signal polarity - unipolar or bipolar

• AC or DC coupled
• Connected in shunt or series with power switch
• Output current magnitude 0 t

• Large Ion shortens turn-on time but lengthens turn-off delay time Unipolar
• Large Ioff shortens turn-off time but lengthens turn-on delay time
• Provisions for power switch protection

• Overcurrents
• Blanking times for bridge circuit drives 0 t
• Waveshaping to improve switch performance Bipolar

• Controlled diB/dt for BJT turn-off
• Anti-saturation diodes for BJT drives
• Speedup capacitors
• Front-porch/backporch currents
• Component layout to minimize stray inductance and shielding from switching noise

Unipolar DC-coupled Drive Circuit - BJT Example
• Circuit operation
• Vcontrol > Vreference - BJT at comparator output on
which puts Qpnp and Qsw on
• Vcontrol < Vreference - BJT at comparator output off
V
which turns Qpnp off and thus Qsw off BB V
d
• Design procedure
VBE,off
Io
• R2 =
IB,off
; IB,off based on desired turn-off time. Comparator Q pnp
VBE,on
• Ipnp = IB,on + ; IB,on value based on BJT beta and R1
R2 Vcontrol
value of Io.
Q sw
• VBB = VCE,on(Qpnp) + R1 IC,pnp + VBE,on(Qsw) R
2
• VBB = 8 to 10 V ; compromise between larger values which
minimize effects of VBE variations and smaller values
which minimize power dissipation in drive circuit
Vreference

Unipolar DC-coupled Drive Circuits- MOSFET examples
V V
BB d
• Vcontrol > Vreference
Io comparator output
Comparator R1 high and Q sw on
R2
Vcontrol • Vcontrol < Vreference
Q sw
-
comparator output
+ low and Q sw off
Vreference
V V • Vcontrol > Vreference

GG d
comparator output
Io
high putting Q npn
Comparator R on and thus Q sw on
1
Vcontrol • Vcontrol < Vreference
Q sw
+ R comparator output
G
low putting Q pnp on
- and thus Q sw off
Vreference
V
V d
GG
Io
Vcontrol IC buffer amp with R

G
totem pole output Q sw
DS0026 or UC1706/07

Bipolar DC-coupled Drive Circuit- BJT Example
• Vcontrol < Vreference - comparator output

V V low, TB- on and Qsw off.
BB+ d
Comparator R Io
B Df • Large reverse base current flows to
minimize turn-off time and base-emitter
Vcontrol C BB+ of Qsw reversed biased to insure off-
T state.
+ B+
Q sw
- T
Vreference B- • Vcontrol > Vreference - comparator output
high, TB+ on and Qsw on.
C
BB-
• Large forward base current to minimize
V turn-on time and to insure saturation of
BB-
Qsw for low on-state losses

Bipolar DC-coupled Drive Circuit- MOSFET Example
V V
GG+ d
Comparator Io
D
f
T B+
Vcontrol C • Bipolar drive with substantial output
GG+
current capability
+
Q sw
R
- G
Vreference TB-
C
GG-
V
GG-
V
V d
GG+
Io
C GG+
Vcontrol IC buffer amp with

• Simple bipolar drive circuit with
totem pole output Q sw
R moderate (1 amp)output current
DS0026 or UC1706/07 G
capability
C
GG-
V
GG-

Need for Electrical Isolation of Drive Circuits
Isolated auxiliary
• Negative half cycle of vs(t) - positive dc power to base
drive circuits
rail near safety ground potential. T-
emitter potential large and negative with
respect to safety and logic ground
base D
Signal T+ F+
• Postive half cycle of vs(t) - negative dc drive
isolation circuit
rail near safety ground potential. T+ V Logic and
+ d
emitter substantially positive with espect Control
v Electronics
to safety ground if T- is off S
base D
- Signal T- F-
isolation drive
circuit
Control
• Variation in emitter potentials with Inputs
respect to safety and logic ground means
that electrical isolation of emitters from
logic ground is needed.
Safety
Ground

Methods of Control Signal Isolation
Input to remainder of
Logic level isolated drive circuit
control ckts • Transformer isolation
Power switch reference node

(BJT emitter, MOSFET source)
Logic ground
Light- V Isolated
BB+
emitting dc supply
diode
Signal
Input to remainder of
from
isolated drive circuit • Opto-coupler isolation
control
logic
Power switch
Control logic reference node
ground Photo-transistor
V
BB+
AC
power in
• Isolated dc power supplies
for drive circuits
V BB-

Opto-Coupler Isolated BJT Drive
V
BB+
Signal
from Opto-coupler
control
electronics
R
B C
BB+
T
B+
Q sw
TB-
C BB-
V
BB-

Transformer-coupled BJT Drive
V
d
Fast
High signal R Io
B D
Oscillator frequency diodes f
C
transformer BB+
TB+
Q Q
Qsw
T
B-
C
BB-
V
control
V
BB+
AC
power
in
VBB-
Oscillator output
t
V
control
t
Transformer
t primary voltage
Input to
t comparator

Opto-Coupler Isolated MOSFET Drives
Signal V V
Opto-coupler GG+ d
from control
electronics Io
D
f
T
B+ C
GG+
Q sw
R
G
T
B-
C
GG-
V
GG-
AC
power
in
V V
Signal GG+ d
Opto-coupler
from control
electronics Io
C GG+
IC buffer amp with

totem pole output
DS0026 or R Q sw
G
UC1706/07
C
GG-
V (Circuitry for isolated

GG-
dc supplies not shown)

Isolated Drives Without Auxiliary DC Supplies
- Proportional Flyback BJT Example
• Regenerative circuit operation
• T1 on - current ip = VBB/Rp and Qsw off
V • T1 turned off - stored energy in gapped transformer core

BB induces positive base current iB in Qsw causing it to go active
and collector current iC begins to flow
iC
R p Cp N
1 N2 Q sw • Regenerative action of transformer connections supplies a
base current iB = N3iC/N2 which keeps Qsw on even with ip = 0
ip i
B
• T1 turned on - positive current ip causes a base current
iB = N3iC/N2 - N1ip/N2 in Qsw
T1 • Initially ip quite large (ip(0+) = biB1(0+)) so Qsw turned off
N3 • Circuit design must insure turn-off iB has adequate negative

magnitude and duration
• Best suited for high frequency operation - lower volt-second

requirements on transformer.
• Also best suited for limited variations in duty cycle

Isolated Drives Without Auxiliary DC Supplies
- MOSFET Example
V
DD v
+ C
Buffer
+
v
sec
Buffer
output v = V (1 - D)
voltage
C DD Most suitable for applications
where duty cycle D is 50% or
0
t duty
less. Positive-going secondary
v
ratio voltage decreases as D increases.
sec D= 0.5
t
0
Buffer output
v
voltage C
0
t
duty
v ratio
sec
D= 0.3
t
0

Isolated Drive Without Auxiliary DC Supplies
- MOSFET Example
Vc o n t r o l
Inverting A
Buffer
v
sec vc a p
C Noninverting
Buffer B
Schmitt
Zener diode voltage VZ
trigger must be less than negative
Vc o n t r o l t
pulse out of transformer
secondary or pulse will not
v
A t
reach MOSFET gate to turn
v C t it off.
v t
B
v v
A B t
V
Z
V
v Z
sec t
(dotted) vc a p

Isolated Drive Without Auxiliary DC Supplies
- MOSFET Example
4011
Q Buffer
4047 +
vc o n t r o l v
oscillator Q trans
-
(1 MHz) Buffer
C
R C 1
2 2
7555
+ R
G
+ v
v 2s
D 1s
B
- -
vc o n t r o l
v
Q
C1 charges up to a
positive voltage at
v power-up and remains
Q
there. D B prevents
discharge
v
trans
v Decay of
1s
voltage on C 2
via R
v 2
2s

Emitter-Open Switching of BJTs
V i
BB+ C standard emitter open
RBSOA switching RBSOA
Power
BJT
T
E
control
v
CE
switching switching
locus with locus with
standard emitter open
base drive base drive
• Circuit operation
• Turn on power BJT by turning on MOSFET TE.
• Turn off power BJT by turning off MOSFET TE.
• Collector current flows out base as negative base current.
• Greater iB(off) compared to standard drive circuits iC = b iB(off) removes stored charge much faster
• Turn off times reduced (up to ten times).
• On-state losses of series combination of MOSFET and BJT minimized.

• Low voltage MOSFET which has low losses can be used. Maximum off-state MOSFET voltage limited by
Zener diode.
• BJT base emitter junction reverse biased when TE off so breakdown rating of BJT given by BVCBO instead o
of BVCEO. With lower BVCEO rating, BJT losses in on-state reduced.
• Circuit also useful for GTOs and FCTs.

Thyristor Gate Drive Circuit
1 4
Line
Voltage
3 2
DC power supply for

gate trigger circuit
Delay angle block is
commercially available
integrated circuit -
zero crossing
detection gate pulse
TCA780 circuit family
isolation
transformers
Input Delay Pulse

Control Angle Amplifier
Signal Block
gate pulse
Control isolation
Logic transformers
Ground

Thyristor Gate Drive Circuit (cont.)
Transformer
Line Voltage
a a a Ramp
Control
voltage Thyristor gate drive waveforms
Control of
1 & 2
Control of
3 & 4
D1
15 V
D
f
R Gate pulse amplifier
G
T
Trigger signal G

GTO Gate Drive Circuit
R R
2 4
T T
G2 G1
R
1 10 A
pulse V
R GG+
R 6
5
2 A
Ls 1 • Turn on TG1and TG2 to get

R
large front-porch current
Control 3
Circuit
L
G
Ls 2 • Turn off TG1 after some
V
GG-
specified time to reduce total
R
7 gate current to back-porch
T
G3 value.
turn-off
pulse
Auxilliary
power supply
for gate drive
circuit

Overcurrent Protection With Drive Circuits
V
d
V
BB+
R R B I
1 R o
p
C
Dp
overcurrent
protection BJT
control
V BB-
• Point C one diode drop above VCE(sat) when BJT is on. Overcurrent will increase
VCE and thus potential at C.
• If C rises above a threshold value and control signal is biasing BJT on,
overcurrent protection block will turn off BJT. Conservate design would keep
BJT off until a manual reset had been done.

Limiting Overcurrents by Limiting On-state Base Current
+ D Io
F
Vd • Stepdown converter with
Cd
short curcuit at t = t sc
-
i i
C C
I I
C,sc B,max
I
C(on)max
V v t sc t
in CE
• Overcurrent limited to IC(on)max < IC,sc by keeping IB,max < IC,sc/b
• IC,sc = maximum allowable instantaneous collector current
• Same approach can be used with MOSFETs and IGBTs. VGS mustbe restricted to keep drain current to
safe values.

Blanking Times in Bridge Circuit Drives
Optocoupler or
V transformer
1+
Vcontrol, T
+ T+ +
• Turn off T+ before turning on
Vd T- in order to avoid cross signal ground
Io -conduction (shorting out of Vd)
T-
- Vcontrol, T
-
V
1- Optocoupler or
Control for
transformer
converter leg
V control,
bridge
V
1+
V
1-
dead
time
V control, T
+
blanking collector blanking
time current time
V control, T
- dead
time

Drive Circuit Waveshaping for Improved Operation
V
BB+
R • Anti-saturation diode Das keeps Qsw active.
B
• VAE = VBE(on) + VD1 = VCE(on) + Vdas
TB+ Da s • VCE(on) = VBE(on) > VCE(sat) because VD1 = Vdas
D1
Qsw
• Ds provides path for negative base current at Qsw turn-off.
A
D
• Storage delay time at turn-off reduced but on-state losses increase slightly.
T 2
B- E
V Speed-up capacitors
BB-
V i
BB+ B
R
B C on
T B+
t
i
B • Transient overdrive
Qsw
provided via C on for
faster turn-on of switch
T
B-
• Same concept can be applied to
MOSFET and IGBT drive circuits
V
BB-

Drive Circuit Waveshaping (cont.)
V
BB+
R
B
Controlled rate of change of turn-off base current
T • Excessively long collector current tailing time at BJT turn-off if
B+ i
B diB(off)/dt is too large.
Q sw
• Inductor Loff restricts diB(off)/dt to - VBB/Loff
L off
TB-
V
BB-
Gate/base Back porch Front porch, back porch gate/base currents at
current V current
BB+ turn-on
Front Front
porch R R porch
B1 B2 • Faster turn-on without putting device
current Back current
porch deeply into on-state where turn-off delay
Control
current T time will be substantially increased.
B+ i
B
Q
sw
T • Applicable to BJTs, MOSFETs, IGBTs, and
B-
V GTOs.
BB-
t

Circuit/Component Layout Considerations
V V Prime consideration is minimizing stray inductance

d d
Control • Stray inductance in series with high-voltage side
D Io Signal Df Io
f of power device Qsw causes overvoltage at turn-
Drive off.
Control Q
Signal Circui sw
Ls
t • Stray inductance in series with low-voltage side
Drive Q
Ls power device Qsw can cause oscill-ations at turn-
Circui sw
on and turn-off.
t
• One cm of unshielded lead has about 5 nH of

series inductance.
V
d
• Keep unshielded lead lengths to an absolute
Control Df minimum.
Twisted or Io
Signal
shielded
Drive conductors D
Q sw
Circui
t G Power terminals
Control terminals
S
S
Use shielded conductors to connect drive

circuit to power switch if there must be Some power devices provided with four leads, two input
any appreciable separation (few cm or leads and two power leads, to minimize stray inductance
more) between them in input circuit.

Lecture Notes
Heat Sinks and Component Temperature Control
Copyright © by John Wiley & Sons 2003 Heat Sinks - 1

Need for Component Temperature Control
• All components, capacitors, inductors and transformers, and semiconductor devices
and circuits have maximum operating temperatures specified by manufacturer.
• Component reliability decreases with increasing temperature.Semiconductor
failure rate doubles for every 10 - 15 °C increase in temperature above 50 °C
(approx. rule-of-thumb).
• High component operating temperatures have undesirable effects on components.
Capacitors Magnetic Components Semconductors

Electrolyte evaporation • Losses (at constant power • Unequal power sharing in
rate increases input) increase above 100 paralleled or seriesed
significantly with °C devices.
temperature increases
• Winding insulation (lacquer • Reduction in breakdown
and thus shortens
or varnish) degrades above voltage in some devices.
lifetime.
100 °C
• Increase in leakage currents.
• Increase in switching times.

Temperature Control Methods
• Control voltages across and current through components via good design practices.
• Snubbers may be required for semiconductor devices.
• Free-wheeling diodes may be needed with magnetic components.
• Use components designed by manufacturers to maximize heat transfer via

convection and radiation from component to ambient.
• Short heat flow paths from interior to component surface and large component
surface area.
• Component user has responsibility to properly mount temperature-critical

components on heat sinks.
• Apply recommended torque on mounting bolts and nuts and use thermal grease
between component and heat sink.
• Properly design system layout and enclosure for adequate air flow so that heat
sinks can operate properly to dissipate heat to the ambient.

Heat Conduction Thermal Resistance
b
• Generic geometry h
Pcond heat flow
of heat flow via direction
conduction
Temperature = T2 T2 > T Temperature = T1

1
• Heat flow Pcond [W/m2] = l A (T2 - T1) / d = (T2 - T1) / Rqcond
• Thermal resistance Rqcond = d / [l A]

• Cross-sectional area A = hb
• l = Thermal conductivity has units of W-m-1-°C-1 (lAl = 220 W-m-1-°C-1 ).
• Units of thermal resistance are °C/W

Thermal Equivalent Circuits
• Heat flow through • Thermal equivalent circuit

a structure composed simplifies calculation of
of layers of different temperatures in various parts
materials. of structure.
Chip Tj Junction Case Sink Ambient
+ R qjc + R + R qs a +
qc s
P Tj Tc Ts Ta
Case Tc
- - - -
Isolation pad
Heat sink Ts
• Ti = Pd (Rqjc + Rqcs + Rqsa) + Ta
• If there parallel heat flow paths,
then thermal resistances of the
parallel paths combine as do
electrical resistors in parallel.
Ambient Temperature T a

Transient Thermal Impedance
• Heat capacity per unit volume Cv = dQ/dT [Joules /°C] prevents short duration high
power dissipation surges from raising component temperature beyond operating limits.
Tj (t)
• Transient thermal equivalent Rq

P(t) Cs
circuit. Cs = CvV where V is the
volume of the component.
Ta
• Transient thermal impedance Zq(t) = [Tj(t) - Ta]/P(t)

P(t)
log Z (t)
q
• tq = π Rq Cs /4 = thermal time
Po Rq constant
• Tj(t = tq) = 0.833 Po Rq

t tq t
Slope = 0.5

Application of Transient Thermal Impedance
• Symbolic response for a rectangular power dissipation pulse P(t) = Po {u(t) - u(t - t1)}.
P(t) Z (t)
q
Po Rq
net response
• Tj(t) = Po { Zq(t) - Zq(t - t1) }

t1 t t1 tq t
-Z (t - t 1)
q
P(t) -R
q
Half sine pulse
P
o
Equivalent • Symbolic solution for half sine power
rectangular dissipation pulse.
pulse
• P(t) = Po {u(t - T/8) - u(t - 3T/8)} ; area
T/2 under two curves identical.
T/8 3T/8 t • Tj(t) = Po { Zq(t - T/8) - Zq(t - 3T/8) }

Zq for Multilayer Structures
P(t)
Tj
Silicon
TCu
• Multilayer geometry Tc
Copper mount
Heat sink
Ta
Tj R (Si) TCu R (Cu) Tc R (sink)

q q q
• Transient thermal P(t) C s (Si) C s (Cu) Cs (sink)

equivalent circuit
log[Z (t)] Ta
q
R (Si) + R (Cu) + R (sink)

q q q • Transient thermal
R (Si) + R (Cu)
q q
impedance (asymptotic)
of multilayer structure
R (Si)
q assuming widely
separated thermal time
constants.
t (Si) t (Cu) t (sink) log(t)
q q q
Heat Sinks
• Aluminum heat sinks of various shapes and sizes widely available for cooling components.
• Often anodized with black oxide coating to reduce thermal resistance by up to 25%.
• Sinks cooled by natural convection have thermal time constants of 4 - 15 minutes.
• Forced-air cooled sinks have substantially smaller thermal time constants, typically
less than one minute.
• Choice of heat sink depends on required thermal resistance, Rqsa, which is determined by
several factors.
• Maximum power, Pdiss, dissipated in the component mounted on the heat sink.
• Component's maximum internal temperature, Tj,max
• Component's junction-to-case thermal resistance, Rqjc.
• Maximum ambient temperature, Ta,max.
• Rqsa = {Tj,max - Ta,max}Pdiss - Rqjc

• Pdiss and Ta,max determined by particular application.
• Tj,max and Rqjc set by component manufacturer.
Radiative Thermal Resistance
• Stefan-Boltzmann law describes radiative heat transfer.
• Prad = 5.7x10-8 EA [( Ts)4 -( Ta)4 ] ; [Prad] = [watts]
• E = emissivity; black anodized aluminum E = 0.9 ; polished aluminum E = 0.05
• A = surface area [m2]through which heat radiation emerges.
• Ts = surface temperature [°K] of component. Ta = ambient temperature [°K].
• (Ts - Ta )/Prad = R q,rad = [Ts - Ta][5.7EA {( Ts/100)4 -( Ta/100)4 }]-1
• Example - black anodized cube of aluminum 10 cm on a side. Ts = 120 °C and

Ta = 20 °C
• Rq,rad = [393 - 293][(5.7) (0.9)(6x10-2){(393/100)4 - (293/100)4 }]-1
• Rq,rad = 2.2 °C/W

Convective Thermal Resistance
• Pconv = convective heat loss to surrounding air from a vertical surface at sea level having
a height dvert [in meters] less than one meter.
• Pconv = 1.34 A [Ts - Ta]1.25 dvert-0.25
• A = total surface area in [m2]
• Ts = surface temperature [°K] of component. Ta = ambient temperature [°K].
• [Ts - Ta ]/Pconv = Rq,conv = [Ts - Ta ] [dvert]0.25[1.34 A (Ts - Ta )1.25]-1

• Rq,conv = [dvert]0.25 {1.34 A [Ts - Ta]0.25}-1
• Example - black anodized cube of aluminum 10 cm on a side. Ts = 120 °C and Ta = 20 °C.

• Rq,conv = [10-1]0.25([1.34] [6x10-2] [120 - 20]0.25)-1
• Rq,conv = 2.2 °C/W
Combined Effects of Convection and Radiation
• Heat loss via convection and radiation occur in parallel.

Ts
• Steady-state thermal equivalent circuit R

P q,rad R q,conv
Ta
• Rq,sink = Rq,rad Rq,conv / [Rq,rad + Rq,conv]
• Example - black anodized aluminum cube 10 cm per side
• Rq,rad = 2.2 °C/W and Rq,conv = 2.2 °C/W
• Rq,sink = (2.2) (2.2) /(2.2 + 2.2) = 1.1 °C/W

Design of Magnetic Components
Outline
A. Inductor/Transformer Design Relationships
B. Magnetic Cores and Materials
C. Power Dissipation in Copper Windings
D. Thermal Considerations
E. Analysis of Specific Inductor Design
F. Inductor Design Procedures
G. Analysis of Specific Transformer Design
H. Eddy Currents
J. Transformer Leakage Inductance
K. Transformer Design Procedures
Copyright © by John Wiley & Sons 2003 Magnetics - 1

Magnetic Component Design Responsibility of Circuit Designer
• Ratings for inductors and transformers in power

Core
electronic circuits vary too much for commercial
(double E)
vendors to stock full range of standard parts.
• Instead only magnetic cores are available in a
wide range of sizes, geometries, and materials as
standard parts.
• Circuit designer must design the
inductor/transformer for the particular
application. Winding
Bobbin
• Design consists of:
1. Selecting appropriate core material, geometry,
and size
2. Selecting appropriate copper winding Assembled
core and
parameters: wire type, size, and number of winding
turns.

Review of Inductor Fundamentals
Cross-sectional
• Assumptions l m= mean path length
area of core = A
• No core losses or copper winding losses
• Linearized B-H curve for core with
mm >> mo
i1
• lm >> g and A >> g2
• Magnetic circuit approximations (flux
uniform over core cross-section, no N1 Air gap: H g
fringing flux) g
• Hm lm + Hg g = N I (Ampere’s Law)
• Bm A = Bg A = f (Continuity of flux Core: Hm
assuming no leakage flux) B

• mm Hm= Bm (linearized B-H curve) ; Bs
mo Hg = Bg
DB
H
• Results DH
NI
• Bs > Bm = Bg = = f/A
lm/mm!+!g/mo
A!N2 linear region
• LI = Nf ; L =
lm/mm!+!g/mo DB B
m= =
DH H
Review of Transformer Fundamentals
• Assumptions same as for inductor Cross-sectional
l m= mean path length area of core = A
• H1Lm = N1I1 ; H2Lm = N2I2
(Ampere's Law) i1 i2
• HmLm = (H1 - H2)Lm = N1I1- N2I2
+ +
• µmHm = Bm (linearized B-H curve) v1 N1 v
2
N2
df1 df2 - -
• v1= N1 ; v2 = N2
dt dt f1 f2
(Faraday's Law)
• Net flux f = f1 - f2 = µmHmA
Magnetic flux f
µmA(N1I1-!N2I2)
=
Lm B
Bs
• Results assuming µm fi •, i.e. ideal core
DB
or ideal transformer approximation.
H
f DH
• = 0 and thus N1I1= N2I2
µm
d(f1-!f2) v1 v2 v1 v2
• = 0 = - ; = linear region
dt N1 N2 N1 N2
DB B
m= =
DH H
Current/Flux Density Versus Core Size
• Larger electrical ratings require larger current I and
larger flux density B. B
Bs
• Core losses (hysteresis, eddy currents) increase
Minor
as B2 (or greater)
hystersis
• Winding (ohmic) losses increase as I2 and are loop
accentuated at high frequencies (skin effect,
proximity effect)
H
• To control component temperature, surface area of
component and thus size of component must be
increased to reject increased heat to ambient.
• At constant winding current density J and core - Bs
flux density B, heat generation increases with
volume V but surface area only increases as V2/3.
core
• Maximum J and B must be reduced as electrical
ratings increase.
• Flux density B must be < Bs
g
• Higher electrical ratings fi larger total flux
fi larger component size
• Flux leakage, nonuniform flux distribution fringing
complicate design flux

Magnetic Component Design Problem
• Challenge - conversion of component operating specs
in converter circuit into component design parameters. • Design procedure outputs.
• Core geometry and material.
• Core size (Acore , Aw)
• Goal - simple, easy-to-use procedure that produces • Number of turns in windings.
component design specs that result in an acceptable • Conductor type and area Acu.
design having a minimum size, weight, and cost. • Air gap size (if needed).
• Inductor electrical (e.g.converter circuit) • Three impediments to a simple design procedure.

specifications.
• Inductance value L
• Inductor currents rated peak current I, rated rms 1. Dependence of Jrms and B on core size.
current Irms , and rated dc current (if any) Idc
• Operating frequency f. .
• Allowable power dissipation in inductor or 2. How to chose a core from a wide range of
equivalently maximum surface temperature of the
inductor Ts and maximum ambient temperature Ta. materials and geometries.
• Transformer electrical (converter circuit) 3. How to design low loss windings at high
specifications. operating frequencies.
• Rated rms primary voltage Vpri
• Rated rms primary current Ipri
• Turns ratio Npri/Nsec
• Operating frequency f • Detailed consideration of core losses, winding
• Allowable power dissipation in transformer or losses, high frequency effects (skin and proximity
equivalently maximum temperatures Ts and Ta effects), heat transfer mechanisms required for good
design procedures.

Core Shapes and Sizes
• Magnetic cores available in a wide variety of sizes and shapes.
• Ferrite cores available as U, E, and I shapes as well as pot cores

and toroids.
• Laminated (conducting) materials available in E, U, and I shapes
as well as tape wound toroids and C-shapes.
• Open geometries such as E-core make for easier fabrication but
more stray flux and hence potentially more severe EMI problems.
• Closed geometries such as pot cores make for more difficult
fabrication but much less stray flux and hence EMI problems.
insulating layer
• Bobbin or coil former provided with most cores. magnetic steel
lamination
• Dimensions of core are optimized by the manufacturer so that for a

given rating (i.e. stored magnetic energy for an inductor or V-I
rating for a transformer), the volume or weight of the core plus
winding is minimized or the total cost is minimized.
• Larger ratings require larger cores and windings.

• Optimization requires experience and computerized optimization
algorithm.
• Vendors usually are in much better position to do the
optimization than the core user.

Double-E Core Example
d
a
2
a a
2 1.9 a
1.4 a
hw
ha bw
2
ba Assembled core and winding
Bobbin
Core
Characteristic Relative Size Absolute Size for
a = 1 cm
Core area Acore 1.5 a2 1.5 cm2
Winding area Aw 1.4 a2 1.4 cm2
Area product AP = AwAc 2.1 a4 2.1 cm4
Core volume Vcore 13.5 a3 13.5 cm3
Winding volume Vw 12.3a3 12.3 cm3
Total surface area of 59.6 a2 59.6 cm2
assembled core and
winding

Types of Core Materials
• Iron-based alloys • Ferrite cores
• Various compositions • Various compositions - iron oxides,

• Fe-Si (few percent Si) Fe-Ni-Mn oxides
• Fe-Cr-Mn
• METGLASS (Fe-B, Fe-B-Si, plus many • Important properties
other compositions)
• Resistivity r very large (insulator) -
• Important properties no ohmic losses and hence skin
• Resistivity _ = (10 - 100) r effect problems at high
Cu
• Bs = 1 - 1.8 T (T = tesla = 104 oe) frequencies.
• METGLASS materials available only as • Bs = 0.3 T (T = tesla = 104 oe)

tapes of various widths and thickness.
• Other iron alloys available as laminations

of various shapes.
• Powdered iron can be sintered into

various core shapes. Powdered iron cores
have larger effective resistivities.
Hysteresis Loss in Magnetic Materials
B
Bs
Bac
Minor 0
hystersis t
loop
H Bac
Bdc B(t)
0
- Bs t
• Area encompassed by hysteresis • Typical waveforms of flux density,

loop equals work done on material B(t) versus time, in an inductor.
during one cycle of applied ac
magnetic field. Area times frequency • Only Bac contributes to hysteresis
equals power dissipated per unit loss.
volume.
Quantitative Description of Core Losses
• Eddy current loss plus hysteresis loss =

core loss. • 3F3 core losses in graphical form.
d
• Empirical equation - Pm,sp = k fa [Bac]
.
f = frequency of applied field. Bac =
base-to-peak value of applied ac field. k,
a, and d are constants which vary from
material to material
2.5
• Pm,sp = 1.5x10-6 f1.3 [Bac]
mW/cm3 for 3F3 ferrite. (f in kHz and
B in mT)
• Pm,sp = 3.2x10-6 f1.8 [Bac]2
mW/cm3 METGLAS 2705M (f in kHz
and B in mT)
• Example: 3F3 ferrite with f = 100 kHz
and Bac = 100 mT, Pm,sp = 60
mW/cm3

Core Material Performance Factor
• Volt-amp (V-A) rating of transformers proportional to f Bac
• Core materials have different allowable values of Bac at a specific frequency. Bac limted by allowable Pm,sp.
• Most desirable material is one with largest Bac.
• Choosing best material aided by defining an emperical performance factor PF = f Bac. Plots of PF versus
frequency for a specified value of Pm,sp permit rapid selection of best material for an application.
• Plot of PF versus frequency at Pm,sp = 100 mW/cm3 for several different ferrites shown below.

Eddy Current Losses in Magnetic Cores
Eddy current
Bi(r)
• = exp({r - a}/d)
Bo
B (r) B (r)
i i
B
2
B (t)
o
o Bo
• d = skin depth = wms
• w = 2π f, f = frequency
r • m = magnetic permeability ;
a a
0
mo for magnetic materials.
• s = conductivity of material.
• AC magnetic fields generate eddy currents

• Numerical example
in conducting magnetic materials.
• Eddy currents dissipate power. • s = 0.05 scu ; m = 103 mo
• Shield interior of material from magnetic f = 100 Hz
field.
• d = 1 mm

Laminated Cores
• Cores made from conductive magnetic

materials must be made of many thin
laminations. Lamination thickness < skin
depth.
t
• Stacking factor kstack = !t!+!0.05t 0.5 t
t (typically
0.3 mm)
Insulator
Magnetic steel
lamination

Eddy Current Losses in Laminated Cores
• Flux f(t) intercepted by current loop • Average power Pec dissipated in lamination
of area 2xw given by f(t) = 2xwB(t)
w!L!d3!w2!B2
dB(t) Û
given by Pec = <ıdp(t)dV > =
• Voltage in current loop v(t) = 2xw 24!rcore
dt
= 2wxwBcos(wt) Pec w!L!d3!w2!B2 1 d2!w2!B2
2wrcore • Pec,sp = = =
V 24!rcore dwL 24!rcore
• Current loop resistance r = ; w >> d
L!dx
• Instantaneous power dissipated in thin loop
[v(t)]2 w
dp(t) =
r
x
• Average power Pec dissipated in lamination
z
d
w!L!d3!w2!B2
given by Pec = <Û
ıdp(t)dV > = y
24!rcore L
Pec w!L!d3!w2!B2 1 d2!w2!B2

• Pec,sp = = =
V 24!rcore dwL 24!rcore
dx
B sin( wt)
x
-x
Eddy current flow path

Power Dissipation in Windings
bobbin
• Average power per unit volume of copper dissipated Winding conductor
in copper winding = Pcu,sp = rcu (Jrms)2 where
Jrms = Irms/Acu and rcu = copper resistivity. airgap
• Average power dissipated per unit volume of

winding = Pw,sp = kcu rcu (Jrms)2 ; Vcu = kcu hw
Aw
Vw where Vcu = total volume of copper in the g

winding and Vw = total volume of the winding. g
>
N!Acu 2
bw
• Copper fill factor kcu = A < 1
w
Double-E core example
• N = number of turns; Acu = cross-sectional area
of copper conductor from which winding is made; • kcu < 1 because:
Aw = bw lw = area of winding window.
• Insulation on wire to avoid shorting
• kcu = 0.3 for Leitz wire; kcu = 0.6 for round out adjacent turns in winding.
conductors; kcu fi 0.7-0.8 for rectangular
• Geometric restrictions. (e.g. tight-packed
conductors.
circles cannot cover 100% of a square
area.)
Eddy Currents Increase Winding Losses
Eddy currents
• AC currents in conductors generate ac H(t)
magnetic fields which in turn generate eddy
currents that cause a nonuniform current
density in the conductor . Effective resistance I(t)
J(t) J(t)
of conductor increased over dc value.
• Pw,sp > kcu rcu (Jrms)2 if conductor I(t)
dimensions greater than a skin depth. r

a a
J(r) 0
• J = exp({r - a}/d) B sin( wt)

o
2
• d = skin depth = wms - + - +
• w = 2π f, f = frequency of ac current + - + -
• m = magnetic permeability of conductor;
m = mo for nonmagnetic conductors. B sin( wt)
• s = conductivity of conductor material.
• Mnimize eddy currents using Leitz wire
bundle. Each conductor in bundle has a
• Numerical example using copper at 100 °C
diameter less than a skin depth.
Frequency 50 5 20 500
Hz kHz kHz kHz • Twisting of paralleled wires causes effects of
Skin 10.6 1.06 0.53 0.106 intercepted flux to be canceled out between
Depth mm mm mm mm adjacent twists of the conductors. Hence little if
Copyright © by John Wiley & Sons 2003 any eddy currents.
Magnetics - 17
Proximity Effect Further Increases Winding Losses
(a) d > d (b) d < d
x x
x
A A
x
x
x
x
x x
• Proximity effect - losses due to eddy
B B current generated by the magnetic
field experienced by a particular
MMF conductor section but generated
by the current flowing in the rest of
the winding.
x x
• Design methods for minimizing
proximity effect losses discussed
10
Eddy
100 later.
Current
30
Losses
3 10
1 1
x x

Minimum Winding Loss
• Pw = Pdc + Pec ; Pec = eddy current loss. Optimum conductor size
Resistance
• Pw = { Rdc + R ec} [Irms]2 = Rac [Irms]2
R
dc
R
• Rac = FR Rdc = [1 + Rec/Rdc] Rdc ec
• Minimum winding loss at optimum conductor size.
• Pw = 1.5 Pdc
• Pec = 0.5 P dc d opt ≈ d d = conductor

diameter or
thickness
• High frequencies require small conductor sizes minimize loss.
• Pdc kept small by putting may small-size conductors in parallel using

Litz wire or thin but wide foil conductors.

Thermal Considerations in Magnetic Components
• Losses (winding and core) raise core • Surface temperature of component nearly equal to
temperature. Common design practice to interior temperature. Minimal temperature gradient
limit maximum interior temperature to 100-125 °C. between interior and exterior surface.
• Power dissipated uniformly in component volume.
• Core losses (at constant flux density) increase • Large cross-sectional area and short path
with temperature increases above 100 °C lengths to surface of components.
• Core and winding materials have large thermal
• Saturation flux density Bs decreases with temp. conductivity.
Increases
.• Thermal resistance (surface to ambient) of magnetic
• Nearby components such as power semi- component determines its temperature.
conductor devices, integrated circuits, capacitors
have similar limits. Ts!-!Ta h
• Psp = R (V !+!V ) ; Rqsa = A
qsa w c s
• Temperature limitations in copper windings
• h = convective heat transfer coefficient =
• Copper resistivity increases with temperature 10 °C-m2/W
increases. Thus losses, at constant current
density increase with temperature. • As = surface area of inductor (core + winding).
Estimate using core dimensions and simple
• Reliability of insulating materials degrade with geometric considerations.
temperature increases.
• Uncertain accuracy in h and other heat transfer
parameters do not justify more accurate thermal
modeling of inductor.
Scaling of Core Flux Density and Winding Current Density
Psp 1
• Power per unit volume, Psp, dissipated in magnetic • Jrms = kcu!rcu = k2 k a ; k2 = constant
component is Psp = k1/a ; k1 = constant and cu
a = core scaling dimension.
Ts!-!Ta
• Pw,sp Vw + Pm,sp Vm = R : • Pm,sp = Psp = k fb [Bac]d ; Hence
qsa
d P k3
Ta = ambient temperature and Rqsa = sp
Bac = = where k3 = constant
surface-to-ambient thermal resistance of component. kfb d
fb!a
• For optimal design Pw,sp = Pc,sp = Psp :

Ts!-!Ta • Plots of Jrms , Bac , and Psp versus core size
Hence Psp = R
qsa(Vw!+!Vc) (scale factor a) for a specific core material, geometry,
frequency, and Ts - Ta value very useful for picking
• Rqsa proportional to a2 and (Vw + Vc) appropriate core size and winding conductor size.
proportional to a3

Example of Power Density and Current Density Scaling
J rms P
sp
A/mm 2 mW/cm 3
8 400
7 350
Assumptions 6 300
1. Double-E core made from 3F3 ferrite 5 250
4 200
2. Ts = 100 °C and Ta = 40 °C.
J rms
3 150
3. Winding made with Leitz wire - kcu =
0.3 2 100
P
sp
1 50
0 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Core scaling parameter a [cm]

Analysis of a Specific Inductor Design
• Inductor specifications
• Maximum current = 4 ams rms at 100 kHz
• Double-E core with a = 1 cm using 3F3 ferrite.
• Distributed air-gap with four gaps, two in series in each leg;
total gap length Sg = 3 mm.
• Winding - 66 turns of Leitz wire with Acu = 0.64 mm2
g
• Inductor surface black with emissivity = 0.9
• Ta,max = 40 °C
• Find; inductance L, Ts,max ; effect of a 25% overcurrent on Ts

fringing
• Power dissipation in winding, Pw = Vw kcu rcu (Jrms)2 = 3.2 Watts flux
• Vw = 12.3 cm3 (table of core characteristics)
• kcu = 0.3 (Leitz wire)
• rcu at 100 °C (approx. max. Ts) = 2.2x10-8 ohm-m
g
• Jrms = 4/(.64) = 6.25 A/mm2
• Power dissipation in 3F3 ferrite core, g

Pcore = Vc1.5x10-6 f1.3 (Bac)2.5 = 3.3 W A core
d
Ag"mo"N 2"Irms
• Bac ≈ = 0.18 mT; assumes Hg >> Hcore
Ac"Sg
• Ag = (a + g)(d + g) = 1.71 cm2 ; g = 3mm/4 = .075 mm
• Ac = 1.5 cm2 (table of core characteristics a
• Vc = 13.5 cm3 (table of core characteristics)
• f = 100 kHz
Ag
Analysis of a Specific Inductor Design (cont.)
N!f
• L = = 310 mH
I
• f = Bac Ac = (0.18 T)(1.5x10-4 m2) = 2.6x10-5 Wb
• Surface temperature Ts = Ta + Rqsa (Pw + Pcore) = 104 °C

g
• Rqsa = Rq,rad || Rq,conv = 9.8 °C/W
60
• Rq,rad = ÊÊ373ˆ4 Ê ˆ4 ˆ = 20.1 [°C/W]
(5.1)!(0.006)!ÁËÁË ˜ !-!Á313˜ !˜! fringing
100¯ Ë100¯ ¯
flux
4
1 0.035
• Rq,conv = = 19.3 [°C/W]
(1.34)(0.006) 60
g
g
• Overcurrent of 25% (I= 5 amp rms) makes Ts = 146 °C
A core
d
• Pw = (3.2 W)(1.25)2 = 5 W ; Pcore = (3.3 W)(1.25)2.5 = 5.8 W
• Ts = (9.8 °C/W)(10.8 W) + 40 °C = 146 °C a
Ag

Stored Energy Relation - Basis of Inductor Design
• Input specifications for inductor design • Design procedure starting point - stored energy relation
• Inductance value L.
• [L I] Irms = [N f] Irms
• Rated peak current I
• Rated rms current Irms. kcu!Aw
• N= A
• Rated dc current (if any) Idc. cu
• Operating frequency f. • f = B Acore ; Irms = Jrms Acu
• Maximum inductor surface temperature Ts
and maximum ambient temperature Ta. • L I Irms = kcu Jrms B Aw Acore
• Design consists of the following:

• Equation relates input specifications (left-hand side) to
• Selection of core geometric shape and size needed core and winding parameters (right-hand side)
• Core material
• Winding conductor geometric shape and size • A good design procedure will consists of a systematic,
• Number of turns in winding single-pass method of selecting kcu, Jrms, B, Aw, and Acore.
Goal: Minimize inductor size, weight, and cost.

Core Database - Basic Inductor Design Tool
• Interactive core database (spreadsheet-based) key to a single pass inductor design procedure.
• User enters input specifications from converter design requirements. Type of conductor for windings
(round wire, Leitz wire, or rectangular wire or foil) must be made so that copper fill factor kcu is known.
• Spreadsheet calculates capability of all cores in database and displays smallest size core of each type
that meets stored energy specification.
• Also can be designed to calculate (and display as desired) design output parameters including Jrms, B,
Acu, N, and air-gap length.
• Multiple iterations of core material and winding conductor choices can be quickly done to aid in
selection of most appropriate inductor design.
• Information on all core types, sizes, and materials must be stored on spreadsheet. Info includes
dimensions, Aw, Acore, surface area of assembled inductor, and loss data for all materials of interest.
• Pre-stored information combined with user inputs to produce performance data for each core in
spreadsheet. Sample of partial output shown below.
Core No. Material AP = Rq Psp @ Jrms @ Bac @ ^

kcu Jrms B
AwAcore DT=60 °C DT=60 °C DT=60 °C DT=60 °C •Aw A core
& Psp & 100 kHz
• • • • • • • •
8 3F3 2.1 9.8 °C/W 237 3.3/ kcu 170 mT .0125 kcu
cm 4 mW/cm 3
• • • • • • • •

Details of Interactive Inductor Core Database Calculations
• User inputs: L, I, Irms, Idc, f, Ts, Ta, and kcu
• Stored information (static, independent of converter requirements)

• Core dimensions, Aw, Acore, Vc, Vw, surface area, mean turn length, mean magnetic path length, etc.
• Quantitative core loss formulas for all materials of interest including approximate temperature dependence.
• Calculation of core capabilities (stored energy value)

1. Compute converter-required stored energy value: L I Irms.
2. Compute allowable specific power dissipation Psp = [Ts - Ta] /{ Rqsa [Vc + Vw ]}. Rqsa = h/As or calculated
interactively using input temperatures and formulas for convective and radiative heat transfer from Heat Sink
chapter.
3. Compute allowable flux density Psp = k fb [Bac]d and current density Psp = kcu rcu {Jrms}2.
4. Compute core capabilities kcu Aw Acore B Jrms
• Calculation of inductor design parameters.

1. Area of winding conductor Acu = I / Jrms.
2. Calculate skin depth d in winding. If Acu > d2at the operating frequency, then single round conductor cannot
be used for winding.
• Construct winding using Leitz wire, thin foils, or paralleled small dia. (≤ d) round wires.

Details of Interactive Core Database Calculations (cont.)
3. Calculate number turns of N in winding: N = kcu Aw/ Acu.
4. Calculate air-gap length Lg. Air-gap length determined on basis that when inductor current
equals peak value I, flux density equals peak value B.
• Formulas for air-gap length different for different core types. Example for double-E core
given in next slide.
5. Calculate maximum inductance Lmax that core can support. Lmax = N Acore Bpeak / Ipeak .
If Lmax > required L value, reduce Lmax by removing winding turns.
• Save on copper costs, weight, and volume.
• Pw can be kept constant by increasing Pw,sp
• Keep flux density Bpeak constant by adjusting gap length Lg.
6. Alternative Lmax reduction procedure, increasing the value of Lg, keeping everything else
constant, is a poor approach. Would not reduce copper weight and volume and thus achieve
cost savings. Full capability of core would not be utilized.

Setting Double-E Core Air-gap Length
• Set total airgap length Lg so that Bpeak generated at the peak
current Ipeak.
• Lg = Ng g ; Ng = number of distributed gaps each of length g.
Distributed gaps used to minimize amount of flux fringing into
winding and thus causing additional eddy current losses.
N!Ipeak Lg!
• Rm = = Rm,core + Rm,gap ≈ Rm,gap = g
!Ac!Bpeak moAg
N!Ipeak!mo!Ag
• Lg =
!Ac!Bpeak
fringing
Lg Lg flux
• For a double-E core, Ag = (a + ) (d + )
Ng Ng
Lg Lg
• Ag ≈ ad + (a + d) ; << a g
Ng Ng
• Insertion of expression for Ag(Lg) into expression for L g(Ag) g
and solving for Lg yields A core
d
a
Lg =
Bpeak!Ac a!+!d
! !-!
d!mo!N!Ipeak d!Ng
a
• Above expression for Lg only valid for double-E core, but

similar expressions can be developed for other core shapes. Ag

Single Pass Inductor Design Procedure
Start
Enter design inputs

into core database
Examine database
outputs & select core
Neglect skin,
proximity effects?
Yes No
Iterative selection of
Select wires
conductor type/size.
No Yes
Estimate Lmax.
Too large?
Remove turns and

readjust airgap
Finish

Inductor Design Example
• Assemble design inputs • Core flux density B =170 mT from database.

• L = 300 microhenries No Idc, Bpeak = 170 mT.
• Peak current = 5.6 A,
sinewave current, Irms = 4 A • Winding parameters.
• Frequency = 100 kHz • Litz wire used, so kcu = 0.3. Jrms = 6 A/mm2
• Ts = 100 °C ; Ta = 40 °C
• Acu = (4 A)/(6 A/mm2) = 0.67 mm2
• Stored energy L I Irms = (3x10-4)(5.6)(4) • N = (140 mm2)((0.3)/(0.67 mm2) = 63 turns.
= 0.00068 J-m-3
(63)(170!mT)(1.5x10-4!m2)
• Lmax = 5.6!A
• Core material and geometric shape
• High frequency operation dictates ferrite ≈ 290 microhenries
material. 3F3 material has highest
performance factor PF at 100 kHz. 10-2
• Double-E core chosen for core shape. • Lg =
(0.17)!(1.5x10-4) 2.5x10-2
! !-!
• Double-E core with a = 1 cm meets requirements. (1.5x10-2)(4πx10-7)(63)(5.6) (4)(1.5x10-2)!
kcu Jrms B^ A A Lg ≈ 3 mm
w core ≥ 0.0125 kcu 0.0068
for kcu > 0.3
• Lmax ≈ L so no adjustment of inductance value
is needed.
• Database output: Rq = 9.8 °C/W and
Psp = 237 mW/cm3

Iterative Inductor Design Procedure
Start
• Iterative design procedure essentially

Assemble design inputs Design winding (k cu,J, A cu
, N) consists of constructing the core
database until a suitable core is found.
• Choose core material and shape and

Compute L I I rms Corrected inductance-
conductor type as usual.
current product greater
than L I I ?
rms • Use stored energy relation to find an
No Yes
Choose core size using initial initial area product AwAc and thus an
values of J and B initial core size.
Select larger core size
Find allowable power

• Use initial values of Jrms = 2-4 A/mm2
dissipation density P and Bac = 50-100 mT.
sp
Find maximum inductance • Use initial core size estimate (value of a in

Find corrected core flux double-E core example) to find corrected
density B
ac values of Jrms and Bac and thus corrected value
^ A A
of kcu Jrms B
Design airgap length g w core.
Find corrected peak core flux
density B ^ A A
• Compare kcu Jrms B w core with
Set L to design value L I Irms and iterate as needed into proper
size is found.

Simple, Non-optimal Inductor Design Method
• Assemble design inputs and compute required LI Irms
Start
Assemble design inputs

• Choose core geometry and core material based on
considerations discussed previously.
Compute L I I r m s
• Assume Jrms= 2-4 A/mm2 and Bac = 50-100 mT and use
LI Irms = kcu Jrms Bac Aw Acore to find the required area
Determine core size using product Aw Acore and thus the core size.
assumed values of J and B
• Assumed values of Jrmsand Bac based on experience.
Design winding (k cu
,J, A cu
, N)
• Complete design of inductor as indicated.
Set airgap length g to • Check power dissipation and surface temperature using
obtain desired inductance L Select
assumed values of Jrmsand Bac. If dissipation or
larger
core size temperature are excessive, select a larger core size and repeat
design steps until dissipation/temperature are acceptable.
No Check power dissipation Yes
and surface temperature.
Excessive?.
• Procedure is so-called area product method. Useful in
situations where only one ore two inductors are to be built
Done and size/weight considerations are secondary to rapid
construction and testing..
Analysis of Specific Transformer Design
• Transformer specifications • Areas of primary and secondary conductors,
Acu,pri and Acu,sec.
• Wound on double-E core with
a = 1 cm using 3F3 ferrite.
Npri!Acu,pri Nsec!Acu,sec
• Ipri = 4 A rms, sinusoidal waveform; • Aw,pri = !kcu,pri ; A w,sec = !kcu,sec
Vpri = 300 V rms.
Npri!Acu,pri Nsec!Acu,sec
• Frequency = 100 kHz • Aw,pri + Aw,sec = Aw = !kcu + !kcu
where kcu,pri = kcu,sec = kcu since we assume primary and
• Turns ratio Npri/Nsec = 4 and
secondary are wound with same type of conductor.
Npri = 32.
• Equal power dissipation density in primary and secondary gives
• Winding window split evenly between
primary and secondary and wound Ipri Acu,pri Nsec
with Litz wire. Isec = !Acu,sec = N
pri
• Transformer surface black (E = 0.9) kcu!Aw
and Ta ≤ 40 °C. • Using above equations yields Acu,pri = 2!N and
pri
kcu!Aw
• Find: core flux density, leakage inductance, Acu,sec = 2!N
and maximum surface temperature Ts, and sec
(0.3)(140!mm2)
effect of 25% overcurrent on Ts. • Numerical values: Acu,pri = (2)(32) = 0.64 mm2
(0.3)(140!mm2)
and Acu,sec = (2)(8) = 2.6 mm2
Analysis of Specific Transformer Design (cont.)
Mean turn length l w
• Power dissipation in winding Pw = kcu rcu(Jrms)2 Vw Top view
r adi us = b /2
w
of bobbin
• Jrms = (4 A)/(0.64 mm2) = (16 A)/(2.6 mm2) = 6.2 A/mm2
1.9 a
• Pw = (0.3)(2.2x10-8 ohm-m) (6.2x106 A/m2)2(1.23x10-5 m3) 1.4 a
Pw = 3.1 watts
• Flux density and core loss
• Vpri,max = Npri Ac w Bac = (1.414)(300) = 425 V b w = 0.7a
l w = (2)(1.4a) + (2)(1.9a) + 2π (0.35bw ) = 8 a

425
• Bac = = 0.140 T
(32)(1.5x10-4!m2)(2π)(105!Hz) • Surface temperature Ts.
• Assume Rq,sa ≈ 9.8 °C/W.
• Pcore = (13.5 cm3)(1.5x10-6)(100 kHz)1.3(140 mT)2.5 = 1.9 W
Same geometry as inductor.
• Ts = (9.8)(3.1 + 1.9) + 40 = 89 °C
mo(Npri)2!bw!lw
• Effect of 25% overcurrent.
• Leakage inductance Lleak =
3!hw • No change in core flux density.
• lw = 8 a = 8 cm Constant voltage applied to
primary keeps flux density constant.
(4πx10-7)(32)2(0.7)(10-2)(8x10-2)
• Lleak = ≈ 12 microhenries • Pw = (3.1)(1.25)2 = 4.8 watts
(3)(2x10-2)
•` Ts = (9.8)(4.8 + 1.9) + 40 = 106 °C

Sectioning of Transformer Windings to Reduce Winding Losses
x x x
x Primary
x x x • Reduce winding losses by reducing magnetic
x x x
Secondary field (or equivently the mmf) seen by
x x x
conductors in winding. Not possible in an
inductor.
MMF
• Simple two-section transformer winding
Npri I pri = Nsec I sec situation.
x
0 b
w
P P P S P S P
S
2 2 4 2 2 2 4 • Division into multiple
sections reduces MMF and
hence eddy current losses.
MMF MMF
0 x 0 x
Npri I pri
Npri I pri Npri I pri
2 Npri I pri
4 4
2

Optimization of Solid Conductor Windings
• Nomalized power dissipation =
Pw FRRdc
=
Rdc,h=d(Irms)2 Rdc,h=d
Fl!h
• Conductor height/diameter d
• Fl = copper layer factor
• Fl = b/bo for rectangular conductors
• Fl = d/do for round conductors
• h = effective conductor height
π
• h= d for round conductors
4
• m = number of layers
hw
b hw
N l turns per layer =
bo bo
do
hw
hw
N l turns per layer =
do

Transformer Leakage Inductance
• Transformer leakage inductance causes • Linear variation of mmf in winding window indicates
overvoltages across power switches at turn-off. spatial variation of magnetic flux in the window and thus
incomplete flux linkage of primary and secondary windings.
• Leakage inductance caused by magnetic
flux which does not completely link primary 2!Npri!Ipri!x
and secondary windings. • Hwindow = Hleak = ; 0 < x < bw/2
hw!bw
2!Npri!Ipri
Direction and relative Hleak = (1 - x/bw) ; bw/2 < x < bw
magnitude of leakage hw
magnetic field.
Lleak!(Ipri)2 1 Û
ımo(Hleak)2dV
x Ù
Primary • =
2 2
x = current Vw
x x x into page
hw x x x • Volume element dV = hw lw(x)dx ; lw(x) equals the
x x x Secondary length of the conductor turn located at position x.
x x x • Assume a mean turn length lw ≈ 8a for double-E
• = current
out of page core independent of x.
bw/2
MMF
Lleak!(Ipri)2
Û
1 Ù 2!Npri!Ipri!x
• = (2) Ùm [ ]2!hw!lwdx
Npri I pri = Nsec I sec 2 2 ı o hw!bw
0
mo!(Npri)2!lw!bw
x • Lleak =
0 bw 3!p2!!hw
• If winding is split into p+1 sections, with p > 1,
leakage inductance is greatly reduced.
Volt-Amp (Power) Rating - Basis of Transformer Design
• Input design specifications • Design proceedure starting point - transformer V-A rating S
• Rated rms primary voltage Vpri • S = Vpri Ipri + Vsec Isec = 2 Vpri Ipri
df Npri!Acore!w!Bac
• Rated rms primary current Ipri • Vpri = Npri dt = ; Ipri = Jrms Acu,pri
2
• Turns ratio Npri/Nsec Npri!Acore!w!Bac
• S = 2 Vpri Ipri = 2 Jrms Acu,pri
2
• Operating frequency f
kcu!Aw
• Maximum temperatures Ts and Ta • Acu,pri = 2!N
pri
• Design consists of the following: Npri!Acore!w!Bac kcu!Aw

• S = 2 Vpri Ipri = 2 Jrms 2!N
• Selection of core geometric shape and size 2 pri
• Core material • S = Vpri Ipri = 4.4 kcu f Acore Aw Jrms Bac
• Winding conductor geometric shape and size

• Number of turns in primary and secondary • Equation relates input specifications (left-hand side) to core
windings. and winding parameters (right-hand side).
• Desired design procedure will consist of a systematic,

single-pass method of selecting kcu, Acore, Aw, Jrms, and Bac.

Core Database - Basic Transformer Design Tool
• Interactive core database (spreadsheet-based) key to a single pass tramsformer design procedure.
• User enters input specifications from converter design requirements. Type of conductor for windings
(round wire, Leitz wire, or rectangular wire or foil) must be made so that copper fill factor kcu is known.
• Spreadsheet calculates capability of all cores in database and displays smallest size core of each type
that meets V- I specification.
• Also can be designed to calculate (and display as desired) design output parameters including Jrms, B,
Acu,pri, Acu,sec, Npri, Nsec, and leakage inductance..
• Multiple iterations of core material and winding conductor choices can be quickly done to aid in
selection of most appropriate tranformer design.
• Information on all core types, sizes, and materials must be stored on spreadsheet. Info includes
dimensions, Aw, Acore, surface area of assembled transformer , and loss data for all materials of interest.
• Pre-stored information combined with user inputs to produce performance data for each core in
spreadsheet. Sample of partial output shown below.
Core Material AP = Rq Psp @ Jrms @ ^

B ^ AP
No. rated @ 2.22 kcu f Jrms B
AwAc DT=60 °C Ts=100 °C Ts=100 °C Ts=100 °C (f = 100kHz)
& Psp & 100 kHz
• • • • • • • •
8 3F3 2.1 9.8 °C/W 237 (3.3/ kcu 170 mT 2.6x103 •
4 3
cm mW/cm ) kcuRdc
Rdc Rac
• Rac [V-A]
A/mm2
• • • • • • • •

Details of Interactive Transformer Core Database Calculations
• User inputs: Vpri, Ipri, turns ratio Ndc/ Nsec, f, Ts, Ta, and kcu
• Stored information (static, independent of converter requirements)

• Core dimensions, Aw, Acore, Vc, Vw, surface area, mean turn length, mean magnetic path length, etc.
• Quantitative core loss formulas for all materials of interest including approximate temperature dependence.
• Calculation of core capabilities

1. Compute converter-required stored energy value: S = 2 Vpri Ipri
2. Compute allowable specific power dissipation Psp = [Ts - Ta] /{ Rqsa [Vc + Vw ]}. Rqsa = h/As or calculated
interactively using input temperatures and formulas for convective and radiative heat transfer from Heat Sink
chapter.
3. Compute allowable flux density Psp = k fb [Bac]d and current density Psp = kcu rcu {Jrms}2.
4. Compute core capabilities 4.4 f kcu Aw Acore Bac Jrms
• Calculation transformer parameters.

1. Calculate number of primary turns Npri = Vpri /{2π f AcpreBac} and secondary turns Nsec = Vsec /{2π f AcpreBac}
2. Calculate winding conductor areas assuming low frequencies or use of Leitz wire
• Acu,pri = [kcuAw]/[2 Npri] and Acu,sec = [kcuAw]/[2 Nsec]

Details of Interactive Transformer Core Database Calculations (cont.)
3. Calculate winding areas assuming eddy current/proximity effect is important
• Only solid conductors, round wires or rectangular wires (foils), used.Jrms = [{Psp Rdc}/{Rac kcu rcu}]1/2
• Conductor dimensions must simultaneously satisfy area requirements and requirements of normalized
power dissipation versus normalized conductor dimensions.
• May require change in choice of conductor shape. Most likely will require choice of foils (rectangular
shapes).
• Several iterations may be needed to find proper combinations of dimensions, number of turns per layer,
and number of layers and sections.
• Best illustrated by a specific design example.
4. Estimate leakage inductance Lleak= {µo{Npri}2 lw bw}/ {3 p2 hw}
5. Estimate Smax = 4.4 kcu f Acore Aw Jrms Bac
6. IfSmax > S = 2 Vpri Ipri reduce Smax and save on copper cost, weight, and volume.
• If Npri w Ac Bac > Vpri, reduce Smax by reducing Npri and Nsec.
• If Jrms Acu, pri > Irms, reduce Acu,pri and Acu, sec.
• If S > Smax by only a moderate amount (10-20%) and smaller than Smax of next core size, increase Smax of
present core size.
• Increase Irms (and thus winding power dissipation) as needed.Temperature Ts will increase a modest amount
above design limit, but may be preferable to going to larger core size.

Single Pass Transformer Design Procedure
Start
Enter design inputs

into core database
Examine database
outputs & select core
Neglect skin,
proximity effects?
Yes No
Iterative selection of
Select wires
conductor type/size.
No Yes
Estimate S max.
Too large?
Remove turns
Finish

Transformer Design Example
• Design inputs
• Vpri = 300 V rms ; Irms = 4 A rms • Using core database, Rq = 9.8 °C/W
• Turns ratio n = 4 and Psp = 240 mW/cm3.
• Operating frequency f = 100 kHz
• Ts = 100 °C and Ta = 40 °C • Flux density and number of primary
and secondary turns.
• V - I rating S = (300 V rms)(4 A rms) • From core database, Bac = 170 mT.
= 1200 watts
300! 2
• Npri =
• Core material, shape, and size. (1.5x10-4m2)(2π)(105Hz)(0.17!T)
• Use 3F3 ferrite because it has largest = 26.5 ≈ 24. Rounded down to 24 to increase
performance factor at 100 kHz. flexibility in designing sectionalized
• Use double-E core. Relatively easy to transformer winding.
fabricate winding. 24
• Nsec = 6 = 6.
Rdc
• Core volt-amp rating = 2,600 kcu 3.3
Rac • From core database Jrms =
(0.6)(1.5)
• Use solid rectangular conductor for
windings because of high frequency. = 3.5 A/mm2.
Thus kcu = 0.6 and Rac/Rdc = 1.5. 4!A!rms
• Acu,pri = 2 = 1.15 mm2
!3.5!A!rms/mm
0.6
• Core volt-amp capability = 2,600 1.5 • Acu,sec = (4)(1.15 mm2) = 4.6 mm2
= 1644 watts. > 1200 watt transformer rating.
Size is adequate.

Transformer Design Example (cont.)
• Primary and secondary conductor areas - Acu,sec
proximity effect/eddy currents included. • Secondary layer height hsec= F !h
l w
Assume rectangular (foil) conductors with
kcu = 0.6 and layer factor Fl = 0.9. 4.6!mm2
= (0.9)(20!mm) ≈ 0.26 mm.
• Iterate to find compatible foil thicknesses • Normalized secondary conductor height

and number of winding sections.
• 1st iteration - assume a single primary section Fl!hsec 0.9!(0.26!mm)
and a single secondary section and each section f= d = (0.24!mm) =1
having single turn per layer. Primary has 24
layers and secondary has 6 layers. • However a six layer section has an optimum
f = 0.6. A two layer section has an optimum
Acu,pri f = 1. 2nd iteration needed.
• Primary layer height hpri = F !h
l w
• 2nd iteration - sectionalize the windings.
1.15!mm2
= (0.9)(20!mm) = 0.064 mm
• Use a secondary of 3 sections, each having two
layers, of height hsec = 0.26 mm.
• Normalized primary conductor height
Fl!hpri 0.9!(0.064!mm) • Secondary must have single turn per layer.
f= d = (0.24!mm) = 0.25 ;
Two turns per layer would require hsec = 0.52 mm
d = 0.24 mm in copper at100 kHz and 100 °C.
and thus f = 2. Examination of normalized power
• Optimum normalized primary conductor height dissipation curves shows no optimum f = 2.
f = 0.3 so primary winding design is satisfactory.

Transformer Design Example (cont.)
P S P S P S P
6 3 3 3 3 3 6
• Three secondary sections requires four primary sections. • Leakage inductance Lleak
• Two outer primary sections would have 24/6 = 4 (4πx10-9)(24)2(8)(0.7)(1)

= = 0.2 mH
turns each and the inner two sections would have (3)(6)2(2)
24/3 = 8 turns each.
• Need to determine number of turns per layer and • Sectionalizing increases capacitance
hence number of layers per section. between windings and thus lowers the
transformer self-resonant frequency.
Turns/ hpri No. of f Optimum
layer Layers f
1 0.064 mm 8 0.25 0.45 • Smax = 1644 watts
2 0.128 mm 4 0.5 0.6
4 0.26 mm 2 1 1
• Rated value of S = 1200 watts only
marginally smaller than Smax. Little to
• Use four turns per layer. Two interior primary
be gained in reducing Smax to S unless a
sections have two layers and optimum value of f.
large number of transformer of this design
Two outer sections have one layer each and f not
are to be fabricated.
optimum, but only results in slight increase in loss
above the minimum.
Iterative Transformer Design Procedure
Start
• Iterative design procedure essentially
Design windings ( A cu,pri, N pri, consists of constructing the core
A cu,sec , N sec ) database until a suitable core is found.
• Choose core material and shape and

Compute 2 Vpri I pri conductor type as usual.
Corrected V-I rating greater
than 2 Vpri I pri ?
• Use V - I rating to find an initial area
No Yes product AwAc and thus an initial core size.
Choose core size using initial
values of J and B
Select larger core size • Use initial values of Jrms = 2-4 A/mm2
Find allowable power and Bac = 50-100 mT.
dissipation density P
sp
• Use initial core size estimate (value of a in
Find maximum V - I rating double-E core example) to find corrected
Find corrected core flux
density B
values of Jrms and Bac and thus corrected
ac
^ A A
value of 4.4 f kcu Jrms B w core.
Set S max to desired S
Find corrected current
density J r m s • Compare 4.4 f kcu Jrms B ^ A A
w core with
2 Vpri Ipri and iterate as needed into proper
Estimate leakage inductance
size is found.
End

Simple, Non-optimal Transformer Design Method
• Assemble design inputs and compute required 2 Vpri Ipri
Start

• Choose core geometry and core material based on
considerations discussed previously.
Compute 2 Vpri I pri

• Assume Jrms= 2-4 A/mm2 and Bac = 50-100 mT and use
2 Vpri Ipri = 4.4 f kcu Jrms Bac Aw Acore to find the required area
Determine core size using product Aw Acore and thus the core size.
assumed values of J and B
• Assumed values of Jrmsand Bac based on experience.
Design winding ( A cu,pri , N pri ,

A cu,sec , N sec ) • Complete design of transformer as indicated.
Set S max to desired S • Check power dissipation and surface temperature using
Select
larger assumed values of Jrmsand Bac. If dissipation or
core size temperature are excessive, select a larger core size and repeat
design steps until dissipation/temperature are acceptable.
No Check power dissipation Yes
and surface temperature.
Excessive?.
• Procedure is so-called area product method. Useful in
situations where only one ore two transformers are to be built
Done and size/weight considerations are secondary to rapid
construction and testing..

Power Electronics Converters, Applications, and Design

Încărcat de

Informații document

Descriere originală:

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Power Electronics Converters, Applications, and Design

Încărcat de

Drepturi de autor:

Formate disponibile

Chapter 1 Power Electronic Systems

Copyright © 2003 Chapter 1 Introduction 1-1

Copyright © 2003 Chapter 1 Introduction 1-2

• Series transistor as an adjustable resistor

Copyright © 2003 Chapter 1 Introduction 1-4

• Constant switching frequency

Copyright © 2003 Chapter 1 Introduction 1-5

• Conventional drive wastes energy across the throttling

Copyright © 2003 Chapter 1 Introduction 1-6

Copyright © 2003 Chapter 1 Introduction 1-7

• Most practical topologies require an energy

• Converter is a general term

Copyright © 2003 Chapter 1 Introduction 1-9

• Converter 1 rectifies line-frequency ac into dc

• Very general structure

Copyright © 2003 Chapter 1 Introduction 1-12

Copyright © 2003 Chapter 2 Power Semiconductor 2-1

• On and off states controlled by the power circuit

Copyright © 2003 Chapter 2 Power Semiconductor 2-2

• Fast-recovery diodes have a small reverse-recovery time

Copyright © 2003 Chapter 2 Power Semiconductor 2-3

• For successful turn-off, reverse voltage required

• Idealized switch symbol

Copyright © 2003 Chapter 2 Power Semiconductor 2-6

Switching Power Loss is

Copyright © 2003 Chapter 2 Power Semiconductor 2-7

• Used commonly in the past

Copyright © 2003 Chapter 2 Power Semiconductor 2-8

Copyright © 2003 Chapter 2 Power Semiconductor 2-9

• Easy to control by the gate

Copyright © 2003 Chapter 2 Power Semiconductor 2-10

• Slow switching speeds

Copyright © 2003 Chapter 2 Power Semiconductor 2-11

• Need a turn-off snubber

Copyright © 2003 Chapter 2 Power Semiconductor 2-12

Copyright © 2003 Chapter 2 Power Semiconductor 2-13

Copyright © 2003 Chapter 2 Power Semiconductor 2-14

Copyright © 2003 Chapter 2 Power Semiconductor 2-15

Copyright © 2003 Chapter 2 Power Semiconductor 2-16

Copyright © 2003 Chapter 3 Basic Electrical and 3-1

Copyright © 2003 Chapter 3 Basic Electrical and 3-2

Copyright © 2003 Chapter 3 Basic Electrical and 3-3

Copyright © 2003 Chapter 3 Basic Electrical and 3-4

Copyright © 2003 Chapter 3 Basic Electrical and 3-5

Copyright © 2003 Chapter 3 Basic Electrical and 3-6

• Voltage is assumed to be sinusoidal

Copyright © 2003 Chapter 3 Basic Electrical and 3-7

Copyright © 2003 Chapter 3 Basic Electrical and 3-8

Copyright © 2003 Chapter 3 Basic Electrical and 3-9

• Volt-seconds over T equal zero.

Copyright © 2003 Chapter 3 Basic Electrical and 3-11

• Direction of magnetic field due to currents

Copyright © 2003 Chapter 3 Basic Electrical and 3-12

Copyright © 2003 Chapter 3 Basic Electrical and 3-13

Copyright © 2003 Chapter 3 Basic Electrical and 3-14

• Flux is related to ampere-turns by reluctance

Copyright © 2003 Chapter 3 Basic Electrical and 3-16

Copyright © 2003 Chapter 3 Basic Electrical and 3-17

Copyright © 2003 Chapter 3 Basic Electrical and 3-18

Copyright © 2003 Chapter 3 Basic Electrical and 3-19

Copyright © 2003 Chapter 3 Basic Electrical and 3-20

• Inductance relates flux-linkage to current