FPGA Quartus II TimeQuest Tutorial

Alex Yang
Northwestern Polytechnic University
Fremont CA
Copyright 2014, All Rights Reserved

Step 1: Create new project

Step 2: Generate a module

Step 3: Compile module

Step 4: Open TimeQuest

Step 5: Double-clicking Create Timing Netlist

Step 6: Double-clicking Read SDC File

Note: Initially, no constraints are specified and the default constraint of 1 GHz on the clock
signal is applied automatically.

Step 7: Double-clicking Update Timing Netlist

Step 8: Double-clicking Report Setup Summary

Step 9: Right-clicking Report Timing on the clock

Step 10: Setting Up Timing Constraints for a Design

Step 11: Double-clicking Write SDC File

Step 12: Recompile the module

Step 13: Double-clicking Create Timing Netlist, Create

SDC file, Update Timing Netlist and Report Setup
Summary

Very Good!
We know how to use TimeQuest in Quartus II.