Sunteți pe pagina 1din 3

HOME

ABOUT

CONTACT

SYSTEMVERILOG

Saturday, February 27, 2016

UVM

SYSTEMC

PROTOCOLS

VIDEOS

LINUX COMMANDS

UVM Interview Questions


1. Whatisuvm_transaction,uvm_object,uvm_component?
2.

CanwehaveuserdefinedphaseinUVM?

3.

Whatisthedifferencebetweennew()andcreate?

4.

Whatisanalysisport?

5.

WhatisTLMFIFO?

6. Howsequencestarts?

Whatistheadvantageof`uvm_component_utils()and`uvm_object_utils()?
8. Whatisobjection?
7.

9. WhatarethebenefitsofusingUVM?
10.

WhatisthedifferencebetweenActivemodeandPassivemode?

11. Whatisthedifferencebetweencopyandclone?

Whatisfactory?
13. Whatarethetypesofsequencer?Explaineach?
12.

14.

Whatarethedifferentphasesofuvm_component?Explaineach?

Howset_config_*works?
16. Whatissuperkeyword?Whatistheneedofcallingsuper.build()andsuper.connect()?
17. Whatisthedifferentbetweenset_config_*anduvm_config_db?
15.

18.

Whatarethedifferentoverridetypes?

19. Whatisvirtualsequenceandvirtualsequencer?
20. ExplainendofsimulationinUVM?

SCRIPTING

20. ExplainendofsimulationinUVM?
21.

Howtodeclaremultipleimports?

22. Whatissymbolicrepresentationofport,exportandanalysisport?
23. Whatisthedifferenceinusageof$finishandglobalstoprequestinUVM?
24. Whatisthedifferencebetween`uvm_doand`uvm_ran_send?
25. Whyweneedtoregisterclasswithuvmfactory?
26.

diffbetweenuvm_transactionanduvm_seq_item?

27.

canweuseset_configandget_configinsequence?

28. Whatisuvm_heartbeat?

TestyourSystemVerilogknowledgebytaking"SystemVerilogOnlineTest".
alsofind,

DownloadThisToPDF
FreetoDownloadandConvert.GetItInstantly,DownloadNow.

Copyright 2014 :: all rights reserved ASIC BABA. Designed By GT. Subscribe For Updates

S-ar putea să vă placă și